1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32MP1xx_LL_SDMMC_H 22 #define STM32MP1xx_LL_SDMMC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32mp1xx_hal_def.h" 30 31 /** @addtogroup STM32MP1xx_Driver 32 * @{ 33 */ 34 35 /** @addtogroup SDMMC_LL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief SDMMC Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 50 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 51 52 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 53 disabled when the bus is idle. 54 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 55 56 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 57 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 58 59 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 60 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 61 62 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 63 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 64 65 }SDMMC_InitTypeDef; 66 67 68 /** 69 * @brief SDMMC Command Control structure 70 */ 71 typedef struct 72 { 73 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 74 to a card as part of a command message. If a command 75 contains an argument, it must be loaded into this register 76 before writing the command to the command register. */ 77 78 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 79 Max_Data = 64 */ 80 81 uint32_t Response; /*!< Specifies the SDMMC response type. 82 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 83 84 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 85 enabled or disabled. 86 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 87 88 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 89 is enabled or disabled. 90 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 91 }SDMMC_CmdInitTypeDef; 92 93 94 /** 95 * @brief SDMMC Data Control structure 96 */ 97 typedef struct 98 { 99 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 100 101 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 102 103 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 104 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 105 106 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 107 is a read or write. 108 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 109 110 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 111 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 112 113 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 114 is enabled or disabled. 115 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 116 }SDMMC_DataInitTypeDef; 117 118 /** 119 * @} 120 */ 121 122 /* Exported constants --------------------------------------------------------*/ 123 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 124 * @{ 125 */ 126 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 127 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 128 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 129 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 130 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 131 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 132 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 133 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 134 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the 135 number of transferred bytes does not match the block length */ 136 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 137 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 138 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 139 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock 140 command or if there was an attempt to access a locked card */ 141 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 142 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 143 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 144 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 145 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 146 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 147 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 148 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 149 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 150 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 151 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out 152 of erase sequence command was received */ 153 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 154 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 155 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 156 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 157 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 158 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 159 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 160 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 161 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 162 163 /** 164 * @brief SDMMC Commands Index 165 */ 166 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 167 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 168 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 169 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 170 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 171 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 172 operating condition register (OCR) content in the response on the CMD line. */ 173 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 174 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 175 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 176 and asks the card whether card supports voltage. */ 177 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 178 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 179 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 180 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 181 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 182 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 183 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 184 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands 185 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 186 for SDHS and SDXC. */ 187 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 188 fixed 512 bytes in case of SDHC and SDXC. */ 189 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by 190 STOP_TRANSMISSION command. */ 191 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 192 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 193 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 194 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 195 fixed 512 bytes in case of SDHC and SDXC. */ 196 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 197 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 198 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 199 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 200 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 201 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 202 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 203 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 204 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command 205 system set by switch function command (CMD6). */ 206 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. 207 Reserved for each command system set by switch function command (CMD6). */ 208 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 209 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 210 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 211 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 212 the SET_BLOCK_LEN command. */ 213 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather 214 than a standard command. */ 215 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card 216 for general purpose/application specific commands. */ 217 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 218 219 /** 220 * @brief Following commands are SD Card Specific commands. 221 * SDMMC_APP_CMD should be sent before sending these commands. 222 */ 223 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 224 widths are given in SCR register. */ 225 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 226 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 227 32bit+CRC data block. */ 228 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 229 send its operating condition register (OCR) content in the response on the CMD line. */ 230 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 231 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 232 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 233 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 234 235 /** 236 * @brief Following commands are SD Card Specific security commands. 237 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 238 */ 239 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 240 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 241 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 242 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 243 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 244 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 245 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 246 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 247 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 248 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 249 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 250 251 /** 252 * @brief Masks for errors Card Status R1 (OCR Register) 253 */ 254 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 255 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 256 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 257 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 258 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 259 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 260 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 261 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 262 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 263 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 264 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 265 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 266 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 267 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 268 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 269 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 270 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 271 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 272 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 273 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 274 275 /** 276 * @brief Masks for R6 Response 277 */ 278 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 279 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 280 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 281 282 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 283 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 284 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 285 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 286 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 287 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 288 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 289 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 290 291 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 292 293 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 294 295 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 296 297 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 298 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 299 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 300 301 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 302 303 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 304 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 305 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 306 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 307 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 308 309 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 310 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 311 312 /** 313 * @brief Command Class supported 314 */ 315 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 316 317 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 318 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 319 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 320 321 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 322 * @{ 323 */ 324 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 325 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 326 327 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 328 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 329 /** 330 * @} 331 */ 332 333 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 334 * @{ 335 */ 336 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 337 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 338 339 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 340 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 341 /** 342 * @} 343 */ 344 345 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 346 * @{ 347 */ 348 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 349 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 350 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 351 352 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 353 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 354 ((WIDE) == SDMMC_BUS_WIDE_8B)) 355 /** 356 * @} 357 */ 358 359 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 360 * @{ 361 */ 362 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 363 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 364 365 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 366 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 367 /** 368 * @} 369 */ 370 371 /** @defgroup SDMMC_LL_Clock_Division Clock Division 372 * @{ 373 */ 374 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 375 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 376 /** 377 * @} 378 */ 379 380 381 /** @defgroup SDMMC_LL_Command_Index Command Index 382 * @{ 383 */ 384 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 385 /** 386 * @} 387 */ 388 389 /** @defgroup SDMMC_LL_Response_Type Response Type 390 * @{ 391 */ 392 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 393 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 394 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 395 396 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 397 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 398 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 399 /** 400 * @} 401 */ 402 403 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 404 * @{ 405 */ 406 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 407 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 408 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 409 410 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 411 ((WAIT) == SDMMC_WAIT_IT) || \ 412 ((WAIT) == SDMMC_WAIT_PEND)) 413 /** 414 * @} 415 */ 416 417 /** @defgroup SDMMC_LL_CPSM_State CPSM State 418 * @{ 419 */ 420 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 421 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 422 423 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 424 ((CPSM) == SDMMC_CPSM_ENABLE)) 425 /** 426 * @} 427 */ 428 429 /** @defgroup SDMMC_LL_Response_Registers Response Register 430 * @{ 431 */ 432 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 433 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 434 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 435 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 436 437 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 438 ((RESP) == SDMMC_RESP2) || \ 439 ((RESP) == SDMMC_RESP3) || \ 440 ((RESP) == SDMMC_RESP4)) 441 442 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 443 * @{ 444 */ 445 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 446 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 447 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 448 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 449 450 /** 451 * @} 452 */ 453 454 /** @defgroup SDMMC_LL_Data_Length Data Lenght 455 * @{ 456 */ 457 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 458 /** 459 * @} 460 */ 461 462 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 463 * @{ 464 */ 465 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 466 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 467 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 468 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 469 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 470 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 471 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 472 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 473 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 474 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 475 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 476 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 477 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 478 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 479 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 480 481 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 482 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 483 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 484 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 485 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 486 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 487 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 488 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 489 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 490 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 491 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 492 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 493 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 494 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 495 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 496 /** 497 * @} 498 */ 499 500 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 501 * @{ 502 */ 503 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 504 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 505 506 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 507 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 508 /** 509 * @} 510 */ 511 512 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 513 * @{ 514 */ 515 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 516 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 517 518 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 519 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 520 /** 521 * @} 522 */ 523 524 /** @defgroup SDMMC_LL_DPSM_State DPSM State 525 * @{ 526 */ 527 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 528 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 529 530 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 531 ((DPSM) == SDMMC_DPSM_ENABLE)) 532 /** 533 * @} 534 */ 535 536 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 537 * @{ 538 */ 539 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 540 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 541 542 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 543 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 544 /** 545 * @} 546 */ 547 548 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 549 * @{ 550 */ 551 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 552 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 553 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 554 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 555 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 556 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 557 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 558 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 559 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 560 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 561 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 562 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 563 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 564 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 565 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 566 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 567 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 568 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 569 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 570 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 571 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 572 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 573 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 574 /** 575 * @} 576 */ 577 578 /** @defgroup SDMMC_LL_Flags Flags 579 * @{ 580 */ 581 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 582 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 583 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 584 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 585 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 586 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 587 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 588 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 589 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 590 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 591 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 592 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 593 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 594 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 595 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 596 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 597 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 598 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 599 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 600 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 601 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 602 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 603 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 604 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 605 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 606 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 607 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 608 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 609 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 610 611 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 612 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 613 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 614 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 615 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 616 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 617 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 618 619 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 620 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 621 622 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 623 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 624 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 625 SDMMC_FLAG_IDMABTC)) 626 /** 627 * @} 628 */ 629 630 /** 631 * @} 632 */ 633 634 /* Exported macro ------------------------------------------------------------*/ 635 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 636 * @{ 637 */ 638 639 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 640 * @brief SDMMC_LL registers bit address in the alias region 641 * @{ 642 */ 643 /* ---------------------- SDMMC registers bit mask --------------------------- */ 644 /* --- CLKCR Register ---*/ 645 /* CLKCR register clear mask */ 646 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 647 SDMMC_CLKCR_WIDBUS |\ 648 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 649 650 /* --- DCTRL Register ---*/ 651 /* SDMMC DCTRL Clear Mask */ 652 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 653 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 654 655 /* --- CMD Register ---*/ 656 /* CMD Register clear mask */ 657 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 658 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 659 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 660 661 /* SDMMC Initialization Frequency (400KHz max) for IP CLK 200MHz*/ 662 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) 663 664 /* SDMMC Default Speed Frequency (25Mhz max) for IP CLK 200MHz*/ 665 #define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4) 666 667 /* SDMMC High Speed Frequency (50Mhz max) for IP CLK 200MHz*/ 668 #define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2) 669 /** 670 * @} 671 */ 672 673 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 674 * @brief macros to handle interrupts and specific clock configurations 675 * @{ 676 */ 677 678 /** 679 * @brief Enable the SDMMC device interrupt. 680 * @param __INSTANCE__ : Pointer to SDMMC register base 681 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. 682 * This parameter can be one or a combination of the following values: 683 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 684 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 685 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 686 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 687 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 688 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 689 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 690 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 691 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 692 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 693 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 694 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 695 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 696 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 697 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 698 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 699 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 700 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 701 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 702 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 703 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 704 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 705 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 706 * @retval None 707 */ 708 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 709 710 /** 711 * @brief Disable the SDMMC device interrupt. 712 * @param __INSTANCE__ : Pointer to SDMMC register base 713 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. 714 * This parameter can be one or a combination of the following values: 715 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 716 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 717 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 718 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 719 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 720 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 721 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 722 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 723 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 724 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 725 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 726 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 727 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 728 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 729 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 730 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 731 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 732 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 733 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 734 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 735 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 736 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 737 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 738 * @retval None 739 */ 740 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 741 742 /** 743 * @brief Checks whether the specified SDMMC flag is set or not. 744 * @param __INSTANCE__ : Pointer to SDMMC register base 745 * @param __FLAG__: specifies the flag to check. 746 * This parameter can be one of the following values: 747 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 748 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 749 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 750 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 751 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 752 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 753 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 754 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 755 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 756 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 757 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 758 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 759 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 760 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 761 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 762 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 763 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 764 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 765 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 766 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 767 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 768 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 769 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 770 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 771 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 772 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 773 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 774 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 775 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 776 * @retval The new state of SDMMC_FLAG (SET or RESET). 777 */ 778 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 779 780 781 /** 782 * @brief Clears the SDMMC pending flags. 783 * @param __INSTANCE__ : Pointer to SDMMC register base 784 * @param __FLAG__: specifies the flag to clear. 785 * This parameter can be one or a combination of the following values: 786 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 787 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 788 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 789 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 790 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 791 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 792 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 793 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 794 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 795 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 796 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 797 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 798 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 799 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 800 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 801 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 802 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 803 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 804 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 805 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 806 * @retval None 807 */ 808 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 809 810 /** 811 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 812 * @param __INSTANCE__ : Pointer to SDMMC register base 813 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 814 * This parameter can be one of the following values: 815 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 816 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 817 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 818 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 819 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 820 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 821 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 822 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 823 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 824 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 825 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 826 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 827 * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt 828 * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt 829 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 830 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 831 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 832 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 833 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 834 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 835 * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 836 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 837 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 838 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 839 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 840 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 841 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 842 * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt 843 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 844 * @retval The new state of SDMMC_IT (SET or RESET). 845 */ 846 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 847 848 /** 849 * @brief Clears the SDMMC's interrupt pending bits. 850 * @param __INSTANCE__ : Pointer to SDMMC register base 851 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 852 * This parameter can be one or a combination of the following values: 853 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 854 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 855 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 856 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 857 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 858 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 859 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 860 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 861 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 862 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 863 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 864 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 865 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 866 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 867 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 868 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 869 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 870 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 871 * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt 872 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 873 * @retval None 874 */ 875 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 876 877 /** 878 * @brief Enable Start the SD I/O Read Wait operation. 879 * @param __INSTANCE__ : Pointer to SDMMC register base 880 * @retval None 881 */ 882 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 883 884 /** 885 * @brief Disable Start the SD I/O Read Wait operations. 886 * @param __INSTANCE__ : Pointer to SDMMC register base 887 * @retval None 888 */ 889 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 890 891 /** 892 * @brief Enable Start the SD I/O Read Wait operation. 893 * @param __INSTANCE__ : Pointer to SDMMC register base 894 * @retval None 895 */ 896 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 897 898 /** 899 * @brief Disable Stop the SD I/O Read Wait operations. 900 * @param __INSTANCE__ : Pointer to SDMMC register base 901 * @retval None 902 */ 903 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 904 905 /** 906 * @brief Enable the SD I/O Mode Operation. 907 * @param __INSTANCE__ : Pointer to SDMMC register base 908 * @retval None 909 */ 910 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 911 912 /** 913 * @brief Disable the SD I/O Mode Operation. 914 * @param __INSTANCE__ : Pointer to SDMMC register base 915 * @retval None 916 */ 917 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 918 919 /** 920 * @brief Enable the SD I/O Suspend command sending. 921 * @param __INSTANCE__ : Pointer to SDMMC register base 922 * @retval None 923 */ 924 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 925 926 /** 927 * @brief Disable the SD I/O Suspend command sending. 928 * @param __INSTANCE__ : Pointer to SDMMC register base 929 * @retval None 930 */ 931 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 932 933 /** 934 * @brief Enable the CMDTRANS mode. 935 * @param __INSTANCE__ : Pointer to SDMMC register base 936 * @retval None 937 */ 938 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 939 940 /** 941 * @brief Disable the CMDTRANS mode. 942 * @param __INSTANCE__ : Pointer to SDMMC register base 943 * @retval None 944 */ 945 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 946 947 /** 948 * @brief Enable the CMDSTOP mode. 949 * @param __INSTANCE__ : Pointer to SDMMC register base 950 * @retval None 951 */ 952 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 953 954 /** 955 * @brief Disable the CMDSTOP mode. 956 * @param __INSTANCE__ : Pointer to SDMMC register base 957 * @retval None 958 */ 959 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 960 961 /** 962 * @} 963 */ 964 965 /** 966 * @} 967 */ 968 969 /* Exported functions --------------------------------------------------------*/ 970 /** @addtogroup SDMMC_LL_Exported_Functions 971 * @{ 972 */ 973 974 /* Initialization/de-initialization functions **********************************/ 975 /** @addtogroup HAL_SDMMC_LL_Group1 976 * @{ 977 */ 978 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 979 /** 980 * @} 981 */ 982 983 /* I/O operation functions *****************************************************/ 984 /** @addtogroup HAL_SDMMC_LL_Group2 985 * @{ 986 */ 987 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 988 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 989 /** 990 * @} 991 */ 992 993 /* Peripheral Control functions ************************************************/ 994 /** @addtogroup HAL_SDMMC_LL_Group3 995 * @{ 996 */ 997 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 998 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 999 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1000 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1001 1002 /* Command path state machine (CPSM) management functions */ 1003 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1004 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1005 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1006 1007 /* Data path state machine (DPSM) management functions */ 1008 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 1009 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1010 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1011 1012 /* SDMMC Cards mode management functions */ 1013 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1014 1015 /* SDMMC Commands management functions */ 1016 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1017 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1018 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1019 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1020 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1021 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1022 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1023 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1024 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1025 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); 1026 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1027 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 1028 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1029 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1030 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1031 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1032 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1033 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1034 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1035 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1036 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1037 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1038 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1039 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1040 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1041 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1042 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1043 1044 /** 1045 * @} 1046 */ 1047 1048 /** 1049 * @} 1050 */ 1051 1052 /** 1053 * @} 1054 */ 1055 1056 /** 1057 * @} 1058 */ 1059 1060 /** 1061 * @} 1062 */ 1063 1064 /** 1065 * @} 1066 */ 1067 #ifdef __cplusplus 1068 } 1069 #endif 1070 1071 #endif /* STM32MP1xx_LL_SDMMC_H */ 1072 1073 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1074
