1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_PWR_H
21 #define STM32MP1xx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
44 * @{
45 */
46
47 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
48 * @brief Flags defines which can be used with LL_PWR_WriteReg function
49 * @{
50 */
51 /* Wake-Up Pins PWR register offsets */
52 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
53 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
54 /**
55 * @}
56 */
57 /**
58 * @}
59 */
60 /* Private macros ------------------------------------------------------------*/
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
64 * @{
65 */
66
67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
68 * @brief Flags defines which can be used with LL_PWR_WriteReg function
69 * @{
70 */
71 #define LL_PWR_FLAG_CPU_CSSF PWR_MCUCR_CSSF /*!< Clear MCU STANDBY, STOP flags */
72 #define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear WKUP pin 6 */
73 #define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear WKUP pin 5 */
74 #define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear WKUP pin 4 */
75 #define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear WKUP pin 3 */
76 #define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear WKUP pin 2 */
77 #define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear WKUP pin 1 */
78 /**
79 * @}
80 */
81
82 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
83 * @brief Flags defines which can be used with LL_PWR_ReadReg function
84 * @{
85 */
86 #define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog Voltage Detect Output */
87 #define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Power voltage detector output flag */
88
89 #define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */
90 #define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */
91 #define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */
92 #define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */
93 #define LL_PWR_FLAG_RRRDY PWR_CR2_RRRDY /*!< Retention Regulator ready flag */
94 #define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */
95
96 #define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */
97 #define LL_PWR_FLAG_R18RDY PWR_CR3_REG18RDY /*!< 1V8 regulator supply ready */
98 #define LL_PWR_FLAG_R11RDY PWR_CR3_REG11RDY /*!< 1V1 regulator supply ready */
99
100 #define LL_PWR_FLAG_CPU_SBF PWR_MCUCR_SBF /*!< MCU System STANDBY Flag */
101 #define LL_PWR_FLAG_CPU_STOPF PWR_MCUCR_STOPF /*!< MCU STOP Flag */
102
103 #define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup Pin Flag 6 */
104 #define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup Pin Flag 5 */
105 #define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup Pin Flag 4 */
106 #define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup Pin Flag 3 */
107 #define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup Pin Flag 2 */
108 #define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup Pin Flag 1 */
109 /**
110 * @}
111 */
112
113 /** @defgroup PWR_LL_EC_MODE_PWR Power mode
114 * @{
115 */
116 #define LL_PWR_MCU_MODE_STOP 0x00000000U /*!< Keep STOP mode when MCU enters to CSTOP */
117 #define LL_PWR_MCU_MODE_STANDBY PWR_MCUCR_PDDS /*!< Allow STANDBY mode when MCU enters to CSTOP */
118 /**
119 * @}
120 */
121
122 /** @defgroup PWR_LL_EC_PVDLEVEL Programmable Voltage Detector Level
123 * @{
124 */
125 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */
126 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */
127 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */
128 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */
129 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */
130 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */
131 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */
132 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
133 /**
134 * @}
135 */
136
137 /** @defgroup PWR_LL_EC_AVDLEVEL Analog Voltage Detector Level
138 * @{
139 */
140 #define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */
141 #define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */
142 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */
143 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */
144
145 /**
146 * @}
147 */
148
149 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR VBAT charging resistor selection
150 * @{
151 */
152 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge VBAT through a 5 kO resistor */
153 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge VBAT through a 1.5 kO resistor */
154 /**
155 * @}
156 */
157
158 /** @defgroup PWR_LL_EC_WAKEUP_PIN MCU Wakeup Pins
159 * @{
160 */
161 #define LL_PWR_WAKEUP_PIN1 PWR_MCUWKUPENR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
162 #define LL_PWR_WAKEUP_PIN2 PWR_MCUWKUPENR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
163 #define LL_PWR_WAKEUP_PIN3 PWR_MCUWKUPENR_WKUPEN3 /*!< Wake-Up pin 3 : PC1 */
164 #define LL_PWR_WAKEUP_PIN4 PWR_MCUWKUPENR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */
165 #define LL_PWR_WAKEUP_PIN5 PWR_MCUWKUPENR_WKUPEN5 /*!< Wake-Up pin 5 : PI8 */
166 #define LL_PWR_WAKEUP_PIN6 PWR_MCUWKUPENR_WKUPEN6 /*!< Wake-Up pin 6 : PI11 */
167 /**
168 * @}
169 */
170
171 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
172 * @{
173 */
174 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
175 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
176 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
177 /**
178 * @}
179 */
180
181 /**
182 * @}
183 */
184 /* Exported macro ------------------------------------------------------------*/
185 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
186 * @{
187 */
188
189 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
190 * @{
191 */
192
193 /**
194 * @brief Write a value in PWR register
195 * @param __REG__ Register to be written
196 * @param __VALUE__ Value to be written in the register
197 * @retval None
198 */
199 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
200
201 /**
202 * @brief Read a value in PWR register
203 * @param __REG__ Register to be read
204 * @retval Register value
205 */
206 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
207 /**
208 * @}
209 */
210
211 /**
212 * @}
213 */
214 /* Exported functions --------------------------------------------------------*/
215 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
216 * @{
217 */
218
219 /** @defgroup PWR_LL_EF_Configuration Configuration
220 * @{
221 */
222
223 /**
224 * @brief Enable Programable Voltage Detector
225 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD
226 * @retval None
227 */
LL_PWR_EnablePVD(void)228 __STATIC_INLINE void LL_PWR_EnablePVD(void)
229 {
230 SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
231 }
232
233 /**
234 * @brief Disable Programable Voltage Detector
235 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD
236 * @retval None
237 */
LL_PWR_DisablePVD(void)238 __STATIC_INLINE void LL_PWR_DisablePVD(void)
239 {
240 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
241 }
242
243 /**
244 * @brief Check if Programable Voltage Detector is enabled
245 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
246 * @retval State of bit (1 or 0).
247 */
LL_PWR_IsEnabledPVD(void)248 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
249 {
250 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
251 }
252
253 /**
254 * @brief Configure the voltage threshold detected by the Programable Voltage Detector
255 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
256 * @param PVDLevel This parameter can be one of the following values:
257 * @arg @ref LL_PWR_PVDLEVEL_0
258 * @arg @ref LL_PWR_PVDLEVEL_1
259 * @arg @ref LL_PWR_PVDLEVEL_2
260 * @arg @ref LL_PWR_PVDLEVEL_3
261 * @arg @ref LL_PWR_PVDLEVEL_4
262 * @arg @ref LL_PWR_PVDLEVEL_5
263 * @arg @ref LL_PWR_PVDLEVEL_6
264 * @arg @ref LL_PWR_PVDLEVEL_7
265 * @retval None
266 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)267 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
268 {
269 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
270 }
271
272 /**
273 * @brief Get the voltage threshold detection
274 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
275 * @retval Returned value can be one of the following values:
276 * @arg @ref LL_PWR_PVDLEVEL_0
277 * @arg @ref LL_PWR_PVDLEVEL_1
278 * @arg @ref LL_PWR_PVDLEVEL_2
279 * @arg @ref LL_PWR_PVDLEVEL_3
280 * @arg @ref LL_PWR_PVDLEVEL_4
281 * @arg @ref LL_PWR_PVDLEVEL_5
282 * @arg @ref LL_PWR_PVDLEVEL_6
283 * @arg @ref LL_PWR_PVDLEVEL_7
284 */
LL_PWR_GetPVDLevel(void)285 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
286 {
287 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
288 }
289
290 /**
291 * @brief Enable access to the backup domain
292 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
293 * @retval None
294 */
LL_PWR_EnableBkUpAccess(void)295 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
296 {
297 SET_BIT(PWR->CR1, PWR_CR1_DBP);
298 }
299
300 /**
301 * @brief Disable access to the backup domain
302 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
303 * @retval None
304 */
LL_PWR_DisableBkUpAccess(void)305 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
306 {
307 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
308 }
309
310 /**
311 * @brief Check if the backup domain is enabled
312 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
313 * @retval State of bit (1 or 0).
314 */
LL_PWR_IsEnabledBkUpAccess(void)315 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
316 {
317 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
318 }
319
320 /**
321 * @brief Enable Analog Power Voltage Detector
322 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD
323 * @retval None
324 */
LL_PWR_EnableAVD(void)325 __STATIC_INLINE void LL_PWR_EnableAVD(void)
326 {
327 SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
328 }
329
330 /**
331 * @brief Disable Analog Power Voltage Detector
332 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD
333 * @retval None
334 */
LL_PWR_DisableAVD(void)335 __STATIC_INLINE void LL_PWR_DisableAVD(void)
336 {
337 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
338 }
339
340 /**
341 * @brief Check if Analog Power Voltage Detector is enabled
342 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
343 * @retval State of bit (1 or 0).
344 */
LL_PWR_IsEnabledAVD(void)345 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
346 {
347 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
348 }
349
350 /**
351 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
352 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel
353 * @param AVDLevel This parameter can be one of the following values:
354 * @arg @ref LL_PWR_AVDLEVEL_0
355 * @arg @ref LL_PWR_AVDLEVEL_1
356 * @arg @ref LL_PWR_AVDLEVEL_2
357 * @arg @ref LL_PWR_AVDLEVEL_3
358 * @retval None
359 */
LL_PWR_SetAVDLevel(uint32_t AVDLevel)360 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
361 {
362 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
363 }
364
365 /**
366 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
367 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
368 * @retval Returned value can be one of the following values:
369 * @arg @ref LL_PWR_AVDLEVEL_0
370 * @arg @ref LL_PWR_AVDLEVEL_1
371 * @arg @ref LL_PWR_AVDLEVEL_2
372 * @arg @ref LL_PWR_AVDLEVEL_3
373 */
LL_PWR_GetAVDLevel(void)374 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
375 {
376 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
377 }
378
379 /**
380 * @brief Enable Backup Regulator
381 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
382 * @note When set, the Backup Regulator (used to maintain backup SRAM content
383 * in Standby and VBAT modes) is enabled. If BRE is reset, the backup
384 * Regulator is switched off. The backup SRAM can still be used in Run
385 * mode and Stop mode but its content will be lost in the Standby and VBAT
386 * modes. Once set, the application must wait that the Backup Regulator
387 * Ready flag (BRR) is set to indicate that the data written into the RAM
388 * will be maintained in the Standby and VBAT modes.
389 * @retval None
390 */
LL_PWR_EnableBkUpRegulator(void)391 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
392 {
393 SET_BIT(PWR->CR2, PWR_CR2_BREN);
394 }
395
396 /**
397 * @brief Disable Backup Regulator
398 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
399 * @retval None
400 */
LL_PWR_DisableBkUpRegulator(void)401 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
402 {
403 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
404 }
405
406 /**
407 * @brief Check if the backup Regulator is enabled
408 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
409 * @retval State of bit (1 or 0).
410 */
LL_PWR_IsEnabledBkUpRegulator(void)411 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
412 {
413 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
414 }
415
416 /**
417 * @brief Enable Retention Regulator
418 * @rmtoll CR2 RREN LL_PWR_EnableRetRegulator
419 * @note When set, the retention regulator (used to maintain retention RAM
420 * content in Standby and VBAT modes) is enabled.
421 * If RREN is reset, the Retention Regulator is switched off. The retention
422 * RAM can still be used in Run mode and Stop mode but its content is lost
423 * in the Standby and VBAT modes.
424 * Once set, the application must wait that the retention regulator Ready
425 * flag (RRRDY) is set to indicate that the data written into the SRAM is
426 * maintained in the Standby and VBAT modes.
427 * @retval None
428 */
LL_PWR_EnableRetRegulator(void)429 __STATIC_INLINE void LL_PWR_EnableRetRegulator(void)
430 {
431 SET_BIT(PWR->CR2, PWR_CR2_RREN);
432 }
433
434 /**
435 * @brief Disable Retention Regulator
436 * @rmtoll CR2 RREN LL_PWR_DisableRetRegulator
437 * @retval None
438 */
LL_PWR_DisableRetRegulator(void)439 __STATIC_INLINE void LL_PWR_DisableRetRegulator(void)
440 {
441 CLEAR_BIT(PWR->CR2, PWR_CR2_RREN);
442 }
443
444 /**
445 * @brief Check if the Retention Regulator is enabled
446 * @rmtoll CR2 RREN LL_PWR_IsEnabledRetRegulator
447 * @retval State of bit (1 or 0).
448 */
LL_PWR_IsEnabledRetRegulator(void)449 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRetRegulator(void)
450 {
451 return ((READ_BIT(PWR->CR2, PWR_CR2_RREN) == (PWR_CR2_RREN)) ? 1UL : 0UL);
452 }
453
454 /**
455 * @brief Enable VBAT and Temperature monitoring
456 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
457 * @retval None
458 */
LL_PWR_EnableMonitoring(void)459 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
460 {
461 SET_BIT(PWR->CR2, PWR_CR2_MONEN);
462 }
463
464 /**
465 * @brief Disable VBAT and Temperature monitoring
466 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
467 * @retval None
468 */
LL_PWR_DisableMonitoring(void)469 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
470 {
471 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
472 }
473
474 /**
475 * @brief Check if the VBAT and Temperature monitoring is enabled
476 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
477 * @retval State of bit (1 or 0).
478 */
LL_PWR_IsEnabledMonitoring(void)479 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
480 {
481 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
482 }
483
484 /**
485 * @brief Enable battery charging
486 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
487 * @retval None
488 */
LL_PWR_EnableBatteryCharging(void)489 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
490 {
491 SET_BIT(PWR->CR3, PWR_CR3_VBE);
492 }
493
494 /**
495 * @brief Disable battery charging
496 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
497 * @retval None
498 */
LL_PWR_DisableBatteryCharging(void)499 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
500 {
501 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
502 }
503
504 /**
505 * @brief Check if battery charging is enabled
506 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
507 * @retval State of bit (1 or 0).
508 */
LL_PWR_IsEnabledBatteryCharging(void)509 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
510 {
511 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
512 }
513
514 /**
515 * @brief Set the Battery charge resistor impedance
516 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
517 * @param Resistor This parameter can be one of the following values:
518 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
519 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
520 * @retval None
521 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)522 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
523 {
524 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
525 }
526
527 /**
528 * @brief Get the Battery charge resistor impedance
529 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
530 * @retval Returned value can be one of the following values:
531 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
532 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
533 */
LL_PWR_GetBattChargResistor(void)534 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
535 {
536 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
537 }
538
539 /**
540 * @brief Enable 1V1 regulator
541 * @rmtoll CR3 REG11EN LL_PWR_Enable1V1Regulator
542 * @retval None
543 */
LL_PWR_Enable1V1Regulator(void)544 __STATIC_INLINE void LL_PWR_Enable1V1Regulator(void)
545 {
546 SET_BIT(PWR->CR3, PWR_CR3_REG11EN);
547 }
548
549 /**
550 * @brief Disable the 1V1 regulator
551 * @rmtoll CR3 REG11EN LL_PWR_Disable1V1Regulator
552 * @retval None
553 */
LL_PWR_Disable1V1Regulator(void)554 __STATIC_INLINE void LL_PWR_Disable1V1Regulator(void)
555 {
556 CLEAR_BIT(PWR->CR3, PWR_CR3_REG11EN);
557 }
558
559 /**
560 * @brief Check if the 1V1 regulator is enabled
561 * @rmtoll CR3 PWR_CR3_REG11EN LL_PWR_IsEnabled1V1Regulator
562 * @retval State of bit (1 or 0).
563 */
LL_PWR_IsEnabled1V1Regulator(void)564 __STATIC_INLINE uint32_t LL_PWR_IsEnabled1V1Regulator(void)
565 {
566 return ((READ_BIT(PWR->CR3, PWR_CR3_REG11EN) == (PWR_CR3_REG11EN)) ? 1UL : 0UL);
567 }
568
569 /**
570 * @brief Enable 1V8 regulator
571 * @rmtoll CR3 REG18EN LL_PWR_Enable1V8Regulator
572 * @retval None
573 */
LL_PWR_Enable1V8Regulator(void)574 __STATIC_INLINE void LL_PWR_Enable1V8Regulator(void)
575 {
576 SET_BIT(PWR->CR3, PWR_CR3_REG18EN);
577 }
578
579 /**
580 * @brief Disable the 1V8 regulator
581 * @rmtoll CR3 REG18EN LL_PWR_Disable1V8Regulator
582 * @retval None
583 */
LL_PWR_Disable1V8Regulator(void)584 __STATIC_INLINE void LL_PWR_Disable1V8Regulator(void)
585 {
586 CLEAR_BIT(PWR->CR3, PWR_CR3_REG18EN);
587 }
588
589 /**
590 * @brief Check if the 1V8 regulator is enabled
591 * @rmtoll CR3 PWR_CR3_REG18EN LL_PWR_IsEnabled1V8Regulator
592 * @retval State of bit (1 or 0).
593 */
LL_PWR_IsEnabled1V8Regulator(void)594 __STATIC_INLINE uint32_t LL_PWR_IsEnabled1V8Regulator(void)
595 {
596 return ((READ_BIT(PWR->CR3, PWR_CR3_REG18EN) == (PWR_CR3_REG18EN)) ? 1UL : 0UL);
597 }
598
599 /**
600 * @brief Enable the USB voltage detector
601 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
602 * @retval None
603 */
LL_PWR_EnableUSBVoltageDetector(void)604 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
605 {
606 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
607 }
608
609 /**
610 * @brief Disable the USB voltage detector
611 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
612 * @retval None
613 */
LL_PWR_DisableUSBVoltageDetector(void)614 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
615 {
616 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
617 }
618
619 /**
620 * @brief Check if the USB voltage detector is enabled
621 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
622 * @retval State of bit (1 or 0).
623 */
LL_PWR_IsEnabledUSBVoltageDetector(void)624 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
625 {
626 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
627 }
628
629 /**
630 * @brief Set mode when MCU enters enters deepsleep (CSTOP)
631 * @rmtoll MCUCR PDDS LL_PWR_CPU_SetD1PowerMode\n
632 * @param PDMode This parameter can be one of the following values:
633 * @arg @ref LL_PWR_MCU_MODE_STOP
634 * @arg @ref LL_PWR_MCU_MODE_STANDBY
635 * @retval None
636 */
LL_PWR_MCU_SetPowerMode(uint32_t PDMode)637 __STATIC_INLINE void LL_PWR_MCU_SetPowerMode(uint32_t PDMode)
638 {
639 MODIFY_REG(PWR->MCUCR, PWR_MCUCR_PDDS, PDMode);
640 }
641
642 /**
643 * @brief Get the mode when MCU enters enters deepsleep (CSTOP)
644 * @rmtoll MCUCR PDDS LL_PWR_MCU_GetPowerMode\n
645 * @retval Returned value can be one of the following values:
646 * @arg @ref LL_PWR_MCU_MODE_STOP
647 * @arg @ref LL_PWR_MCU_MODE_STANDBY
648 */
LL_PWR_MCU_GetPowerMode(void)649 __STATIC_INLINE uint32_t LL_PWR_MCU_GetPowerMode(void)
650 {
651 return (uint32_t)(READ_BIT(PWR->MCUCR, PWR_MCUCR_PDDS));
652 }
653
654 /**
655 * @brief Enable the WakeUp PINx functionality
656 * @rmtoll MCUWKUPENR WKUPEN1 LL_PWR_EnableWakeUpPin\n
657 * MCUWKUPENR WKUPEN2 LL_PWR_EnableWakeUpPin\n
658 * MCUWKUPENR WKUPEN3 LL_PWR_EnableWakeUpPin\n
659 * MCUWKUPENR WKUPEN4 LL_PWR_EnableWakeUpPin\n
660 * MCUWKUPENR WKUPEN5 LL_PWR_EnableWakeUpPin\n
661 * MCUWKUPENR WKUPEN6 LL_PWR_EnableWakeUpPin
662 * @param WakeUpPin This parameter can be one of the following values:
663 * @arg @ref LL_PWR_WAKEUP_PIN1
664 * @arg @ref LL_PWR_WAKEUP_PIN2
665 * @arg @ref LL_PWR_WAKEUP_PIN3
666 * @arg @ref LL_PWR_WAKEUP_PIN4
667 * @arg @ref LL_PWR_WAKEUP_PIN5
668 * @arg @ref LL_PWR_WAKEUP_PIN6
669 * @retval None
670 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)671 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
672 {
673 SET_BIT(PWR->MCUWKUPENR, WakeUpPin);
674 }
675
676 /**
677 * @brief Disable the WakeUp PINx functionality
678 * @rmtoll MCUWKUPENR WKUPEN1 LL_PWR_DisableWakeUpPin\n
679 * MCUWKUPENR WKUPEN2 LL_PWR_DisableWakeUpPin\n
680 * MCUWKUPENR WKUPEN3 LL_PWR_DisableWakeUpPin\n
681 * MCUWKUPENR WKUPEN4 LL_PWR_DisableWakeUpPin\n
682 * MCUWKUPENR WKUPEN5 LL_PWR_DisableWakeUpPin\n
683 * MCUWKUPENR WKUPEN6 LL_PWR_DisableWakeUpPin
684 * @param WakeUpPin This parameter can be one of the following values:
685 * @arg @ref LL_PWR_WAKEUP_PIN1
686 * @arg @ref LL_PWR_WAKEUP_PIN2
687 * @arg @ref LL_PWR_WAKEUP_PIN3
688 * @arg @ref LL_PWR_WAKEUP_PIN4
689 * @arg @ref LL_PWR_WAKEUP_PIN5
690 * @arg @ref LL_PWR_WAKEUP_PIN6
691 * @retval None
692 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)693 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
694 {
695 CLEAR_BIT(PWR->MCUWKUPENR, WakeUpPin);
696 }
697
698 /**
699 * @brief Check if the WakeUp PINx functionality is enabled
700 * @rmtoll MCUWKUPENR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
701 * MCUWKUPENR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
702 * MCUWKUPENR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
703 * MCUWKUPENR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
704 * MCUWKUPENR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
705 * MCUWKUPENR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
706 * @param WakeUpPin This parameter can be one of the following values:
707 * @arg @ref LL_PWR_WAKEUP_PIN1
708 * @arg @ref LL_PWR_WAKEUP_PIN2
709 * @arg @ref LL_PWR_WAKEUP_PIN3
710 * @arg @ref LL_PWR_WAKEUP_PIN4
711 * @arg @ref LL_PWR_WAKEUP_PIN5
712 * @arg @ref LL_PWR_WAKEUP_PIN6
713 * @retval State of bit (1 or 0).
714 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)715 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
716 {
717 return ((READ_BIT(PWR->MCUWKUPENR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
718 }
719
720 /**
721 * @brief Set the Wake-Up pin polarity low for the event detection
722 * @rmtoll WKUPCR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
723 * WKUPCR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
724 * WKUPCR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
725 * WKUPCR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
726 * WKUPCR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
727 * WKUPCR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
728 * @param WakeUpPin This parameter can be one of the following values:
729 * @arg @ref LL_PWR_WAKEUP_PIN1
730 * @arg @ref LL_PWR_WAKEUP_PIN2
731 * @arg @ref LL_PWR_WAKEUP_PIN3
732 * @arg @ref LL_PWR_WAKEUP_PIN4
733 * @arg @ref LL_PWR_WAKEUP_PIN5
734 * @arg @ref LL_PWR_WAKEUP_PIN6
735 * @retval None
736 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)737 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
738 {
739 SET_BIT(PWR->WKUPCR, (WakeUpPin << PWR_WKUPCR_WKUPP_Pos));
740 }
741
742 /**
743 * @brief Set the Wake-Up pin polarity high for the event detection
744 * @rmtoll WKUPCR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
745 * WKUPCR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
746 * WKUPCR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
747 * WKUPCR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
748 * WKUPCR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
749 * WKUPCR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
750 * @param WakeUpPin This parameter can be one of the following values:
751 * @arg @ref LL_PWR_WAKEUP_PIN1
752 * @arg @ref LL_PWR_WAKEUP_PIN2
753 * @arg @ref LL_PWR_WAKEUP_PIN3
754 * @arg @ref LL_PWR_WAKEUP_PIN4
755 * @arg @ref LL_PWR_WAKEUP_PIN5
756 * @arg @ref LL_PWR_WAKEUP_PIN6
757 * @retval None
758 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)759 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
760 {
761 CLEAR_BIT(PWR->WKUPCR, (WakeUpPin << PWR_WKUPCR_WKUPP_Pos));
762 }
763
764 /**
765 * @brief Get the Wake-Up pin polarity for the event detection
766 * @rmtoll WKUPCR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
767 * WKUPCR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
768 * WKUPCR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
769 * WKUPCR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
770 * WKUPCR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
771 * WKUPCR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
772 * @param WakeUpPin This parameter can be one of the following values:
773 * @arg @ref LL_PWR_WAKEUP_PIN1
774 * @arg @ref LL_PWR_WAKEUP_PIN2
775 * @arg @ref LL_PWR_WAKEUP_PIN3
776 * @arg @ref LL_PWR_WAKEUP_PIN4
777 * @arg @ref LL_PWR_WAKEUP_PIN5
778 * @arg @ref LL_PWR_WAKEUP_PIN6
779 * @retval State of bit (1 or 0).
780 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)781 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
782 {
783 return ((READ_BIT(PWR->WKUPCR, (WakeUpPin << PWR_WKUPCR_WKUPP_Pos)) == (WakeUpPin << PWR_WKUPCR_WKUPP_Pos)) ? 1UL : 0UL);
784 }
785
786 /**
787 * @brief Set the Wake-Up pin Pull None
788 * @rmtoll WKUPCR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
789 * WKUPCR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
790 * WKUPCR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
791 * WKUPCR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
792 * WKUPCR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
793 * WKUPCR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
794 * @param WakeUpPin This parameter can be one of the following values:
795 * @arg @ref LL_PWR_WAKEUP_PIN1
796 * @arg @ref LL_PWR_WAKEUP_PIN2
797 * @arg @ref LL_PWR_WAKEUP_PIN3
798 * @arg @ref LL_PWR_WAKEUP_PIN4
799 * @arg @ref LL_PWR_WAKEUP_PIN5
800 * @arg @ref LL_PWR_WAKEUP_PIN6
801 * @retval None
802 */
LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)803 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
804 {
805 MODIFY_REG(PWR->WKUPCR, \
806 (PWR_WKUPCR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
807 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPCR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
808 }
809
810 /**
811 * @brief Set the Wake-Up pin Pull Up
812 * @rmtoll WKUPCR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
813 * WKUPCR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
814 * WKUPCR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
815 * WKUPCR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
816 * WKUPCR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
817 * WKUPCR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
818 * @param WakeUpPin This parameter can be one of the following values:
819 * @arg @ref LL_PWR_WAKEUP_PIN1
820 * @arg @ref LL_PWR_WAKEUP_PIN2
821 * @arg @ref LL_PWR_WAKEUP_PIN3
822 * @arg @ref LL_PWR_WAKEUP_PIN4
823 * @arg @ref LL_PWR_WAKEUP_PIN5
824 * @arg @ref LL_PWR_WAKEUP_PIN6
825 * @retval None
826 */
LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)827 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
828 {
829 MODIFY_REG(PWR->WKUPCR, \
830 (PWR_WKUPCR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
831 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPCR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
832 }
833
834 /**
835 * @brief Set the Wake-Up pin Pull Down
836 * @rmtoll WKUPCR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
837 * WKUPCR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
838 * WKUPCR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
839 * WKUPCR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
840 * WKUPCR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
841 * WKUPCR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
842 * @param WakeUpPin This parameter can be one of the following values:
843 * @arg @ref LL_PWR_WAKEUP_PIN1
844 * @arg @ref LL_PWR_WAKEUP_PIN2
845 * @arg @ref LL_PWR_WAKEUP_PIN3
846 * @arg @ref LL_PWR_WAKEUP_PIN4
847 * @arg @ref LL_PWR_WAKEUP_PIN5
848 * @arg @ref LL_PWR_WAKEUP_PIN6
849 * @retval None
850 */
LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)851 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
852 {
853 MODIFY_REG(PWR->WKUPCR, \
854 (PWR_WKUPCR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
855 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPCR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
856 }
857
858 /**
859 * @brief Get the Wake-Up pin pull
860 * @rmtoll WKUPCR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
861 * WKUPCR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
862 * WKUPCR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
863 * WKUPCR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
864 * WKUPCR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
865 * WKUPCR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
866 * @param WakeUpPin This parameter can be one of the following values:
867 * @arg @ref LL_PWR_WAKEUP_PIN1
868 * @arg @ref LL_PWR_WAKEUP_PIN2
869 * @arg @ref LL_PWR_WAKEUP_PIN3
870 * @arg @ref LL_PWR_WAKEUP_PIN4
871 * @arg @ref LL_PWR_WAKEUP_PIN5
872 * @arg @ref LL_PWR_WAKEUP_PIN6
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
875 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
876 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
877 */
LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)878 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
879 {
880 register uint32_t regValue = READ_BIT(PWR->WKUPCR, (PWR_WKUPCR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
881
882 return (uint32_t)(regValue >> ((PWR_WKUPCR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
883 }
884
885 /**
886 * @}
887 */
888
889 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
890 * @{
891 */
892
893 /**
894 * @brief Indicate whether VDD voltage is below the selected PVD threshold
895 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
896 * @retval State of bit (1 or 0).
897 */
LL_PWR_IsActiveFlag_PVDO(void)898 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
899 {
900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
901 }
902
903 /**
904 * @brief Indicate whether VDDA voltage is below the selected AVD threshold
905 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
906 * @retval State of bit (1 or 0).
907 */
LL_PWR_IsActiveFlag_AVDO(void)908 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
909 {
910 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
911 }
912
913 /**
914 * @brief Get Backup Regulator ready Flag
915 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
916 * @retval State of bit (1 or 0).
917 */
LL_PWR_IsActiveFlag_BRR(void)918 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
919 {
920 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
921 }
922
923 /**
924 * @brief Get Retention Regulator ready Flag
925 * @rmtoll CR2 RRRDY LL_PWR_IsActiveFlag_RRR
926 * @retval State of bit (1 or 0).
927 */
LL_PWR_IsActiveFlag_RRR(void)928 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RRR(void)
929 {
930 return ((READ_BIT(PWR->CR2, PWR_CR2_RRRDY) == (PWR_CR2_RRRDY)) ? 1UL : 0UL);
931 }
932
933 /**
934 * @brief Indicate whether the VBAT level is equal or below low threshold
935 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
936 * @retval State of bit (1 or 0).
937 */
LL_PWR_IsActiveFlag_VBATL(void)938 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
939 {
940 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
941 }
942
943 /**
944 * @brief Indicate whether the VBAT level is equal or above high threshold
945 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
946 * @retval State of bit (1 or 0).
947 */
LL_PWR_IsActiveFlag_VBATH(void)948 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
949 {
950 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
951 }
952
953 /**
954 * @brief Indicate whether the device temperature level is equal or below low threshold
955 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
956 * @retval State of bit (1 or 0).
957 */
LL_PWR_IsActiveFlag_TEMPL(void)958 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
959 {
960 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
961 }
962
963 /**
964 * @brief Indicate whether the CPU temperature level is equal or above high threshold
965 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
966 * @retval State of bit (1 or 0).
967 */
LL_PWR_IsActiveFlag_TEMPH(void)968 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
969 {
970 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
971 }
972
973 /**
974 * @brief Indicate whether the USB supply is ready or not
975 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
976 * @retval State of bit (1 or 0).
977 */
LL_PWR_IsActiveFlag_USB(void)978 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
979 {
980 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
981 }
982
983 /**
984 * @brief Indicate whether the 1V1 regulator is ready or not
985 * @rmtoll CR3 REG11RDY LL_PWR_IsActiveFlag_R1V1
986 * @retval State of bit (1 or 0).
987 */
LL_PWR_IsActiveFlag_R1V1(void)988 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_R1V1(void)
989 {
990 return ((READ_BIT(PWR->CR3, PWR_CR3_REG11RDY) == (PWR_CR3_REG11RDY)) ? 1UL : 0UL);
991 }
992
993 /**
994 * @brief Indicate whether the 1V8 regulator is ready or not
995 * @rmtoll CR3 REG18RDY LL_PWR_IsActiveFlag_R1V8
996 * @retval State of bit (1 or 0).
997 */
LL_PWR_IsActiveFlag_R1V8(void)998 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_R1V8(void)
999 {
1000 return ((READ_BIT(PWR->CR3, PWR_CR3_REG18RDY) == (PWR_CR3_REG18RDY)) ? 1UL : 0UL);
1001 }
1002
1003 /**
1004 * @brief Get MCU System Stop Flag
1005 * @rmtoll MCUCR STOPF LL_PWR_MCU_IsActiveFlag_STOP
1006 * @retval State of bit (1 or 0).
1007 */
LL_PWR_MCU_IsActiveFlag_STOP(void)1008 __STATIC_INLINE uint32_t LL_PWR_MCU_IsActiveFlag_STOP(void)
1009 {
1010 return ((READ_BIT(PWR->MCUCR, PWR_MCUCR_STOPF) == (PWR_MCUCR_STOPF)) ? 1UL : 0UL);
1011 }
1012
1013 /**
1014 * @brief Get MCU System Standby Flag
1015 * @rmtoll MCUCR SBF LL_PWR_MCU_IsActiveFlag_SB
1016 * @retval State of bit (1 or 0).
1017 */
LL_PWR_MCU_IsActiveFlag_SB(void)1018 __STATIC_INLINE uint32_t LL_PWR_MCU_IsActiveFlag_SB(void)
1019 {
1020 return ((READ_BIT(PWR->MCUCR, PWR_MCUCR_SBF) == (PWR_MCUCR_SBF)) ? 1UL : 0UL);
1021 }
1022
1023 /**
1024 * @brief Get Wake-up Flag 6
1025 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
1026 * @retval State of bit (1 or 0).
1027 */
LL_PWR_IsActiveFlag_WU6(void)1028 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
1029 {
1030 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
1031 }
1032
1033 /**
1034 * @brief Get Wake-up Flag 5
1035 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
1036 * @retval State of bit (1 or 0).
1037 */
LL_PWR_IsActiveFlag_WU5(void)1038 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1039 {
1040 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
1041 }
1042
1043 /**
1044 * @brief Get Wake-up Flag 4
1045 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
1046 * @retval State of bit (1 or 0).
1047 */
LL_PWR_IsActiveFlag_WU4(void)1048 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1049 {
1050 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
1051 }
1052
1053 /**
1054 * @brief Get Wake-up Flag 3
1055 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
1056 * @retval State of bit (1 or 0).
1057 */
LL_PWR_IsActiveFlag_WU3(void)1058 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1059 {
1060 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
1061 }
1062
1063 /**
1064 * @brief Get Wake-up Flag 2
1065 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
1066 * @retval State of bit (1 or 0).
1067 */
LL_PWR_IsActiveFlag_WU2(void)1068 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1069 {
1070 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
1071 }
1072
1073 /**
1074 * @brief Get Wake-up Flag 1
1075 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
1076 * @retval State of bit (1 or 0).
1077 */
LL_PWR_IsActiveFlag_WU1(void)1078 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1079 {
1080 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
1081 }
1082
1083 /**
1084 * @brief Clear MCU STANDBY and STOP flags
1085 * @rmtoll MCUCR CSSF LL_PWR_ClearFlag_CPU
1086 * @retval None
1087 */
LL_PWR_ClearFlag_MCU(void)1088 __STATIC_INLINE void LL_PWR_ClearFlag_MCU(void)
1089 {
1090 SET_BIT(PWR->MCUCR, PWR_MCUCR_CSSF);
1091 }
1092
1093 /**
1094 * @brief Clear Wake-up Flag 6
1095 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
1096 * @retval None
1097 */
LL_PWR_ClearFlag_WU6(void)1098 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
1099 {
1100 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
1101 }
1102
1103 /**
1104 * @brief Clear Wake-up Flag 5
1105 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
1106 * @retval None
1107 */
LL_PWR_ClearFlag_WU5(void)1108 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1109 {
1110 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
1111 }
1112
1113 /**
1114 * @brief Clear Wake-up Flag 4
1115 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
1116 * @retval None
1117 */
LL_PWR_ClearFlag_WU4(void)1118 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1119 {
1120 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
1121 }
1122
1123 /**
1124 * @brief Clear Wake-up Flag 3
1125 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
1126 * @retval None
1127 */
LL_PWR_ClearFlag_WU3(void)1128 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1129 {
1130 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
1131 }
1132
1133 /**
1134 * @brief Clear Wake-up Flag 2
1135 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
1136 * @retval None
1137 */
LL_PWR_ClearFlag_WU2(void)1138 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1139 {
1140 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
1141 }
1142
1143 /**
1144 * @brief Clear Wake-up Flag 1
1145 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
1146 * @retval None
1147 */
LL_PWR_ClearFlag_WU1(void)1148 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1149 {
1150 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
1151 }
1152
1153 #if defined(USE_FULL_LL_DRIVER)
1154 /** @defgroup PWR_LL_EF_Init De-initialization function
1155 * @{
1156 */
1157 ErrorStatus LL_PWR_DeInit(void);
1158 /**
1159 * @}
1160 */
1161 #endif /* USE_FULL_LL_DRIVER */
1162
1163
1164 /**
1165 * @}
1166 */
1167
1168 /**
1169 * @}
1170 */
1171
1172 /**
1173 * @}
1174 */
1175
1176 #endif /* defined(PWR) */
1177
1178 /**
1179 * @}
1180 */
1181
1182 #ifdef __cplusplus
1183 }
1184 #endif
1185
1186 #endif /* STM32MP1xx_LL_PWR_H */
1187
