1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_LPTIM_H
21 #define STM32MP1xx_LL_LPTIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)
35
36 /** @defgroup LPTIM_LL LPTIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44
45 /* Private macros ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
48 * @{
49 */
50 /**
51 * @}
52 */
53 #endif /*USE_FULL_LL_DRIVER*/
54
55 /* Exported types ------------------------------------------------------------*/
56 #if defined(USE_FULL_LL_DRIVER)
57 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
58 * @{
59 */
60
61 /**
62 * @brief LPTIM Init structure definition
63 */
64 typedef struct
65 {
66 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
67 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
68
69 This feature can be modified afterwards using unitary
70 function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary
76 function @ref LL_LPTIM_SetPrescaler().*/
77
78 uint32_t Waveform; /*!< Specifies the waveform shape.
79 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
80
81 This feature can be modified afterwards using unitary
82 function @ref LL_LPTIM_ConfigOutput().*/
83
84 uint32_t Polarity; /*!< Specifies waveform polarity.
85 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
86
87 This feature can be modified afterwards using unitary
88 function @ref LL_LPTIM_ConfigOutput().*/
89 } LL_LPTIM_InitTypeDef;
90
91 /**
92 * @}
93 */
94 #endif /* USE_FULL_LL_DRIVER */
95
96 /* Exported constants --------------------------------------------------------*/
97 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
98 * @{
99 */
100
101 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
102 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
103 * @{
104 */
105 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
106 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
107 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
108 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
109 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
110 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
111 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
112 /**
113 * @}
114 */
115
116 /** @defgroup LPTIM_LL_EC_IT IT Defines
117 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
118 * @{
119 */
120 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
121 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
122 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
123 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
124 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
125 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
126 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
127 /**
128 * @}
129 */
130
131 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
132 * @{
133 */
134 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
135 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
136 /**
137 * @}
138 */
139
140 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
141 * @{
142 */
143 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
144 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
145 /**
146 * @}
147 */
148
149 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
150 * @{
151 */
152 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
153 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
154 /**
155 * @}
156 */
157
158 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
159 * @{
160 */
161 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
162 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
163 /**
164 * @}
165 */
166
167 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
168 * @{
169 */
170 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
171 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
172 /**
173 * @}
174 */
175
176 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
177 * @{
178 */
179 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
180 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
181 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
182 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
183 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
184 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
185 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
186 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
187 /**
188 * @}
189 */
190
191 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
192 * @{
193 */
194 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
197 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
198 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
199 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
200 #define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!<External input trigger is connected to LPTIM2 output*/
201 #define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM3 output*/
202 #define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM4 output*/
203 #define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/
204 #define LL_LPTIM_TRIG_SOURCE_SAI1A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI1A output*/
205 #define LL_LPTIM_TRIG_SOURCE_SAI1B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1B output*/
206 #define LL_LPTIM_TRIG_SOURCE_SAI2A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI2A output*/
207 #define LL_LPTIM_TRIG_SOURCE_SAI2B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2B output*/
208 #define LL_LPTIM_TRIG_SOURCE_SAI4A (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4A output*/
209 #define LL_LPTIM_TRIG_SOURCE_SAI4B LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI4B output*/
210 /**
211 * @}
212 */
213
214 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
215 * @{
216 */
217 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
219 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
220 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
226 * @{
227 */
228 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
229 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
230 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
236 * @{
237 */
238 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
239 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
245 * @{
246 */
247 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
248 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
249 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
250 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
256 * @{
257 */
258 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
266 * @{
267 */
268 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
269 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
270 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
271 /**
272 * @}
273 */
274
275 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
276 * @{
277 */
278 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
279 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM3 */
280 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM3 */
281 /**
282 * @}
283 */
284
285 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
286 * @{
287 */
288 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
289 /**
290 * @}
291 */
292
293 /**
294 * @}
295 */
296
297 /* Exported macro ------------------------------------------------------------*/
298 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
299 * @{
300 */
301
302 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
303 * @{
304 */
305
306 /**
307 * @brief Write a value in LPTIM register
308 * @param __INSTANCE__ LPTIM Instance
309 * @param __REG__ Register to be written
310 * @param __VALUE__ Value to be written in the register
311 * @retval None
312 */
313 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
314
315 /**
316 * @brief Read a value in LPTIM register
317 * @param __INSTANCE__ LPTIM Instance
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329
330 /* Exported functions --------------------------------------------------------*/
331 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
332 * @{
333 */
334
335 #if defined(USE_FULL_LL_DRIVER)
336 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
337 * @{
338 */
339
340 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
341 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
342 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
343 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
344 /**
345 * @}
346 */
347 #endif /* USE_FULL_LL_DRIVER */
348
349 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
350 * @{
351 */
352
353 /**
354 * @brief Enable the LPTIM instance
355 * @note After setting the ENABLE bit, a delay of two counter clock is needed
356 * before the LPTIM instance is actually enabled.
357 * @rmtoll CR ENABLE LL_LPTIM_Enable
358 * @param LPTIMx Low-Power Timer instance
359 * @retval None
360 */
LL_LPTIM_Enable(LPTIM_TypeDef * LPTIMx)361 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
362 {
363 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
364 }
365
366 /**
367 * @brief Indicates whether the LPTIM instance is enabled.
368 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
369 * @param LPTIMx Low-Power Timer instance
370 * @retval State of bit (1 or 0).
371 */
LL_LPTIM_IsEnabled(LPTIM_TypeDef * LPTIMx)372 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
373 {
374 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
375 }
376
377 /**
378 * @brief Starts the LPTIM counter in the desired mode.
379 * @note LPTIM instance must be enabled before starting the counter.
380 * @note It is possible to change on the fly from One Shot mode to
381 * Continuous mode.
382 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
383 * CR SNGSTRT LL_LPTIM_StartCounter
384 * @param LPTIMx Low-Power Timer instance
385 * @param OperatingMode This parameter can be one of the following values:
386 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
387 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
388 * @retval None
389 */
LL_LPTIM_StartCounter(LPTIM_TypeDef * LPTIMx,uint32_t OperatingMode)390 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
391 {
392 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
393 }
394
395 /**
396 * @brief Enable reset after read.
397 * @note After calling this function any read access to LPTIM_CNT
398 * register will asynchronously reset the LPTIM_CNT register content.
399 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
400 * @param LPTIMx Low-Power Timer instance
401 * @retval None
402 */
LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef * LPTIMx)403 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
404 {
405 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
406 }
407
408 /**
409 * @brief Disable reset after read.
410 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
411 * @param LPTIMx Low-Power Timer instance
412 * @retval None
413 */
LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef * LPTIMx)414 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
415 {
416 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
417 }
418
419 /**
420 * @brief Indicate whether the reset after read feature is enabled.
421 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
422 * @param LPTIMx Low-Power Timer instance
423 * @retval State of bit (1 or 0).
424 */
LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef * LPTIMx)425 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
426 {
427 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
428 }
429
430 /**
431 * @brief Reset of the LPTIM_CNT counter register (synchronous).
432 * @note Due to the synchronous nature of this reset, it only takes
433 * place after a synchronization delay of 3 LPTIM core clock cycles
434 * (LPTIM core clock may be different from APB clock).
435 * @note COUNTRST is automatically cleared by hardware
436 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
437 * @param LPTIMx Low-Power Timer instance
438 * @retval None
439 */
LL_LPTIM_ResetCounter(LPTIM_TypeDef * LPTIMx)440 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
441 {
442 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
443 }
444
445 /**
446 * @brief Set the LPTIM registers update mode (enable/disable register preload)
447 * @note This function must be called when the LPTIM instance is disabled.
448 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
449 * @param LPTIMx Low-Power Timer instance
450 * @param UpdateMode This parameter can be one of the following values:
451 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
452 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
453 * @retval None
454 */
LL_LPTIM_SetUpdateMode(LPTIM_TypeDef * LPTIMx,uint32_t UpdateMode)455 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
456 {
457 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
458 }
459
460 /**
461 * @brief Get the LPTIM registers update mode
462 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
463 * @param LPTIMx Low-Power Timer instance
464 * @retval Returned value can be one of the following values:
465 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
466 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
467 */
LL_LPTIM_GetUpdateMode(LPTIM_TypeDef * LPTIMx)468 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
469 {
470 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
471 }
472
473 /**
474 * @brief Set the auto reload value
475 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
476 * @note After a write to the LPTIMx_ARR register a new write operation to the
477 * same register can only be performed when the previous write operation
478 * is completed. Any successive write before the ARROK flag is set, will
479 * lead to unpredictable results.
480 * @note autoreload value be strictly greater than the compare value.
481 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
482 * @param LPTIMx Low-Power Timer instance
483 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
484 * @retval None
485 */
LL_LPTIM_SetAutoReload(LPTIM_TypeDef * LPTIMx,uint32_t AutoReload)486 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
487 {
488 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
489 }
490
491 /**
492 * @brief Get actual auto reload value
493 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
494 * @param LPTIMx Low-Power Timer instance
495 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
496 */
LL_LPTIM_GetAutoReload(LPTIM_TypeDef * LPTIMx)497 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
498 {
499 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
500 }
501
502 /**
503 * @brief Set the compare value
504 * @note After a write to the LPTIMx_CMP register a new write operation to the
505 * same register can only be performed when the previous write operation
506 * is completed. Any successive write before the CMPOK flag is set, will
507 * lead to unpredictable results.
508 * @rmtoll CMP CMP LL_LPTIM_SetCompare
509 * @param LPTIMx Low-Power Timer instance
510 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
511 * @retval None
512 */
LL_LPTIM_SetCompare(LPTIM_TypeDef * LPTIMx,uint32_t CompareValue)513 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
514 {
515 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
516 }
517
518 /**
519 * @brief Get actual compare value
520 * @rmtoll CMP CMP LL_LPTIM_GetCompare
521 * @param LPTIMx Low-Power Timer instance
522 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
523 */
LL_LPTIM_GetCompare(LPTIM_TypeDef * LPTIMx)524 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
525 {
526 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
527 }
528
529 /**
530 * @brief Get actual counter value
531 * @note When the LPTIM instance is running with an asynchronous clock, reading
532 * the LPTIMx_CNT register may return unreliable values. So in this case
533 * it is necessary to perform two consecutive read accesses and verify
534 * that the two returned values are identical.
535 * @rmtoll CNT CNT LL_LPTIM_GetCounter
536 * @param LPTIMx Low-Power Timer instance
537 * @retval Counter value
538 */
LL_LPTIM_GetCounter(LPTIM_TypeDef * LPTIMx)539 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
540 {
541 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
542 }
543
544 /**
545 * @brief Set the counter mode (selection of the LPTIM counter clock source).
546 * @note The counter mode can be set only when the LPTIM instance is disabled.
547 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
548 * @param LPTIMx Low-Power Timer instance
549 * @param CounterMode This parameter can be one of the following values:
550 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
551 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
552 * @retval None
553 */
LL_LPTIM_SetCounterMode(LPTIM_TypeDef * LPTIMx,uint32_t CounterMode)554 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
555 {
556 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
557 }
558
559 /**
560 * @brief Get the counter mode
561 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
562 * @param LPTIMx Low-Power Timer instance
563 * @retval Returned value can be one of the following values:
564 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
565 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
566 */
LL_LPTIM_GetCounterMode(LPTIM_TypeDef * LPTIMx)567 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
568 {
569 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
570 }
571
572 /**
573 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
574 * @note This function must be called when the LPTIM instance is disabled.
575 * @note Regarding the LPTIM output polarity the change takes effect
576 * immediately, so the output default value will change immediately after
577 * the polarity is re-configured, even before the timer is enabled.
578 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
579 * CFGR WAVPOL LL_LPTIM_ConfigOutput
580 * @param LPTIMx Low-Power Timer instance
581 * @param Waveform This parameter can be one of the following values:
582 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
583 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
584 * @param Polarity This parameter can be one of the following values:
585 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
586 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
587 * @retval None
588 */
LL_LPTIM_ConfigOutput(LPTIM_TypeDef * LPTIMx,uint32_t Waveform,uint32_t Polarity)589 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
590 {
591 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
592 }
593
594 /**
595 * @brief Set waveform shape
596 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
597 * @param LPTIMx Low-Power Timer instance
598 * @param Waveform This parameter can be one of the following values:
599 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
600 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
601 * @retval None
602 */
LL_LPTIM_SetWaveform(LPTIM_TypeDef * LPTIMx,uint32_t Waveform)603 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
604 {
605 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
606 }
607
608 /**
609 * @brief Get actual waveform shape
610 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
611 * @param LPTIMx Low-Power Timer instance
612 * @retval Returned value can be one of the following values:
613 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
614 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
615 */
LL_LPTIM_GetWaveform(LPTIM_TypeDef * LPTIMx)616 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
617 {
618 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
619 }
620
621 /**
622 * @brief Set output polarity
623 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
624 * @param LPTIMx Low-Power Timer instance
625 * @param Polarity This parameter can be one of the following values:
626 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
627 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
628 * @retval None
629 */
LL_LPTIM_SetPolarity(LPTIM_TypeDef * LPTIMx,uint32_t Polarity)630 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
631 {
632 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
633 }
634
635 /**
636 * @brief Get actual output polarity
637 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
638 * @param LPTIMx Low-Power Timer instance
639 * @retval Returned value can be one of the following values:
640 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
641 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
642 */
LL_LPTIM_GetPolarity(LPTIM_TypeDef * LPTIMx)643 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
644 {
645 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
646 }
647
648 /**
649 * @brief Set actual prescaler division ratio.
650 * @note This function must be called when the LPTIM instance is disabled.
651 * @note When the LPTIM is configured to be clocked by an internal clock source
652 * and the LPTIM counter is configured to be updated by active edges
653 * detected on the LPTIM external Input1, the internal clock provided to
654 * the LPTIM must be not be prescaled.
655 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
656 * @param LPTIMx Low-Power Timer instance
657 * @param Prescaler This parameter can be one of the following values:
658 * @arg @ref LL_LPTIM_PRESCALER_DIV1
659 * @arg @ref LL_LPTIM_PRESCALER_DIV2
660 * @arg @ref LL_LPTIM_PRESCALER_DIV4
661 * @arg @ref LL_LPTIM_PRESCALER_DIV8
662 * @arg @ref LL_LPTIM_PRESCALER_DIV16
663 * @arg @ref LL_LPTIM_PRESCALER_DIV32
664 * @arg @ref LL_LPTIM_PRESCALER_DIV64
665 * @arg @ref LL_LPTIM_PRESCALER_DIV128
666 * @retval None
667 */
LL_LPTIM_SetPrescaler(LPTIM_TypeDef * LPTIMx,uint32_t Prescaler)668 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
669 {
670 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
671 }
672
673 /**
674 * @brief Get actual prescaler division ratio.
675 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
676 * @param LPTIMx Low-Power Timer instance
677 * @retval Returned value can be one of the following values:
678 * @arg @ref LL_LPTIM_PRESCALER_DIV1
679 * @arg @ref LL_LPTIM_PRESCALER_DIV2
680 * @arg @ref LL_LPTIM_PRESCALER_DIV4
681 * @arg @ref LL_LPTIM_PRESCALER_DIV8
682 * @arg @ref LL_LPTIM_PRESCALER_DIV16
683 * @arg @ref LL_LPTIM_PRESCALER_DIV32
684 * @arg @ref LL_LPTIM_PRESCALER_DIV64
685 * @arg @ref LL_LPTIM_PRESCALER_DIV128
686 */
LL_LPTIM_GetPrescaler(LPTIM_TypeDef * LPTIMx)687 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
688 {
689 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
690 }
691
692 /**
693 * @brief Set LPTIM input 1 source (default GPIO).
694 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src
695 * @param LPTIMx Low-Power Timer instance
696 * @param Src This parameter can be one of the following values:
697 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
698 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A
699 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B
700 * @retval None
701 */
LL_LPTIM_SetInput1Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)702 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
703 {
704 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);
705 }
706
707 /**
708 * @brief Set LPTIM input 2 source (default GPIO).
709 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src
710 * @param LPTIMx Low-Power Timer instance
711 * @param Src This parameter can be one of the following values:
712 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
713 * @retval None
714 */
LL_LPTIM_SetInput2Src(LPTIM_TypeDef * LPTIMx,uint32_t Src)715 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
716 {
717 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);
718 }
719
720 /**
721 * @}
722 */
723
724 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
725 * @{
726 */
727
728 /**
729 * @brief Enable the timeout function
730 * @note This function must be called when the LPTIM instance is disabled.
731 * @note The first trigger event will start the timer, any successive trigger
732 * event will reset the counter and the timer will restart.
733 * @note The timeout value corresponds to the compare value; if no trigger
734 * occurs within the expected time frame, the MCU is waked-up by the
735 * compare match event.
736 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
737 * @param LPTIMx Low-Power Timer instance
738 * @retval None
739 */
LL_LPTIM_EnableTimeout(LPTIM_TypeDef * LPTIMx)740 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
741 {
742 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
743 }
744
745 /**
746 * @brief Disable the timeout function
747 * @note This function must be called when the LPTIM instance is disabled.
748 * @note A trigger event arriving when the timer is already started will be
749 * ignored.
750 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
751 * @param LPTIMx Low-Power Timer instance
752 * @retval None
753 */
LL_LPTIM_DisableTimeout(LPTIM_TypeDef * LPTIMx)754 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
755 {
756 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
757 }
758
759 /**
760 * @brief Indicate whether the timeout function is enabled.
761 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
762 * @param LPTIMx Low-Power Timer instance
763 * @retval State of bit (1 or 0).
764 */
LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef * LPTIMx)765 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
766 {
767 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
768 }
769
770 /**
771 * @brief Start the LPTIM counter
772 * @note This function must be called when the LPTIM instance is disabled.
773 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
774 * @param LPTIMx Low-Power Timer instance
775 * @retval None
776 */
LL_LPTIM_TrigSw(LPTIM_TypeDef * LPTIMx)777 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
778 {
779 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
780 }
781
782 /**
783 * @brief Configure the external trigger used as a trigger event for the LPTIM.
784 * @note This function must be called when the LPTIM instance is disabled.
785 * @note An internal clock source must be present when a digital filter is
786 * required for the trigger.
787 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
788 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
789 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
790 * @param LPTIMx Low-Power Timer instance
791 * @param Source This parameter can be one of the following values:
792 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
793 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
794 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
795 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
796 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
797 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
798 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
799 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
800 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
801 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
802 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1A (*)
803 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1B (*)
804 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2A (*)
805 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2B (*)
806 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4A (*)
807 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4B (*)
808 *
809 * @param Filter This parameter can be one of the following values:
810 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
811 * @arg @ref LL_LPTIM_TRIG_FILTER_2
812 * @arg @ref LL_LPTIM_TRIG_FILTER_4
813 * @arg @ref LL_LPTIM_TRIG_FILTER_8
814 * @param Polarity This parameter can be one of the following values:
815 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
816 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
817 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
818 * @retval None
819 */
LL_LPTIM_ConfigTrigger(LPTIM_TypeDef * LPTIMx,uint32_t Source,uint32_t Filter,uint32_t Polarity)820 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
821 {
822 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
823 }
824
825 /**
826 * @brief Get actual external trigger source.
827 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
828 * @param LPTIMx Low-Power Timer instance
829 * @retval Returned value can be one of the following values:
830 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
831 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
832 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
833 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
834 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
835 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
836 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*)
837 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*)
838 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*)
839 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*)
840 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1A (*)
841 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1B (*)
842 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2A (*)
843 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2B (*)
844 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4A (*)
845 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4B (*)
846 *
847 * (*) Value not defined in all devices. \n
848 *
849 */
LL_LPTIM_GetTriggerSource(LPTIM_TypeDef * LPTIMx)850 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
851 {
852 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
853 }
854
855 /**
856 * @brief Get actual external trigger filter.
857 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
858 * @param LPTIMx Low-Power Timer instance
859 * @retval Returned value can be one of the following values:
860 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
861 * @arg @ref LL_LPTIM_TRIG_FILTER_2
862 * @arg @ref LL_LPTIM_TRIG_FILTER_4
863 * @arg @ref LL_LPTIM_TRIG_FILTER_8
864 */
LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef * LPTIMx)865 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
866 {
867 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
868 }
869
870 /**
871 * @brief Get actual external trigger polarity.
872 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
873 * @param LPTIMx Low-Power Timer instance
874 * @retval Returned value can be one of the following values:
875 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
876 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
877 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
878 */
LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef * LPTIMx)879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
880 {
881 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
882 }
883
884 /**
885 * @}
886 */
887
888 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
889 * @{
890 */
891
892 /**
893 * @brief Set the source of the clock used by the LPTIM instance.
894 * @note This function must be called when the LPTIM instance is disabled.
895 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
896 * @param LPTIMx Low-Power Timer instance
897 * @param ClockSource This parameter can be one of the following values:
898 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
899 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
900 * @retval None
901 */
LL_LPTIM_SetClockSource(LPTIM_TypeDef * LPTIMx,uint32_t ClockSource)902 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
903 {
904 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
905 }
906
907 /**
908 * @brief Get actual LPTIM instance clock source.
909 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
910 * @param LPTIMx Low-Power Timer instance
911 * @retval Returned value can be one of the following values:
912 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
913 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
914 */
LL_LPTIM_GetClockSource(LPTIM_TypeDef * LPTIMx)915 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
916 {
917 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
918 }
919
920 /**
921 * @brief Configure the active edge or edges used by the counter when
922 the LPTIM is clocked by an external clock source.
923 * @note This function must be called when the LPTIM instance is disabled.
924 * @note When both external clock signal edges are considered active ones,
925 * the LPTIM must also be clocked by an internal clock source with a
926 * frequency equal to at least four times the external clock frequency.
927 * @note An internal clock source must be present when a digital filter is
928 * required for external clock.
929 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
930 * CFGR CKPOL LL_LPTIM_ConfigClock
931 * @param LPTIMx Low-Power Timer instance
932 * @param ClockFilter This parameter can be one of the following values:
933 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
934 * @arg @ref LL_LPTIM_CLK_FILTER_2
935 * @arg @ref LL_LPTIM_CLK_FILTER_4
936 * @arg @ref LL_LPTIM_CLK_FILTER_8
937 * @param ClockPolarity This parameter can be one of the following values:
938 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
939 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
940 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
941 * @retval None
942 */
LL_LPTIM_ConfigClock(LPTIM_TypeDef * LPTIMx,uint32_t ClockFilter,uint32_t ClockPolarity)943 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
944 {
945 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
946 }
947
948 /**
949 * @brief Get actual clock polarity
950 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
951 * @param LPTIMx Low-Power Timer instance
952 * @retval Returned value can be one of the following values:
953 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
954 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
955 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
956 */
LL_LPTIM_GetClockPolarity(LPTIM_TypeDef * LPTIMx)957 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
958 {
959 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
960 }
961
962 /**
963 * @brief Get actual clock digital filter
964 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
965 * @param LPTIMx Low-Power Timer instance
966 * @retval Returned value can be one of the following values:
967 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
968 * @arg @ref LL_LPTIM_CLK_FILTER_2
969 * @arg @ref LL_LPTIM_CLK_FILTER_4
970 * @arg @ref LL_LPTIM_CLK_FILTER_8
971 */
LL_LPTIM_GetClockFilter(LPTIM_TypeDef * LPTIMx)972 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
973 {
974 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
975 }
976
977 /**
978 * @}
979 */
980
981 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
982 * @{
983 */
984
985 /**
986 * @brief Configure the encoder mode.
987 * @note This function must be called when the LPTIM instance is disabled.
988 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
989 * @param LPTIMx Low-Power Timer instance
990 * @param EncoderMode This parameter can be one of the following values:
991 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
992 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
993 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
994 * @retval None
995 */
LL_LPTIM_SetEncoderMode(LPTIM_TypeDef * LPTIMx,uint32_t EncoderMode)996 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
997 {
998 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
999 }
1000
1001 /**
1002 * @brief Get actual encoder mode.
1003 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1004 * @param LPTIMx Low-Power Timer instance
1005 * @retval Returned value can be one of the following values:
1006 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1007 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1008 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1009 */
LL_LPTIM_GetEncoderMode(LPTIM_TypeDef * LPTIMx)1010 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
1011 {
1012 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1013 }
1014
1015 /**
1016 * @brief Enable the encoder mode
1017 * @note This function must be called when the LPTIM instance is disabled.
1018 * @note In this mode the LPTIM instance must be clocked by an internal clock
1019 * source. Also, the prescaler division ratio must be equal to 1.
1020 * @note LPTIM instance must be configured in continuous mode prior enabling
1021 * the encoder mode.
1022 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1023 * @param LPTIMx Low-Power Timer instance
1024 * @retval None
1025 */
LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef * LPTIMx)1026 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1027 {
1028 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1029 }
1030
1031 /**
1032 * @brief Disable the encoder mode
1033 * @note This function must be called when the LPTIM instance is disabled.
1034 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1035 * @param LPTIMx Low-Power Timer instance
1036 * @retval None
1037 */
LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef * LPTIMx)1038 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1039 {
1040 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1041 }
1042
1043 /**
1044 * @brief Indicates whether the LPTIM operates in encoder mode.
1045 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1046 * @param LPTIMx Low-Power Timer instance
1047 * @retval State of bit (1 or 0).
1048 */
LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef * LPTIMx)1049 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1050 {
1051 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
1052 }
1053
1054 /**
1055 * @}
1056 */
1057
1058 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1059 * @{
1060 */
1061
1062 /**
1063 * @brief Clear the compare match flag (CMPMCF)
1064 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1065 * @param LPTIMx Low-Power Timer instance
1066 * @retval None
1067 */
LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef * LPTIMx)1068 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1069 {
1070 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1071 }
1072
1073 /**
1074 * @brief Inform application whether a compare match interrupt has occurred.
1075 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1076 * @param LPTIMx Low-Power Timer instance
1077 * @retval State of bit (1 or 0).
1078 */
LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef * LPTIMx)1079 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1080 {
1081 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
1082 }
1083
1084 /**
1085 * @brief Clear the autoreload match flag (ARRMCF)
1086 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1087 * @param LPTIMx Low-Power Timer instance
1088 * @retval None
1089 */
LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef * LPTIMx)1090 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1091 {
1092 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1093 }
1094
1095 /**
1096 * @brief Inform application whether a autoreload match interrupt has occurred.
1097 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1098 * @param LPTIMx Low-Power Timer instance
1099 * @retval State of bit (1 or 0).
1100 */
LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef * LPTIMx)1101 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1102 {
1103 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
1104 }
1105
1106 /**
1107 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1108 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1109 * @param LPTIMx Low-Power Timer instance
1110 * @retval None
1111 */
LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1112 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1113 {
1114 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1115 }
1116
1117 /**
1118 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1119 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1120 * @param LPTIMx Low-Power Timer instance
1121 * @retval State of bit (1 or 0).
1122 */
LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef * LPTIMx)1123 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1124 {
1125 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
1126 }
1127
1128 /**
1129 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1130 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1131 * @param LPTIMx Low-Power Timer instance
1132 * @retval None
1133 */
LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1134 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1135 {
1136 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1137 }
1138
1139 /**
1140 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
1141 completed. If so, a new one can be initiated.
1142 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1143 * @param LPTIMx Low-Power Timer instance
1144 * @retval State of bit (1 or 0).
1145 */
LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef * LPTIMx)1146 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1147 {
1148 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
1149 }
1150
1151 /**
1152 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1153 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1154 * @param LPTIMx Low-Power Timer instance
1155 * @retval None
1156 */
LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef * LPTIMx)1157 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1158 {
1159 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1160 }
1161
1162 /**
1163 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
1164 completed. If so, a new one can be initiated.
1165 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1166 * @param LPTIMx Low-Power Timer instance
1167 * @retval State of bit (1 or 0).
1168 */
LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef * LPTIMx)1169 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1170 {
1171 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
1172 }
1173
1174 /**
1175 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1176 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1177 * @param LPTIMx Low-Power Timer instance
1178 * @retval None
1179 */
LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef * LPTIMx)1180 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1181 {
1182 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1183 }
1184
1185 /**
1186 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
1187 operates in encoder mode).
1188 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1189 * @param LPTIMx Low-Power Timer instance
1190 * @retval State of bit (1 or 0).
1191 */
LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef * LPTIMx)1192 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1193 {
1194 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
1195 }
1196
1197 /**
1198 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1199 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1200 * @param LPTIMx Low-Power Timer instance
1201 * @retval None
1202 */
LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef * LPTIMx)1203 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1204 {
1205 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1206 }
1207
1208 /**
1209 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
1210 operates in encoder mode).
1211 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1212 * @param LPTIMx Low-Power Timer instance
1213 * @retval State of bit (1 or 0).
1214 */
LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef * LPTIMx)1215 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1216 {
1217 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
1218 }
1219
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1225 * @{
1226 */
1227
1228 /**
1229 * @brief Enable compare match interrupt (CMPMIE).
1230 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1231 * @param LPTIMx Low-Power Timer instance
1232 * @retval None
1233 */
LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef * LPTIMx)1234 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1235 {
1236 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1237 }
1238
1239 /**
1240 * @brief Disable compare match interrupt (CMPMIE).
1241 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1242 * @param LPTIMx Low-Power Timer instance
1243 * @retval None
1244 */
LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef * LPTIMx)1245 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1246 {
1247 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1248 }
1249
1250 /**
1251 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1252 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1253 * @param LPTIMx Low-Power Timer instance
1254 * @retval State of bit (1 or 0).
1255 */
LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef * LPTIMx)1256 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1257 {
1258 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
1259 }
1260
1261 /**
1262 * @brief Enable autoreload match interrupt (ARRMIE).
1263 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1264 * @param LPTIMx Low-Power Timer instance
1265 * @retval None
1266 */
LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef * LPTIMx)1267 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1268 {
1269 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1270 }
1271
1272 /**
1273 * @brief Disable autoreload match interrupt (ARRMIE).
1274 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1275 * @param LPTIMx Low-Power Timer instance
1276 * @retval None
1277 */
LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef * LPTIMx)1278 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1279 {
1280 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1281 }
1282
1283 /**
1284 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1285 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1286 * @param LPTIMx Low-Power Timer instance
1287 * @retval State of bit (1 or 0).
1288 */
LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef * LPTIMx)1289 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1290 {
1291 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
1292 }
1293
1294 /**
1295 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1296 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1297 * @param LPTIMx Low-Power Timer instance
1298 * @retval None
1299 */
LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1300 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1301 {
1302 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1303 }
1304
1305 /**
1306 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1307 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1308 * @param LPTIMx Low-Power Timer instance
1309 * @retval None
1310 */
LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1311 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1312 {
1313 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1314 }
1315
1316 /**
1317 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1318 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1319 * @param LPTIMx Low-Power Timer instance
1320 * @retval State of bit (1 or 0).
1321 */
LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef * LPTIMx)1322 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1323 {
1324 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
1325 }
1326
1327 /**
1328 * @brief Enable compare register write completed interrupt (CMPOKIE).
1329 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1330 * @param LPTIMx Low-Power Timer instance
1331 * @retval None
1332 */
LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1333 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1334 {
1335 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1336 }
1337
1338 /**
1339 * @brief Disable compare register write completed interrupt (CMPOKIE).
1340 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1341 * @param LPTIMx Low-Power Timer instance
1342 * @retval None
1343 */
LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef * LPTIMx)1344 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1345 {
1346 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1347 }
1348
1349 /**
1350 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1351 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1352 * @param LPTIMx Low-Power Timer instance
1353 * @retval State of bit (1 or 0).
1354 */
LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef * LPTIMx)1355 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1356 {
1357 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
1358 }
1359
1360 /**
1361 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1362 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1363 * @param LPTIMx Low-Power Timer instance
1364 * @retval None
1365 */
LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef * LPTIMx)1366 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1367 {
1368 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1369 }
1370
1371 /**
1372 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1373 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1374 * @param LPTIMx Low-Power Timer instance
1375 * @retval None
1376 */
LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef * LPTIMx)1377 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1378 {
1379 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1380 }
1381
1382 /**
1383 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1384 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1385 * @param LPTIMx Low-Power Timer instance
1386 * @retval State of bit(1 or 0).
1387 */
LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef * LPTIMx)1388 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1389 {
1390 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
1391 }
1392
1393 /**
1394 * @brief Enable direction change to up interrupt (UPIE).
1395 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1396 * @param LPTIMx Low-Power Timer instance
1397 * @retval None
1398 */
LL_LPTIM_EnableIT_UP(LPTIM_TypeDef * LPTIMx)1399 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1400 {
1401 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1402 }
1403
1404 /**
1405 * @brief Disable direction change to up interrupt (UPIE).
1406 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1407 * @param LPTIMx Low-Power Timer instance
1408 * @retval None
1409 */
LL_LPTIM_DisableIT_UP(LPTIM_TypeDef * LPTIMx)1410 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1411 {
1412 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1413 }
1414
1415 /**
1416 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1417 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1418 * @param LPTIMx Low-Power Timer instance
1419 * @retval State of bit(1 or 0).
1420 */
LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef * LPTIMx)1421 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1422 {
1423 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
1424 }
1425
1426 /**
1427 * @brief Enable direction change to down interrupt (DOWNIE).
1428 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1429 * @param LPTIMx Low-Power Timer instance
1430 * @retval None
1431 */
LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef * LPTIMx)1432 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1433 {
1434 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1435 }
1436
1437 /**
1438 * @brief Disable direction change to down interrupt (DOWNIE).
1439 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1440 * @param LPTIMx Low-Power Timer instance
1441 * @retval None
1442 */
LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef * LPTIMx)1443 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1444 {
1445 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1446 }
1447
1448 /**
1449 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1450 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1451 * @param LPTIMx Low-Power Timer instance
1452 * @retval State of bit(1 or 0).
1453 */
LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef * LPTIMx)1454 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1455 {
1456 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
1457 }
1458
1459 /**
1460 * @}
1461 */
1462
1463 /**
1464 * @}
1465 */
1466
1467 /**
1468 * @}
1469 */
1470
1471 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */
1472
1473 /**
1474 * @}
1475 */
1476
1477 #ifdef __cplusplus
1478 }
1479 #endif
1480
1481 #endif /* STM32MP1xx_LL_LPTIM_H */
1482
