1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) API to access to MCU info (CPUID register)
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32MP1xx_LL_CORTEX_H
35 #define __STM32MP1xx_LL_CORTEX_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32mp1xx.h"
43
44 /** @addtogroup STM32MP1xx_LL_Driver
45 * @{
46 */
47
48 /** @defgroup CORTEX_LL CORTEX
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56
57 /* Private macros ------------------------------------------------------------*/
58
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
69 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
70 /**
71 * @}
72 */
73
74 /**
75 * @}
76 */
77
78 /* Exported macro ------------------------------------------------------------*/
79
80 /* Exported functions --------------------------------------------------------*/
81 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
82 * @{
83 */
84
85 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
86 * @{
87 */
88
89 /**
90 * @brief This function checks if the Systick counter flag is active or not.
91 * @note It can be used in timeout function on application side.
92 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
93 * @retval State of bit (1 or 0).
94 */
LL_SYSTICK_IsActiveCounterFlag(void)95 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
96 {
97 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
98 }
99
100 /**
101 * @brief Configures the SysTick clock source
102 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
103 * @param Source This parameter can be one of the following values:
104 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
105 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
106 * @retval None
107 */
LL_SYSTICK_SetClkSource(uint32_t Source)108 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
109 {
110 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
111 {
112 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
113 }
114 else
115 {
116 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
117 }
118 }
119
120 /**
121 * @brief Get the SysTick clock source
122 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
123 * @retval Returned value can be one of the following values:
124 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
125 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
126 */
LL_SYSTICK_GetClkSource(void)127 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
128 {
129 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
130 }
131
132 /**
133 * @brief Enable SysTick exception request
134 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
135 * @retval None
136 */
LL_SYSTICK_EnableIT(void)137 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
138 {
139 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
140 }
141
142 /**
143 * @brief Disable SysTick exception request
144 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
145 * @retval None
146 */
LL_SYSTICK_DisableIT(void)147 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
148 {
149 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
150 }
151
152 /**
153 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
154 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
155 * @retval State of bit (1 or 0).
156 */
LL_SYSTICK_IsEnabledIT(void)157 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
158 {
159 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
160 }
161
162 /**
163 * @}
164 */
165
166 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
167 * @{
168 */
169
170 /**
171 * @brief Processor uses sleep as its low power mode
172 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
173 * @retval None
174 */
LL_LPM_EnableSleep(void)175 __STATIC_INLINE void LL_LPM_EnableSleep(void)
176 {
177 /* Clear SLEEPDEEP bit of Cortex System Control Register */
178 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
179 }
180
181 /**
182 * @brief Processor uses deep sleep as its low power mode
183 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
184 * @retval None
185 */
LL_LPM_EnableDeepSleep(void)186 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
187 {
188 /* Set SLEEPDEEP bit of Cortex System Control Register */
189 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
190 }
191
192 /**
193 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
194 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
195 * empty main application.
196 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
197 * @retval None
198 */
LL_LPM_EnableSleepOnExit(void)199 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
200 {
201 /* Set SLEEPONEXIT bit of Cortex System Control Register */
202 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
203 }
204
205 /**
206 * @brief Do not sleep when returning to Thread mode.
207 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
208 * @retval None
209 */
LL_LPM_DisableSleepOnExit(void)210 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
211 {
212 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
213 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
214 }
215
216 /**
217 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
218 * processor.
219 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
220 * @retval None
221 */
LL_LPM_EnableEventOnPend(void)222 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
223 {
224 /* Set SEVEONPEND bit of Cortex System Control Register */
225 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
226 }
227
228 /**
229 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
230 * excluded
231 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
232 * @retval None
233 */
LL_LPM_DisableEventOnPend(void)234 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
235 {
236 /* Clear SEVEONPEND bit of Cortex System Control Register */
237 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
238 }
239
240 /**
241 * @}
242 */
243
244 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
245 * @{
246 */
247
248 /**
249 * @brief Get Implementer code
250 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
251 * @retval Value should be equal to 0x41 for ARM
252 */
LL_CPUID_GetImplementer(void)253 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
254 {
255 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
256 }
257
258 /**
259 * @brief Get Variant number (The r value in the rnpn product revision identifier)
260 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
261 * @retval Value between 0 and 255 (0x0: revision 0)
262 */
LL_CPUID_GetVariant(void)263 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
264 {
265 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
266 }
267
268 /**
269 * @brief Get Architecture number
270 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
271 * @retval Value should be equal to 0xC for Cortex-M0 devices
272 */
LL_CPUID_GetArchitecture(void)273 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
274 {
275 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
276 }
277
278 /**
279 * @brief Get Part number
280 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
281 * @retval Value should be equal to 0xC20 for Cortex-M0
282 */
LL_CPUID_GetParNo(void)283 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
284 {
285 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
286 }
287
288 /**
289 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
290 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
291 * @retval Value between 0 and 255 (0x1: patch 1)
292 */
LL_CPUID_GetRevision(void)293 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
294 {
295 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
296 }
297
298 /**
299 * @}
300 */
301
302 /**
303 * @}
304 */
305
306 /**
307 * @}
308 */
309
310 /**
311 * @}
312 */
313
314 #ifdef __cplusplus
315 }
316 #endif
317
318 #endif /* __STM32MP1xx_LL_CORTEX_H */
319
