1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization and de-initialization functions
9 * + AES processing functions
10 * + DES processing functions
11 * + TDES processing functions
12 * + DMA callback functions
13 * + CRYP IRQ handler management
14 * + Peripheral State functions
15 *
16 ******************************************************************************
17 * @attention
18 *
19 * Copyright (c) 2019 STMicroelectronics.
20 * All rights reserved.
21 *
22 * This software is licensed under terms that can be found in the LICENSE file
23 * in the root directory of this software component.
24 * If no LICENSE file comes with this software, it is provided AS-IS.
25 *
26 ******************************************************************************
27 @verbatim
28 ==============================================================================
29 ##### How to use this driver #####
30 ==============================================================================
31 [..]
32 The CRYP HAL driver can be used in CRYP IP as follows:
33
34 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
35 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
36 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
37 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
38 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
39 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
40 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
41 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
42 (+++) Configure and enable two DMA streams one for managing data transfer from
43 memory to peripheral (input stream) and another stream for managing data
44 transfer from peripheral to memory (output stream)
45 (+++) Associate the initialized DMA handle to the CRYP DMA handle
46 using __HAL_LINKDMA()
47 (+++) Configure the priority and enable the NVIC for the transfer complete
48 interrupt on the two DMA Streams. The output stream should have higher
49 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
50
51 (#)Initialize the CRYP according to the specified parameters :
52 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
53 (##) The key size: 128, 192 or 256.
54 (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
55 (##) The initialization vector (counter). It is not used in ECB mode.
56 (##) The key buffer used for encryption/decryption.
57 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
58 (##) The HeaderSize The size of header buffer in word.
59 (##) The B0 block is the first authentication block used only in AES CCM mode.
60
61 (#)Three processing (encryption/decryption) functions are available:
62 (##) Polling mode: encryption and decryption APIs are blocking functions
63 i.e. they process the data and wait till the processing is finished,
64 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
65 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
66 i.e. they process the data under interrupt,
67 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
68 (##) DMA mode: encryption and decryption APIs are not blocking functions
69 i.e. the data transfer is ensured by DMA,
70 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
71
72 (#)When the processing function is called at first time after HAL_CRYP_Init()
73 the CRYP peripheral is configured and processes the buffer in input.
74 At second call, no need to Initialize the CRYP, user have to get current configuration via
75 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
76 new parametres, finally user can start encryption/decryption.
77
78 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
79
80 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
81 without having to configure again the Key or the Initialization Vector between each API call,
82 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
83 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
84 or HAL_CRYP_Decrypt_DMA().
85
86 [..]
87 The cryptographic processor supports following standards:
88 (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
89 (##)64-bit data block processing
90 (##) chaining modes supported :
91 (+++) Electronic Code Book(ECB)
92 (+++) Cipher Block Chaining (CBC)
93 (##) keys length supported :64-bit, 128-bit and 192-bit.
94 (#) The advanced encryption standard (AES) supported by CRYP1:
95 (##)128-bit data block processing
96 (##) chaining modes supported :
97 (+++) Electronic Code Book(ECB)
98 (+++) Cipher Block Chaining (CBC)
99 (+++) Counter mode (CTR)
100 (+++) Galois/counter mode (GCM/GMAC)
101 (+++) Counter with Cipher Block Chaining-Message(CCM)
102 (##) keys length Supported :
103 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
104
105 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
106 (#) Algorithm supported :
107 (##) Galois/counter mode (GCM)
108 (##) Galois message authentication code (GMAC) :is exactly the same as
109 GCM algorithm composed only by an header.
110 (#) Four phases are performed in GCM :
111 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
112 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
113 computation only.
114 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
115 encryption + data XORing. It works in a similar way for ciphertext (C).
116 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
117 (#) structure of message construction in GCM is defined as below :
118 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
119 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
120 this part of the message is only authenticated, not encrypted.
121 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
122 GCM standard specifies that ciphertext has same bit length as the plaintext.
123 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
124 (on 64 bits)
125
126 [..] This section describe The AES Counter with Cipher Block Chaining-Message
127 Authentication Code (CCM) supported by both CRYP1 IP:
128 (#) Specific parameters for CCM :
129
130 (##) B0 block : According to NIST Special Publication 800-38C,
131 The first block B0 is formatted as follows, where l(m) is encoded in
132 most-significant-byte first order(see below table 3)
133
134 (+++) Q: a bit string representation of the octet length of P (plaintext)
135 (+++) q The octet length of the binary representation of the octet length of the payload
136 (+++) A nonce (N), n The octet length of the where n+q=15.
137 (+++) Flags: most significant octet containing four flags for control information,
138 (+++) t The octet length of the MAC.
139 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
140 the associated data length expressed in bytes (a) defined as below:
141 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
142 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
143 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
144 (##) CTRx block : control blocks
145 (+++) Generation of CTR1 from first block B0 information :
146 equal to B0 with first 5 bits zeroed and most significant bits storing octet
147 length of P also zeroed, then incremented by one ( see below Table 4)
148 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
149
150 (#) Four phases are performed in CCM for CRYP1 IP:
151 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
152 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
153 computation only.
154 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
155 encryption + data XORing. It works in a similar way for ciphertext (C).
156 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
157
158 *** Callback registration ***
159 =============================
160
161 [..]
162 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
163 allows the user to configure dynamically the driver callbacks.
164 Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
165 to register an interrupt callback.
166
167 [..]
168 Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
169 (+) InCpltCallback : Input FIFO transfer completed callback.
170 (+) OutCpltCallback : Output FIFO transfer completed callback.
171 (+) ErrorCallback : callback for error detection.
172 (+) MspInitCallback : CRYP MspInit.
173 (+) MspDeInitCallback : CRYP MspDeInit.
174 This function takes as parameters the HAL peripheral handle, the Callback ID
175 and a pointer to the user callback function.
176
177 [..]
178 Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
179 weak function.
180 @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
181 and the Callback ID.
182 This function allows to reset following callbacks:
183 (+) InCpltCallback : Input FIFO transfer completed callback.
184 (+) OutCpltCallback : Output FIFO transfer completed callback.
185 (+) ErrorCallback : callback for error detection.
186 (+) MspInitCallback : CRYP MspInit.
187 (+) MspDeInitCallback : CRYP MspDeInit.
188
189 [..]
190 By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
191 all callbacks are set to the corresponding weak functions :
192 examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
193 Exception done for MspInit and MspDeInit functions that are
194 reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when
195 these callbacks are null (not registered beforehand).
196 if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
197 keep and use the user MspInit/MspDeInit functions (registered beforehand)
198
199 [..]
200 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
201 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
202 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
203 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
204 In that case first register the MspInit/MspDeInit user callbacks
205 using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
206 or @ref HAL_CRYP_Init() function.
207
208 [..]
209 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
210 not defined, the callback registration feature is not available and all callbacks
211 are set to the corresponding weak functions.
212
213 @endverbatim
214
215 Table 1. Initial Counter Block (ICB)
216 +-------------------------------------------------------+
217 | Initialization vector (IV) | Counter |
218 |----------------|----------------|-----------|---------|
219 127 95 63 31 0
220
221
222 Bit Number Register Contents
223 ---------- --------------- -----------
224 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
225 95 ...64 CRYP_IV1L[31:0] B0[95:64]
226 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
227 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
228
229 Table 2. GCM last block definition
230
231 +-------------------------------------------------------------------+
232 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
233 |-----------|--------------------|-----------|----------------------|
234 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
235 |-----------|--------------------|-----------|----------------------|
236
237 Table 3. B0 block
238 Octet Number Contents
239 ------------ ---------
240 0 Flags
241 1 ... 15-q Nonce N
242 16-q ... 15 Q
243
244 the Flags field is formatted as follows:
245
246 Bit Number Contents
247 ---------- ----------------------
248 7 Reserved (always zero)
249 6 Adata
250 5 ... 3 (t-2)/2
251 2 ... 0 [q-1]3
252
253 Table 4. CTRx block
254 Bit Number Register Contents
255 ---------- --------------- -----------
256 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
257 bit 0 that is set to 1
258 95 ...64 CRYP_IV1L[31:0] B0[95:64]
259 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
260 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
261
262
263 ******************************************************************************
264 */
265
266 /* Includes ------------------------------------------------------------------*/
267 #include "stm32mp1xx_hal.h"
268
269 /** @addtogroup STM32MP1xx_HAL_Driver
270 * @{
271 */
272
273 #if defined (CRYP1) || defined (CRYP2)
274
275 /** @defgroup CRYP CRYP
276 * @brief CRYP HAL module driver.
277 * @{
278 */
279
280
281 #ifdef HAL_CRYP_MODULE_ENABLED
282
283 /* Private typedef -----------------------------------------------------------*/
284 /* Private define ------------------------------------------------------------*/
285 /** @addtogroup CRYP_Private_Defines
286 * @{
287 */
288 #define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
289 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
290 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
291
292 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
293 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
294
295 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
296 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
297 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
298 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
299 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
300 #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
301
302
303 /* CTR1 information to use in CCM algorithm */
304 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
305 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
306 #define CRYP_CCM_CTR1_2 0x00000001U
307
308 /**
309 * @}
310 */
311
312
313 /* Private macro -------------------------------------------------------------*/
314 /** @addtogroup CRYP_Private_Macros
315 * @{
316 */
317
318 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
319 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
320 }while(0)
321
322 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
323
324
325 /**
326 * @}
327 */
328
329 /* Private struct -------------------------------------------------------------*/
330 /* Private variables ---------------------------------------------------------*/
331 /* Private function prototypes -----------------------------------------------*/
332 /** @addtogroup CRYP_Private_Functions_prototypes
333 * @{
334 */
335
336 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
337 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
338 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
339 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
340 #ifdef HAL_MDMA_MODULE_ENABLED
341 static void CRYP_SetMDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
342 static void CRYP_MDMAInCplt(MDMA_HandleTypeDef *hmdma);
343 static void CRYP_MDMAOutCplt(MDMA_HandleTypeDef *hmdma);
344 static void CRYP_MDMAError(MDMA_HandleTypeDef *hmdma);
345 #endif
346 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
347 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
348 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
349 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
350 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
351 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
352 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
353 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
354 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
355 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
356 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
357 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
358 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
359 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
360 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
362 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
363 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
364 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
365 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
366 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
369
370 /**
371 * @}
372 */
373
374 /* Exported functions ---------------------------------------------------------*/
375
376 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
377 * @{
378 */
379
380
381 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
382 * @brief CRYP Initialization and Configuration functions.
383 *
384 @verbatim
385 ========================================================================================
386 ##### Initialization, de-initialization and Set and Get configuration functions #####
387 ========================================================================================
388 [..] This section provides functions allowing to:
389 (+) Initialize the CRYP
390 (+) DeInitialize the CRYP
391 (+) Initialize the CRYP MSP
392 (+) DeInitialize the CRYP MSP
393 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
394 Parameters which are configured in This section are :
395 (++) Key size
396 (++) Data Type : 32,16, 8 or 1bit
397 (++) AlgoMode : for CRYP1 IP
398 ECB and CBC in DES/TDES Standard
399 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
400 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
401
402
403 @endverbatim
404 * @{
405 */
406
407
408 /**
409 * @brief Initializes the CRYP according to the specified
410 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
411 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
412 * the configuration information for CRYP module
413 * @retval HAL status
414 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)415 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
416 {
417 /* Check the CRYP handle allocation */
418 if (hcryp == NULL)
419 {
420 return HAL_ERROR;
421 }
422
423 /* Check parameters */
424 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
425 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
426 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
427 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
428
429 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
430 if (hcryp->State == HAL_CRYP_STATE_RESET)
431 {
432 /* Allocate lock resource and initialize it */
433 hcryp->Lock = HAL_UNLOCKED;
434
435 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
436 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
437 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
438
439 if (hcryp->MspInitCallback == NULL)
440 {
441 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
442 }
443
444 /* Init the low level hardware */
445 hcryp->MspInitCallback(hcryp);
446 }
447 #else
448 if (hcryp->State == HAL_CRYP_STATE_RESET)
449 {
450 /* Allocate lock resource and initialize it */
451 hcryp->Lock = HAL_UNLOCKED;
452
453 /* Init the low level hardware */
454 HAL_CRYP_MspInit(hcryp);
455 }
456 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
457
458 /* Set the key size(This bit field is �don�t care� in the DES or TDES modes) data type and Algorithm */
459 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
460 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
461 /* Reset Error Code field */
462 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
463
464 /* Reset peripheral Key and IV configuration flag */
465 hcryp->KeyIVConfig = 0U;
466
467 /* Change the CRYP state */
468 hcryp->State = HAL_CRYP_STATE_READY;
469
470 /* Set the default CRYP phase */
471 hcryp->Phase = CRYP_PHASE_READY;
472
473 /* Return function status */
474 return HAL_OK;
475 }
476
477 /**
478 * @brief De-Initializes the CRYP peripheral.
479 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
480 * the configuration information for CRYP module
481 * @retval HAL status
482 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)483 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
484 {
485 /* Check the CRYP handle allocation */
486 if (hcryp == NULL)
487 {
488 return HAL_ERROR;
489 }
490
491 /* Set the default CRYP phase */
492 hcryp->Phase = CRYP_PHASE_READY;
493
494 /* Reset CrypInCount and CrypOutCount */
495 hcryp->CrypInCount = 0;
496 hcryp->CrypOutCount = 0;
497 hcryp->CrypHeaderCount = 0;
498
499 /* Disable the CRYP peripheral clock */
500 __HAL_CRYP_DISABLE(hcryp);
501
502 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
503 if (hcryp->MspDeInitCallback == NULL)
504 {
505 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
506 }
507 /* DeInit the low level hardware */
508 hcryp->MspDeInitCallback(hcryp);
509
510 #else
511 /* DeInit the low level hardware: CLOCK, NVIC.*/
512 HAL_CRYP_MspDeInit(hcryp);
513 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
514
515 /* Change the CRYP state */
516 hcryp->State = HAL_CRYP_STATE_RESET;
517
518 /* Release Lock */
519 __HAL_UNLOCK(hcryp);
520
521 /* Return function status */
522 return HAL_OK;
523 }
524
525 /**
526 * @brief Configure the CRYP according to the specified
527 * parameters in the CRYP_ConfigTypeDef
528 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
529 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
530 * the configuration information for CRYP module
531 * @retval HAL status
532 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)533 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
534 {
535 /* Check the CRYP handle allocation */
536 if ((hcryp == NULL) || (pConf == NULL))
537 {
538 return HAL_ERROR;
539 }
540
541 /* Check parameters */
542 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
543 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
544 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
545
546 if (hcryp->State == HAL_CRYP_STATE_READY)
547 {
548 /* Change the CRYP state */
549 hcryp->State = HAL_CRYP_STATE_BUSY;
550
551 /* Process locked */
552 __HAL_LOCK(hcryp);
553
554 /* Set CRYP parameters */
555 hcryp->Init.DataType = pConf->DataType;
556 hcryp->Init.pKey = pConf->pKey;
557 hcryp->Init.Algorithm = pConf->Algorithm;
558 hcryp->Init.KeySize = pConf->KeySize;
559 hcryp->Init.pInitVect = pConf->pInitVect;
560 hcryp->Init.Header = pConf->Header;
561 hcryp->Init.HeaderSize = pConf->HeaderSize;
562 hcryp->Init.B0 = pConf->B0;
563 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
564
565 /* Set the key size(This bit field is �don�t care� in the DES or TDES modes) data type, AlgoMode and operating mode*/
566 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
567 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
568
569 /* Process Unlocked */
570 __HAL_UNLOCK(hcryp);
571
572 /* Reset Error Code field */
573 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
574
575 /* Change the CRYP state */
576 hcryp->State = HAL_CRYP_STATE_READY;
577
578 /* Set the default CRYP phase */
579 hcryp->Phase = CRYP_PHASE_READY;
580
581 /* Return function status */
582 return HAL_OK;
583 }
584 else
585 {
586 /* Process Unlocked */
587 __HAL_UNLOCK(hcryp);
588
589 /* Busy error code field */
590 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
591 return HAL_ERROR;
592 }
593 }
594
595 /**
596 * @brief Get CRYP Configuration parameters in associated handle.
597 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
598 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
599 * the configuration information for CRYP module
600 * @retval HAL status
601 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)602 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
603 {
604 /* Check the CRYP handle allocation */
605 if ((hcryp == NULL) || (pConf == NULL))
606 {
607 return HAL_ERROR;
608 }
609
610 if (hcryp->State == HAL_CRYP_STATE_READY)
611 {
612 /* Change the CRYP state */
613 hcryp->State = HAL_CRYP_STATE_BUSY;
614
615 /* Process locked */
616 __HAL_LOCK(hcryp);
617
618 /* Get CRYP parameters */
619 pConf->DataType = hcryp->Init.DataType;
620 pConf->pKey = hcryp->Init.pKey;
621 pConf->Algorithm = hcryp->Init.Algorithm;
622 pConf->KeySize = hcryp->Init.KeySize ;
623 pConf->pInitVect = hcryp->Init.pInitVect;
624 pConf->Header = hcryp->Init.Header ;
625 pConf->HeaderSize = hcryp->Init.HeaderSize;
626 pConf->B0 = hcryp->Init.B0;
627 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
628
629 /* Process Unlocked */
630 __HAL_UNLOCK(hcryp);
631
632 /* Change the CRYP state */
633 hcryp->State = HAL_CRYP_STATE_READY;
634
635 /* Return function status */
636 return HAL_OK;
637 }
638 else
639 {
640 /* Process Unlocked */
641 __HAL_UNLOCK(hcryp);
642
643 /* Busy error code field */
644 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
645 return HAL_ERROR;
646 }
647 }
648 /**
649 * @brief Initializes the CRYP MSP.
650 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
651 * the configuration information for CRYP module
652 * @retval None
653 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)654 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
655 {
656 /* Prevent unused argument(s) compilation warning */
657 UNUSED(hcryp);
658
659 /* NOTE : This function Should not be modified, when the callback is needed,
660 the HAL_CRYP_MspInit could be implemented in the user file
661 */
662 }
663
664 /**
665 * @brief DeInitializes CRYP MSP.
666 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
667 * the configuration information for CRYP module
668 * @retval None
669 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)670 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
671 {
672 /* Prevent unused argument(s) compilation warning */
673 UNUSED(hcryp);
674
675 /* NOTE : This function Should not be modified, when the callback is needed,
676 the HAL_CRYP_MspDeInit could be implemented in the user file
677 */
678 }
679
680 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
681 /**
682 * @brief Register a User CRYP Callback
683 * To be used instead of the weak predefined callback
684 * @param hcryp cryp handle
685 * @param CallbackID ID of the callback to be registered
686 * This parameter can be one of the following values:
687 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
688 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
689 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
690 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
691 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
692 * @param pCallback pointer to the Callback function
693 * @retval status
694 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)695 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
696 pCRYP_CallbackTypeDef pCallback)
697 {
698 HAL_StatusTypeDef status = HAL_OK;
699
700 if (pCallback == NULL)
701 {
702 /* Update the error code */
703 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
704
705 return HAL_ERROR;
706 }
707 /* Process locked */
708 __HAL_LOCK(hcryp);
709
710 if (hcryp->State == HAL_CRYP_STATE_READY)
711 {
712 switch (CallbackID)
713 {
714 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
715 hcryp->InCpltCallback = pCallback;
716 break;
717
718 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
719 hcryp->OutCpltCallback = pCallback;
720 break;
721
722 case HAL_CRYP_ERROR_CB_ID :
723 hcryp->ErrorCallback = pCallback;
724 break;
725
726 case HAL_CRYP_MSPINIT_CB_ID :
727 hcryp->MspInitCallback = pCallback;
728 break;
729
730 case HAL_CRYP_MSPDEINIT_CB_ID :
731 hcryp->MspDeInitCallback = pCallback;
732 break;
733
734 default :
735 /* Update the error code */
736 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
737 /* Return error status */
738 status = HAL_ERROR;
739 break;
740 }
741 }
742 else if (hcryp->State == HAL_CRYP_STATE_RESET)
743 {
744 switch (CallbackID)
745 {
746 case HAL_CRYP_MSPINIT_CB_ID :
747 hcryp->MspInitCallback = pCallback;
748 break;
749
750 case HAL_CRYP_MSPDEINIT_CB_ID :
751 hcryp->MspDeInitCallback = pCallback;
752 break;
753
754 default :
755 /* Update the error code */
756 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
757 /* Return error status */
758 status = HAL_ERROR;
759 break;
760 }
761 }
762 else
763 {
764 /* Update the error code */
765 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
766 /* Return error status */
767 status = HAL_ERROR;
768 }
769
770 /* Release Lock */
771 __HAL_UNLOCK(hcryp);
772
773 return status;
774 }
775
776 /**
777 * @brief Unregister an CRYP Callback
778 * CRYP callabck is redirected to the weak predefined callback
779 * @param hcryp cryp handle
780 * @param CallbackID ID of the callback to be unregistered
781 * This parameter can be one of the following values:
782 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
783 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
784 * @arg @ref HAL_CRYP_ERROR_CB_ID Rx Half Error callback ID
785 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
786 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
787 * @retval status
788 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)789 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
790 {
791 HAL_StatusTypeDef status = HAL_OK;
792
793 /* Process locked */
794 __HAL_LOCK(hcryp);
795
796 if (hcryp->State == HAL_CRYP_STATE_READY)
797 {
798 switch (CallbackID)
799 {
800 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
801 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
802 break;
803
804 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
805 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
806 break;
807
808 case HAL_CRYP_ERROR_CB_ID :
809 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
810 break;
811
812 case HAL_CRYP_MSPINIT_CB_ID :
813 hcryp->MspInitCallback = HAL_CRYP_MspInit;
814 break;
815
816 case HAL_CRYP_MSPDEINIT_CB_ID :
817 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
818 break;
819
820 default :
821 /* Update the error code */
822 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
823 /* Return error status */
824 status = HAL_ERROR;
825 break;
826 }
827 }
828 else if (hcryp->State == HAL_CRYP_STATE_RESET)
829 {
830 switch (CallbackID)
831 {
832 case HAL_CRYP_MSPINIT_CB_ID :
833 hcryp->MspInitCallback = HAL_CRYP_MspInit;
834 break;
835
836 case HAL_CRYP_MSPDEINIT_CB_ID :
837 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
838 break;
839
840 default :
841 /* Update the error code */
842 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
843 /* Return error status */
844 status = HAL_ERROR;
845 break;
846 }
847 }
848 else
849 {
850 /* Update the error code */
851 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;;
852 /* Return error status */
853 status = HAL_ERROR;
854 }
855
856 /* Release Lock */
857 __HAL_UNLOCK(hcryp);
858
859 return status;
860 }
861 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
862
863 /**
864 * @}
865 */
866
867 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
868 * @brief CRYP processing functions.
869 *
870 @verbatim
871 ==============================================================================
872 ##### Encrypt Decrypt functions #####
873 ==============================================================================
874 [..] This section provides API allowing to Encrypt/Decrypt Data following
875 Standard DES/TDES or AES, and Algorithm configured by the user:
876 (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
877 (++) Electronic Code Book(ECB)
878 (++) Cipher Block Chaining (CBC)
879 (+) Standard AES supported by CRYP1 IP , list of Algorithm supported:
880 (++) Electronic Code Book(ECB)
881 (++) Cipher Block Chaining (CBC)
882 (++) Counter mode (CTR)
883 (++) Cipher Block Chaining (CBC)
884 (++) Counter mode (CTR)
885 (++) Galois/counter mode (GCM)
886 (++) Counter with Cipher Block Chaining-Message(CCM)
887 [..] Three processing functions are available:
888 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
889 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
890 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
891
892 @endverbatim
893 * @{
894 */
895
896
897 /**
898 * @brief Encryption mode.
899 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
900 * the configuration information for CRYP module
901 * @param Input: Pointer to the input buffer (plaintext)
902 * @param Size: Length of the plaintext buffer in word.
903 * @param Output: Pointer to the output buffer(ciphertext)
904 * @param Timeout: Specify Timeout value
905 * @retval HAL status
906 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)907 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
908 uint32_t Timeout)
909 {
910 uint32_t algo;
911 HAL_StatusTypeDef status;
912
913 if (hcryp->State == HAL_CRYP_STATE_READY)
914 {
915 /* Change state Busy */
916 hcryp->State = HAL_CRYP_STATE_BUSY;
917
918 /* Process locked */
919 __HAL_LOCK(hcryp);
920
921 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
922 hcryp->CrypInCount = 0U;
923 hcryp->CrypOutCount = 0U;
924 hcryp->pCrypInBuffPtr = Input;
925 hcryp->pCrypOutBuffPtr = Output;
926
927 /* Calculate Size parameter in Byte*/
928 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
929 {
930 hcryp->Size = Size * 4U;
931 }
932 else
933 {
934 hcryp->Size = Size;
935 }
936
937 /* Set Encryption operating mode*/
938 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
939
940 /* algo get algorithm selected */
941 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
942
943 switch (algo)
944 {
945 case CRYP_DES_ECB:
946 case CRYP_DES_CBC:
947 case CRYP_TDES_ECB:
948 case CRYP_TDES_CBC:
949
950 /*Set Key */
951 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
952 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
953 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
954 {
955 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
956 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
957 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
958 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
959 }
960
961 /*Set Initialization Vector (IV)*/
962 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
963 {
964 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
965 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
966 }
967
968 /* Flush FIFO */
969 HAL_CRYP_FIFO_FLUSH(hcryp);
970
971 /* Set the phase */
972 hcryp->Phase = CRYP_PHASE_PROCESS;
973
974 /* Statrt DES/TDES encryption process */
975 status = CRYP_TDES_Process(hcryp, Timeout);
976 break;
977
978 case CRYP_AES_ECB:
979 case CRYP_AES_CBC:
980 case CRYP_AES_CTR:
981
982 /* AES encryption */
983 status = CRYP_AES_Encrypt(hcryp, Timeout);
984 break;
985
986 case CRYP_AES_GCM:
987
988 /* AES GCM encryption */
989 status = CRYP_AESGCM_Process(hcryp, Timeout);
990 break;
991
992 case CRYP_AES_CCM:
993
994 /* AES CCM encryption */
995 status = CRYP_AESCCM_Process(hcryp, Timeout);
996 break;
997
998 default:
999 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1000 status = HAL_ERROR;
1001 break;
1002 }
1003
1004 if (status == HAL_OK)
1005 {
1006 /* Change the CRYP peripheral state */
1007 hcryp->State = HAL_CRYP_STATE_READY;
1008
1009 /* Process unlocked */
1010 __HAL_UNLOCK(hcryp);
1011 }
1012 }
1013 else
1014 {
1015 /* Process unlocked */
1016 __HAL_UNLOCK(hcryp);
1017
1018 /* Busy error code field */
1019 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1020 status = HAL_ERROR;
1021 }
1022
1023 /* Return function status */
1024 return status ;
1025 }
1026
1027 /**
1028 * @brief Decryption mode.
1029 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1030 * the configuration information for CRYP module
1031 * @param Input: Pointer to the input buffer (ciphertext )
1032 * @param Size: Length of the plaintext buffer in word.
1033 * @param Output: Pointer to the output buffer(plaintext)
1034 * @param Timeout: Specify Timeout value
1035 * @retval HAL status
1036 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1037 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1038 uint32_t Timeout)
1039 {
1040 HAL_StatusTypeDef status;
1041 uint32_t algo;
1042
1043 if (hcryp->State == HAL_CRYP_STATE_READY)
1044 {
1045 /* Change state Busy */
1046 hcryp->State = HAL_CRYP_STATE_BUSY;
1047
1048 /* Process locked */
1049 __HAL_LOCK(hcryp);
1050
1051 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1052 hcryp->CrypInCount = 0U;
1053 hcryp->CrypOutCount = 0U;
1054 hcryp->pCrypInBuffPtr = Input;
1055 hcryp->pCrypOutBuffPtr = Output;
1056
1057 /* Calculate Size parameter in Byte*/
1058 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1059 {
1060 hcryp->Size = Size * 4U;
1061 }
1062 else
1063 {
1064 hcryp->Size = Size;
1065 }
1066
1067 /* Set Decryption operating mode*/
1068 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1069
1070 /* algo get algorithm selected */
1071 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1072
1073 switch (algo)
1074 {
1075 case CRYP_DES_ECB:
1076 case CRYP_DES_CBC:
1077 case CRYP_TDES_ECB:
1078 case CRYP_TDES_CBC:
1079
1080 /*Set Key */
1081 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1082 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1083 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1084 {
1085 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1086 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1087 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1088 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1089 }
1090
1091 /*Set Initialization Vector (IV)*/
1092 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1093 {
1094 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1095 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1096 }
1097
1098 /* Flush FIFO */
1099 HAL_CRYP_FIFO_FLUSH(hcryp);
1100
1101 /* Set the phase */
1102 hcryp->Phase = CRYP_PHASE_PROCESS;
1103
1104 /* Start DES/TDES decryption process */
1105 status = CRYP_TDES_Process(hcryp, Timeout);
1106
1107 break;
1108
1109 case CRYP_AES_ECB:
1110 case CRYP_AES_CBC:
1111 case CRYP_AES_CTR:
1112
1113 /* AES decryption */
1114 status = CRYP_AES_Decrypt(hcryp, Timeout);
1115 break;
1116
1117 case CRYP_AES_GCM:
1118
1119 /* AES GCM decryption */
1120 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1121 break;
1122
1123 case CRYP_AES_CCM:
1124
1125 /* AES CCM decryption */
1126 status = CRYP_AESCCM_Process(hcryp, Timeout);
1127 break;
1128
1129 default:
1130 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1131 status = HAL_ERROR;
1132 break;
1133 }
1134
1135 if (status == HAL_OK)
1136 {
1137 /* Change the CRYP peripheral state */
1138 hcryp->State = HAL_CRYP_STATE_READY;
1139
1140 /* Process unlocked */
1141 __HAL_UNLOCK(hcryp);
1142 }
1143 }
1144 else
1145 {
1146 /* Process unlocked */
1147 __HAL_UNLOCK(hcryp);
1148
1149 /* Busy error code field */
1150 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1151 status = HAL_ERROR;
1152 }
1153
1154 /* Return function status */
1155 return status;
1156 }
1157
1158 /**
1159 * @brief Encryption in interrupt mode.
1160 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1161 * the configuration information for CRYP module
1162 * @param Input: Pointer to the input buffer (plaintext)
1163 * @param Size: Length of the plaintext buffer in word
1164 * @param Output: Pointer to the output buffer(ciphertext)
1165 * @retval HAL status
1166 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1167 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1168 {
1169 uint32_t algo;
1170 HAL_StatusTypeDef status = HAL_OK;
1171
1172 if (hcryp->State == HAL_CRYP_STATE_READY)
1173 {
1174 /* Change state Busy */
1175 hcryp->State = HAL_CRYP_STATE_BUSY;
1176
1177 /* Process locked */
1178 __HAL_LOCK(hcryp);
1179
1180 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1181 hcryp->CrypInCount = 0U;
1182 hcryp->CrypOutCount = 0U;
1183 hcryp->pCrypInBuffPtr = Input;
1184 hcryp->pCrypOutBuffPtr = Output;
1185
1186 /* Calculate Size parameter in Byte*/
1187 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1188 {
1189 hcryp->Size = Size * 4U;
1190 }
1191 else
1192 {
1193 hcryp->Size = Size;
1194 }
1195
1196 /* Set encryption operating mode*/
1197 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1198
1199 /* algo get algorithm selected */
1200 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1201
1202 switch (algo)
1203 {
1204 case CRYP_DES_ECB:
1205 case CRYP_DES_CBC:
1206 case CRYP_TDES_ECB:
1207 case CRYP_TDES_CBC:
1208
1209 /*Set Key */
1210 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1211 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1212 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1213 {
1214 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1215 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1216 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1217 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1218 }
1219 /* Set the Initialization Vector*/
1220 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1221 {
1222 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1223 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1224 }
1225
1226 /* Flush FIFO */
1227 HAL_CRYP_FIFO_FLUSH(hcryp);
1228
1229 /* Set the phase */
1230 hcryp->Phase = CRYP_PHASE_PROCESS;
1231
1232 /* Enable interrupts */
1233 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1234
1235 /* Enable CRYP to start DES/TDES process*/
1236 __HAL_CRYP_ENABLE(hcryp);
1237
1238 status = HAL_OK;
1239 break;
1240
1241 case CRYP_AES_ECB:
1242 case CRYP_AES_CBC:
1243 case CRYP_AES_CTR:
1244
1245 status = CRYP_AES_Encrypt_IT(hcryp);
1246 break;
1247
1248 case CRYP_AES_GCM:
1249
1250 status = CRYP_AESGCM_Process_IT(hcryp) ;
1251 break;
1252
1253 case CRYP_AES_CCM:
1254
1255 status = CRYP_AESCCM_Process_IT(hcryp);
1256 break;
1257
1258 default:
1259 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1260 status = HAL_ERROR;
1261 break;
1262 }
1263 }
1264 else
1265 {
1266 /* Busy error code field */
1267 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1268 status = HAL_ERROR;
1269 }
1270
1271 /* Return function status */
1272 return status ;
1273 }
1274
1275 /**
1276 * @brief Decryption in itnterrupt mode.
1277 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1278 * the configuration information for CRYP module
1279 * @param Input: Pointer to the input buffer (ciphertext )
1280 * @param Size: Length of the plaintext buffer in word.
1281 * @param Output: Pointer to the output buffer(plaintext)
1282 * @retval HAL status
1283 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1284 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1285 {
1286 uint32_t algo;
1287 HAL_StatusTypeDef status = HAL_OK;
1288
1289 if (hcryp->State == HAL_CRYP_STATE_READY)
1290 {
1291 /* Change state Busy */
1292 hcryp->State = HAL_CRYP_STATE_BUSY;
1293
1294 /* Process locked */
1295 __HAL_LOCK(hcryp);
1296
1297 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1298 hcryp->CrypInCount = 0U;
1299 hcryp->CrypOutCount = 0U;
1300 hcryp->pCrypInBuffPtr = Input;
1301 hcryp->pCrypOutBuffPtr = Output;
1302
1303 /* Calculate Size parameter in Byte*/
1304 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1305 {
1306 hcryp->Size = Size * 4U;
1307 }
1308 else
1309 {
1310 hcryp->Size = Size;
1311 }
1312
1313 /* Set decryption operating mode*/
1314 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1315
1316 /* algo get algorithm selected */
1317 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1318
1319 switch (algo)
1320 {
1321 case CRYP_DES_ECB:
1322 case CRYP_DES_CBC:
1323 case CRYP_TDES_ECB:
1324 case CRYP_TDES_CBC:
1325
1326 /*Set Key */
1327 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1328 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1329 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1330 {
1331 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1332 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1333 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1334 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1335 }
1336
1337 /* Set the Initialization Vector*/
1338 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1339 {
1340 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1341 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1342 }
1343 /* Flush FIFO */
1344 HAL_CRYP_FIFO_FLUSH(hcryp);
1345
1346 /* Set the phase */
1347 hcryp->Phase = CRYP_PHASE_PROCESS;
1348
1349 /* Enable interrupts */
1350 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1351
1352 /* Enable CRYP and start DES/TDES process*/
1353 __HAL_CRYP_ENABLE(hcryp);
1354
1355 break;
1356
1357 case CRYP_AES_ECB:
1358 case CRYP_AES_CBC:
1359 case CRYP_AES_CTR:
1360
1361 /* AES decryption */
1362 status = CRYP_AES_Decrypt_IT(hcryp);
1363 break;
1364
1365 case CRYP_AES_GCM:
1366
1367 /* AES GCM decryption */
1368 status = CRYP_AESGCM_Process_IT(hcryp) ;
1369 break;
1370
1371 case CRYP_AES_CCM:
1372
1373 /* AES CCMdecryption */
1374 status = CRYP_AESCCM_Process_IT(hcryp);
1375 break;
1376
1377 default:
1378 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1379 status = HAL_ERROR;
1380 break;
1381 }
1382 }
1383 else
1384 {
1385 /* Busy error code field */
1386 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1387 status = HAL_ERROR;
1388 }
1389
1390 /* Return function status */
1391 return status;
1392 }
1393
1394 /**
1395 * @brief Encryption in DMA mode.
1396 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1397 * the configuration information for CRYP module
1398 * @param Input: Pointer to the input buffer (plaintext)
1399 * @param Size: Length of the plaintext buffer in word.
1400 * @param Output: Pointer to the output buffer(ciphertext)
1401 * @retval HAL status
1402 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1403 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1404 {
1405 uint32_t algo;
1406 HAL_StatusTypeDef status = HAL_OK;
1407 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1408
1409 if (hcryp->State == HAL_CRYP_STATE_READY)
1410 {
1411 /* Change state Busy */
1412 hcryp->State = HAL_CRYP_STATE_BUSY;
1413
1414 /* Process locked */
1415 __HAL_LOCK(hcryp);
1416
1417 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1418 hcryp->CrypInCount = 0U;
1419 hcryp->CrypOutCount = 0U;
1420 hcryp->pCrypInBuffPtr = Input;
1421 hcryp->pCrypOutBuffPtr = Output;
1422
1423 /* Calculate Size parameter in Byte*/
1424 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1425 {
1426 hcryp->Size = Size * 4U;
1427 }
1428 else
1429 {
1430 hcryp->Size = Size;
1431 }
1432
1433 /* Set encryption operating mode*/
1434 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1435
1436 /* algo get algorithm selected */
1437 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1438
1439 switch (algo)
1440 {
1441 case CRYP_DES_ECB:
1442 case CRYP_DES_CBC:
1443 case CRYP_TDES_ECB:
1444 case CRYP_TDES_CBC:
1445
1446 /*Set Key */
1447 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1448 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1449 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1450 {
1451 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1452 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1453 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1454 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1455 }
1456
1457 /* Set the Initialization Vector*/
1458 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1459 {
1460 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1461 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1462 }
1463
1464 /* Flush FIFO */
1465 HAL_CRYP_FIFO_FLUSH(hcryp);
1466
1467 /* Set the phase */
1468 hcryp->Phase = CRYP_PHASE_PROCESS;
1469
1470 /* Start DMA process transfer for DES/TDES */
1471 if (hcryp->hdmain != NULL)
1472 {
1473 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1474 }
1475 #ifdef HAL_MDMA_MODULE_ENABLED
1476 else if (hcryp->hmdmain != NULL)
1477 {
1478 CRYP_SetMDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1479 }
1480 #endif
1481
1482 break;
1483
1484 case CRYP_AES_ECB:
1485 case CRYP_AES_CBC:
1486 case CRYP_AES_CTR:
1487
1488 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1489 {
1490 if (hcryp->KeyIVConfig == 1U)
1491 {
1492 /* If the Key and IV configuration has to be done only once
1493 and if it has already been done, skip it */
1494 DoKeyIVConfig = 0U;
1495 }
1496 else
1497 {
1498 /* If the Key and IV configuration has to be done only once
1499 and if it has not been done already, do it and set KeyIVConfig
1500 to keep track it won't have to be done again next time */
1501 hcryp->KeyIVConfig = 1U;
1502 }
1503 }
1504
1505 if (DoKeyIVConfig == 1U)
1506 {
1507 /* Set the Key*/
1508 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1509
1510 /* Set the Initialization Vector*/
1511 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1512 {
1513 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1514 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1515 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1516 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1517 }
1518 } /* if (DoKeyIVConfig == 1U) */
1519
1520 /* Set the phase */
1521 hcryp->Phase = CRYP_PHASE_PROCESS;
1522
1523 /* Start DMA process transfer for AES */
1524 if (hcryp->hdmain != NULL)
1525 {
1526 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1527 }
1528 #ifdef HAL_MDMA_MODULE_ENABLED
1529 else if (hcryp->hmdmain != NULL)
1530 {
1531 CRYP_SetMDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1532 }
1533 #endif
1534 break;
1535
1536 case CRYP_AES_GCM:
1537
1538 /* AES GCM encryption */
1539 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1540 break;
1541
1542 case CRYP_AES_CCM:
1543
1544 /* AES CCM encryption */
1545 status = CRYP_AESCCM_Process_DMA(hcryp);
1546 break;
1547
1548 default:
1549 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1550 status = HAL_ERROR;
1551 break;
1552 }
1553 }
1554 else
1555 {
1556 /* Busy error code field */
1557 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1558 status = HAL_ERROR;
1559 }
1560
1561 /* Return function status */
1562 return status;
1563 }
1564
1565 /**
1566 * @brief Decryption in DMA mode.
1567 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1568 * the configuration information for CRYP module
1569 * @param Input: Pointer to the input buffer (ciphertext )
1570 * @param Size: Length of the plaintext buffer in word
1571 * @param Output: Pointer to the output buffer(plaintext)
1572 * @retval HAL status
1573 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1574 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1575 {
1576 uint32_t algo;
1577 HAL_StatusTypeDef status = HAL_OK;
1578
1579 if (hcryp->State == HAL_CRYP_STATE_READY)
1580 {
1581 /* Change state Busy */
1582 hcryp->State = HAL_CRYP_STATE_BUSY;
1583
1584 /* Process locked */
1585 __HAL_LOCK(hcryp);
1586
1587 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1588 hcryp->CrypInCount = 0U;
1589 hcryp->CrypOutCount = 0U;
1590 hcryp->pCrypInBuffPtr = Input;
1591 hcryp->pCrypOutBuffPtr = Output;
1592
1593 /* Calculate Size parameter in Byte*/
1594 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1595 {
1596 hcryp->Size = Size * 4U;
1597 }
1598 else
1599 {
1600 hcryp->Size = Size;
1601 }
1602
1603 /* Set decryption operating mode*/
1604 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1605
1606 /* algo get algorithm selected */
1607 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1608
1609 switch (algo)
1610 {
1611 case CRYP_DES_ECB:
1612 case CRYP_DES_CBC:
1613 case CRYP_TDES_ECB:
1614 case CRYP_TDES_CBC:
1615
1616 /*Set Key */
1617 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1618 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1619 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1620 {
1621 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1622 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1623 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1624 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1625 }
1626
1627 /* Set the Initialization Vector*/
1628 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1629 {
1630 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1631 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1632 }
1633
1634 /* Flush FIFO */
1635 HAL_CRYP_FIFO_FLUSH(hcryp);
1636
1637 /* Set the phase */
1638 hcryp->Phase = CRYP_PHASE_PROCESS;
1639
1640 /* Start DMA process transfer for DES/TDES */
1641 if (hcryp->hdmain != NULL)
1642 {
1643 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4), (uint32_t)(hcryp->pCrypOutBuffPtr));
1644 }
1645 #ifdef HAL_MDMA_MODULE_ENABLED
1646 else if (hcryp->hmdmain != NULL)
1647 {
1648 CRYP_SetMDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1649 }
1650 #endif
1651 break;
1652
1653 case CRYP_AES_ECB:
1654 case CRYP_AES_CBC:
1655 case CRYP_AES_CTR:
1656
1657 /* AES decryption */
1658 status = CRYP_AES_Decrypt_DMA(hcryp);
1659 break;
1660
1661 case CRYP_AES_GCM:
1662
1663 /* AES GCM decryption */
1664 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1665
1666 break;
1667
1668 case CRYP_AES_CCM:
1669
1670 /* AES CCM decryption */
1671 status = CRYP_AESCCM_Process_DMA(hcryp);
1672 break;
1673
1674 default:
1675 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1676 status = HAL_ERROR;
1677 break;
1678 }
1679 }
1680 else
1681 {
1682 /* Busy error code field */
1683 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1684 status = HAL_ERROR;
1685 }
1686
1687 /* Return function status */
1688 return status;
1689 }
1690
1691 /**
1692 * @}
1693 */
1694
1695 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
1696 * @brief CRYP IRQ handler.
1697 *
1698 @verbatim
1699 ==============================================================================
1700 ##### CRYP IRQ handler management #####
1701 ==============================================================================
1702 [..] This section provides CRYP IRQ handler and callback functions.
1703 (+) HAL_CRYP_IRQHandler CRYP interrupt request
1704 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
1705 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
1706 (+) HAL_CRYP_ErrorCallback CRYP error callback
1707 (+) HAL_CRYP_GetState return the CRYP state
1708 (+) HAL_CRYP_GetError return the CRYP error code
1709 @endverbatim
1710 * @{
1711 */
1712
1713 /**
1714 * @brief This function handles cryptographic interrupt request.
1715 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1716 * the configuration information for CRYP module
1717 * @retval None
1718 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)1719 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
1720 {
1721 uint32_t itstatus = hcryp->Instance->MISR;
1722
1723 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
1724 {
1725 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1726 {
1727 CRYP_TDES_IT(hcryp); /* DES or TDES*/
1728 }
1729 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
1730 {
1731 CRYP_AES_IT(hcryp); /*AES*/
1732 }
1733
1734 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
1735 {
1736 /* if header phase */
1737 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
1738 {
1739 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
1740 }
1741 else /* if payload phase */
1742 {
1743 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
1744 }
1745 }
1746 else
1747 {
1748 /* Nothing to do */
1749 }
1750 }
1751 }
1752
1753 /**
1754 * @brief Return the CRYP error code.
1755 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
1756 * the configuration information for the CRYP IP
1757 * @retval CRYP error code
1758 */
HAL_CRYP_GetError(CRYP_HandleTypeDef * hcryp)1759 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
1760 {
1761 return hcryp->ErrorCode;
1762 }
1763
1764 /**
1765 * @brief Returns the CRYP state.
1766 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1767 * the configuration information for CRYP module.
1768 * @retval HAL state
1769 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)1770 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
1771 {
1772 return hcryp->State;
1773 }
1774
1775 /**
1776 * @brief Input FIFO transfer completed callback.
1777 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1778 * the configuration information for CRYP module.
1779 * @retval None
1780 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)1781 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
1782 {
1783 /* Prevent unused argument(s) compilation warning */
1784 UNUSED(hcryp);
1785
1786 /* NOTE : This function Should not be modified, when the callback is needed,
1787 the HAL_CRYP_InCpltCallback could be implemented in the user file
1788 */
1789 }
1790
1791 /**
1792 * @brief Output FIFO transfer completed callback.
1793 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1794 * the configuration information for CRYP module.
1795 * @retval None
1796 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)1797 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
1798 {
1799 /* Prevent unused argument(s) compilation warning */
1800 UNUSED(hcryp);
1801
1802 /* NOTE : This function Should not be modified, when the callback is needed,
1803 the HAL_CRYP_OutCpltCallback could be implemented in the user file
1804 */
1805 }
1806
1807 /**
1808 * @brief CRYP error callback.
1809 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1810 * the configuration information for CRYP module.
1811 * @retval None
1812 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)1813 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
1814 {
1815 /* Prevent unused argument(s) compilation warning */
1816 UNUSED(hcryp);
1817
1818 /* NOTE : This function Should not be modified, when the callback is needed,
1819 the HAL_CRYP_ErrorCallback could be implemented in the user file
1820 */
1821 }
1822 /**
1823 * @}
1824 */
1825
1826 /* Private functions ---------------------------------------------------------*/
1827 /** @addtogroup CRYP_Private_Functions
1828 * @{
1829 */
1830
1831 /**
1832 * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
1833 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1834 * the configuration information for CRYP module
1835 * @param Timeout: Timeout value
1836 * @retval HAL status
1837 */
CRYP_TDES_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)1838 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
1839 {
1840
1841 uint32_t temp; /* Temporary CrypOutBuff */
1842 uint16_t incount; /* Temporary CrypInCount Value */
1843 uint16_t outcount; /* Temporary CrypOutCount Value */
1844
1845 /* Enable CRYP */
1846 __HAL_CRYP_ENABLE(hcryp);
1847 /*Temporary CrypOutCount Value*/
1848 outcount = hcryp->CrypOutCount;
1849
1850 /*Start processing*/
1851 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
1852 {
1853 /* Temporary CrypInCount Value */
1854 incount = hcryp->CrypInCount;
1855 /* Write plain data and get cipher data */
1856 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
1857 {
1858 /* Write the input block in the IN FIFO */
1859 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
1860 hcryp->CrypInCount++;
1861 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
1862 hcryp->CrypInCount++;
1863 }
1864
1865 /* Wait for OFNE flag to be raised */
1866 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
1867 {
1868 /* Disable the CRYP peripheral clock */
1869 __HAL_CRYP_DISABLE(hcryp);
1870
1871 /* Change state & errorCode*/
1872 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
1873 hcryp->State = HAL_CRYP_STATE_READY;
1874
1875 /* Process unlocked */
1876 __HAL_UNLOCK(hcryp);
1877 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
1878 /*Call registered error callback*/
1879 hcryp->ErrorCallback(hcryp);
1880 #else
1881 /*Call legacy weak error callback*/
1882 HAL_CRYP_ErrorCallback(hcryp);
1883 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
1884 }
1885
1886 /*Temporary CrypOutCount Value*/
1887 outcount = hcryp->CrypOutCount;
1888
1889 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
1890 {
1891 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
1892 temp = hcryp->Instance->DOUT;
1893 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
1894 hcryp->CrypOutCount++;
1895 temp = hcryp->Instance->DOUT;
1896 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
1897 hcryp->CrypOutCount++;
1898 }
1899 /*Temporary CrypOutCount Value*/
1900 outcount = hcryp->CrypOutCount;
1901 }
1902 /* Disable CRYP */
1903 __HAL_CRYP_DISABLE(hcryp);
1904 /* Change the CRYP state */
1905 hcryp->State = HAL_CRYP_STATE_READY;
1906
1907 /* Return function status */
1908 return HAL_OK;
1909 }
1910
1911 /**
1912 * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
1913 * @note The function is called under interruption only, once
1914 * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
1915 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1916 * the configuration information for CRYP module.
1917 * @retval HAL status
1918 */
CRYP_TDES_IT(CRYP_HandleTypeDef * hcryp)1919 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
1920 {
1921 uint32_t temp; /* Temporary CrypOutBuff */
1922
1923 if (hcryp->State == HAL_CRYP_STATE_BUSY)
1924 {
1925 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
1926 {
1927 if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
1928 {
1929 /* Write input block in the IN FIFO */
1930 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
1931 hcryp->CrypInCount++;
1932 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
1933 hcryp->CrypInCount++;
1934
1935 if (hcryp->CrypInCount == (hcryp->Size / 4U))
1936 {
1937 /* Disable interruption */
1938 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
1939
1940 /* Call the input data transfer complete callback */
1941 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
1942 /*Call registered Input complete callback*/
1943 hcryp->InCpltCallback(hcryp);
1944 #else
1945 /*Call legacy weak Input complete callback*/
1946 HAL_CRYP_InCpltCallback(hcryp);
1947 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
1948 }
1949 }
1950 }
1951
1952 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
1953 {
1954 if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
1955 {
1956 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
1957 temp = hcryp->Instance->DOUT;
1958 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
1959 hcryp->CrypOutCount++;
1960 temp = hcryp->Instance->DOUT;
1961 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
1962 hcryp->CrypOutCount++;
1963 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
1964 {
1965 /* Disable interruption */
1966 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
1967
1968 /* Disable CRYP */
1969 __HAL_CRYP_DISABLE(hcryp);
1970
1971 /* Process unlocked */
1972 __HAL_UNLOCK(hcryp);
1973
1974 /* Change the CRYP state */
1975 hcryp->State = HAL_CRYP_STATE_READY;
1976
1977 /* Call output transfer complete callback */
1978 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
1979 /*Call registered Output complete callback*/
1980 hcryp->OutCpltCallback(hcryp);
1981 #else
1982 /*Call legacy weak Output complete callback*/
1983 HAL_CRYP_OutCpltCallback(hcryp);
1984 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
1985
1986 }
1987 }
1988 }
1989 }
1990 else
1991 {
1992 /* Process unlocked */
1993 __HAL_UNLOCK(hcryp);
1994 /* Busy error code field */
1995 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1996 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
1997 /*Call registered error callback*/
1998 hcryp->ErrorCallback(hcryp);
1999 #else
2000 /*Call legacy weak error callback*/
2001 HAL_CRYP_ErrorCallback(hcryp);
2002 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2003 }
2004 }
2005
2006 /**
2007 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2008 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2009 * @param Timeout: specify Timeout value
2010 * @retval HAL status
2011 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2012 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2013 {
2014 uint16_t outcount; /* Temporary CrypOutCount Value */
2015 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2016
2017 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2018 {
2019 if (hcryp->KeyIVConfig == 1U)
2020 {
2021 /* If the Key and IV configuration has to be done only once
2022 and if it has already been done, skip it */
2023 DoKeyIVConfig = 0U;
2024 }
2025 else
2026 {
2027 /* If the Key and IV configuration has to be done only once
2028 and if it has not been done already, do it and set KeyIVConfig
2029 to keep track it won't have to be done again next time */
2030 hcryp->KeyIVConfig = 1U;
2031 }
2032 }
2033
2034 if (DoKeyIVConfig == 1U)
2035 {
2036 /* Set the Key*/
2037 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2038
2039 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2040 {
2041 /* Set the Initialization Vector*/
2042 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2043 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2044 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2045 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2046 }
2047 } /* if (DoKeyIVConfig == 1U) */
2048
2049 /* Set the phase */
2050 hcryp->Phase = CRYP_PHASE_PROCESS;
2051
2052 /* Enable CRYP */
2053 __HAL_CRYP_ENABLE(hcryp);
2054 /*Temporary CrypOutCount Value*/
2055 outcount = hcryp->CrypOutCount;
2056
2057 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2058 {
2059 /* Write plain Ddta and get cipher data */
2060 CRYP_AES_ProcessData(hcryp, Timeout);
2061 /*Temporary CrypOutCount Value*/
2062 outcount = hcryp->CrypOutCount;
2063 }
2064
2065 /* Disable CRYP */
2066 __HAL_CRYP_DISABLE(hcryp);
2067
2068 /* Change the CRYP state */
2069 hcryp->State = HAL_CRYP_STATE_READY;
2070
2071 /* Return function status */
2072 return HAL_OK;
2073 }
2074
2075 /**
2076 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2077 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2078 * the configuration information for CRYP module
2079 * @retval HAL status
2080 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2081 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2082 {
2083 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2084
2085 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2086 {
2087 if (hcryp->KeyIVConfig == 1U)
2088 {
2089 /* If the Key and IV configuration has to be done only once
2090 and if it has already been done, skip it */
2091 DoKeyIVConfig = 0U;
2092 }
2093 else
2094 {
2095 /* If the Key and IV configuration has to be done only once
2096 and if it has not been done already, do it and set KeyIVConfig
2097 to keep track it won't have to be done again next time */
2098 hcryp->KeyIVConfig = 1U;
2099 }
2100 }
2101
2102 if (DoKeyIVConfig == 1U)
2103 {
2104 /* Set the Key*/
2105 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2106
2107 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2108 {
2109 /* Set the Initialization Vector*/
2110 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2111 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
2112 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
2113 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
2114 }
2115 } /* if (DoKeyIVConfig == 1U) */
2116
2117 /* Set the phase */
2118 hcryp->Phase = CRYP_PHASE_PROCESS;
2119
2120 if (hcryp->Size != 0U)
2121 {
2122 /* Enable interrupts */
2123 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2124
2125 /* Enable CRYP */
2126 __HAL_CRYP_ENABLE(hcryp);
2127 }
2128 else
2129 {
2130 /* Change the CRYP state */
2131 hcryp->State = HAL_CRYP_STATE_READY;
2132
2133 /* Process unlocked */
2134 __HAL_UNLOCK(hcryp);
2135 }
2136
2137 /* Return function status */
2138 return HAL_OK;
2139 }
2140
2141 /**
2142 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2143 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2144 * @param Timeout: Specify Timeout value
2145 * @retval HAL status
2146 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2147 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2148 {
2149 uint16_t outcount; /* Temporary CrypOutCount Value */
2150 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2151
2152 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2153 {
2154 if (hcryp->KeyIVConfig == 1U)
2155 {
2156 /* If the Key and IV configuration has to be done only once
2157 and if it has already been done, skip it */
2158 DoKeyIVConfig = 0U;
2159 }
2160 else
2161 {
2162 /* If the Key and IV configuration has to be done only once
2163 and if it has not been done already, do it and set KeyIVConfig
2164 to keep track it won't have to be done again next time */
2165 hcryp->KeyIVConfig = 1U;
2166 }
2167 }
2168
2169 if (DoKeyIVConfig == 1U)
2170 {
2171 /* Key preparation for ECB/CBC */
2172 if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/
2173 {
2174 /* change ALGOMODE to key preparation for decryption*/
2175 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2176
2177 /* Set the Key*/
2178 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2179
2180 /* Enable CRYP */
2181 __HAL_CRYP_ENABLE(hcryp);
2182
2183 /* Wait for BUSY flag to be raised */
2184 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2185 {
2186 /* Disable the CRYP peripheral clock */
2187 __HAL_CRYP_DISABLE(hcryp);
2188
2189 /* Change state */
2190 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2191 hcryp->State = HAL_CRYP_STATE_READY;
2192
2193 /* Process unlocked */
2194 __HAL_UNLOCK(hcryp);
2195 return HAL_ERROR;
2196 }
2197 /* Turn back to ALGOMODE of the configuration */
2198 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2199 }
2200 else /*Algorithm CTR */
2201 {
2202 /* Set the Key*/
2203 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2204 }
2205
2206 /* Set IV */
2207 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2208 {
2209 /* Set the Initialization Vector*/
2210 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2211 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2212 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2213 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2214 }
2215 } /* if (DoKeyIVConfig == 1U) */
2216
2217 /* Set the phase */
2218 hcryp->Phase = CRYP_PHASE_PROCESS;
2219
2220 /* Enable CRYP */
2221 __HAL_CRYP_ENABLE(hcryp);
2222
2223 /*Temporary CrypOutCount Value*/
2224 outcount = hcryp->CrypOutCount;
2225
2226 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2227 {
2228 /* Write plain data and get cipher data */
2229 CRYP_AES_ProcessData(hcryp, Timeout);
2230 /*Temporary CrypOutCount Value*/
2231 outcount = hcryp->CrypOutCount;
2232 }
2233
2234 /* Disable CRYP */
2235 __HAL_CRYP_DISABLE(hcryp);
2236
2237 /* Change the CRYP state */
2238 hcryp->State = HAL_CRYP_STATE_READY;
2239
2240 /* Return function status */
2241 return HAL_OK;
2242 }
2243 /**
2244 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2245 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2246 * the configuration information for CRYP module
2247 * @retval HAL status
2248 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2249 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2250 {
2251 __IO uint32_t count = 0U;
2252 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2253
2254 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2255 {
2256 if (hcryp->KeyIVConfig == 1U)
2257 {
2258 /* If the Key and IV configuration has to be done only once
2259 and if it has already been done, skip it */
2260 DoKeyIVConfig = 0U;
2261 }
2262 else
2263 {
2264 /* If the Key and IV configuration has to be done only once
2265 and if it has not been done already, do it and set KeyIVConfig
2266 to keep track it won't have to be done again next time */
2267 hcryp->KeyIVConfig = 1U;
2268 }
2269 }
2270
2271 if (DoKeyIVConfig == 1U)
2272 {
2273 /* Key preparation for ECB/CBC */
2274 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2275 {
2276 /* change ALGOMODE to key preparation for decryption*/
2277 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2278
2279 /* Set the Key*/
2280 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2281
2282 /* Enable CRYP */
2283 __HAL_CRYP_ENABLE(hcryp);
2284
2285 /* Wait for BUSY flag to be raised */
2286 count = CRYP_TIMEOUT_KEYPREPARATION;
2287 do
2288 {
2289 count-- ;
2290 if (count == 0U)
2291 {
2292 /* Change state */
2293 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2294 hcryp->State = HAL_CRYP_STATE_READY;
2295
2296 /* Process unlocked */
2297 __HAL_UNLOCK(hcryp);
2298 return HAL_ERROR;
2299 }
2300 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2301
2302 /* Turn back to ALGOMODE of the configuration */
2303 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2304 }
2305 else /*Algorithm CTR */
2306 {
2307 /* Set the Key*/
2308 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2309 }
2310
2311 /* Set IV */
2312 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2313 {
2314 /* Set the Initialization Vector*/
2315 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2316 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2317 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2318 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2319 }
2320 } /* if (DoKeyIVConfig == 1U) */
2321
2322 /* Set the phase */
2323 hcryp->Phase = CRYP_PHASE_PROCESS;
2324 if (hcryp->Size != 0U)
2325 {
2326 /* Enable interrupts */
2327 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2328
2329 /* Enable CRYP */
2330 __HAL_CRYP_ENABLE(hcryp);
2331 }
2332 else
2333 {
2334 /* Process locked */
2335 __HAL_UNLOCK(hcryp);
2336
2337 /* Change the CRYP state */
2338 hcryp->State = HAL_CRYP_STATE_READY;
2339 }
2340 /* Return function status */
2341 return HAL_OK;
2342 }
2343 /**
2344 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2345 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2346 * the configuration information for CRYP module
2347 * @retval HAL status
2348 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)2349 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2350 {
2351 __IO uint32_t count = 0U;
2352 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2353
2354 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2355 {
2356 if (hcryp->KeyIVConfig == 1U)
2357 {
2358 /* If the Key and IV configuration has to be done only once
2359 and if it has already been done, skip it */
2360 DoKeyIVConfig = 0U;
2361 }
2362 else
2363 {
2364 /* If the Key and IV configuration has to be done only once
2365 and if it has not been done already, do it and set KeyIVConfig
2366 to keep track it won't have to be done again next time */
2367 hcryp->KeyIVConfig = 1U;
2368 }
2369 }
2370
2371 if (DoKeyIVConfig == 1U)
2372 {
2373 /* Key preparation for ECB/CBC */
2374 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2375 {
2376 /* change ALGOMODE to key preparation for decryption*/
2377 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2378
2379 /* Set the Key*/
2380 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2381
2382 /* Enable CRYP */
2383 __HAL_CRYP_ENABLE(hcryp);
2384
2385 /* Wait for BUSY flag to be raised */
2386 count = CRYP_TIMEOUT_KEYPREPARATION;
2387 do
2388 {
2389 count-- ;
2390 if (count == 0U)
2391 {
2392 /* Disable the CRYP peripheral clock */
2393 __HAL_CRYP_DISABLE(hcryp);
2394
2395 /* Change state */
2396 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2397 hcryp->State = HAL_CRYP_STATE_READY;
2398
2399 /* Process unlocked */
2400 __HAL_UNLOCK(hcryp);
2401 return HAL_ERROR;
2402 }
2403 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2404
2405 /* Turn back to ALGOMODE of the configuration */
2406 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2407 }
2408 else /*Algorithm CTR */
2409 {
2410 /* Set the Key*/
2411 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2412 }
2413
2414 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2415 {
2416 /* Set the Initialization Vector*/
2417 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2418 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2419 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2420 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2421 }
2422 } /* if (DoKeyIVConfig == 1U) */
2423
2424 /* Set the phase */
2425 hcryp->Phase = CRYP_PHASE_PROCESS;
2426
2427 if (hcryp->Size != 0U)
2428 {
2429 /* Set the input and output addresses and start DMA transfer */
2430 if (hcryp->hdmain != NULL)
2431 {
2432 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
2433 }
2434 #ifdef HAL_MDMA_MODULE_ENABLED
2435 else if (hcryp->hmdmain != NULL)
2436 {
2437 CRYP_SetMDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
2438 }
2439 #endif
2440 }
2441 else
2442 {
2443 /* Process unlocked */
2444 __HAL_UNLOCK(hcryp);
2445
2446 /* Change the CRYP state */
2447 hcryp->State = HAL_CRYP_STATE_READY;
2448 }
2449
2450 /* Return function status */
2451 return HAL_OK;
2452 }
2453
2454
2455 /**
2456 * @brief DMA CRYP input data process complete callback.
2457 * @param hdma: DMA handle
2458 * @retval None
2459 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)2460 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
2461 {
2462 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2463
2464 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
2465 in the DMACR register */
2466 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
2467
2468 /* Call input data transfer complete callback */
2469 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2470 /*Call registered Input complete callback*/
2471 hcryp->InCpltCallback(hcryp);
2472 #else
2473 /*Call legacy weak Input complete callback*/
2474 HAL_CRYP_InCpltCallback(hcryp);
2475 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2476 }
2477
2478 /**
2479 * @brief DMA CRYP output data process complete callback.
2480 * @param hdma: DMA handle
2481 * @retval None
2482 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)2483 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
2484 {
2485 uint32_t count;
2486 uint32_t npblb;
2487 uint32_t lastwordsize;
2488 uint32_t temp; /* Temporary CrypOutBuff */
2489 uint32_t temp_cr_algodir;
2490 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2491
2492
2493 /* Disable the DMA transfer for output FIFO */
2494 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
2495
2496 /* Last block transfer in case of GCM or CCM with Size not %16*/
2497 if (((hcryp->Size) % 16U) != 0U)
2498 {
2499 /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
2500 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
2501 hcryp->CrypOutCount = hcryp->CrypInCount;
2502
2503 /* Compute the number of padding bytes in last block of payload */
2504 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
2505 /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
2506 temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
2507 if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
2508 ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
2509 {
2510 /* Disable the CRYP */
2511 __HAL_CRYP_DISABLE(hcryp);
2512
2513 /* Specify the number of non-valid bytes using NPBLB register*/
2514 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
2515
2516 /* Enable CRYP to start the final phase */
2517 __HAL_CRYP_ENABLE(hcryp);
2518 }
2519
2520 /* Number of valid words (lastwordsize) in last block */
2521 if ((npblb % 4U) == 0U)
2522 {
2523 lastwordsize = (16U - npblb) / 4U;
2524 }
2525 else
2526 {
2527 lastwordsize = ((16U - npblb) / 4U) + 1U;
2528 }
2529 /* Write the last input block in the IN FIFO */
2530 for (count = 0U; count < lastwordsize; count ++)
2531 {
2532 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2533 hcryp->CrypInCount++;
2534 }
2535 /* Pad the data with zeros to have a complete block */
2536 while (count < 4U)
2537 {
2538 hcryp->Instance->DIN = 0U;
2539 count++;
2540 }
2541 /* Wait for OFNE flag to be raised */
2542 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
2543 do
2544 {
2545 count-- ;
2546 if (count == 0U)
2547 {
2548 /* Disable the CRYP peripheral clock */
2549 __HAL_CRYP_DISABLE(hcryp);
2550
2551 /* Change state */
2552 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2553 hcryp->State = HAL_CRYP_STATE_READY;
2554
2555 /* Process unlocked */
2556 __HAL_UNLOCK(hcryp);
2557 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2558 /*Call registered error callback*/
2559 hcryp->ErrorCallback(hcryp);
2560 #else
2561 /*Call legacy weak error callback*/
2562 HAL_CRYP_ErrorCallback(hcryp);
2563 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2564 }
2565 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
2566
2567 /*Read the output block from the output FIFO */
2568 for (count = 0U; count < 4U; count++)
2569 {
2570 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
2571 temp = hcryp->Instance->DOUT;
2572
2573 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
2574 hcryp->CrypOutCount++;
2575 }
2576 } /*End of last block transfer in case of GCM or CCM */
2577
2578 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
2579 {
2580 /* Disable CRYP (not allowed in GCM)*/
2581 __HAL_CRYP_DISABLE(hcryp);
2582 }
2583
2584 /* Change the CRYP state to ready */
2585 hcryp->State = HAL_CRYP_STATE_READY;
2586
2587 /* Process unlocked */
2588 __HAL_UNLOCK(hcryp);
2589
2590 /* Call output data transfer complete callback */
2591 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2592 /*Call registered Output complete callback*/
2593 hcryp->OutCpltCallback(hcryp);
2594 #else
2595 /*Call legacy weak Output complete callback*/
2596 HAL_CRYP_OutCpltCallback(hcryp);
2597 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2598 }
2599
2600 /**
2601 * @brief DMA CRYP communication error callback.
2602 * @param hdma: DMA handle
2603 * @retval None
2604 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)2605 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
2606 {
2607 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
2608
2609 /* Change the CRYP peripheral state */
2610 hcryp->State = HAL_CRYP_STATE_READY;
2611
2612 /* DMA error code field */
2613 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2614
2615 /* Call error callback */
2616 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2617 /*Call registered error callback*/
2618 hcryp->ErrorCallback(hcryp);
2619 #else
2620 /*Call legacy weak error callback*/
2621 HAL_CRYP_ErrorCallback(hcryp);
2622 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2623 }
2624 #ifdef HAL_MDMA_MODULE_ENABLED
2625 /**
2626 * @brief MDMA CRYP input data process complete callback.
2627 * @param hmdma: MDMA handle
2628 * @retval None
2629 */
CRYP_MDMAInCplt(MDMA_HandleTypeDef * hmdma)2630 static void CRYP_MDMAInCplt(MDMA_HandleTypeDef *hmdma)
2631 {
2632 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
2633
2634 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
2635 in the DMACR register */
2636 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
2637
2638 /* Call input data transfer complete callback */
2639 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2640 /*Call registered Input complete callback*/
2641 hcryp->InCpltCallback(hcryp);
2642 #else
2643 /*Call legacy weak Input complete callback*/
2644 HAL_CRYP_InCpltCallback(hcryp);
2645 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2646 }
2647
2648 /**
2649 * @brief MDMA CRYP output data process complete callback.
2650 * @param hmdma: MDMA handle
2651 * @retval None
2652 */
CRYP_MDMAOutCplt(MDMA_HandleTypeDef * hmdma)2653 static void CRYP_MDMAOutCplt(MDMA_HandleTypeDef *hmdma)
2654 {
2655 uint32_t count;
2656 uint32_t npblb;
2657 uint32_t lastwordsize;
2658 uint32_t temp; /* Temporary CrypOutBuff */
2659 uint32_t temp_cr_algodir;
2660 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
2661
2662 /* Disable the DMA transfer for output FIFO */
2663 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
2664
2665 /* Last block transfer in case of GCM or CCM with Size not %16*/
2666 if (((hcryp->Size) % 16U) != 0U)
2667 {
2668 /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
2669 hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
2670 hcryp->CrypOutCount = hcryp->CrypInCount;
2671
2672 /* Compute the number of padding bytes in last block of payload */
2673 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
2674
2675 /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
2676 temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
2677 if(((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
2678 ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
2679 {
2680 /* Disable the CRYP */
2681 __HAL_CRYP_DISABLE(hcryp);
2682
2683 /* Specify the number of non-valid bytes using NPBLB register*/
2684 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
2685
2686 /* Enable CRYP to start the final phase */
2687 __HAL_CRYP_ENABLE(hcryp);
2688 }
2689
2690 /* Number of valid words (lastwordsize) in last block */
2691 if ((npblb % 4U) == 0U)
2692 {
2693 lastwordsize = (16U - npblb) / 4U;
2694 }
2695 else
2696 {
2697 lastwordsize = ((16U - npblb) / 4U) + 1U;
2698 }
2699 /* Write the last input block in the IN FIFO */
2700 for(count = 0U; count < lastwordsize; count ++)
2701 {
2702 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
2703 hcryp->CrypInCount++;
2704 }
2705 /* Pad the data with zeros to have a complete block */
2706 while(count < 4U)
2707 {
2708 hcryp->Instance->DIN = 0U;
2709 count++;
2710 }
2711 /* Wait for OFNE flag to be raised */
2712 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
2713 do
2714 {
2715 count--;
2716 if(count == 0U)
2717 {
2718 /* Disable the CRYP peripheral clock */
2719 __HAL_CRYP_DISABLE(hcryp);
2720
2721 /* Change state */
2722 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2723 hcryp->State = HAL_CRYP_STATE_READY;
2724
2725 /* Process unlocked */
2726 __HAL_UNLOCK(hcryp);
2727 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2728 /*Call registered error callback*/
2729 hcryp->ErrorCallback(hcryp);
2730 #else
2731 /*Call legacy weak error callback*/
2732 HAL_CRYP_ErrorCallback(hcryp);
2733 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2734 }
2735 } while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
2736
2737 /*Read the output block from the output FIFO */
2738 for(count = 0U; count < 4U; count++)
2739 {
2740 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
2741 temp = hcryp->Instance->DOUT;
2742
2743 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= temp;
2744 hcryp->CrypOutCount++;
2745 }
2746 } /*End of last block transfer in case of GCM or CCM */
2747
2748 if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
2749 {
2750 /* Disable CRYP (not allowed in GCM)*/
2751 __HAL_CRYP_DISABLE(hcryp);
2752 }
2753
2754 /* Change the CRYP state to ready */
2755 hcryp->State = HAL_CRYP_STATE_READY;
2756
2757 /* Process unlocked */
2758 __HAL_UNLOCK(hcryp);
2759
2760 /* Call output data transfer complete callback */
2761 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2762 /*Call registered Output complete callback*/
2763 hcryp->OutCpltCallback(hcryp);
2764 #else
2765 /*Call legacy weak Output complete callback*/
2766 HAL_CRYP_OutCpltCallback(hcryp);
2767 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2768 }
2769
2770 /**
2771 * @brief MDMA CRYP communication error callback.
2772 * @param hmdma: MDMA handle
2773 * @retval None
2774 */
CRYP_MDMAError(MDMA_HandleTypeDef * hmdma)2775 static void CRYP_MDMAError(MDMA_HandleTypeDef *hmdma)
2776 {
2777 CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((MDMA_HandleTypeDef*)hmdma)->Parent;
2778
2779 /* Change the CRYP peripheral state */
2780 hcryp->State= HAL_CRYP_STATE_READY;
2781
2782 /* DMA error code field */
2783 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2784
2785 /* Call error callback */
2786 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2787 /*Call registered error callback*/
2788 hcryp->ErrorCallback(hcryp);
2789 #else
2790 /*Call legacy weak error callback*/
2791 HAL_CRYP_ErrorCallback(hcryp);
2792 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2793 }
2794 #endif
2795
2796 /**
2797 * @brief Set the DMA configuration and start the DMA transfer
2798 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2799 * the configuration information for CRYP module
2800 * @param inputaddr: address of the input buffer
2801 * @param Size: size of the input buffer, must be a multiple of 16.
2802 * @param outputaddr: address of the output buffer
2803 * @retval None
2804 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)2805 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2806 {
2807 /* Set the CRYP DMA transfer complete callback */
2808 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
2809
2810 /* Set the DMA input error callback */
2811 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
2812
2813 /* Set the CRYP DMA transfer complete callback */
2814 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
2815
2816 /* Set the DMA output error callback */
2817 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
2818
2819 /* Enable CRYP */
2820 __HAL_CRYP_ENABLE(hcryp);
2821
2822 /* Enable the input DMA Stream */
2823 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
2824 {
2825 /* DMA error code field */
2826 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2827
2828 /* Call error callback */
2829 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2830 /*Call registered error callback*/
2831 hcryp->ErrorCallback(hcryp);
2832 #else
2833 /*Call legacy weak error callback*/
2834 HAL_CRYP_ErrorCallback(hcryp);
2835 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2836 }
2837
2838 /* Enable the output DMA Stream */
2839 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
2840 {
2841 /* DMA error code field */
2842 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2843
2844 /* Call error callback */
2845 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2846 /*Call registered error callback*/
2847 hcryp->ErrorCallback(hcryp);
2848 #else
2849 /*Call legacy weak error callback*/
2850 HAL_CRYP_ErrorCallback(hcryp);
2851 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2852 }
2853 /* Enable In/Out DMA request */
2854 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
2855 }
2856 #ifdef HAL_MDMA_MODULE_ENABLED
2857 /**
2858 * @brief Set the MDMA configuration and start the MDMA transfer
2859 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2860 * the configuration information for CRYP module
2861 * @param inputaddr: address of the input buffer
2862 * @param Size: size of the input buffer, must be a multiple of 16.
2863 * @param outputaddr: address of the output buffer
2864 * @retval None
2865 */
CRYP_SetMDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)2866 static void CRYP_SetMDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
2867 {
2868 /* Set the CRYP DMA transfer complete callback */
2869 hcryp->hmdmain->XferCpltCallback = CRYP_MDMAInCplt;
2870
2871 /* Set the DMA input error callback */
2872 hcryp->hmdmain->XferErrorCallback = CRYP_MDMAError;
2873
2874 /* Set the CRYP DMA transfer complete callback */
2875 hcryp->hmdmaout->XferCpltCallback = CRYP_MDMAOutCplt;
2876
2877 /* Set the DMA output error callback */
2878 hcryp->hmdmaout->XferErrorCallback = CRYP_MDMAError;
2879
2880 /* Enable CRYP */
2881 __HAL_CRYP_ENABLE(hcryp);
2882
2883 /* Enable the input DMA Stream */
2884 if (HAL_MDMA_Start_IT(hcryp->hmdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, (Size * 4U), 1U) != HAL_OK)
2885 {
2886 /* DMA error code field */
2887 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2888
2889 /* Call error callback */
2890 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2891 /*Call registered error callback*/
2892 hcryp->ErrorCallback(hcryp);
2893 #else
2894 /*Call legacy weak error callback*/
2895 HAL_CRYP_ErrorCallback(hcryp);
2896 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2897 }
2898
2899 /* Enable the output DMA Stream */
2900 if (HAL_MDMA_Start_IT(hcryp->hmdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size * 4U, 1U) != HAL_OK)
2901 {
2902 /* DMA error code field */
2903 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
2904
2905 /* Call error callback */
2906 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2907 /*Call registered error callback*/
2908 hcryp->ErrorCallback(hcryp);
2909 #else
2910 /*Call legacy weak error callback*/
2911 HAL_CRYP_ErrorCallback(hcryp);
2912 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2913 }
2914 /* Enable In/Out DMA request */
2915 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
2916 }
2917 #endif
2918
2919 /**
2920 * @brief Process Data: Write Input data in polling mode and used in AES functions.
2921 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2922 * the configuration information for CRYP module
2923 * @param Timeout: Specify Timeout value
2924 * @retval None
2925 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2926 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2927 {
2928
2929 uint32_t temp[4]; /* Temporary CrypOutBuff */
2930 uint16_t incount; /* Temporary CrypInCount Value */
2931 uint16_t outcount; /* Temporary CrypOutCount Value */
2932 uint32_t i;
2933
2934 /*Temporary CrypOutCount Value*/
2935 incount = hcryp->CrypInCount;
2936
2937 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < ((hcryp->Size) / 4U)))
2938 {
2939 /* Write the input block in the IN FIFO */
2940 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2941 hcryp->CrypInCount++;
2942 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2943 hcryp->CrypInCount++;
2944 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2945 hcryp->CrypInCount++;
2946 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2947 hcryp->CrypInCount++;
2948 }
2949
2950 /* Wait for OFNE flag to be raised */
2951 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2952 {
2953 /* Disable the CRYP peripheral clock */
2954 __HAL_CRYP_DISABLE(hcryp);
2955
2956 /* Change state & error code*/
2957 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2958 hcryp->State = HAL_CRYP_STATE_READY;
2959
2960 /* Process unlocked */
2961 __HAL_UNLOCK(hcryp);
2962 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2963 /*Call registered error callback*/
2964 hcryp->ErrorCallback(hcryp);
2965 #else
2966 /*Call legacy weak error callback*/
2967 HAL_CRYP_ErrorCallback(hcryp);
2968 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2969 }
2970 /*Temporary CrypOutCount Value*/
2971 outcount = hcryp->CrypOutCount;
2972
2973 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
2974 {
2975 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
2976 for (i = 0U; i < 4U; i++)
2977 {
2978 temp[i] = hcryp->Instance->DOUT;
2979 }
2980 i = 0U;
2981 while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
2982 {
2983 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2984 hcryp->CrypOutCount++;
2985 i++;
2986 }
2987 }
2988 }
2989
2990 /**
2991 * @brief Handle CRYP block input/output data handling under interruption.
2992 * @note The function is called under interruption only, once
2993 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
2994 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2995 * the configuration information for CRYP module.
2996 * @retval HAL status
2997 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)2998 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
2999 {
3000 uint32_t temp[4]; /* Temporary CrypOutBuff */
3001 uint16_t incount; /* Temporary CrypInCount Value */
3002 uint16_t outcount; /* Temporary CrypOutCount Value */
3003 uint32_t i;
3004
3005 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3006 {
3007 /*Temporary CrypOutCount Value*/
3008 incount = hcryp->CrypInCount;
3009
3010 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3011 {
3012 /* Write the input block in the IN FIFO */
3013 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3014 hcryp->CrypInCount++;
3015 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3016 hcryp->CrypInCount++;
3017 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3018 hcryp->CrypInCount++;
3019 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3020 hcryp->CrypInCount++;
3021 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3022 {
3023 /* Disable interrupts */
3024 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3025
3026 /* Call the input data transfer complete callback */
3027 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3028 /*Call registered Input complete callback*/
3029 hcryp->InCpltCallback(hcryp);
3030 #else
3031 /*Call legacy weak Input complete callback*/
3032 HAL_CRYP_InCpltCallback(hcryp);
3033 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3034 }
3035 }
3036
3037 /*Temporary CrypOutCount Value*/
3038 outcount = hcryp->CrypOutCount;
3039
3040 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3041 {
3042 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3043 for (i = 0U; i < 4U; i++)
3044 {
3045 temp[i] = hcryp->Instance->DOUT;
3046 }
3047 i = 0U;
3048 while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
3049 {
3050 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3051 hcryp->CrypOutCount++;
3052 i++;
3053 }
3054 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3055 {
3056 /* Disable interrupts */
3057 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3058
3059 /* Change the CRYP state */
3060 hcryp->State = HAL_CRYP_STATE_READY;
3061
3062 /* Disable CRYP */
3063 __HAL_CRYP_DISABLE(hcryp);
3064
3065 /* Process unlocked */
3066 __HAL_UNLOCK(hcryp);
3067
3068 /* Call output transfer complete callback */
3069 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3070 /*Call registered Output complete callback*/
3071 hcryp->OutCpltCallback(hcryp);
3072 #else
3073 /*Call legacy weak Output complete callback*/
3074 HAL_CRYP_OutCpltCallback(hcryp);
3075 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3076 }
3077 }
3078 }
3079 else
3080 {
3081 /* Process unlocked */
3082 __HAL_UNLOCK(hcryp);
3083 /* Busy error code field */
3084 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3085 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3086 /*Call registered error callback*/
3087 hcryp->ErrorCallback(hcryp);
3088 #else
3089 /*Call legacy weak error callback*/
3090 HAL_CRYP_ErrorCallback(hcryp);
3091 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3092 }
3093 }
3094
3095 /**
3096 * @brief Writes Key in Key registers.
3097 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3098 * the configuration information for CRYP module
3099 * @param KeySize: Size of Key
3100 * @retval None
3101 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)3102 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3103 {
3104 switch (KeySize)
3105 {
3106 case CRYP_KEYSIZE_256B:
3107 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3108 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3109 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3110 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3111 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3112 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3113 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3114 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3115 break;
3116 case CRYP_KEYSIZE_192B:
3117 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3118 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3119 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3120 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3121 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3122 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3123 break;
3124 case CRYP_KEYSIZE_128B:
3125 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3126 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3127 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3128 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3129
3130 break;
3131 default:
3132 break;
3133 }
3134 }
3135
3136 /**
3137 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3138 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3139 * the configuration information for CRYP module
3140 * @param Timeout: Timeout duration
3141 * @retval HAL status
3142 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3143 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3144 {
3145 uint32_t tickstart;
3146 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
3147 uint32_t npblb ;
3148 uint32_t temp[4]; /* Temporary CrypOutBuff */
3149 uint32_t index ;
3150 uint32_t lastwordsize ;
3151 uint16_t outcount; /* Temporary CrypOutCount Value */
3152 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3153
3154 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3155 {
3156 if (hcryp->KeyIVConfig == 1U)
3157 {
3158 /* If the Key and IV configuration has to be done only once
3159 and if it has already been done, skip it */
3160 DoKeyIVConfig = 0U;
3161 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3162 }
3163 else
3164 {
3165 /* If the Key and IV configuration has to be done only once
3166 and if it has not been done already, do it and set KeyIVConfig
3167 to keep track it won't have to be done again next time */
3168 hcryp->KeyIVConfig = 1U;
3169 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3170 }
3171 }
3172 else
3173 {
3174 hcryp->SizesSum = hcryp->Size;
3175 }
3176
3177 if (DoKeyIVConfig == 1U)
3178 {
3179 /* Reset CrypHeaderCount */
3180 hcryp->CrypHeaderCount = 0U;
3181
3182 /****************************** Init phase **********************************/
3183
3184 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3185
3186 /* Set the key */
3187 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3188
3189 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3190 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3191 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3192 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3193 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3194
3195 /* Enable the CRYP peripheral */
3196 __HAL_CRYP_ENABLE(hcryp);
3197
3198 /* Get tick */
3199 tickstart = HAL_GetTick();
3200
3201 /*Wait for the CRYPEN bit to be cleared*/
3202 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3203 {
3204 /* Check for the Timeout */
3205 if (Timeout != HAL_MAX_DELAY)
3206 {
3207 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3208 {
3209 /* Disable the CRYP peripheral clock */
3210 __HAL_CRYP_DISABLE(hcryp);
3211
3212 /* Change state */
3213 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3214 hcryp->State = HAL_CRYP_STATE_READY;
3215
3216 /* Process unlocked */
3217 __HAL_UNLOCK(hcryp);
3218 return HAL_ERROR;
3219 }
3220 }
3221 }
3222
3223 /************************ Header phase *************************************/
3224
3225 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3226 {
3227 return HAL_ERROR;
3228 }
3229
3230 /*************************Payload phase ************************************/
3231
3232 /* Set the phase */
3233 hcryp->Phase = CRYP_PHASE_PROCESS;
3234
3235 /* Disable the CRYP peripheral */
3236 __HAL_CRYP_DISABLE(hcryp);
3237 /* Set to 0 the number of non-valid bytes using NPBLB register*/
3238 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
3239
3240 /* Select payload phase once the header phase is performed */
3241 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3242
3243 /* Enable the CRYP peripheral */
3244 __HAL_CRYP_ENABLE(hcryp);
3245 } /* if (DoKeyIVConfig == 1U) */
3246
3247 if ((hcryp->Size % 16U) != 0U)
3248 {
3249 /* recalculate wordsize */
3250 wordsize = ((wordsize / 4U) * 4U) ;
3251 }
3252
3253 /* Get tick */
3254 tickstart = HAL_GetTick();
3255 /*Temporary CrypOutCount Value*/
3256 outcount = hcryp->CrypOutCount;
3257
3258 /* Write input data and get output Data */
3259 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3260 {
3261 /* Write plain data and get cipher data */
3262 CRYP_AES_ProcessData(hcryp, Timeout);
3263
3264 /*Temporary CrypOutCount Value*/
3265 outcount = hcryp->CrypOutCount;
3266
3267 /* Check for the Timeout */
3268 if (Timeout != HAL_MAX_DELAY)
3269 {
3270 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3271 {
3272 /* Disable the CRYP peripheral clock */
3273 __HAL_CRYP_DISABLE(hcryp);
3274
3275 /* Change state & error code */
3276 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3277 hcryp->State = HAL_CRYP_STATE_READY;
3278
3279 /* Process unlocked */
3280 __HAL_UNLOCK(hcryp);
3281 return HAL_ERROR;
3282 }
3283 }
3284 }
3285
3286 if ((hcryp->Size % 16U) != 0U)
3287 {
3288 /* Compute the number of padding bytes in last block of payload */
3289 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
3290
3291 /* Set Npblb in case of AES GCM payload encryption to get right tag*/
3292 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
3293 {
3294 /* Disable the CRYP */
3295 __HAL_CRYP_DISABLE(hcryp);
3296
3297 /* Specify the number of non-valid bytes using NPBLB register*/
3298 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
3299
3300 /* Enable CRYP to start the final phase */
3301 __HAL_CRYP_ENABLE(hcryp);
3302 }
3303 /* Number of valid words (lastwordsize) in last block */
3304 if ((npblb % 4U) == 0U)
3305 {
3306 lastwordsize = (16U - npblb) / 4U;
3307 }
3308 else
3309 {
3310 lastwordsize = ((16U - npblb) / 4U) + 1U;
3311 }
3312
3313 /* Write the last input block in the IN FIFO */
3314 for (index = 0U; index < lastwordsize; index ++)
3315 {
3316 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3317 hcryp->CrypInCount++;
3318 }
3319
3320 /* Pad the data with zeros to have a complete block */
3321 while (index < 4U)
3322 {
3323 hcryp->Instance->DIN = 0U;
3324 index++;
3325 }
3326
3327 /* Wait for OFNE flag to be raised */
3328 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3329 {
3330 /* Disable the CRYP peripheral clock */
3331 __HAL_CRYP_DISABLE(hcryp);
3332
3333 /* Change state */
3334 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3335 hcryp->State = HAL_CRYP_STATE_READY;
3336
3337 /* Process Unlocked */
3338 __HAL_UNLOCK(hcryp);
3339 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3340 /*Call registered error callback*/
3341 hcryp->ErrorCallback(hcryp);
3342 #else
3343 /*Call legacy weak error callback*/
3344 HAL_CRYP_ErrorCallback(hcryp);
3345 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3346 }
3347
3348 /*Read the output block from the output FIFO */
3349 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
3350 {
3351 for (index = 0U; index < 4U; index++)
3352 {
3353 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3354 temp[index] = hcryp->Instance->DOUT;
3355 }
3356 for (index=0; index<lastwordsize; index++)
3357 {
3358 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
3359 hcryp->CrypOutCount++;
3360 }
3361 }
3362 }
3363
3364 /* Return function status */
3365 return HAL_OK;
3366 }
3367
3368 /**
3369 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3370 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3371 * the configuration information for CRYP module
3372 * @retval HAL status
3373 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)3374 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3375 {
3376 __IO uint32_t count = 0U;
3377 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3378
3379 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3380 {
3381 if (hcryp->KeyIVConfig == 1U)
3382 {
3383 /* If the Key and IV configuration has to be done only once
3384 and if it has already been done, skip it */
3385 DoKeyIVConfig = 0U;
3386 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3387 }
3388 else
3389 {
3390 /* If the Key and IV configuration has to be done only once
3391 and if it has not been done already, do it and set KeyIVConfig
3392 to keep track it won't have to be done again next time */
3393 hcryp->KeyIVConfig = 1U;
3394 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3395 }
3396 }
3397 else
3398 {
3399 hcryp->SizesSum = hcryp->Size;
3400 }
3401
3402 /* Configure Key, IV and process message (header and payload) */
3403 if (DoKeyIVConfig == 1U)
3404 {
3405 /* Reset CrypHeaderCount */
3406 hcryp->CrypHeaderCount = 0U;
3407
3408 /******************************* Init phase *********************************/
3409
3410 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3411
3412 /* Set the key */
3413 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3414
3415 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3416 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3417 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3418 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3419 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3420
3421 /* Enable the CRYP peripheral */
3422 __HAL_CRYP_ENABLE(hcryp);
3423
3424 /*Wait for the CRYPEN bit to be cleared*/
3425 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3426 do
3427 {
3428 count-- ;
3429 if (count == 0U)
3430 {
3431 /* Disable the CRYP peripheral clock */
3432 __HAL_CRYP_DISABLE(hcryp);
3433
3434 /* Change state */
3435 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3436 hcryp->State = HAL_CRYP_STATE_READY;
3437
3438 /* Process unlocked */
3439 __HAL_UNLOCK(hcryp);
3440 return HAL_ERROR;
3441 }
3442 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3443
3444 /***************************** Header phase *********************************/
3445
3446 /* Select header phase */
3447 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3448 } /* end of if (DoKeyIVConfig == 1U) */
3449 /* Enable interrupts */
3450 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
3451
3452 /* Enable CRYP */
3453 __HAL_CRYP_ENABLE(hcryp);
3454
3455 /* Return function status */
3456 return HAL_OK;
3457 }
3458
3459
3460 /**
3461 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
3462 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3463 * the configuration information for CRYP module
3464 * @retval HAL status
3465 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)3466 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
3467 {
3468 __IO uint32_t count = 0U;
3469 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3470 uint32_t index;
3471 uint32_t npblb;
3472 uint32_t lastwordsize;
3473 uint32_t temp[4]; /* Temporary CrypOutBuff */
3474 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3475
3476 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3477 {
3478 if (hcryp->KeyIVConfig == 1U)
3479 {
3480 /* If the Key and IV configuration has to be done only once
3481 and if it has already been done, skip it */
3482 DoKeyIVConfig = 0U;
3483 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3484 }
3485 else
3486 {
3487 /* If the Key and IV configuration has to be done only once
3488 and if it has not been done already, do it and set KeyIVConfig
3489 to keep track it won't have to be done again next time */
3490 hcryp->KeyIVConfig = 1U;
3491 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3492 }
3493 }
3494 else
3495 {
3496 hcryp->SizesSum = hcryp->Size;
3497 }
3498
3499 if (DoKeyIVConfig == 1U)
3500 {
3501 /* Reset CrypHeaderCount */
3502 hcryp->CrypHeaderCount = 0U;
3503
3504 /*************************** Init phase ************************************/
3505
3506 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3507
3508 /* Set the key */
3509 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3510
3511 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3512 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3513 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3514 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3515 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3516
3517 /* Enable the CRYP peripheral */
3518 __HAL_CRYP_ENABLE(hcryp);
3519
3520 /*Wait for the CRYPEN bit to be cleared*/
3521 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3522 do
3523 {
3524 count-- ;
3525 if (count == 0U)
3526 {
3527 /* Disable the CRYP peripheral clock */
3528 __HAL_CRYP_DISABLE(hcryp);
3529
3530 /* Change state */
3531 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3532 hcryp->State = HAL_CRYP_STATE_READY;
3533
3534 /* Process unlocked */
3535 __HAL_UNLOCK(hcryp);
3536 return HAL_ERROR;
3537 }
3538 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3539
3540 /************************ Header phase *************************************/
3541
3542 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
3543 {
3544 return HAL_ERROR;
3545 }
3546
3547 /************************ Payload phase ************************************/
3548
3549 /* Set the phase */
3550 hcryp->Phase = CRYP_PHASE_PROCESS;
3551
3552 /* Disable the CRYP peripheral */
3553 __HAL_CRYP_DISABLE(hcryp);
3554
3555 /* Set to 0 the number of non-valid bytes using NPBLB register*/
3556 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
3557
3558 /* Select payload phase once the header phase is performed */
3559 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3560
3561 } /* if (DoKeyIVConfig == 1U) */
3562
3563 if (hcryp->Size == 0U)
3564 {
3565 /* Process unLocked */
3566 __HAL_UNLOCK(hcryp);
3567
3568 /* Change the CRYP state and phase */
3569 hcryp->State = HAL_CRYP_STATE_READY;
3570 }
3571 else if (hcryp->Size >= 16U)
3572 {
3573 /* for STM32H7 below rev.B : Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
3574 Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise TAG is incorrectly generated */
3575
3576 /*DMA transfer must not include the last block in case of Size is not %16 */
3577 wordsize = wordsize - (wordsize % 4U);
3578
3579 /*DMA transfer */
3580 if (hcryp->hdmain != NULL)
3581 CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
3582 #ifdef HAL_MDMA_MODULE_ENABLED
3583 else if (hcryp->hmdmain != NULL)
3584 CRYP_SetMDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
3585 #endif
3586 }
3587 else /* length of input data is < 16 */
3588 {
3589 /* Compute the number of padding bytes in last block of payload */
3590 npblb = 16U - (uint32_t)hcryp->Size;
3591
3592 /* Set Npblb in case of AES GCM payload encryption to get right tag*/
3593 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
3594 {
3595 /* Specify the number of non-valid bytes using NPBLB register*/
3596 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
3597 }
3598 /* Enable CRYP to start the final phase */
3599 __HAL_CRYP_ENABLE(hcryp);
3600
3601 /* Number of valid words (lastwordsize) in last block */
3602 if ((npblb % 4U) == 0U)
3603 {
3604 lastwordsize = (16U - npblb) / 4U;
3605 }
3606 else
3607 {
3608 lastwordsize = ((16U - npblb) / 4U) + 1U;
3609 }
3610
3611 /* Write the last input block in the IN FIFO */
3612 for (index = 0; index < lastwordsize; index ++)
3613 {
3614 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3615 hcryp->CrypInCount++;
3616 }
3617
3618 /* Pad the data with zeros to have a complete block */
3619 while (index < 4U)
3620 {
3621 hcryp->Instance->DIN = 0U;
3622 index++;
3623 }
3624
3625 /* Wait for OFNE flag to be raised */
3626 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
3627 do
3628 {
3629 count-- ;
3630 if (count == 0U)
3631 {
3632 /* Disable the CRYP peripheral clock */
3633 __HAL_CRYP_DISABLE(hcryp);
3634
3635 /* Change state */
3636 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3637 hcryp->State = HAL_CRYP_STATE_READY;
3638
3639 /* Process unlocked */
3640 __HAL_UNLOCK(hcryp);
3641 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3642 /*Call registered error callback*/
3643 hcryp->ErrorCallback(hcryp);
3644 #else
3645 /*Call legacy weak error callback*/
3646 HAL_CRYP_ErrorCallback(hcryp);
3647 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3648 }
3649 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
3650
3651 /*Read the output block from the output FIFO */
3652 for (index = 0U; index < 4U; index++)
3653 {
3654 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3655 temp[index] = hcryp->Instance->DOUT;
3656 }
3657 for (index=0; index<lastwordsize; index++)
3658 {
3659 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
3660 hcryp->CrypOutCount++;
3661 }
3662
3663 /* Change the CRYP state to ready */
3664 hcryp->State = HAL_CRYP_STATE_READY;
3665
3666 /* Process unlocked */
3667 __HAL_UNLOCK(hcryp);
3668 }
3669
3670 /* Return function status */
3671 return HAL_OK;
3672 }
3673
3674
3675 /**
3676 * @brief AES CCM encryption/decryption processing in polling mode
3677 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3678 * the configuration information for CRYP module
3679 * @param Timeout: Timeout duration
3680 * @retval HAL status
3681 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3682 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3683 {
3684 uint32_t tickstart;
3685 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
3686 uint32_t npblb ;
3687 uint32_t lastwordsize ;
3688 uint32_t temp[4] ; /* Temporary CrypOutBuff */
3689 uint32_t index ;
3690 uint16_t outcount; /* Temporary CrypOutCount Value */
3691 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3692
3693 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3694 {
3695 if (hcryp->KeyIVConfig == 1U)
3696 {
3697 /* If the Key and IV configuration has to be done only once
3698 and if it has already been done, skip it */
3699 DoKeyIVConfig = 0U;
3700 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3701 }
3702 else
3703 {
3704 /* If the Key and IV configuration has to be done only once
3705 and if it has not been done already, do it and set KeyIVConfig
3706 to keep track it won't have to be done again next time */
3707 hcryp->KeyIVConfig = 1U;
3708 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3709 }
3710 }
3711 else
3712 {
3713 hcryp->SizesSum = hcryp->Size;
3714 }
3715
3716 if (DoKeyIVConfig == 1U)
3717 {
3718 /* Reset CrypHeaderCount */
3719 hcryp->CrypHeaderCount = 0U;
3720
3721 /********************** Init phase ******************************************/
3722
3723 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3724
3725 /* Set the key */
3726 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3727
3728 /* Set the initialization vector (IV) with CTR1 information */
3729 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
3730 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
3731 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
3732 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
3733
3734 /* Enable the CRYP peripheral */
3735 __HAL_CRYP_ENABLE(hcryp);
3736
3737 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
3738 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
3739 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
3740 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
3741 /* Get tick */
3742 tickstart = HAL_GetTick();
3743
3744 /*Wait for the CRYPEN bit to be cleared*/
3745 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3746 {
3747 /* Check for the Timeout */
3748 if (Timeout != HAL_MAX_DELAY)
3749 {
3750 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3751 {
3752 /* Disable the CRYP peripheral clock */
3753 __HAL_CRYP_DISABLE(hcryp);
3754
3755 /* Change state */
3756 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3757 hcryp->State = HAL_CRYP_STATE_READY;
3758
3759 /* Process unlocked */
3760 __HAL_UNLOCK(hcryp);
3761 return HAL_ERROR;
3762 }
3763 }
3764 }
3765
3766 /************************* Header phase *************************************/
3767 /* Header block(B1) : associated data length expressed in bytes concatenated
3768 with Associated Data (A)*/
3769
3770 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3771 {
3772 return HAL_ERROR;
3773 }
3774 /********************** Payload phase ***************************************/
3775
3776 /* Set the phase */
3777 hcryp->Phase = CRYP_PHASE_PROCESS;
3778
3779 /* Disable the CRYP peripheral */
3780 __HAL_CRYP_DISABLE(hcryp);
3781
3782 /* Set to 0 the number of non-valid bytes using NPBLB register*/
3783 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
3784
3785 /* Select payload phase once the header phase is performed */
3786 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3787
3788 /* Enable the CRYP peripheral */
3789 __HAL_CRYP_ENABLE(hcryp);
3790
3791 } /* if (DoKeyIVConfig == 1U) */
3792
3793 if ((hcryp->Size % 16U) != 0U)
3794 {
3795 /* recalculate wordsize */
3796 wordsize = ((wordsize / 4U) * 4U) ;
3797 }
3798 /* Get tick */
3799 tickstart = HAL_GetTick();
3800
3801 /*Temporary CrypOutCount Value*/
3802 outcount = hcryp->CrypOutCount;
3803
3804 /* Write input data and get output data */
3805 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3806 {
3807 /* Write plain data and get cipher data */
3808 CRYP_AES_ProcessData(hcryp, Timeout);
3809
3810 /*Temporary CrypOutCount Value*/
3811 outcount = hcryp->CrypOutCount;
3812
3813 /* Check for the Timeout */
3814 if (Timeout != HAL_MAX_DELAY)
3815 {
3816 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3817 {
3818 /* Disable the CRYP peripheral clock */
3819 __HAL_CRYP_DISABLE(hcryp);
3820
3821 /* Change state */
3822 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3823 hcryp->State = HAL_CRYP_STATE_READY;
3824
3825 /* Process unlocked */
3826 __HAL_UNLOCK(hcryp);
3827 return HAL_ERROR;
3828 }
3829 }
3830 }
3831
3832 if ((hcryp->Size % 16U) != 0U)
3833 {
3834 /* Compute the number of padding bytes in last block of payload */
3835 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
3836
3837 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
3838 {
3839 /* Disable the CRYP */
3840 __HAL_CRYP_DISABLE(hcryp);
3841
3842 /* Set Npblb in case of AES CCM payload decryption to get right tag */
3843 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
3844
3845 /* Enable CRYP to start the final phase */
3846 __HAL_CRYP_ENABLE(hcryp);
3847 }
3848
3849 /* Number of valid words (lastwordsize) in last block */
3850 if ((npblb % 4U) == 0U)
3851 {
3852 lastwordsize = (16U - npblb) / 4U;
3853 }
3854 else
3855 {
3856 lastwordsize = ((16U - npblb) / 4U) + 1U;
3857 }
3858
3859 /* Write the last input block in the IN FIFO */
3860 for (index = 0U; index < lastwordsize; index ++)
3861 {
3862 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3863 hcryp->CrypInCount++;
3864 }
3865
3866 /* Pad the data with zeros to have a complete block */
3867 while (index < 4U)
3868 {
3869 hcryp->Instance->DIN = 0U;
3870 index++;
3871 }
3872
3873 /* Wait for OFNE flag to be raised */
3874 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3875 {
3876 /* Disable the CRYP peripheral clock */
3877 __HAL_CRYP_DISABLE(hcryp);
3878
3879 /* Change state */
3880 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3881 hcryp->State = HAL_CRYP_STATE_READY;
3882
3883 /* Process Unlocked */
3884 __HAL_UNLOCK(hcryp);
3885 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3886 /*Call registered error callback*/
3887 hcryp->ErrorCallback(hcryp);
3888 #else
3889 /*Call legacy weak error callback*/
3890 HAL_CRYP_ErrorCallback(hcryp);
3891 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3892 }
3893
3894 /*Read the output block from the output FIFO */
3895 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
3896 {
3897 for (index = 0U; index < 4U; index++)
3898 {
3899 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3900 temp[index] = hcryp->Instance->DOUT;
3901 }
3902 for (index=0; index<lastwordsize; index++)
3903 {
3904 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
3905 hcryp->CrypOutCount++;
3906 }
3907 }
3908 }
3909
3910 /* Return function status */
3911 return HAL_OK;
3912 }
3913
3914 /**
3915 * @brief AES CCM encryption/decryption process in interrupt mode
3916 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3917 * the configuration information for CRYP module
3918 * @retval HAL status
3919 */
CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef * hcryp)3920 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3921 {
3922 __IO uint32_t count = 0U;
3923 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3924
3925 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3926 {
3927 if (hcryp->KeyIVConfig == 1U)
3928 {
3929 /* If the Key and IV configuration has to be done only once
3930 and if it has already been done, skip it */
3931 DoKeyIVConfig = 0U;
3932 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3933 }
3934 else
3935 {
3936 /* If the Key and IV configuration has to be done only once
3937 and if it has not been done already, do it and set KeyIVConfig
3938 to keep track it won't have to be done again next time */
3939 hcryp->KeyIVConfig = 1U;
3940 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3941 }
3942 }
3943 else
3944 {
3945 hcryp->SizesSum = hcryp->Size;
3946 }
3947
3948 /* Configure Key, IV and process message (header and payload) */
3949 if (DoKeyIVConfig == 1U)
3950 {
3951 /* Reset CrypHeaderCount */
3952 hcryp->CrypHeaderCount = 0U;
3953
3954 /************ Init phase ************/
3955
3956 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3957
3958 /* Set the key */
3959 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3960
3961 /* Set the initialization vector (IV) with CTR1 information */
3962 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
3963 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
3964 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
3965 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
3966
3967 /* Enable the CRYP peripheral */
3968 __HAL_CRYP_ENABLE(hcryp);
3969
3970 /*Write the B0 packet into CRYP_DR*/
3971 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
3972 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
3973 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
3974 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
3975
3976 /*Wait for the CRYPEN bit to be cleared*/
3977 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3978 do
3979 {
3980 count-- ;
3981 if (count == 0U)
3982 {
3983 /* Disable the CRYP peripheral clock */
3984 __HAL_CRYP_DISABLE(hcryp);
3985
3986 /* Change state */
3987 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3988 hcryp->State = HAL_CRYP_STATE_READY;
3989
3990 /* Process unlocked */
3991 __HAL_UNLOCK(hcryp);
3992 return HAL_ERROR;
3993 }
3994 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3995
3996 /* Select header phase */
3997 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3998 } /* end of if (DoKeyIVConfig == 1U) */
3999 /* Enable interrupts */
4000 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4001
4002 /* Enable CRYP */
4003 __HAL_CRYP_ENABLE(hcryp);
4004
4005 /* Return function status */
4006 return HAL_OK;
4007 }
4008 /**
4009 * @brief AES CCM encryption/decryption process in DMA mode
4010 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4011 * the configuration information for CRYP module
4012 * @retval HAL status
4013 */
CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4014 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4015 {
4016 __IO uint32_t count = 0U;
4017 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
4018 uint32_t index;
4019 uint32_t npblb;
4020 uint32_t lastwordsize;
4021 uint32_t temp[4]; /* Temporary CrypOutBuff */
4022 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4023
4024 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4025 {
4026 if (hcryp->KeyIVConfig == 1U)
4027 {
4028 /* If the Key and IV configuration has to be done only once
4029 and if it has already been done, skip it */
4030 DoKeyIVConfig = 0U;
4031 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4032 }
4033 else
4034 {
4035 /* If the Key and IV configuration has to be done only once
4036 and if it has not been done already, do it and set KeyIVConfig
4037 to keep track it won't have to be done again next time */
4038 hcryp->KeyIVConfig = 1U;
4039 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4040 }
4041 }
4042 else
4043 {
4044 hcryp->SizesSum = hcryp->Size;
4045 }
4046
4047 if (DoKeyIVConfig == 1U)
4048 {
4049 /* Reset CrypHeaderCount */
4050 hcryp->CrypHeaderCount = 0U;
4051
4052 /************************** Init phase **************************************/
4053
4054 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4055
4056 /* Set the key */
4057 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4058
4059 /* Set the initialization vector (IV) with CTR1 information */
4060 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4061 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4062 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4063 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4064
4065 /* Enable the CRYP peripheral */
4066 __HAL_CRYP_ENABLE(hcryp);
4067
4068 /*Write the B0 packet into CRYP_DR*/
4069 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4070 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4071 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4072 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4073
4074 /*Wait for the CRYPEN bit to be cleared*/
4075 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4076 do
4077 {
4078 count-- ;
4079 if (count == 0U)
4080 {
4081 /* Disable the CRYP peripheral clock */
4082 __HAL_CRYP_DISABLE(hcryp);
4083
4084 /* Change state */
4085 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4086 hcryp->State = HAL_CRYP_STATE_READY;
4087
4088 /* Process unlocked */
4089 __HAL_UNLOCK(hcryp);
4090 return HAL_ERROR;
4091 }
4092 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4093
4094 /********************* Header phase *****************************************/
4095
4096 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4097 {
4098 return HAL_ERROR;
4099 }
4100
4101 /******************** Payload phase *****************************************/
4102
4103 /* Set the phase */
4104 hcryp->Phase = CRYP_PHASE_PROCESS;
4105
4106 /* Disable the CRYP peripheral */
4107 __HAL_CRYP_DISABLE(hcryp);
4108
4109 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4110 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
4111
4112 /* Select payload phase once the header phase is performed */
4113 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4114 } /* if (DoKeyIVConfig == 1U) */
4115
4116 if (hcryp->Size == 0U)
4117 {
4118 /* Process unLocked */
4119 __HAL_UNLOCK(hcryp);
4120
4121 /* Change the CRYP state and phase */
4122 hcryp->State = HAL_CRYP_STATE_READY;
4123 }
4124 else if (hcryp->Size >= 16U)
4125 {
4126 /* for STM32H7 below rev.B :: Size should be %4 otherwise Tag will be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/
4127 /*DMA transfer must not include the last block in case of Size is not %16 */
4128 wordsize = wordsize - (wordsize % 4U);
4129
4130 /*DMA transfer */
4131 if (hcryp->hdmain != NULL)
4132 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
4133 #ifdef HAL_MDMA_MODULE_ENABLED
4134 else if (hcryp->hmdmain != NULL)
4135 CRYP_SetMDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
4136 #endif
4137 }
4138 else /* length of input data is < 16U */
4139 {
4140 /* Compute the number of padding bytes in last block of payload */
4141 npblb = 16U - (uint32_t)(hcryp->Size);
4142
4143 /* Set Npblb in case of AES CCM payload decryption to get right tag*/
4144 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
4145 {
4146 /* Specify the number of non-valid bytes using NPBLB register*/
4147 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
4148 }
4149 /* Enable CRYP to start the final phase */
4150 __HAL_CRYP_ENABLE(hcryp);
4151
4152 /* Number of valid words (lastwordsize) in last block */
4153 if ((npblb % 4U) == 0U)
4154 {
4155 lastwordsize = (16U - npblb) / 4U;
4156 }
4157 else
4158 {
4159 lastwordsize = ((16U - npblb) / 4U) + 1U;
4160 }
4161
4162 /* Write the last input block in the IN FIFO */
4163 for (index = 0U; index < lastwordsize; index ++)
4164 {
4165 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4166 hcryp->CrypInCount++;
4167 }
4168
4169 /* Pad the data with zeros to have a complete block */
4170 while (index < 4U)
4171 {
4172 hcryp->Instance->DIN = 0U;
4173 index++;
4174 }
4175
4176 /* Wait for OFNE flag to be raised */
4177 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
4178 do
4179 {
4180 count-- ;
4181 if (count == 0U)
4182 {
4183 /* Disable the CRYP peripheral clock */
4184 __HAL_CRYP_DISABLE(hcryp);
4185
4186 /* Change state */
4187 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4188 hcryp->State = HAL_CRYP_STATE_READY;
4189
4190 /* Process unlocked */
4191 __HAL_UNLOCK(hcryp);
4192 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4193 /*Call registered error callback*/
4194 hcryp->ErrorCallback(hcryp);
4195 #else
4196 /*Call legacy weak error callback*/
4197 HAL_CRYP_ErrorCallback(hcryp);
4198 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4199 }
4200 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
4201
4202 /*Read the output block from the output FIFO */
4203 for (index = 0U; index < 4U; index++)
4204 {
4205 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
4206 temp[index] = hcryp->Instance->DOUT;
4207 }
4208 for (index=0; index<lastwordsize; index++)
4209 {
4210 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
4211 hcryp->CrypOutCount++;
4212 }
4213
4214 /* Change the CRYP state to ready */
4215 hcryp->State = HAL_CRYP_STATE_READY;
4216
4217 /* Process unlocked */
4218 __HAL_UNLOCK(hcryp);
4219 }
4220
4221 /* Return function status */
4222 return HAL_OK;
4223 }
4224
4225 /**
4226 * @brief Sets the payload phase in interrupt mode
4227 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4228 * the configuration information for CRYP module
4229 * @retval state
4230 */
CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef * hcryp)4231 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
4232 {
4233 uint32_t loopcounter;
4234 uint32_t temp[4]; /* Temporary CrypOutBuff */
4235 uint32_t lastwordsize;
4236 uint32_t npblb;
4237 uint32_t temp_cr_algodir;
4238 uint8_t negative = 0U;
4239 uint32_t i;
4240
4241 /***************************** Payload phase *******************************/
4242
4243 if ((hcryp->Size / 4U) < hcryp->CrypInCount)
4244 {
4245 negative = 1U;
4246 }
4247
4248 if (hcryp->Size == 0U)
4249 {
4250 /* Disable interrupts */
4251 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
4252
4253 /* Process unlocked */
4254 __HAL_UNLOCK(hcryp);
4255
4256 /* Change the CRYP state */
4257 hcryp->State = HAL_CRYP_STATE_READY;
4258 }
4259
4260 else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
4261 (negative == 0U))
4262 {
4263 if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
4264 {
4265 /* Write the input block in the IN FIFO */
4266 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4267 hcryp->CrypInCount++;
4268 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4269 hcryp->CrypInCount++;
4270 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4271 hcryp->CrypInCount++;
4272 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4273 hcryp->CrypInCount++;
4274 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
4275 {
4276 /* Disable interrupts */
4277 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
4278 /* Call the input data transfer complete callback */
4279 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4280 /*Call registered Input complete callback*/
4281 hcryp->InCpltCallback(hcryp);
4282 #else
4283 /*Call legacy weak Input complete callback*/
4284 HAL_CRYP_InCpltCallback(hcryp);
4285 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4286 }
4287
4288 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
4289 {
4290 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
4291 {
4292 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
4293 for (i = 0U; i < 4U; i++)
4294 {
4295 temp[i] = hcryp->Instance->DOUT;
4296 }
4297 i = 0U;
4298 while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
4299 {
4300 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
4301 hcryp->CrypOutCount++;
4302 i++;
4303 }
4304 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
4305 {
4306 /* Disable interrupts */
4307 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
4308
4309 /* Change the CRYP state */
4310 hcryp->State = HAL_CRYP_STATE_READY;
4311
4312 /* Disable CRYP */
4313 __HAL_CRYP_DISABLE(hcryp);
4314
4315 /* Process unlocked */
4316 __HAL_UNLOCK(hcryp);
4317
4318 /* Call output transfer complete callback */
4319 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4320 /*Call registered Output complete callback*/
4321 hcryp->OutCpltCallback(hcryp);
4322 #else
4323 /*Call legacy weak Output complete callback*/
4324 HAL_CRYP_OutCpltCallback(hcryp);
4325 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4326 }
4327 }
4328 }
4329 }
4330 }
4331 else if ((hcryp->Size % 16U) != 0U)
4332 {
4333 /* Set padding only in case of input fifo interrupt */
4334 if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
4335 {
4336 /* Compute the number of padding bytes in last block of payload */
4337 npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4338
4339 /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
4340 temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
4341
4342 if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
4343 ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
4344 {
4345 /* Disable the CRYP */
4346 __HAL_CRYP_DISABLE(hcryp);
4347
4348 /* Specify the number of non-valid bytes using NPBLB register*/
4349 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
4350
4351 /* Enable CRYP to start the final phase */
4352 __HAL_CRYP_ENABLE(hcryp);
4353 }
4354
4355 /* Number of valid words (lastwordsize) in last block */
4356 if ((npblb % 4U) == 0U)
4357 {
4358 lastwordsize = (16U - npblb) / 4U;
4359 }
4360 else
4361 {
4362 lastwordsize = ((16U - npblb) / 4U) + 1U;
4363 }
4364
4365 /* Write the last input block in the IN FIFO */
4366 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
4367 {
4368 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4369 hcryp->CrypInCount++;
4370 }
4371 /* Pad the data with zeros to have a complete block */
4372 while (loopcounter < 4U)
4373 {
4374 hcryp->Instance->DIN = 0U;
4375 loopcounter++;
4376 }
4377
4378 /* Disable the input FIFO Interrupt */
4379 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
4380 }
4381
4382 /*Read the output block from the output FIFO */
4383 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
4384 {
4385 for (i = 0U; i < 4U; i++)
4386 {
4387 temp[i] = hcryp->Instance->DOUT;
4388 }
4389 if (( (hcryp->Size)/4U)==0U)
4390 {
4391 for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++)
4392 {
4393 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
4394 hcryp->CrypOutCount++;
4395 }
4396 }
4397 i = 0U;
4398 while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
4399 {
4400 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
4401 hcryp->CrypOutCount++;
4402 i++;
4403 }
4404 }
4405
4406 /* Disable the output FIFO Interrupt */
4407 if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
4408 {
4409 /* Disable interrupts */
4410 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
4411
4412 /* Change the CRYP peripheral state */
4413 hcryp->State = HAL_CRYP_STATE_READY;
4414
4415 /* Process unlocked */
4416 __HAL_UNLOCK(hcryp);
4417
4418 /* Call output transfer complete callback */
4419 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
4420 /*Call registered Output complete callback*/
4421 hcryp->OutCpltCallback(hcryp);
4422 #else
4423 /*Call legacy weak Output complete callback*/
4424 HAL_CRYP_OutCpltCallback(hcryp);
4425 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4426 }
4427 }
4428 else
4429 {
4430 /* Nothing to do */
4431 }
4432 }
4433
4434
4435 /**
4436 * @brief Sets the header phase in polling mode
4437 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4438 * the configuration information for CRYP module(Header & HeaderSize)
4439 * @param Timeout: Timeout value
4440 * @retval state
4441 */
CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4442 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4443 {
4444 uint32_t loopcounter;
4445
4446 /***************************** Header phase for GCM/GMAC or CCM *********************************/
4447
4448 if ((hcryp->Init.HeaderSize != 0U))
4449 {
4450 /* Select header phase */
4451 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4452
4453 /* Enable the CRYP peripheral */
4454 __HAL_CRYP_ENABLE(hcryp);
4455
4456 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4457 {
4458 /* HeaderSize %4, no padding */
4459 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4460 {
4461 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4462 hcryp->CrypHeaderCount++ ;
4463 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4464 hcryp->CrypHeaderCount++ ;
4465 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4466 hcryp->CrypHeaderCount++ ;
4467 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4468 hcryp->CrypHeaderCount++ ;
4469
4470 /* Wait for IFEM to be raised */
4471 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
4472 {
4473 /* Disable the CRYP peripheral clock */
4474 __HAL_CRYP_DISABLE(hcryp);
4475
4476 /* Change state */
4477 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4478 hcryp->State = HAL_CRYP_STATE_READY;
4479
4480 /* Process unlocked */
4481 __HAL_UNLOCK(hcryp);
4482 return HAL_ERROR;
4483 }
4484 }
4485 }
4486 else
4487 {
4488 /*Write header block in the IN FIFO without last block */
4489 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4490 {
4491 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4492 hcryp->CrypHeaderCount++ ;
4493 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4494 hcryp->CrypHeaderCount++ ;
4495 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4496 hcryp->CrypHeaderCount++ ;
4497 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4498 hcryp->CrypHeaderCount++ ;
4499
4500 /* Wait for IFEM to be raised */
4501 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
4502 {
4503 /* Disable the CRYP peripheral clock */
4504 __HAL_CRYP_DISABLE(hcryp);
4505
4506 /* Change state */
4507 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4508 hcryp->State = HAL_CRYP_STATE_READY;
4509
4510 /* Process unlocked */
4511 __HAL_UNLOCK(hcryp);
4512 return HAL_ERROR;
4513 }
4514 }
4515 /* Last block optionally pad the data with zeros*/
4516 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4517 {
4518 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4519 hcryp->CrypHeaderCount++ ;
4520 }
4521 while (loopcounter < 4U)
4522 {
4523 /* pad the data with zeros to have a complete block */
4524 hcryp->Instance->DIN = 0x0U;
4525 loopcounter++;
4526 }
4527 /* Wait for CCF IFEM to be raised */
4528 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
4529 {
4530 /* Disable the CRYP peripheral clock */
4531 __HAL_CRYP_DISABLE(hcryp);
4532
4533 /* Change state */
4534 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4535 hcryp->State = HAL_CRYP_STATE_READY;
4536
4537 /* Process unlocked */
4538 __HAL_UNLOCK(hcryp);
4539 return HAL_ERROR;
4540 }
4541 }
4542 /* Wait until the complete message has been processed */
4543 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
4544 {
4545 /* Disable the CRYP peripheral clock */
4546 __HAL_CRYP_DISABLE(hcryp);
4547
4548 /* Change state */
4549 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4550 hcryp->State = HAL_CRYP_STATE_READY;
4551
4552 /* Process unlocked & return error */
4553 __HAL_UNLOCK(hcryp);
4554 return HAL_ERROR;
4555 }
4556 }
4557 /* Return function status */
4558 return HAL_OK;
4559 }
4560
4561 /**
4562 * @brief Sets the header phase when using DMA in process
4563 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4564 * the configuration information for CRYP module(Header & HeaderSize)
4565 * @retval None
4566 */
CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef * hcryp)4567 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
4568 {
4569 __IO uint32_t count = 0U;
4570 uint32_t loopcounter;
4571
4572 /***************************** Header phase for GCM/GMAC or CCM *********************************/
4573 if ((hcryp->Init.HeaderSize != 0U))
4574 {
4575 /* Select header phase */
4576 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4577
4578 /* Enable the CRYP peripheral */
4579 __HAL_CRYP_ENABLE(hcryp);
4580
4581 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4582 {
4583 /* HeaderSize %4, no padding */
4584 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4585 {
4586 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4587 hcryp->CrypHeaderCount++ ;
4588 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4589 hcryp->CrypHeaderCount++ ;
4590 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4591 hcryp->CrypHeaderCount++ ;
4592 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4593 hcryp->CrypHeaderCount++ ;
4594
4595 /* Wait for IFEM to be raised */
4596 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
4597 do
4598 {
4599 count-- ;
4600 if (count == 0U)
4601 {
4602 /* Disable the CRYP peripheral clock */
4603 __HAL_CRYP_DISABLE(hcryp);
4604
4605 /* Change state */
4606 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4607 hcryp->State = HAL_CRYP_STATE_READY;
4608
4609 /* Process unlocked */
4610 __HAL_UNLOCK(hcryp);
4611 return HAL_ERROR;
4612 }
4613 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
4614 }
4615 }
4616 else
4617 {
4618 /*Write header block in the IN FIFO without last block */
4619 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4620 {
4621 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4622 hcryp->CrypHeaderCount++ ;
4623 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4624 hcryp->CrypHeaderCount++ ;
4625 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4626 hcryp->CrypHeaderCount++ ;
4627 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4628 hcryp->CrypHeaderCount++ ;
4629
4630 /* Wait for IFEM to be raised */
4631 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
4632 do
4633 {
4634 count-- ;
4635 if (count == 0U)
4636 {
4637 /* Disable the CRYP peripheral clock */
4638 __HAL_CRYP_DISABLE(hcryp);
4639
4640 /* Change state */
4641 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4642 hcryp->State = HAL_CRYP_STATE_READY;
4643
4644 /* Process unlocked */
4645 __HAL_UNLOCK(hcryp);
4646 return HAL_ERROR;
4647 }
4648 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
4649 }
4650 /* Last block optionally pad the data with zeros*/
4651 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4652 {
4653 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4654 hcryp->CrypHeaderCount++ ;
4655 }
4656 while (loopcounter < 4U)
4657 {
4658 /* Pad the data with zeros to have a complete block */
4659 hcryp->Instance->DIN = 0x0U;
4660 loopcounter++;
4661 }
4662 /* Wait for IFEM to be raised */
4663 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
4664 do
4665 {
4666 count-- ;
4667 if (count == 0U)
4668 {
4669 /* Disable the CRYP peripheral clock */
4670 __HAL_CRYP_DISABLE(hcryp);
4671 /* Change state */
4672 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4673 hcryp->State = HAL_CRYP_STATE_READY;
4674 /* Process unlocked */
4675 __HAL_UNLOCK(hcryp);
4676 return HAL_ERROR;
4677 }
4678 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
4679 }
4680 /* Wait until the complete message has been processed */
4681 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
4682 do
4683 {
4684 count-- ;
4685 if (count == 0U)
4686 {
4687 /* Disable the CRYP peripheral clock */
4688 __HAL_CRYP_DISABLE(hcryp);
4689 /* Change state */
4690 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4691 hcryp->State = HAL_CRYP_STATE_READY;
4692 /* Process unlocked */
4693 __HAL_UNLOCK(hcryp);
4694 return HAL_ERROR;
4695 }
4696 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
4697 }
4698
4699 /* Return function status */
4700 return HAL_OK;
4701 }
4702
4703 /**
4704 * @brief Sets the header phase in interrupt mode
4705 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4706 * the configuration information for CRYP module(Header & HeaderSize)
4707 * @retval None
4708 */
CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef * hcryp)4709 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
4710 {
4711 uint32_t loopcounter;
4712
4713 /***************************** Header phase *********************************/
4714
4715 if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount)
4716 {
4717 /* Disable interrupts */
4718 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
4719
4720 /* Disable the CRYP peripheral */
4721 __HAL_CRYP_DISABLE(hcryp);
4722
4723 /* Set to 0 the number of non-valid bytes using NPBLB register*/
4724 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
4725
4726 /* Set the phase */
4727 hcryp->Phase = CRYP_PHASE_PROCESS;
4728
4729 /* Select payload phase once the header phase is performed */
4730 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4731
4732 /* Enable Interrupts */
4733 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
4734
4735 /* Enable the CRYP peripheral */
4736 __HAL_CRYP_ENABLE(hcryp);
4737 }
4738 else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)
4739
4740 {
4741 /* HeaderSize %4, no padding */
4742 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4743 hcryp->CrypHeaderCount++ ;
4744 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4745 hcryp->CrypHeaderCount++ ;
4746 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4747 hcryp->CrypHeaderCount++ ;
4748 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4749 hcryp->CrypHeaderCount++ ;
4750 }
4751 else
4752 {
4753 /* Last block optionally pad the data with zeros*/
4754 for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++)
4755 {
4756 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4757 hcryp->CrypHeaderCount++ ;
4758 }
4759 while (loopcounter < 4U)
4760 {
4761 /* Pad the data with zeros to have a complete block */
4762 hcryp->Instance->DIN = 0x0U;
4763 loopcounter++;
4764 }
4765 }
4766 }
4767
4768 /**
4769 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
4770 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4771 * the configuration information for CRYP module.
4772 * @param Timeout: Timeout duration.
4773 * @retval HAL status
4774 */
CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4775 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4776 {
4777 uint32_t tickstart;
4778
4779 /* Get timeout */
4780 tickstart = HAL_GetTick();
4781
4782 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
4783 {
4784 /* Check for the Timeout */
4785 if (Timeout != HAL_MAX_DELAY)
4786 {
4787 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4788 {
4789 return HAL_ERROR;
4790 }
4791 }
4792 }
4793 return HAL_OK;
4794 }
4795 /**
4796 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
4797 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4798 * the configuration information for CRYP module.
4799 * @param Timeout: Timeout duration.
4800 * @retval HAL status
4801 */
CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4802 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4803 {
4804 uint32_t tickstart;
4805
4806 /* Get timeout */
4807 tickstart = HAL_GetTick();
4808
4809 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
4810 {
4811 /* Check for the Timeout */
4812 if (Timeout != HAL_MAX_DELAY)
4813 {
4814 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4815 {
4816 return HAL_ERROR;
4817 }
4818 }
4819 }
4820 return HAL_OK;
4821 }
4822
4823
4824 /**
4825 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
4826 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4827 * the configuration information for CRYP module.
4828 * @param Timeout: Timeout duration.
4829 * @retval HAL status
4830 */
CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4831 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4832 {
4833 uint32_t tickstart;
4834
4835 /* Get timeout */
4836 tickstart = HAL_GetTick();
4837
4838 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
4839 {
4840 /* Check for the Timeout */
4841 if (Timeout != HAL_MAX_DELAY)
4842 {
4843 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4844 {
4845 return HAL_ERROR;
4846 }
4847 }
4848 }
4849 return HAL_OK;
4850 }
4851
4852
4853 /**
4854 * @}
4855 */
4856
4857
4858
4859 /**
4860 * @}
4861 */
4862
4863 /**
4864 * @}
4865 */
4866
4867 #endif /* HAL_CRYP_MODULE_ENABLED */
4868
4869
4870 /**
4871 * @}
4872 */
4873 #endif /* CRYP1 || CRYP2 */
4874 /**
4875 * @}
4876 */
4877
