1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L5xx_LL_TIM_H
21 #define __STM32L5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_OR2 register */
122 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR1_RMP_SHIFT 16U
127 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
128 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
129 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
130 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
131 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
132 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
133 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
134 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
135
136 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
137 #define DT_DELAY_1 ((uint8_t)0x7F)
138 #define DT_DELAY_2 ((uint8_t)0x3F)
139 #define DT_DELAY_3 ((uint8_t)0x1F)
140 #define DT_DELAY_4 ((uint8_t)0x1F)
141
142 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
143 #define DT_RANGE_1 ((uint8_t)0x00)
144 #define DT_RANGE_2 ((uint8_t)0x80)
145 #define DT_RANGE_3 ((uint8_t)0xC0)
146 #define DT_RANGE_4 ((uint8_t)0xE0)
147
148 /** Legacy definitions for compatibility purpose
149 @cond 0
150 */
151 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
152 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
153 /**
154 @endcond
155 */
156
157 /**
158 * @}
159 */
160
161 /* Private macros ------------------------------------------------------------*/
162 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
163 * @{
164 */
165 /** @brief Convert channel id into channel index.
166 * @param __CHANNEL__ This parameter can be one of the following values:
167 * @arg @ref LL_TIM_CHANNEL_CH1
168 * @arg @ref LL_TIM_CHANNEL_CH1N
169 * @arg @ref LL_TIM_CHANNEL_CH2
170 * @arg @ref LL_TIM_CHANNEL_CH2N
171 * @arg @ref LL_TIM_CHANNEL_CH3
172 * @arg @ref LL_TIM_CHANNEL_CH3N
173 * @arg @ref LL_TIM_CHANNEL_CH4
174 * @arg @ref LL_TIM_CHANNEL_CH5
175 * @arg @ref LL_TIM_CHANNEL_CH6
176 * @retval none
177 */
178 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
179 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
186 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
187
188 /** @brief Calculate the deadtime sampling period(in ps).
189 * @param __TIMCLK__ timer input clock frequency (in Hz).
190 * @param __CKD__ This parameter can be one of the following values:
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
192 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
193 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
194 * @retval none
195 */
196 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
197 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
198 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
199 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
200 /**
201 * @}
202 */
203
204
205 /* Exported types ------------------------------------------------------------*/
206 #if defined(USE_FULL_LL_DRIVER)
207 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
208 * @{
209 */
210
211 /**
212 * @brief TIM Time Base configuration structure definition.
213 */
214 typedef struct
215 {
216 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
217 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
218
219 This feature can be modified afterwards using unitary function
220 @ref LL_TIM_SetPrescaler().*/
221
222 uint32_t CounterMode; /*!< Specifies the counter mode.
223 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
224
225 This feature can be modified afterwards using unitary function
226 @ref LL_TIM_SetCounterMode().*/
227
228 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
229 Auto-Reload Register at the next update event.
230 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
231 Some timer instances may support 32 bits counters. In that case this parameter must
232 be a number between 0x0000 and 0xFFFFFFFF.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_SetAutoReload().*/
236
237 uint32_t ClockDivision; /*!< Specifies the clock division.
238 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
239
240 This feature can be modified afterwards using unitary function
241 @ref LL_TIM_SetClockDivision().*/
242
243 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
244 reaches zero, an update event is generated and counting restarts
245 from the RCR value (N).
246 This means in PWM mode that (N+1) corresponds to:
247 - the number of PWM periods in edge-aligned mode
248 - the number of half PWM period in center-aligned mode
249 GP timers: this parameter must be a number between Min_Data = 0x00 and
250 Max_Data = 0xFF.
251 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
252 Max_Data = 0xFFFF.
253
254 This feature can be modified afterwards using unitary function
255 @ref LL_TIM_SetRepetitionCounter().*/
256 } LL_TIM_InitTypeDef;
257
258 /**
259 * @brief TIM Output Compare configuration structure definition.
260 */
261 typedef struct
262 {
263 uint32_t OCMode; /*!< Specifies the output mode.
264 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
265
266 This feature can be modified afterwards using unitary function
267 @ref LL_TIM_OC_SetMode().*/
268
269 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
270 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
271
272 This feature can be modified afterwards using unitary functions
273 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
274
275 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
276 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
277
278 This feature can be modified afterwards using unitary functions
279 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
280
281 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
282 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
283
284 This feature can be modified afterwards using unitary function
285 LL_TIM_OC_SetCompareCHx (x=1..6).*/
286
287 uint32_t OCPolarity; /*!< Specifies the output polarity.
288 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
289
290 This feature can be modified afterwards using unitary function
291 @ref LL_TIM_OC_SetPolarity().*/
292
293 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
294 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
295
296 This feature can be modified afterwards using unitary function
297 @ref LL_TIM_OC_SetPolarity().*/
298
299
300 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
301 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_OC_SetIdleState().*/
305
306 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
307 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
308
309 This feature can be modified afterwards using unitary function
310 @ref LL_TIM_OC_SetIdleState().*/
311 } LL_TIM_OC_InitTypeDef;
312
313 /**
314 * @brief TIM Input Capture configuration structure definition.
315 */
316
317 typedef struct
318 {
319
320 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
321 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
322
323 This feature can be modified afterwards using unitary function
324 @ref LL_TIM_IC_SetPolarity().*/
325
326 uint32_t ICActiveInput; /*!< Specifies the input.
327 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
328
329 This feature can be modified afterwards using unitary function
330 @ref LL_TIM_IC_SetActiveInput().*/
331
332 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
333 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
334
335 This feature can be modified afterwards using unitary function
336 @ref LL_TIM_IC_SetPrescaler().*/
337
338 uint32_t ICFilter; /*!< Specifies the input capture filter.
339 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
340
341 This feature can be modified afterwards using unitary function
342 @ref LL_TIM_IC_SetFilter().*/
343 } LL_TIM_IC_InitTypeDef;
344
345
346 /**
347 * @brief TIM Encoder interface configuration structure definition.
348 */
349 typedef struct
350 {
351 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
352 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
353
354 This feature can be modified afterwards using unitary function
355 @ref LL_TIM_SetEncoderMode().*/
356
357 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
358 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
359
360 This feature can be modified afterwards using unitary function
361 @ref LL_TIM_IC_SetPolarity().*/
362
363 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
364 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
365
366 This feature can be modified afterwards using unitary function
367 @ref LL_TIM_IC_SetActiveInput().*/
368
369 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
370 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
371
372 This feature can be modified afterwards using unitary function
373 @ref LL_TIM_IC_SetPrescaler().*/
374
375 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
376 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
377
378 This feature can be modified afterwards using unitary function
379 @ref LL_TIM_IC_SetFilter().*/
380
381 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
382 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
383
384 This feature can be modified afterwards using unitary function
385 @ref LL_TIM_IC_SetPolarity().*/
386
387 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
388 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
389
390 This feature can be modified afterwards using unitary function
391 @ref LL_TIM_IC_SetActiveInput().*/
392
393 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
394 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
395
396 This feature can be modified afterwards using unitary function
397 @ref LL_TIM_IC_SetPrescaler().*/
398
399 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
400 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
401
402 This feature can be modified afterwards using unitary function
403 @ref LL_TIM_IC_SetFilter().*/
404
405 } LL_TIM_ENCODER_InitTypeDef;
406
407 /**
408 * @brief TIM Hall sensor interface configuration structure definition.
409 */
410 typedef struct
411 {
412
413 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
414 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
415
416 This feature can be modified afterwards using unitary function
417 @ref LL_TIM_IC_SetPolarity().*/
418
419 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
420 Prescaler must be set to get a maximum counter period longer than the
421 time interval between 2 consecutive changes on the Hall inputs.
422 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
423
424 This feature can be modified afterwards using unitary function
425 @ref LL_TIM_IC_SetPrescaler().*/
426
427 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
428 This parameter can be a value of
429 @ref TIM_LL_EC_IC_FILTER.
430
431 This feature can be modified afterwards using unitary function
432 @ref LL_TIM_IC_SetFilter().*/
433
434 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
435 A positive pulse (TRGO event) is generated with a programmable delay every time
436 a change occurs on the Hall inputs.
437 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
438
439 This feature can be modified afterwards using unitary function
440 @ref LL_TIM_OC_SetCompareCH2().*/
441 } LL_TIM_HALLSENSOR_InitTypeDef;
442
443 /**
444 * @brief BDTR (Break and Dead Time) structure definition
445 */
446 typedef struct
447 {
448 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
449 This parameter can be a value of @ref TIM_LL_EC_OSSR
450
451 This feature can be modified afterwards using unitary function
452 @ref LL_TIM_SetOffStates()
453
454 @note This bit-field cannot be modified as long as LOCK level 2 has been
455 programmed. */
456
457 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
458 This parameter can be a value of @ref TIM_LL_EC_OSSI
459
460 This feature can be modified afterwards using unitary function
461 @ref LL_TIM_SetOffStates()
462
463 @note This bit-field cannot be modified as long as LOCK level 2 has been
464 programmed. */
465
466 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
467 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
468
469 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
470 register has been written, their content is frozen until the next reset.*/
471
472 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
473 switching-on of the outputs.
474 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
475
476 This feature can be modified afterwards using unitary function
477 @ref LL_TIM_OC_SetDeadTime()
478
479 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
480 programmed. */
481
482 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
483 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
484
485 This feature can be modified afterwards using unitary functions
486 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
487
488 @note This bit-field can not be modified as long as LOCK level 1 has been
489 programmed. */
490
491 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
492 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
493
494 This feature can be modified afterwards using unitary function
495 @ref LL_TIM_ConfigBRK()
496
497 @note This bit-field can not be modified as long as LOCK level 1 has been
498 programmed. */
499
500 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
501 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
502
503 This feature can be modified afterwards using unitary function
504 @ref LL_TIM_ConfigBRK()
505
506 @note This bit-field can not be modified as long as LOCK level 1 has been
507 programmed. */
508
509 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
510 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
511
512 This feature can be modified afterwards using unitary functions
513 @ref LL_TIM_ConfigBRK()
514
515 @note Bidirectional break input is only supported by advanced timers instances.
516
517 @note This bit-field can not be modified as long as LOCK level 1 has been
518 programmed. */
519
520 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
521 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
522
523 This feature can be modified afterwards using unitary functions
524 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
525
526 @note This bit-field can not be modified as long as LOCK level 1 has been
527 programmed. */
528
529 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
530 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
531
532 This feature can be modified afterwards using unitary function
533 @ref LL_TIM_ConfigBRK2()
534
535 @note This bit-field can not be modified as long as LOCK level 1 has been
536 programmed. */
537
538 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
539 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
540
541 This feature can be modified afterwards using unitary function
542 @ref LL_TIM_ConfigBRK2()
543
544 @note This bit-field can not be modified as long as LOCK level 1 has been
545 programmed. */
546
547 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
548 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
549
550 This feature can be modified afterwards using unitary functions
551 @ref LL_TIM_ConfigBRK2()
552
553 @note Bidirectional break input is only supported by advanced timers instances.
554
555 @note This bit-field can not be modified as long as LOCK level 1 has been
556 programmed. */
557
558 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
559 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
560
561 This feature can be modified afterwards using unitary functions
562 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
563
564 @note This bit-field can not be modified as long as LOCK level 1 has been
565 programmed. */
566 } LL_TIM_BDTR_InitTypeDef;
567
568 /**
569 * @}
570 */
571 #endif /* USE_FULL_LL_DRIVER */
572
573 /* Exported constants --------------------------------------------------------*/
574 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
575 * @{
576 */
577
578 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
579 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
580 * @{
581 */
582 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
583 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
584 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
585 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
586 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
587 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
588 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
589 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
590 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
591 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
592 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
593 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
594 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
595 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
596 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
597 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
598 /**
599 * @}
600 */
601
602 #if defined(USE_FULL_LL_DRIVER)
603 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
604 * @{
605 */
606 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
607 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
608 /**
609 * @}
610 */
611
612 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
613 * @{
614 */
615 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
616 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
617 /**
618 * @}
619 */
620
621 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
622 * @{
623 */
624 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
625 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
626 /**
627 * @}
628 */
629 #endif /* USE_FULL_LL_DRIVER */
630
631 /** @defgroup TIM_LL_EC_IT IT Defines
632 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
633 * @{
634 */
635 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
636 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
637 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
638 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
639 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
640 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
641 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
642 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
643 /**
644 * @}
645 */
646
647 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
648 * @{
649 */
650 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
651 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
657 * @{
658 */
659 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
660 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
661 /**
662 * @}
663 */
664
665 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
666 * @{
667 */
668 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
669 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
670 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
671 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
672 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
678 * @{
679 */
680 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
681 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
682 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
683 /**
684 * @}
685 */
686
687 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
688 * @{
689 */
690 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
691 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
697 * @{
698 */
699 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
700 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
701 /**
702 * @}
703 */
704
705 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
706 * @{
707 */
708 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
709 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
710 /**
711 * @}
712 */
713
714 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
715 * @{
716 */
717 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
718 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
719 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
720 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
721 /**
722 * @}
723 */
724
725 /** @defgroup TIM_LL_EC_CHANNEL Channel
726 * @{
727 */
728 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
729 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
730 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
731 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
732 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
733 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
734 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
735 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
736 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
737 /**
738 * @}
739 */
740
741 #if defined(USE_FULL_LL_DRIVER)
742 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
743 * @{
744 */
745 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
746 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
747 /**
748 * @}
749 */
750 #endif /* USE_FULL_LL_DRIVER */
751
752 /** Legacy definitions for compatibility purpose
753 @cond 0
754 */
755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
756 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
757 /**
758 @endcond
759 */
760
761 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
762 * @{
763 */
764 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
765 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
766 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
767 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
768 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
769 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
770 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
771 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
772 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
773 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
774 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
775 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
776 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
777 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
778 /**
779 * @}
780 */
781
782 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
783 * @{
784 */
785 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
786 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
792 * @{
793 */
794 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
795 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
801 * @{
802 */
803 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
804 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
805 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
806 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
812 * @{
813 */
814 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
815 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
816 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
817 /**
818 * @}
819 */
820
821 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
822 * @{
823 */
824 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
825 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
826 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
827 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
833 * @{
834 */
835 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
836 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
837 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
838 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
839 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
842 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
843 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
844 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
845 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
846 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
847 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
849 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
850 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
851 /**
852 * @}
853 */
854
855 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
856 * @{
857 */
858 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
859 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
860 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
861 /**
862 * @}
863 */
864
865 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
866 * @{
867 */
868 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
869 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
870 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
876 * @{
877 */
878 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
879 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
880 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
881 /**
882 * @}
883 */
884
885 /** @defgroup TIM_LL_EC_TRGO Trigger Output
886 * @{
887 */
888 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
889 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
890 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
891 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
892 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
893 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
894 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
895 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
896 /**
897 * @}
898 */
899
900 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
901 * @{
902 */
903 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
904 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
905 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
906 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
912 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
913 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
914 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
915 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
916 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
917 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
918 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
919 /**
920 * @}
921 */
922
923 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
924 * @{
925 */
926 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
927 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
928 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
929 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
930 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
931 /**
932 * @}
933 */
934
935 /** @defgroup TIM_LL_EC_TS Trigger Selection
936 * @{
937 */
938 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
939 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
940 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
941 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
942 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
943 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
944 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
945 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
946 /**
947 * @}
948 */
949
950 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
951 * @{
952 */
953 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
954 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
955 /**
956 * @}
957 */
958
959 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
960 * @{
961 */
962 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
963 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
964 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
965 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
966 /**
967 * @}
968 */
969
970 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
971 * @{
972 */
973 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
974 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
975 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
976 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
977 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
978 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
979 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
980 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
981 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
982 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
983 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
984 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
985 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
986 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
987 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
988 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
989 /**
990 * @}
991 */
992
993 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
994 * @{
995 */
996 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
997 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
998 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
999 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_OR2_ETRSEL_1 | TIM1_OR2_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
1000 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_OR2_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
1001 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_OR2_ETRSEL_2 | TIM1_OR2_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
1002 /**
1003 * @}
1004 */
1005
1006 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1007 * @{
1008 */
1009 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1010 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1011 /**
1012 * @}
1013 */
1014
1015 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1016 * @{
1017 */
1018 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1019 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1020 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1021 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1022 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1023 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1024 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1025 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1026 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1027 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1028 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1029 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1030 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1031 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1032 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1033 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1034 /**
1035 * @}
1036 */
1037
1038 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1039 * @{
1040 */
1041 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1042 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1043 /**
1044 * @}
1045 */
1046
1047 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1048 * @{
1049 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1051 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1059 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1060 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1061 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1062 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1063 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1064 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1065 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup TIM_LL_EC_OSSI OSSI
1071 * @{
1072 */
1073 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1074 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup TIM_LL_EC_OSSR OSSR
1080 * @{
1081 */
1082 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1083 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1084 /**
1085 * @}
1086 */
1087
1088 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1089 * @{
1090 */
1091 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1092 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1098 * @{
1099 */
1100 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
1101 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
1102 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
1103 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1109 * @{
1110 */
1111 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */
1112 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1118 * @{
1119 */
1120 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1121 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1127 * @{
1128 */
1129 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1130 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1131 /**
1132 * @}
1133 */
1134
1135 /** Legacy definitions for compatibility purpose
1136 @cond 0
1137 */
1138 #define LL_TIM_ReArmBRK(_PARAM_)
1139 #define LL_TIM_ReArmBRK2(_PARAM_)
1140 /**
1141 @endcond
1142 */
1143
1144 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1145 * @{
1146 */
1147 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1155 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1156 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1157 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1158 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1159 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1160 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1161 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1162 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1163 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1164 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1165 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1166 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1167 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1168 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1169 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */
1170 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */
1171 /**
1172 * @}
1173 */
1174
1175 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1176 * @{
1177 */
1178 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1179 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1180 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1181 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1182 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1183 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1184 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1185 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1186 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1187 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1188 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1189 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1190 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1191 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1192 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1193 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1194 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1195 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1201 * @{
1202 */
1203 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1204 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1205 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1206 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1207 /**
1208 * @}
1209 */
1210
1211 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1212 * @{
1213 */
1214 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1215 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1216 /**
1217 * @}
1218 */
1219
1220 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1221 * @{
1222 */
1223 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1224 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1225 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1226 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1232 * @{
1233 */
1234 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1235 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1236 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1237 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1243 * @{
1244 */
1245 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */
1246 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */
1247 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */
1248 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1254 * @{
1255 */
1256 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */
1257 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1263 * @{
1264 */
1265 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */
1266 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */
1267 /**
1268 * @}
1269 */
1270
1271 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
1272 * @{
1273 */
1274 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/
1275 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1276 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
1277 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1278 /**
1279 * @}
1280 */
1281
1282 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1283 * @{
1284 */
1285 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1286 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1287 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1288 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1289 /**
1290 * @}
1291 */
1292
1293 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1294 * @{
1295 */
1296 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1297 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1298 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1299 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1300 /**
1301 * @}
1302 */
1303
1304 /** Legacy definitions for compatibility purpose
1305 @cond 0
1306 */
1307 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1308 /**
1309 @endcond
1310 */
1311
1312 /**
1313 * @}
1314 */
1315
1316 /* Exported macro ------------------------------------------------------------*/
1317 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1318 * @{
1319 */
1320
1321 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1322 * @{
1323 */
1324 /**
1325 * @brief Write a value in TIM register.
1326 * @param __INSTANCE__ TIM Instance
1327 * @param __REG__ Register to be written
1328 * @param __VALUE__ Value to be written in the register
1329 * @retval None
1330 */
1331 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1332
1333 /**
1334 * @brief Read a value in TIM register.
1335 * @param __INSTANCE__ TIM Instance
1336 * @param __REG__ Register to be read
1337 * @retval Register value
1338 */
1339 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1340 /**
1341 * @}
1342 */
1343
1344 /**
1345 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1346 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1347 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1348 * to TIMx_CNT register bit 31)
1349 * @param __CNT__ Counter value
1350 * @retval UIF status bit
1351 */
1352 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1353 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1354
1355 /**
1356 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1357 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1358 * @param __TIMCLK__ timer input clock frequency (in Hz)
1359 * @param __CKD__ This parameter can be one of the following values:
1360 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1361 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1362 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1363 * @param __DT__ deadtime duration (in ns)
1364 * @retval DTG[0:7]
1365 */
1366 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1367 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1368 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1369 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1370 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1371 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1372 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1373 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1374 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1375 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1376 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1377 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1378 0U)
1379
1380 /**
1381 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1382 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1383 * @param __TIMCLK__ timer input clock frequency (in Hz)
1384 * @param __CNTCLK__ counter clock frequency (in Hz)
1385 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1386 */
1387 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1388 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1389
1390 /**
1391 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1392 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1393 * @param __TIMCLK__ timer input clock frequency (in Hz)
1394 * @param __PSC__ prescaler
1395 * @param __FREQ__ output signal frequency (in Hz)
1396 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1397 */
1398 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1399 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1400
1401 /**
1402 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1403 * active/inactive delay.
1404 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1405 * @param __TIMCLK__ timer input clock frequency (in Hz)
1406 * @param __PSC__ prescaler
1407 * @param __DELAY__ timer output compare active/inactive delay (in us)
1408 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1409 */
1410 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1411 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1412 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1413
1414 /**
1415 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1416 * (when the timer operates in one pulse mode).
1417 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1418 * @param __TIMCLK__ timer input clock frequency (in Hz)
1419 * @param __PSC__ prescaler
1420 * @param __DELAY__ timer output compare active/inactive delay (in us)
1421 * @param __PULSE__ pulse duration (in us)
1422 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1423 */
1424 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1425 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1426 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1427
1428 /**
1429 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1430 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1431 * @param __ICPSC__ This parameter can be one of the following values:
1432 * @arg @ref LL_TIM_ICPSC_DIV1
1433 * @arg @ref LL_TIM_ICPSC_DIV2
1434 * @arg @ref LL_TIM_ICPSC_DIV4
1435 * @arg @ref LL_TIM_ICPSC_DIV8
1436 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1437 */
1438 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1439 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1440
1441
1442 /**
1443 * @}
1444 */
1445
1446 /* Exported functions --------------------------------------------------------*/
1447 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1448 * @{
1449 */
1450
1451 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1452 * @{
1453 */
1454 /**
1455 * @brief Enable timer counter.
1456 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1457 * @param TIMx Timer instance
1458 * @retval None
1459 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1460 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1461 {
1462 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1463 }
1464
1465 /**
1466 * @brief Disable timer counter.
1467 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1468 * @param TIMx Timer instance
1469 * @retval None
1470 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1471 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1472 {
1473 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1474 }
1475
1476 /**
1477 * @brief Indicates whether the timer counter is enabled.
1478 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1479 * @param TIMx Timer instance
1480 * @retval State of bit (1 or 0).
1481 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1482 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1483 {
1484 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1485 }
1486
1487 /**
1488 * @brief Enable update event generation.
1489 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1490 * @param TIMx Timer instance
1491 * @retval None
1492 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1493 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1494 {
1495 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1496 }
1497
1498 /**
1499 * @brief Disable update event generation.
1500 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1501 * @param TIMx Timer instance
1502 * @retval None
1503 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1504 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1505 {
1506 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1507 }
1508
1509 /**
1510 * @brief Indicates whether update event generation is enabled.
1511 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1512 * @param TIMx Timer instance
1513 * @retval Inverted state of bit (0 or 1).
1514 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1515 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1516 {
1517 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1518 }
1519
1520 /**
1521 * @brief Set update event source
1522 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1523 * generate an update interrupt or DMA request if enabled:
1524 * - Counter overflow/underflow
1525 * - Setting the UG bit
1526 * - Update generation through the slave mode controller
1527 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1528 * overflow/underflow generates an update interrupt or DMA request if enabled.
1529 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1530 * @param TIMx Timer instance
1531 * @param UpdateSource This parameter can be one of the following values:
1532 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1533 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1534 * @retval None
1535 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1536 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1537 {
1538 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1539 }
1540
1541 /**
1542 * @brief Get actual event update source
1543 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1544 * @param TIMx Timer instance
1545 * @retval Returned value can be one of the following values:
1546 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1547 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1548 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1549 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1550 {
1551 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1552 }
1553
1554 /**
1555 * @brief Set one pulse mode (one shot v.s. repetitive).
1556 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1557 * @param TIMx Timer instance
1558 * @param OnePulseMode This parameter can be one of the following values:
1559 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1560 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1561 * @retval None
1562 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1563 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1564 {
1565 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1566 }
1567
1568 /**
1569 * @brief Get actual one pulse mode.
1570 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1571 * @param TIMx Timer instance
1572 * @retval Returned value can be one of the following values:
1573 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1574 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1575 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1576 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1577 {
1578 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1579 }
1580
1581 /**
1582 * @brief Set the timer counter counting mode.
1583 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1584 * check whether or not the counter mode selection feature is supported
1585 * by a timer instance.
1586 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1587 * requires a timer reset to avoid unexpected direction
1588 * due to DIR bit readonly in center aligned mode.
1589 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1590 * CR1 CMS LL_TIM_SetCounterMode
1591 * @param TIMx Timer instance
1592 * @param CounterMode This parameter can be one of the following values:
1593 * @arg @ref LL_TIM_COUNTERMODE_UP
1594 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1595 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1596 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1597 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1598 * @retval None
1599 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1600 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1601 {
1602 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1603 }
1604
1605 /**
1606 * @brief Get actual counter mode.
1607 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1608 * check whether or not the counter mode selection feature is supported
1609 * by a timer instance.
1610 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1611 * CR1 CMS LL_TIM_GetCounterMode
1612 * @param TIMx Timer instance
1613 * @retval Returned value can be one of the following values:
1614 * @arg @ref LL_TIM_COUNTERMODE_UP
1615 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1616 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1617 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1618 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1619 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1620 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1621 {
1622 uint32_t counter_mode;
1623
1624 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1625
1626 if (counter_mode == 0U)
1627 {
1628 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1629 }
1630
1631 return counter_mode;
1632 }
1633
1634 /**
1635 * @brief Enable auto-reload (ARR) preload.
1636 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1637 * @param TIMx Timer instance
1638 * @retval None
1639 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1640 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1641 {
1642 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1643 }
1644
1645 /**
1646 * @brief Disable auto-reload (ARR) preload.
1647 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1648 * @param TIMx Timer instance
1649 * @retval None
1650 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1651 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1652 {
1653 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1654 }
1655
1656 /**
1657 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1658 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1659 * @param TIMx Timer instance
1660 * @retval State of bit (1 or 0).
1661 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1662 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1663 {
1664 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1665 }
1666
1667 /**
1668 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1669 * (when supported) and the digital filters.
1670 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1671 * whether or not the clock division feature is supported by the timer
1672 * instance.
1673 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1674 * @param TIMx Timer instance
1675 * @param ClockDivision This parameter can be one of the following values:
1676 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1677 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1678 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1679 * @retval None
1680 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1681 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1682 {
1683 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1684 }
1685
1686 /**
1687 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1688 * generators (when supported) and the digital filters.
1689 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1690 * whether or not the clock division feature is supported by the timer
1691 * instance.
1692 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1693 * @param TIMx Timer instance
1694 * @retval Returned value can be one of the following values:
1695 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1696 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1697 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1698 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1699 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1700 {
1701 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1702 }
1703
1704 /**
1705 * @brief Set the counter value.
1706 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1707 * whether or not a timer instance supports a 32 bits counter.
1708 * @rmtoll CNT CNT LL_TIM_SetCounter
1709 * @param TIMx Timer instance
1710 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1711 * @retval None
1712 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1713 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1714 {
1715 WRITE_REG(TIMx->CNT, Counter);
1716 }
1717
1718 /**
1719 * @brief Get the counter value.
1720 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1721 * whether or not a timer instance supports a 32 bits counter.
1722 * @rmtoll CNT CNT LL_TIM_GetCounter
1723 * @param TIMx Timer instance
1724 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1725 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1726 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1727 {
1728 return (uint32_t)(READ_REG(TIMx->CNT));
1729 }
1730
1731 /**
1732 * @brief Get the current direction of the counter
1733 * @rmtoll CR1 DIR LL_TIM_GetDirection
1734 * @param TIMx Timer instance
1735 * @retval Returned value can be one of the following values:
1736 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1737 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1738 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1739 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1740 {
1741 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1742 }
1743
1744 /**
1745 * @brief Set the prescaler value.
1746 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1747 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1748 * prescaler ratio is taken into account at the next update event.
1749 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1750 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1751 * @param TIMx Timer instance
1752 * @param Prescaler between Min_Data=0 and Max_Data=65535
1753 * @retval None
1754 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1755 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1756 {
1757 WRITE_REG(TIMx->PSC, Prescaler);
1758 }
1759
1760 /**
1761 * @brief Get the prescaler value.
1762 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1763 * @param TIMx Timer instance
1764 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1765 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1766 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1767 {
1768 return (uint32_t)(READ_REG(TIMx->PSC));
1769 }
1770
1771 /**
1772 * @brief Set the auto-reload value.
1773 * @note The counter is blocked while the auto-reload value is null.
1774 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1775 * whether or not a timer instance supports a 32 bits counter.
1776 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1777 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1778 * @param TIMx Timer instance
1779 * @param AutoReload between Min_Data=0 and Max_Data=65535
1780 * @retval None
1781 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1782 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1783 {
1784 WRITE_REG(TIMx->ARR, AutoReload);
1785 }
1786
1787 /**
1788 * @brief Get the auto-reload value.
1789 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1790 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1791 * whether or not a timer instance supports a 32 bits counter.
1792 * @param TIMx Timer instance
1793 * @retval Auto-reload value
1794 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1795 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1796 {
1797 return (uint32_t)(READ_REG(TIMx->ARR));
1798 }
1799
1800 /**
1801 * @brief Set the repetition counter value.
1802 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1803 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1804 * whether or not a timer instance supports a repetition counter.
1805 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1806 * @param TIMx Timer instance
1807 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1808 * @retval None
1809 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1810 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1811 {
1812 WRITE_REG(TIMx->RCR, RepetitionCounter);
1813 }
1814
1815 /**
1816 * @brief Get the repetition counter value.
1817 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1818 * whether or not a timer instance supports a repetition counter.
1819 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1820 * @param TIMx Timer instance
1821 * @retval Repetition counter value
1822 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1823 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1824 {
1825 return (uint32_t)(READ_REG(TIMx->RCR));
1826 }
1827
1828 /**
1829 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1830 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1831 * in an atomic way.
1832 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1833 * @param TIMx Timer instance
1834 * @retval None
1835 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1836 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1837 {
1838 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1839 }
1840
1841 /**
1842 * @brief Disable update interrupt flag (UIF) remapping.
1843 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1844 * @param TIMx Timer instance
1845 * @retval None
1846 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1847 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1848 {
1849 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1850 }
1851
1852 /**
1853 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1854 * @param Counter Counter value
1855 * @retval State of bit (1 or 0).
1856 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1857 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1858 {
1859 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1860 }
1861
1862 /**
1863 * @}
1864 */
1865
1866 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1867 * @{
1868 */
1869 /**
1870 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1871 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1872 * they are updated only when a commutation event (COM) occurs.
1873 * @note Only on channels that have a complementary output.
1874 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1875 * whether or not a timer instance is able to generate a commutation event.
1876 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1877 * @param TIMx Timer instance
1878 * @retval None
1879 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1880 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1881 {
1882 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1883 }
1884
1885 /**
1886 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1887 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1888 * whether or not a timer instance is able to generate a commutation event.
1889 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1890 * @param TIMx Timer instance
1891 * @retval None
1892 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1893 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1894 {
1895 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1896 }
1897
1898 /**
1899 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1900 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1901 * @param TIMx Timer instance
1902 * @retval State of bit (1 or 0).
1903 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)1904 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1905 {
1906 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1907 }
1908
1909 /**
1910 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1911 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1912 * whether or not a timer instance is able to generate a commutation event.
1913 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1914 * @param TIMx Timer instance
1915 * @param CCUpdateSource This parameter can be one of the following values:
1916 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1917 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1918 * @retval None
1919 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1920 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1921 {
1922 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1923 }
1924
1925 /**
1926 * @brief Set the trigger of the capture/compare DMA request.
1927 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1928 * @param TIMx Timer instance
1929 * @param DMAReqTrigger This parameter can be one of the following values:
1930 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1931 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1932 * @retval None
1933 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1934 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1935 {
1936 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1937 }
1938
1939 /**
1940 * @brief Get actual trigger of the capture/compare DMA request.
1941 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1942 * @param TIMx Timer instance
1943 * @retval Returned value can be one of the following values:
1944 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1945 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1946 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1947 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1948 {
1949 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1950 }
1951
1952 /**
1953 * @brief Set the lock level to freeze the
1954 * configuration of several capture/compare parameters.
1955 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1956 * the lock mechanism is supported by a timer instance.
1957 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1958 * @param TIMx Timer instance
1959 * @param LockLevel This parameter can be one of the following values:
1960 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1961 * @arg @ref LL_TIM_LOCKLEVEL_1
1962 * @arg @ref LL_TIM_LOCKLEVEL_2
1963 * @arg @ref LL_TIM_LOCKLEVEL_3
1964 * @retval None
1965 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1966 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1967 {
1968 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1969 }
1970
1971 /**
1972 * @brief Enable capture/compare channels.
1973 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1974 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1975 * CCER CC2E LL_TIM_CC_EnableChannel\n
1976 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1977 * CCER CC3E LL_TIM_CC_EnableChannel\n
1978 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1979 * CCER CC4E LL_TIM_CC_EnableChannel\n
1980 * CCER CC5E LL_TIM_CC_EnableChannel\n
1981 * CCER CC6E LL_TIM_CC_EnableChannel
1982 * @param TIMx Timer instance
1983 * @param Channels This parameter can be a combination of the following values:
1984 * @arg @ref LL_TIM_CHANNEL_CH1
1985 * @arg @ref LL_TIM_CHANNEL_CH1N
1986 * @arg @ref LL_TIM_CHANNEL_CH2
1987 * @arg @ref LL_TIM_CHANNEL_CH2N
1988 * @arg @ref LL_TIM_CHANNEL_CH3
1989 * @arg @ref LL_TIM_CHANNEL_CH3N
1990 * @arg @ref LL_TIM_CHANNEL_CH4
1991 * @arg @ref LL_TIM_CHANNEL_CH5
1992 * @arg @ref LL_TIM_CHANNEL_CH6
1993 * @retval None
1994 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1995 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1996 {
1997 SET_BIT(TIMx->CCER, Channels);
1998 }
1999
2000 /**
2001 * @brief Disable capture/compare channels.
2002 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2003 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2004 * CCER CC2E LL_TIM_CC_DisableChannel\n
2005 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2006 * CCER CC3E LL_TIM_CC_DisableChannel\n
2007 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2008 * CCER CC4E LL_TIM_CC_DisableChannel\n
2009 * CCER CC5E LL_TIM_CC_DisableChannel\n
2010 * CCER CC6E LL_TIM_CC_DisableChannel
2011 * @param TIMx Timer instance
2012 * @param Channels This parameter can be a combination of the following values:
2013 * @arg @ref LL_TIM_CHANNEL_CH1
2014 * @arg @ref LL_TIM_CHANNEL_CH1N
2015 * @arg @ref LL_TIM_CHANNEL_CH2
2016 * @arg @ref LL_TIM_CHANNEL_CH2N
2017 * @arg @ref LL_TIM_CHANNEL_CH3
2018 * @arg @ref LL_TIM_CHANNEL_CH3N
2019 * @arg @ref LL_TIM_CHANNEL_CH4
2020 * @arg @ref LL_TIM_CHANNEL_CH5
2021 * @arg @ref LL_TIM_CHANNEL_CH6
2022 * @retval None
2023 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2024 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2025 {
2026 CLEAR_BIT(TIMx->CCER, Channels);
2027 }
2028
2029 /**
2030 * @brief Indicate whether channel(s) is(are) enabled.
2031 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2032 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2033 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2034 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2035 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2036 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2037 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2038 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2039 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2040 * @param TIMx Timer instance
2041 * @param Channels This parameter can be a combination of the following values:
2042 * @arg @ref LL_TIM_CHANNEL_CH1
2043 * @arg @ref LL_TIM_CHANNEL_CH1N
2044 * @arg @ref LL_TIM_CHANNEL_CH2
2045 * @arg @ref LL_TIM_CHANNEL_CH2N
2046 * @arg @ref LL_TIM_CHANNEL_CH3
2047 * @arg @ref LL_TIM_CHANNEL_CH3N
2048 * @arg @ref LL_TIM_CHANNEL_CH4
2049 * @arg @ref LL_TIM_CHANNEL_CH5
2050 * @arg @ref LL_TIM_CHANNEL_CH6
2051 * @retval State of bit (1 or 0).
2052 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2053 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2054 {
2055 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2056 }
2057
2058 /**
2059 * @}
2060 */
2061
2062 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2063 * @{
2064 */
2065 /**
2066 * @brief Configure an output channel.
2067 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2068 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2069 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2070 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2071 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2072 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2073 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2074 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2075 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2076 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2077 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2078 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2079 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2080 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2081 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2082 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2083 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2084 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2085 * @param TIMx Timer instance
2086 * @param Channel This parameter can be one of the following values:
2087 * @arg @ref LL_TIM_CHANNEL_CH1
2088 * @arg @ref LL_TIM_CHANNEL_CH2
2089 * @arg @ref LL_TIM_CHANNEL_CH3
2090 * @arg @ref LL_TIM_CHANNEL_CH4
2091 * @arg @ref LL_TIM_CHANNEL_CH5
2092 * @arg @ref LL_TIM_CHANNEL_CH6
2093 * @param Configuration This parameter must be a combination of all the following values:
2094 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2095 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2096 * @retval None
2097 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2098 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2099 {
2100 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2101 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2102 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2103 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2104 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2105 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2106 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2107 }
2108
2109 /**
2110 * @brief Define the behavior of the output reference signal OCxREF from which
2111 * OCx and OCxN (when relevant) are derived.
2112 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2113 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2114 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2115 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2116 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2117 * CCMR3 OC6M LL_TIM_OC_SetMode
2118 * @param TIMx Timer instance
2119 * @param Channel This parameter can be one of the following values:
2120 * @arg @ref LL_TIM_CHANNEL_CH1
2121 * @arg @ref LL_TIM_CHANNEL_CH2
2122 * @arg @ref LL_TIM_CHANNEL_CH3
2123 * @arg @ref LL_TIM_CHANNEL_CH4
2124 * @arg @ref LL_TIM_CHANNEL_CH5
2125 * @arg @ref LL_TIM_CHANNEL_CH6
2126 * @param Mode This parameter can be one of the following values:
2127 * @arg @ref LL_TIM_OCMODE_FROZEN
2128 * @arg @ref LL_TIM_OCMODE_ACTIVE
2129 * @arg @ref LL_TIM_OCMODE_INACTIVE
2130 * @arg @ref LL_TIM_OCMODE_TOGGLE
2131 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2132 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2133 * @arg @ref LL_TIM_OCMODE_PWM1
2134 * @arg @ref LL_TIM_OCMODE_PWM2
2135 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2136 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2137 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2138 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2139 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2140 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2141 * @retval None
2142 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2143 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2144 {
2145 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2146 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2147 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2148 }
2149
2150 /**
2151 * @brief Get the output compare mode of an output channel.
2152 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2153 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2154 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2155 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2156 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2157 * CCMR3 OC6M LL_TIM_OC_GetMode
2158 * @param TIMx Timer instance
2159 * @param Channel This parameter can be one of the following values:
2160 * @arg @ref LL_TIM_CHANNEL_CH1
2161 * @arg @ref LL_TIM_CHANNEL_CH2
2162 * @arg @ref LL_TIM_CHANNEL_CH3
2163 * @arg @ref LL_TIM_CHANNEL_CH4
2164 * @arg @ref LL_TIM_CHANNEL_CH5
2165 * @arg @ref LL_TIM_CHANNEL_CH6
2166 * @retval Returned value can be one of the following values:
2167 * @arg @ref LL_TIM_OCMODE_FROZEN
2168 * @arg @ref LL_TIM_OCMODE_ACTIVE
2169 * @arg @ref LL_TIM_OCMODE_INACTIVE
2170 * @arg @ref LL_TIM_OCMODE_TOGGLE
2171 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2172 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2173 * @arg @ref LL_TIM_OCMODE_PWM1
2174 * @arg @ref LL_TIM_OCMODE_PWM2
2175 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2176 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2177 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2178 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2179 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2180 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2181 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2182 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2183 {
2184 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2185 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2186 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2187 }
2188
2189 /**
2190 * @brief Set the polarity of an output channel.
2191 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2192 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2193 * CCER CC2P LL_TIM_OC_SetPolarity\n
2194 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2195 * CCER CC3P LL_TIM_OC_SetPolarity\n
2196 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2197 * CCER CC4P LL_TIM_OC_SetPolarity\n
2198 * CCER CC5P LL_TIM_OC_SetPolarity\n
2199 * CCER CC6P LL_TIM_OC_SetPolarity
2200 * @param TIMx Timer instance
2201 * @param Channel This parameter can be one of the following values:
2202 * @arg @ref LL_TIM_CHANNEL_CH1
2203 * @arg @ref LL_TIM_CHANNEL_CH1N
2204 * @arg @ref LL_TIM_CHANNEL_CH2
2205 * @arg @ref LL_TIM_CHANNEL_CH2N
2206 * @arg @ref LL_TIM_CHANNEL_CH3
2207 * @arg @ref LL_TIM_CHANNEL_CH3N
2208 * @arg @ref LL_TIM_CHANNEL_CH4
2209 * @arg @ref LL_TIM_CHANNEL_CH5
2210 * @arg @ref LL_TIM_CHANNEL_CH6
2211 * @param Polarity This parameter can be one of the following values:
2212 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2213 * @arg @ref LL_TIM_OCPOLARITY_LOW
2214 * @retval None
2215 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2216 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2217 {
2218 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2219 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2220 }
2221
2222 /**
2223 * @brief Get the polarity of an output channel.
2224 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2225 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2226 * CCER CC2P LL_TIM_OC_GetPolarity\n
2227 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2228 * CCER CC3P LL_TIM_OC_GetPolarity\n
2229 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2230 * CCER CC4P LL_TIM_OC_GetPolarity\n
2231 * CCER CC5P LL_TIM_OC_GetPolarity\n
2232 * CCER CC6P LL_TIM_OC_GetPolarity
2233 * @param TIMx Timer instance
2234 * @param Channel This parameter can be one of the following values:
2235 * @arg @ref LL_TIM_CHANNEL_CH1
2236 * @arg @ref LL_TIM_CHANNEL_CH1N
2237 * @arg @ref LL_TIM_CHANNEL_CH2
2238 * @arg @ref LL_TIM_CHANNEL_CH2N
2239 * @arg @ref LL_TIM_CHANNEL_CH3
2240 * @arg @ref LL_TIM_CHANNEL_CH3N
2241 * @arg @ref LL_TIM_CHANNEL_CH4
2242 * @arg @ref LL_TIM_CHANNEL_CH5
2243 * @arg @ref LL_TIM_CHANNEL_CH6
2244 * @retval Returned value can be one of the following values:
2245 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2246 * @arg @ref LL_TIM_OCPOLARITY_LOW
2247 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2248 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2249 {
2250 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2251 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2252 }
2253
2254 /**
2255 * @brief Set the IDLE state of an output channel
2256 * @note This function is significant only for the timer instances
2257 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2258 * can be used to check whether or not a timer instance provides
2259 * a break input.
2260 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2261 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2262 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2263 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2264 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2265 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2266 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2267 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2268 * CR2 OIS6 LL_TIM_OC_SetIdleState
2269 * @param TIMx Timer instance
2270 * @param Channel This parameter can be one of the following values:
2271 * @arg @ref LL_TIM_CHANNEL_CH1
2272 * @arg @ref LL_TIM_CHANNEL_CH1N
2273 * @arg @ref LL_TIM_CHANNEL_CH2
2274 * @arg @ref LL_TIM_CHANNEL_CH2N
2275 * @arg @ref LL_TIM_CHANNEL_CH3
2276 * @arg @ref LL_TIM_CHANNEL_CH3N
2277 * @arg @ref LL_TIM_CHANNEL_CH4
2278 * @arg @ref LL_TIM_CHANNEL_CH5
2279 * @arg @ref LL_TIM_CHANNEL_CH6
2280 * @param IdleState This parameter can be one of the following values:
2281 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2282 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2283 * @retval None
2284 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2285 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2286 {
2287 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2288 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2289 }
2290
2291 /**
2292 * @brief Get the IDLE state of an output channel
2293 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2294 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2295 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2296 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2297 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2298 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2299 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2300 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2301 * CR2 OIS6 LL_TIM_OC_GetIdleState
2302 * @param TIMx Timer instance
2303 * @param Channel This parameter can be one of the following values:
2304 * @arg @ref LL_TIM_CHANNEL_CH1
2305 * @arg @ref LL_TIM_CHANNEL_CH1N
2306 * @arg @ref LL_TIM_CHANNEL_CH2
2307 * @arg @ref LL_TIM_CHANNEL_CH2N
2308 * @arg @ref LL_TIM_CHANNEL_CH3
2309 * @arg @ref LL_TIM_CHANNEL_CH3N
2310 * @arg @ref LL_TIM_CHANNEL_CH4
2311 * @arg @ref LL_TIM_CHANNEL_CH5
2312 * @arg @ref LL_TIM_CHANNEL_CH6
2313 * @retval Returned value can be one of the following values:
2314 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2315 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2316 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2317 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2318 {
2319 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2320 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2321 }
2322
2323 /**
2324 * @brief Enable fast mode for the output channel.
2325 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2326 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2327 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2328 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2329 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2330 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2331 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2332 * @param TIMx Timer instance
2333 * @param Channel This parameter can be one of the following values:
2334 * @arg @ref LL_TIM_CHANNEL_CH1
2335 * @arg @ref LL_TIM_CHANNEL_CH2
2336 * @arg @ref LL_TIM_CHANNEL_CH3
2337 * @arg @ref LL_TIM_CHANNEL_CH4
2338 * @arg @ref LL_TIM_CHANNEL_CH5
2339 * @arg @ref LL_TIM_CHANNEL_CH6
2340 * @retval None
2341 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2342 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2343 {
2344 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2345 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2346 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2347
2348 }
2349
2350 /**
2351 * @brief Disable fast mode for the output channel.
2352 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2353 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2354 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2355 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2356 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2357 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2358 * @param TIMx Timer instance
2359 * @param Channel This parameter can be one of the following values:
2360 * @arg @ref LL_TIM_CHANNEL_CH1
2361 * @arg @ref LL_TIM_CHANNEL_CH2
2362 * @arg @ref LL_TIM_CHANNEL_CH3
2363 * @arg @ref LL_TIM_CHANNEL_CH4
2364 * @arg @ref LL_TIM_CHANNEL_CH5
2365 * @arg @ref LL_TIM_CHANNEL_CH6
2366 * @retval None
2367 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2368 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2369 {
2370 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2371 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2372 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2373
2374 }
2375
2376 /**
2377 * @brief Indicates whether fast mode is enabled for the output channel.
2378 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2379 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2380 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2381 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2382 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2383 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2384 * @param TIMx Timer instance
2385 * @param Channel This parameter can be one of the following values:
2386 * @arg @ref LL_TIM_CHANNEL_CH1
2387 * @arg @ref LL_TIM_CHANNEL_CH2
2388 * @arg @ref LL_TIM_CHANNEL_CH3
2389 * @arg @ref LL_TIM_CHANNEL_CH4
2390 * @arg @ref LL_TIM_CHANNEL_CH5
2391 * @arg @ref LL_TIM_CHANNEL_CH6
2392 * @retval State of bit (1 or 0).
2393 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2394 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2395 {
2396 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2397 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2398 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2399 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2400 }
2401
2402 /**
2403 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2404 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2405 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2406 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2407 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2408 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2409 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2410 * @param TIMx Timer instance
2411 * @param Channel This parameter can be one of the following values:
2412 * @arg @ref LL_TIM_CHANNEL_CH1
2413 * @arg @ref LL_TIM_CHANNEL_CH2
2414 * @arg @ref LL_TIM_CHANNEL_CH3
2415 * @arg @ref LL_TIM_CHANNEL_CH4
2416 * @arg @ref LL_TIM_CHANNEL_CH5
2417 * @arg @ref LL_TIM_CHANNEL_CH6
2418 * @retval None
2419 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2420 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2421 {
2422 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2423 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2424 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2425 }
2426
2427 /**
2428 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2429 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2430 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2431 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2432 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2433 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2434 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2435 * @param TIMx Timer instance
2436 * @param Channel This parameter can be one of the following values:
2437 * @arg @ref LL_TIM_CHANNEL_CH1
2438 * @arg @ref LL_TIM_CHANNEL_CH2
2439 * @arg @ref LL_TIM_CHANNEL_CH3
2440 * @arg @ref LL_TIM_CHANNEL_CH4
2441 * @arg @ref LL_TIM_CHANNEL_CH5
2442 * @arg @ref LL_TIM_CHANNEL_CH6
2443 * @retval None
2444 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2445 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2446 {
2447 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2448 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2449 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2450 }
2451
2452 /**
2453 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2454 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2455 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2456 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2457 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2458 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2459 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2460 * @param TIMx Timer instance
2461 * @param Channel This parameter can be one of the following values:
2462 * @arg @ref LL_TIM_CHANNEL_CH1
2463 * @arg @ref LL_TIM_CHANNEL_CH2
2464 * @arg @ref LL_TIM_CHANNEL_CH3
2465 * @arg @ref LL_TIM_CHANNEL_CH4
2466 * @arg @ref LL_TIM_CHANNEL_CH5
2467 * @arg @ref LL_TIM_CHANNEL_CH6
2468 * @retval State of bit (1 or 0).
2469 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2470 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2471 {
2472 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2473 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2474 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2475 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2476 }
2477
2478 /**
2479 * @brief Enable clearing the output channel on an external event.
2480 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2481 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2482 * or not a timer instance can clear the OCxREF signal on an external event.
2483 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2484 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2485 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2486 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2487 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2488 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2489 * @param TIMx Timer instance
2490 * @param Channel This parameter can be one of the following values:
2491 * @arg @ref LL_TIM_CHANNEL_CH1
2492 * @arg @ref LL_TIM_CHANNEL_CH2
2493 * @arg @ref LL_TIM_CHANNEL_CH3
2494 * @arg @ref LL_TIM_CHANNEL_CH4
2495 * @arg @ref LL_TIM_CHANNEL_CH5
2496 * @arg @ref LL_TIM_CHANNEL_CH6
2497 * @retval None
2498 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2499 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2500 {
2501 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2502 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2503 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2504 }
2505
2506 /**
2507 * @brief Disable clearing the output channel on an external event.
2508 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2509 * or not a timer instance can clear the OCxREF signal on an external event.
2510 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2511 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2512 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2513 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2514 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2515 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2516 * @param TIMx Timer instance
2517 * @param Channel This parameter can be one of the following values:
2518 * @arg @ref LL_TIM_CHANNEL_CH1
2519 * @arg @ref LL_TIM_CHANNEL_CH2
2520 * @arg @ref LL_TIM_CHANNEL_CH3
2521 * @arg @ref LL_TIM_CHANNEL_CH4
2522 * @arg @ref LL_TIM_CHANNEL_CH5
2523 * @arg @ref LL_TIM_CHANNEL_CH6
2524 * @retval None
2525 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2526 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2527 {
2528 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2529 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2530 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2531 }
2532
2533 /**
2534 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2535 * @note This function enables clearing the output channel on an external event.
2536 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2537 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2538 * or not a timer instance can clear the OCxREF signal on an external event.
2539 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2540 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2541 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2542 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2543 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2544 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2545 * @param TIMx Timer instance
2546 * @param Channel This parameter can be one of the following values:
2547 * @arg @ref LL_TIM_CHANNEL_CH1
2548 * @arg @ref LL_TIM_CHANNEL_CH2
2549 * @arg @ref LL_TIM_CHANNEL_CH3
2550 * @arg @ref LL_TIM_CHANNEL_CH4
2551 * @arg @ref LL_TIM_CHANNEL_CH5
2552 * @arg @ref LL_TIM_CHANNEL_CH6
2553 * @retval State of bit (1 or 0).
2554 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2555 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2556 {
2557 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2558 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2559 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2560 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2561 }
2562
2563 /**
2564 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2565 * the Ocx and OCxN signals).
2566 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2567 * dead-time insertion feature is supported by a timer instance.
2568 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2569 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2570 * @param TIMx Timer instance
2571 * @param DeadTime between Min_Data=0 and Max_Data=255
2572 * @retval None
2573 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2574 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2575 {
2576 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2577 }
2578
2579 /**
2580 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2581 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2582 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2583 * whether or not a timer instance supports a 32 bits counter.
2584 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2585 * output channel 1 is supported by a timer instance.
2586 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2587 * @param TIMx Timer instance
2588 * @param CompareValue between Min_Data=0 and Max_Data=65535
2589 * @retval None
2590 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2591 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2592 {
2593 WRITE_REG(TIMx->CCR1, CompareValue);
2594 }
2595
2596 /**
2597 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2598 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2599 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2600 * whether or not a timer instance supports a 32 bits counter.
2601 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2602 * output channel 2 is supported by a timer instance.
2603 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2604 * @param TIMx Timer instance
2605 * @param CompareValue between Min_Data=0 and Max_Data=65535
2606 * @retval None
2607 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2608 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2609 {
2610 WRITE_REG(TIMx->CCR2, CompareValue);
2611 }
2612
2613 /**
2614 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2615 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2616 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2617 * whether or not a timer instance supports a 32 bits counter.
2618 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2619 * output channel is supported by a timer instance.
2620 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2621 * @param TIMx Timer instance
2622 * @param CompareValue between Min_Data=0 and Max_Data=65535
2623 * @retval None
2624 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2625 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2626 {
2627 WRITE_REG(TIMx->CCR3, CompareValue);
2628 }
2629
2630 /**
2631 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2632 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2633 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2634 * whether or not a timer instance supports a 32 bits counter.
2635 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2636 * output channel 4 is supported by a timer instance.
2637 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2638 * @param TIMx Timer instance
2639 * @param CompareValue between Min_Data=0 and Max_Data=65535
2640 * @retval None
2641 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2642 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2643 {
2644 WRITE_REG(TIMx->CCR4, CompareValue);
2645 }
2646
2647 /**
2648 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2649 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2650 * output channel 5 is supported by a timer instance.
2651 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2652 * @param TIMx Timer instance
2653 * @param CompareValue between Min_Data=0 and Max_Data=65535
2654 * @retval None
2655 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2656 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2657 {
2658 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2659 }
2660
2661 /**
2662 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2663 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2664 * output channel 6 is supported by a timer instance.
2665 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2666 * @param TIMx Timer instance
2667 * @param CompareValue between Min_Data=0 and Max_Data=65535
2668 * @retval None
2669 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2670 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2671 {
2672 WRITE_REG(TIMx->CCR6, CompareValue);
2673 }
2674
2675 /**
2676 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2677 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2678 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2679 * whether or not a timer instance supports a 32 bits counter.
2680 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2681 * output channel 1 is supported by a timer instance.
2682 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2683 * @param TIMx Timer instance
2684 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2685 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2686 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2687 {
2688 return (uint32_t)(READ_REG(TIMx->CCR1));
2689 }
2690
2691 /**
2692 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2693 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2694 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2695 * whether or not a timer instance supports a 32 bits counter.
2696 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2697 * output channel 2 is supported by a timer instance.
2698 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2699 * @param TIMx Timer instance
2700 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2701 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2702 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2703 {
2704 return (uint32_t)(READ_REG(TIMx->CCR2));
2705 }
2706
2707 /**
2708 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2709 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2710 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2711 * whether or not a timer instance supports a 32 bits counter.
2712 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2713 * output channel 3 is supported by a timer instance.
2714 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2715 * @param TIMx Timer instance
2716 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2717 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2718 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2719 {
2720 return (uint32_t)(READ_REG(TIMx->CCR3));
2721 }
2722
2723 /**
2724 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2725 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2726 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2727 * whether or not a timer instance supports a 32 bits counter.
2728 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2729 * output channel 4 is supported by a timer instance.
2730 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2731 * @param TIMx Timer instance
2732 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2733 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2734 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2735 {
2736 return (uint32_t)(READ_REG(TIMx->CCR4));
2737 }
2738
2739 /**
2740 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2741 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2742 * output channel 5 is supported by a timer instance.
2743 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2744 * @param TIMx Timer instance
2745 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2746 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2747 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2748 {
2749 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2750 }
2751
2752 /**
2753 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2754 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2755 * output channel 6 is supported by a timer instance.
2756 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2757 * @param TIMx Timer instance
2758 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2759 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2760 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2761 {
2762 return (uint32_t)(READ_REG(TIMx->CCR6));
2763 }
2764
2765 /**
2766 * @brief Select on which reference signal the OC5REF is combined to.
2767 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2768 * whether or not a timer instance supports the combined 3-phase PWM mode.
2769 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2770 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2771 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2772 * @param TIMx Timer instance
2773 * @param GroupCH5 This parameter can be a combination of the following values:
2774 * @arg @ref LL_TIM_GROUPCH5_NONE
2775 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2776 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2777 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2778 * @retval None
2779 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2780 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2781 {
2782 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2783 }
2784
2785 /**
2786 * @}
2787 */
2788
2789 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2790 * @{
2791 */
2792 /**
2793 * @brief Configure input channel.
2794 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2795 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2796 * CCMR1 IC1F LL_TIM_IC_Config\n
2797 * CCMR1 CC2S LL_TIM_IC_Config\n
2798 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2799 * CCMR1 IC2F LL_TIM_IC_Config\n
2800 * CCMR2 CC3S LL_TIM_IC_Config\n
2801 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2802 * CCMR2 IC3F LL_TIM_IC_Config\n
2803 * CCMR2 CC4S LL_TIM_IC_Config\n
2804 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2805 * CCMR2 IC4F LL_TIM_IC_Config\n
2806 * CCER CC1P LL_TIM_IC_Config\n
2807 * CCER CC1NP LL_TIM_IC_Config\n
2808 * CCER CC2P LL_TIM_IC_Config\n
2809 * CCER CC2NP LL_TIM_IC_Config\n
2810 * CCER CC3P LL_TIM_IC_Config\n
2811 * CCER CC3NP LL_TIM_IC_Config\n
2812 * CCER CC4P LL_TIM_IC_Config\n
2813 * CCER CC4NP LL_TIM_IC_Config
2814 * @param TIMx Timer instance
2815 * @param Channel This parameter can be one of the following values:
2816 * @arg @ref LL_TIM_CHANNEL_CH1
2817 * @arg @ref LL_TIM_CHANNEL_CH2
2818 * @arg @ref LL_TIM_CHANNEL_CH3
2819 * @arg @ref LL_TIM_CHANNEL_CH4
2820 * @param Configuration This parameter must be a combination of all the following values:
2821 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2822 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2823 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2824 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2825 * @retval None
2826 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2827 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2828 {
2829 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2830 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2831 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2832 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2833 << SHIFT_TAB_ICxx[iChannel]);
2834 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2835 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2836 }
2837
2838 /**
2839 * @brief Set the active input.
2840 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2841 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2842 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2843 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2844 * @param TIMx Timer instance
2845 * @param Channel This parameter can be one of the following values:
2846 * @arg @ref LL_TIM_CHANNEL_CH1
2847 * @arg @ref LL_TIM_CHANNEL_CH2
2848 * @arg @ref LL_TIM_CHANNEL_CH3
2849 * @arg @ref LL_TIM_CHANNEL_CH4
2850 * @param ICActiveInput This parameter can be one of the following values:
2851 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2852 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2853 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2854 * @retval None
2855 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2856 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2857 {
2858 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2859 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2860 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2861 }
2862
2863 /**
2864 * @brief Get the current active input.
2865 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2866 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2867 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2868 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2869 * @param TIMx Timer instance
2870 * @param Channel This parameter can be one of the following values:
2871 * @arg @ref LL_TIM_CHANNEL_CH1
2872 * @arg @ref LL_TIM_CHANNEL_CH2
2873 * @arg @ref LL_TIM_CHANNEL_CH3
2874 * @arg @ref LL_TIM_CHANNEL_CH4
2875 * @retval Returned value can be one of the following values:
2876 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2877 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2878 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2879 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2880 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2881 {
2882 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2883 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2884 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2885 }
2886
2887 /**
2888 * @brief Set the prescaler of input channel.
2889 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2890 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2891 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2892 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2893 * @param TIMx Timer instance
2894 * @param Channel This parameter can be one of the following values:
2895 * @arg @ref LL_TIM_CHANNEL_CH1
2896 * @arg @ref LL_TIM_CHANNEL_CH2
2897 * @arg @ref LL_TIM_CHANNEL_CH3
2898 * @arg @ref LL_TIM_CHANNEL_CH4
2899 * @param ICPrescaler This parameter can be one of the following values:
2900 * @arg @ref LL_TIM_ICPSC_DIV1
2901 * @arg @ref LL_TIM_ICPSC_DIV2
2902 * @arg @ref LL_TIM_ICPSC_DIV4
2903 * @arg @ref LL_TIM_ICPSC_DIV8
2904 * @retval None
2905 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2906 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2907 {
2908 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2909 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2910 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2911 }
2912
2913 /**
2914 * @brief Get the current prescaler value acting on an input channel.
2915 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2916 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2917 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2918 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2919 * @param TIMx Timer instance
2920 * @param Channel This parameter can be one of the following values:
2921 * @arg @ref LL_TIM_CHANNEL_CH1
2922 * @arg @ref LL_TIM_CHANNEL_CH2
2923 * @arg @ref LL_TIM_CHANNEL_CH3
2924 * @arg @ref LL_TIM_CHANNEL_CH4
2925 * @retval Returned value can be one of the following values:
2926 * @arg @ref LL_TIM_ICPSC_DIV1
2927 * @arg @ref LL_TIM_ICPSC_DIV2
2928 * @arg @ref LL_TIM_ICPSC_DIV4
2929 * @arg @ref LL_TIM_ICPSC_DIV8
2930 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2931 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2932 {
2933 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2934 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2935 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2936 }
2937
2938 /**
2939 * @brief Set the input filter duration.
2940 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2941 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2942 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2943 * CCMR2 IC4F LL_TIM_IC_SetFilter
2944 * @param TIMx Timer instance
2945 * @param Channel This parameter can be one of the following values:
2946 * @arg @ref LL_TIM_CHANNEL_CH1
2947 * @arg @ref LL_TIM_CHANNEL_CH2
2948 * @arg @ref LL_TIM_CHANNEL_CH3
2949 * @arg @ref LL_TIM_CHANNEL_CH4
2950 * @param ICFilter This parameter can be one of the following values:
2951 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2952 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2953 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2954 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2955 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2956 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2957 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2958 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2959 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2960 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2961 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2962 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2963 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2964 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2965 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2967 * @retval None
2968 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2969 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2970 {
2971 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2972 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2973 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2974 }
2975
2976 /**
2977 * @brief Get the input filter duration.
2978 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2979 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2980 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2981 * CCMR2 IC4F LL_TIM_IC_GetFilter
2982 * @param TIMx Timer instance
2983 * @param Channel This parameter can be one of the following values:
2984 * @arg @ref LL_TIM_CHANNEL_CH1
2985 * @arg @ref LL_TIM_CHANNEL_CH2
2986 * @arg @ref LL_TIM_CHANNEL_CH3
2987 * @arg @ref LL_TIM_CHANNEL_CH4
2988 * @retval Returned value can be one of the following values:
2989 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2990 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2991 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2992 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2993 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2994 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2995 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2996 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2997 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2998 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2999 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3000 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3001 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3002 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3003 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3004 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3005 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3006 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3007 {
3008 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3009 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3010 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3011 }
3012
3013 /**
3014 * @brief Set the input channel polarity.
3015 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3016 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3017 * CCER CC2P LL_TIM_IC_SetPolarity\n
3018 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3019 * CCER CC3P LL_TIM_IC_SetPolarity\n
3020 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3021 * CCER CC4P LL_TIM_IC_SetPolarity\n
3022 * CCER CC4NP LL_TIM_IC_SetPolarity
3023 * @param TIMx Timer instance
3024 * @param Channel This parameter can be one of the following values:
3025 * @arg @ref LL_TIM_CHANNEL_CH1
3026 * @arg @ref LL_TIM_CHANNEL_CH2
3027 * @arg @ref LL_TIM_CHANNEL_CH3
3028 * @arg @ref LL_TIM_CHANNEL_CH4
3029 * @param ICPolarity This parameter can be one of the following values:
3030 * @arg @ref LL_TIM_IC_POLARITY_RISING
3031 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3032 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3033 * @retval None
3034 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3035 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3036 {
3037 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3038 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3039 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3040 }
3041
3042 /**
3043 * @brief Get the current input channel polarity.
3044 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3045 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3046 * CCER CC2P LL_TIM_IC_GetPolarity\n
3047 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3048 * CCER CC3P LL_TIM_IC_GetPolarity\n
3049 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3050 * CCER CC4P LL_TIM_IC_GetPolarity\n
3051 * CCER CC4NP LL_TIM_IC_GetPolarity
3052 * @param TIMx Timer instance
3053 * @param Channel This parameter can be one of the following values:
3054 * @arg @ref LL_TIM_CHANNEL_CH1
3055 * @arg @ref LL_TIM_CHANNEL_CH2
3056 * @arg @ref LL_TIM_CHANNEL_CH3
3057 * @arg @ref LL_TIM_CHANNEL_CH4
3058 * @retval Returned value can be one of the following values:
3059 * @arg @ref LL_TIM_IC_POLARITY_RISING
3060 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3061 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3062 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3063 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3064 {
3065 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3066 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3067 SHIFT_TAB_CCxP[iChannel]);
3068 }
3069
3070 /**
3071 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3072 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3073 * a timer instance provides an XOR input.
3074 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3075 * @param TIMx Timer instance
3076 * @retval None
3077 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3078 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3079 {
3080 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3081 }
3082
3083 /**
3084 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3085 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3086 * a timer instance provides an XOR input.
3087 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3088 * @param TIMx Timer instance
3089 * @retval None
3090 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3091 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3092 {
3093 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3094 }
3095
3096 /**
3097 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3098 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3099 * a timer instance provides an XOR input.
3100 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3101 * @param TIMx Timer instance
3102 * @retval State of bit (1 or 0).
3103 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3104 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3105 {
3106 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3107 }
3108
3109 /**
3110 * @brief Get captured value for input channel 1.
3111 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3112 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3113 * whether or not a timer instance supports a 32 bits counter.
3114 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3115 * input channel 1 is supported by a timer instance.
3116 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3117 * @param TIMx Timer instance
3118 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3119 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3120 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3121 {
3122 return (uint32_t)(READ_REG(TIMx->CCR1));
3123 }
3124
3125 /**
3126 * @brief Get captured value for input channel 2.
3127 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3128 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3129 * whether or not a timer instance supports a 32 bits counter.
3130 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3131 * input channel 2 is supported by a timer instance.
3132 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3133 * @param TIMx Timer instance
3134 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3135 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3136 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3137 {
3138 return (uint32_t)(READ_REG(TIMx->CCR2));
3139 }
3140
3141 /**
3142 * @brief Get captured value for input channel 3.
3143 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3144 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3145 * whether or not a timer instance supports a 32 bits counter.
3146 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3147 * input channel 3 is supported by a timer instance.
3148 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3149 * @param TIMx Timer instance
3150 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3151 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3152 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3153 {
3154 return (uint32_t)(READ_REG(TIMx->CCR3));
3155 }
3156
3157 /**
3158 * @brief Get captured value for input channel 4.
3159 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3160 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3161 * whether or not a timer instance supports a 32 bits counter.
3162 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3163 * input channel 4 is supported by a timer instance.
3164 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3165 * @param TIMx Timer instance
3166 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3167 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3168 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3169 {
3170 return (uint32_t)(READ_REG(TIMx->CCR4));
3171 }
3172
3173 /**
3174 * @}
3175 */
3176
3177 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3178 * @{
3179 */
3180 /**
3181 * @brief Enable external clock mode 2.
3182 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3183 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3184 * whether or not a timer instance supports external clock mode2.
3185 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3186 * @param TIMx Timer instance
3187 * @retval None
3188 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3189 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3190 {
3191 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3192 }
3193
3194 /**
3195 * @brief Disable external clock mode 2.
3196 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3197 * whether or not a timer instance supports external clock mode2.
3198 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3199 * @param TIMx Timer instance
3200 * @retval None
3201 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3202 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3203 {
3204 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3205 }
3206
3207 /**
3208 * @brief Indicate whether external clock mode 2 is enabled.
3209 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3210 * whether or not a timer instance supports external clock mode2.
3211 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3212 * @param TIMx Timer instance
3213 * @retval State of bit (1 or 0).
3214 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3215 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3216 {
3217 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3218 }
3219
3220 /**
3221 * @brief Set the clock source of the counter clock.
3222 * @note when selected clock source is external clock mode 1, the timer input
3223 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3224 * function. This timer input must be configured by calling
3225 * the @ref LL_TIM_IC_Config() function.
3226 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3227 * whether or not a timer instance supports external clock mode1.
3228 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3229 * whether or not a timer instance supports external clock mode2.
3230 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3231 * SMCR ECE LL_TIM_SetClockSource
3232 * @param TIMx Timer instance
3233 * @param ClockSource This parameter can be one of the following values:
3234 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3235 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3236 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3237 * @retval None
3238 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3239 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3240 {
3241 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3242 }
3243
3244 /**
3245 * @brief Set the encoder interface mode.
3246 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3247 * whether or not a timer instance supports the encoder mode.
3248 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3249 * @param TIMx Timer instance
3250 * @param EncoderMode This parameter can be one of the following values:
3251 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3252 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3253 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3254 * @retval None
3255 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3256 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3257 {
3258 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3259 }
3260
3261 /**
3262 * @}
3263 */
3264
3265 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3266 * @{
3267 */
3268 /**
3269 * @brief Set the trigger output (TRGO) used for timer synchronization .
3270 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3271 * whether or not a timer instance can operate as a master timer.
3272 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3273 * @param TIMx Timer instance
3274 * @param TimerSynchronization This parameter can be one of the following values:
3275 * @arg @ref LL_TIM_TRGO_RESET
3276 * @arg @ref LL_TIM_TRGO_ENABLE
3277 * @arg @ref LL_TIM_TRGO_UPDATE
3278 * @arg @ref LL_TIM_TRGO_CC1IF
3279 * @arg @ref LL_TIM_TRGO_OC1REF
3280 * @arg @ref LL_TIM_TRGO_OC2REF
3281 * @arg @ref LL_TIM_TRGO_OC3REF
3282 * @arg @ref LL_TIM_TRGO_OC4REF
3283 * @retval None
3284 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3285 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3286 {
3287 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3288 }
3289
3290 /**
3291 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3292 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3293 * whether or not a timer instance can be used for ADC synchronization.
3294 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3295 * @param TIMx Timer Instance
3296 * @param ADCSynchronization This parameter can be one of the following values:
3297 * @arg @ref LL_TIM_TRGO2_RESET
3298 * @arg @ref LL_TIM_TRGO2_ENABLE
3299 * @arg @ref LL_TIM_TRGO2_UPDATE
3300 * @arg @ref LL_TIM_TRGO2_CC1F
3301 * @arg @ref LL_TIM_TRGO2_OC1
3302 * @arg @ref LL_TIM_TRGO2_OC2
3303 * @arg @ref LL_TIM_TRGO2_OC3
3304 * @arg @ref LL_TIM_TRGO2_OC4
3305 * @arg @ref LL_TIM_TRGO2_OC5
3306 * @arg @ref LL_TIM_TRGO2_OC6
3307 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3308 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3309 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3310 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3311 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3312 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3313 * @retval None
3314 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3315 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3316 {
3317 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3318 }
3319
3320 /**
3321 * @brief Set the synchronization mode of a slave timer.
3322 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3323 * a timer instance can operate as a slave timer.
3324 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3325 * @param TIMx Timer instance
3326 * @param SlaveMode This parameter can be one of the following values:
3327 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3328 * @arg @ref LL_TIM_SLAVEMODE_RESET
3329 * @arg @ref LL_TIM_SLAVEMODE_GATED
3330 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3331 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3332 * @retval None
3333 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3334 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3335 {
3336 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3337 }
3338
3339 /**
3340 * @brief Set the selects the trigger input to be used to synchronize the counter.
3341 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3342 * a timer instance can operate as a slave timer.
3343 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3344 * @param TIMx Timer instance
3345 * @param TriggerInput This parameter can be one of the following values:
3346 * @arg @ref LL_TIM_TS_ITR0
3347 * @arg @ref LL_TIM_TS_ITR1
3348 * @arg @ref LL_TIM_TS_ITR2
3349 * @arg @ref LL_TIM_TS_ITR3
3350 * @arg @ref LL_TIM_TS_TI1F_ED
3351 * @arg @ref LL_TIM_TS_TI1FP1
3352 * @arg @ref LL_TIM_TS_TI2FP2
3353 * @arg @ref LL_TIM_TS_ETRF
3354 * @retval None
3355 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3356 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3357 {
3358 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3359 }
3360
3361 /**
3362 * @brief Enable the Master/Slave mode.
3363 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3364 * a timer instance can operate as a slave timer.
3365 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3366 * @param TIMx Timer instance
3367 * @retval None
3368 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3369 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3370 {
3371 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3372 }
3373
3374 /**
3375 * @brief Disable the Master/Slave mode.
3376 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3377 * a timer instance can operate as a slave timer.
3378 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3379 * @param TIMx Timer instance
3380 * @retval None
3381 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3382 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3383 {
3384 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3385 }
3386
3387 /**
3388 * @brief Indicates whether the Master/Slave mode is enabled.
3389 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3390 * a timer instance can operate as a slave timer.
3391 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3392 * @param TIMx Timer instance
3393 * @retval State of bit (1 or 0).
3394 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3395 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3396 {
3397 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3398 }
3399
3400 /**
3401 * @brief Configure the external trigger (ETR) input.
3402 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3403 * a timer instance provides an external trigger input.
3404 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3405 * SMCR ETPS LL_TIM_ConfigETR\n
3406 * SMCR ETF LL_TIM_ConfigETR
3407 * @param TIMx Timer instance
3408 * @param ETRPolarity This parameter can be one of the following values:
3409 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3410 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3411 * @param ETRPrescaler This parameter can be one of the following values:
3412 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3413 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3414 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3415 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3416 * @param ETRFilter This parameter can be one of the following values:
3417 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3418 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3419 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3420 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3421 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3422 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3423 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3424 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3425 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3426 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3427 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3428 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3429 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3430 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3431 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3432 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3433 * @retval None
3434 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3435 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3436 uint32_t ETRFilter)
3437 {
3438 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3439 }
3440
3441 /**
3442 * @brief Select the external trigger (ETR) input source.
3443 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3444 * not a timer instance supports ETR source selection.
3445 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
3446 * @param TIMx Timer instance
3447 * @param ETRSource This parameter can be one of the following values:
3448 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3449 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3450 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3451 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3452 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3453 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3454 * @retval None
3455 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3456 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3457 {
3458 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
3459 }
3460
3461 /**
3462 * @}
3463 */
3464
3465 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3466 * @{
3467 */
3468 /**
3469 * @brief Enable the break function.
3470 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3471 * a timer instance provides a break input.
3472 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3473 * @param TIMx Timer instance
3474 * @retval None
3475 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3476 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3477 {
3478 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3479 }
3480
3481 /**
3482 * @brief Disable the break function.
3483 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3484 * @param TIMx Timer instance
3485 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3486 * a timer instance provides a break input.
3487 * @retval None
3488 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3489 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3490 {
3491 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3492 }
3493
3494 /**
3495 * @brief Configure the break input.
3496 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3497 * a timer instance provides a break input.
3498 * @note Bidirectional mode is only supported by advanced timer instances.
3499 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3500 * a timer instance is an advanced-control timer.
3501 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3502 * in input mode and in open drain output mode. Any active Break event will
3503 * assert a low logic level on the Break input to indicate an internal break
3504 * event to external devices.
3505 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3506 * LL_TIM_BREAK_AFMODE_INPUT.
3507 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3508 * BDTR BKF LL_TIM_ConfigBRK\n
3509 * BDTR BKBID LL_TIM_ConfigBRK
3510 * @param TIMx Timer instance
3511 * @param BreakPolarity This parameter can be one of the following values:
3512 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3513 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3514 * @param BreakFilter This parameter can be one of the following values:
3515 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3516 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3517 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3518 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3519 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3520 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3521 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3522 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3523 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3524 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3525 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3526 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3527 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3528 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3529 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3530 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3531 * @param BreakAFMode This parameter can be one of the following values:
3532 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3533 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3534 * @retval None
3535 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3536 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3537 uint32_t BreakAFMode)
3538 {
3539 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3540 }
3541
3542 /**
3543 * @brief Disarm the break input (when it operates in bidirectional mode).
3544 * @note The break input can be disarmed only when it is configured in
3545 * bidirectional mode and when when MOE is reset.
3546 * @note Purpose is to be able to have the input voltage back to high-state,
3547 * whatever the time constant on the output .
3548 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3549 * @param TIMx Timer instance
3550 * @retval None
3551 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3552 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3553 {
3554 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3555 }
3556
3557 /**
3558 * @brief Enable the break 2 function.
3559 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3560 * a timer instance provides a second break input.
3561 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3562 * @param TIMx Timer instance
3563 * @retval None
3564 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3565 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3566 {
3567 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3568 }
3569
3570 /**
3571 * @brief Disable the break 2 function.
3572 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3573 * a timer instance provides a second break input.
3574 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3575 * @param TIMx Timer instance
3576 * @retval None
3577 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3578 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3579 {
3580 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3581 }
3582
3583 /**
3584 * @brief Configure the break 2 input.
3585 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3586 * a timer instance provides a second break input.
3587 * @note Bidirectional mode is only supported by advanced timer instances.
3588 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3589 * a timer instance is an advanced-control timer.
3590 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3591 * in input mode and in open drain output mode. Any active Break event will
3592 * assert a low logic level on the Break 2 input to indicate an internal break
3593 * event to external devices.
3594 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3595 * LL_TIM_BREAK2_AFMODE_INPUT.
3596 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3597 * BDTR BK2F LL_TIM_ConfigBRK2\n
3598 * BDTR BK2BID LL_TIM_ConfigBRK2
3599 * @param TIMx Timer instance
3600 * @param Break2Polarity This parameter can be one of the following values:
3601 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3602 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3603 * @param Break2Filter This parameter can be one of the following values:
3604 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3605 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3606 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3607 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3608 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3609 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3610 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3611 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3612 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3613 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3614 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3615 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3616 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3617 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3618 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3619 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3620 * @param Break2AFMode This parameter can be one of the following values:
3621 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3622 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3623 * @retval None
3624 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3625 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3626 uint32_t Break2AFMode)
3627 {
3628 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3629 }
3630
3631 /**
3632 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3633 * @note The break 2 input can be disarmed only when it is configured in
3634 * bidirectional mode and when when MOE is reset.
3635 * @note Purpose is to be able to have the input voltage back to high-state,
3636 * whatever the time constant on the output.
3637 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3638 * @param TIMx Timer instance
3639 * @retval None
3640 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3641 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3642 {
3643 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3644 }
3645
3646 /**
3647 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3648 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3649 * a timer instance provides a break input.
3650 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3651 * BDTR OSSR LL_TIM_SetOffStates
3652 * @param TIMx Timer instance
3653 * @param OffStateIdle This parameter can be one of the following values:
3654 * @arg @ref LL_TIM_OSSI_DISABLE
3655 * @arg @ref LL_TIM_OSSI_ENABLE
3656 * @param OffStateRun This parameter can be one of the following values:
3657 * @arg @ref LL_TIM_OSSR_DISABLE
3658 * @arg @ref LL_TIM_OSSR_ENABLE
3659 * @retval None
3660 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3661 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3662 {
3663 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3664 }
3665
3666 /**
3667 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3668 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3669 * a timer instance provides a break input.
3670 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3671 * @param TIMx Timer instance
3672 * @retval None
3673 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3674 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3675 {
3676 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3677 }
3678
3679 /**
3680 * @brief Disable automatic output (MOE can be set only by software).
3681 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3682 * a timer instance provides a break input.
3683 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3684 * @param TIMx Timer instance
3685 * @retval None
3686 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3687 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3688 {
3689 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3690 }
3691
3692 /**
3693 * @brief Indicate whether automatic output is enabled.
3694 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3695 * a timer instance provides a break input.
3696 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3697 * @param TIMx Timer instance
3698 * @retval State of bit (1 or 0).
3699 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3700 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3701 {
3702 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3703 }
3704
3705 /**
3706 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3707 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3708 * software and is reset in case of break or break2 event
3709 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3710 * a timer instance provides a break input.
3711 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3712 * @param TIMx Timer instance
3713 * @retval None
3714 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3715 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3716 {
3717 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3718 }
3719
3720 /**
3721 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3722 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3723 * software and is reset in case of break or break2 event.
3724 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3725 * a timer instance provides a break input.
3726 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3727 * @param TIMx Timer instance
3728 * @retval None
3729 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3730 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3731 {
3732 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3733 }
3734
3735 /**
3736 * @brief Indicates whether outputs are enabled.
3737 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3738 * a timer instance provides a break input.
3739 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3740 * @param TIMx Timer instance
3741 * @retval State of bit (1 or 0).
3742 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3743 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3744 {
3745 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3746 }
3747
3748 /**
3749 * @brief Enable the signals connected to the designated timer break input.
3750 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3751 * or not a timer instance allows for break input selection.
3752 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
3753 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
3754 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
3755 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3756 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
3757 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3758 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3759 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3760 * @param TIMx Timer instance
3761 * @param BreakInput This parameter can be one of the following values:
3762 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3763 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3764 * @param Source This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3766 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3767 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3768 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3769 * @retval None
3770 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3771 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3772 {
3773 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3774 SET_BIT(*pReg, Source);
3775 }
3776
3777 /**
3778 * @brief Disable the signals connected to the designated timer break input.
3779 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3780 * or not a timer instance allows for break input selection.
3781 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
3782 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
3783 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
3784 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3785 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
3786 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3787 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3788 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3789 * @param TIMx Timer instance
3790 * @param BreakInput This parameter can be one of the following values:
3791 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3792 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3793 * @param Source This parameter can be one of the following values:
3794 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3795 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3796 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3797 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3798 * @retval None
3799 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3800 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3801 {
3802 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3803 CLEAR_BIT(*pReg, Source);
3804 }
3805
3806 /**
3807 * @brief Set the polarity of the break signal for the timer break input.
3808 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3809 * or not a timer instance allows for break input selection.
3810 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3811 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3812 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3813 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3814 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3815 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3816 * @param TIMx Timer instance
3817 * @param BreakInput This parameter can be one of the following values:
3818 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3819 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3820 * @param Source This parameter can be one of the following values:
3821 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3822 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3823 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3824 * @param Polarity This parameter can be one of the following values:
3825 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3826 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3827 * @retval None
3828 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3829 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3830 uint32_t Polarity)
3831 {
3832 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3833 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3834 }
3835 /**
3836 * @}
3837 */
3838
3839 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3840 * @{
3841 */
3842 /**
3843 * @brief Configures the timer DMA burst feature.
3844 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3845 * not a timer instance supports the DMA burst mode.
3846 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3847 * DCR DBA LL_TIM_ConfigDMABurst
3848 * @param TIMx Timer instance
3849 * @param DMABurstBaseAddress This parameter can be one of the following values:
3850 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3851 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3852 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3853 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3854 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3855 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3856 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3857 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3858 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3859 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3860 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3861 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3862 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3863 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3864 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3865 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3866 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3867 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3868 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3869 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3870 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3871 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3872 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
3873 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
3874 * @param DMABurstLength This parameter can be one of the following values:
3875 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3876 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3877 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3878 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3879 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3880 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3881 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3882 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3883 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3884 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3885 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3886 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3887 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3888 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3889 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3890 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3891 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3892 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3893 * @retval None
3894 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3895 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3896 {
3897 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3898 }
3899
3900 /**
3901 * @}
3902 */
3903
3904 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3905 * @{
3906 */
3907 /**
3908 * @brief Remap TIM inputs (input channel, internal/external triggers).
3909 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3910 * a some timer inputs can be remapped.
3911 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3912 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3913 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3914 * TIM2_OR1 ETR1_RMP LL_TIM_SetRemap\n
3915 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3916 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
3917 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
3918 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3919 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3920 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3921 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3922 * @param TIMx Timer instance
3923 * @param Remap Remap param depends on the TIMx. Description available only
3924 * in CHM version of the User Manual (not in .pdf).
3925 * Otherwise see Reference Manual description of OR1 registers.
3926 *
3927 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3928 *
3929 * TIM1: any combination of TI1_RMP, ETR_ADC1_RMP where
3930 *
3931 * . . TI1_RMP can be one of the following values
3932 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3933 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3934 *
3935 * . . ETR_ADC1_RMP can be one of the following values
3936 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3937 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3938 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3939 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3940 *
3941 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3942 *
3943 * . . ITR1_RMP can be one of the following values
3944 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3945 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
3946 *
3947 * . . ETR1_RMP can be one of the following values
3948 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3949 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3950 *
3951 * TI4_RMP can be one of the following values
3952 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3953 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3954 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3955 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3956 *
3957 * TIM3: one of the following values
3958 *
3959 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3960 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3961 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
3962 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
3963 *
3964 * TIM8: one of the following values
3965 *
3966 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3967 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
3968 *
3969 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3970 *
3971 * . . TI1_RMP can be one of the following values
3972 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3973 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3974 *
3975 * . . ENCODER_MODE can be one of the following values
3976 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3977 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3978 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3979 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3980 *
3981 * TIM16: one of the following values
3982 *
3983 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3984 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3985 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3986 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3987 *
3988 * TIM17: one of the following values
3989 *
3990 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3991 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3992 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3993 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3994 * @retval None
3995 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3996 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3997 {
3998 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
3999 }
4000
4001 /**
4002 * @}
4003 */
4004
4005 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4006 * @{
4007 */
4008 /**
4009 * @brief Clear the update interrupt flag (UIF).
4010 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4011 * @param TIMx Timer instance
4012 * @retval None
4013 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4014 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4015 {
4016 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4017 }
4018
4019 /**
4020 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4021 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4022 * @param TIMx Timer instance
4023 * @retval State of bit (1 or 0).
4024 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4025 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4026 {
4027 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4028 }
4029
4030 /**
4031 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4032 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4033 * @param TIMx Timer instance
4034 * @retval None
4035 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4036 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4037 {
4038 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4039 }
4040
4041 /**
4042 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4043 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4044 * @param TIMx Timer instance
4045 * @retval State of bit (1 or 0).
4046 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4047 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4048 {
4049 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4050 }
4051
4052 /**
4053 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4054 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4055 * @param TIMx Timer instance
4056 * @retval None
4057 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4058 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4059 {
4060 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4061 }
4062
4063 /**
4064 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4065 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4066 * @param TIMx Timer instance
4067 * @retval State of bit (1 or 0).
4068 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4069 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4070 {
4071 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4072 }
4073
4074 /**
4075 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4076 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4077 * @param TIMx Timer instance
4078 * @retval None
4079 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4080 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4081 {
4082 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4083 }
4084
4085 /**
4086 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4087 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4088 * @param TIMx Timer instance
4089 * @retval State of bit (1 or 0).
4090 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4091 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4092 {
4093 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4094 }
4095
4096 /**
4097 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4098 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4099 * @param TIMx Timer instance
4100 * @retval None
4101 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4102 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4103 {
4104 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4105 }
4106
4107 /**
4108 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4109 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4110 * @param TIMx Timer instance
4111 * @retval State of bit (1 or 0).
4112 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4113 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4114 {
4115 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4116 }
4117
4118 /**
4119 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4120 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4121 * @param TIMx Timer instance
4122 * @retval None
4123 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4124 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4125 {
4126 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4127 }
4128
4129 /**
4130 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4131 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4132 * @param TIMx Timer instance
4133 * @retval State of bit (1 or 0).
4134 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4135 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4136 {
4137 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4138 }
4139
4140 /**
4141 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4142 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4143 * @param TIMx Timer instance
4144 * @retval None
4145 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4146 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4147 {
4148 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4149 }
4150
4151 /**
4152 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4153 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4154 * @param TIMx Timer instance
4155 * @retval State of bit (1 or 0).
4156 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4157 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4158 {
4159 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4160 }
4161
4162 /**
4163 * @brief Clear the commutation interrupt flag (COMIF).
4164 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4165 * @param TIMx Timer instance
4166 * @retval None
4167 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4168 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4169 {
4170 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4171 }
4172
4173 /**
4174 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4175 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4176 * @param TIMx Timer instance
4177 * @retval State of bit (1 or 0).
4178 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4179 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4180 {
4181 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4182 }
4183
4184 /**
4185 * @brief Clear the trigger interrupt flag (TIF).
4186 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4187 * @param TIMx Timer instance
4188 * @retval None
4189 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4190 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4191 {
4192 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4193 }
4194
4195 /**
4196 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4197 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4198 * @param TIMx Timer instance
4199 * @retval State of bit (1 or 0).
4200 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4201 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4202 {
4203 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4204 }
4205
4206 /**
4207 * @brief Clear the break interrupt flag (BIF).
4208 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4209 * @param TIMx Timer instance
4210 * @retval None
4211 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4212 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4213 {
4214 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4215 }
4216
4217 /**
4218 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4219 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4220 * @param TIMx Timer instance
4221 * @retval State of bit (1 or 0).
4222 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4223 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4224 {
4225 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4226 }
4227
4228 /**
4229 * @brief Clear the break 2 interrupt flag (B2IF).
4230 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4231 * @param TIMx Timer instance
4232 * @retval None
4233 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4234 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4235 {
4236 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4237 }
4238
4239 /**
4240 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4241 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4242 * @param TIMx Timer instance
4243 * @retval State of bit (1 or 0).
4244 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4245 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4246 {
4247 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4248 }
4249
4250 /**
4251 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4252 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4253 * @param TIMx Timer instance
4254 * @retval None
4255 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4256 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4257 {
4258 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4259 }
4260
4261 /**
4262 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4263 * (Capture/Compare 1 interrupt is pending).
4264 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4265 * @param TIMx Timer instance
4266 * @retval State of bit (1 or 0).
4267 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4268 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4269 {
4270 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4271 }
4272
4273 /**
4274 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4275 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4276 * @param TIMx Timer instance
4277 * @retval None
4278 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4279 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4280 {
4281 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4282 }
4283
4284 /**
4285 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4286 * (Capture/Compare 2 over-capture interrupt is pending).
4287 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4288 * @param TIMx Timer instance
4289 * @retval State of bit (1 or 0).
4290 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4291 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4292 {
4293 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4294 }
4295
4296 /**
4297 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4298 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4299 * @param TIMx Timer instance
4300 * @retval None
4301 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4302 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4303 {
4304 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4305 }
4306
4307 /**
4308 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4309 * (Capture/Compare 3 over-capture interrupt is pending).
4310 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4311 * @param TIMx Timer instance
4312 * @retval State of bit (1 or 0).
4313 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4314 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4315 {
4316 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4317 }
4318
4319 /**
4320 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4321 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4322 * @param TIMx Timer instance
4323 * @retval None
4324 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4325 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4326 {
4327 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4328 }
4329
4330 /**
4331 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4332 * (Capture/Compare 4 over-capture interrupt is pending).
4333 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4334 * @param TIMx Timer instance
4335 * @retval State of bit (1 or 0).
4336 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4337 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4338 {
4339 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4340 }
4341
4342 /**
4343 * @brief Clear the system break interrupt flag (SBIF).
4344 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4345 * @param TIMx Timer instance
4346 * @retval None
4347 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4348 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4349 {
4350 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4351 }
4352
4353 /**
4354 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4355 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4356 * @param TIMx Timer instance
4357 * @retval State of bit (1 or 0).
4358 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4359 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4360 {
4361 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4362 }
4363
4364 /**
4365 * @}
4366 */
4367
4368 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4369 * @{
4370 */
4371 /**
4372 * @brief Enable update interrupt (UIE).
4373 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4374 * @param TIMx Timer instance
4375 * @retval None
4376 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4377 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4378 {
4379 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4380 }
4381
4382 /**
4383 * @brief Disable update interrupt (UIE).
4384 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4385 * @param TIMx Timer instance
4386 * @retval None
4387 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4388 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4389 {
4390 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4391 }
4392
4393 /**
4394 * @brief Indicates whether the update interrupt (UIE) is enabled.
4395 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4396 * @param TIMx Timer instance
4397 * @retval State of bit (1 or 0).
4398 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4399 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4400 {
4401 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4402 }
4403
4404 /**
4405 * @brief Enable capture/compare 1 interrupt (CC1IE).
4406 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4407 * @param TIMx Timer instance
4408 * @retval None
4409 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4410 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4411 {
4412 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4413 }
4414
4415 /**
4416 * @brief Disable capture/compare 1 interrupt (CC1IE).
4417 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4418 * @param TIMx Timer instance
4419 * @retval None
4420 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4421 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4422 {
4423 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4424 }
4425
4426 /**
4427 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4428 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4429 * @param TIMx Timer instance
4430 * @retval State of bit (1 or 0).
4431 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4432 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4433 {
4434 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4435 }
4436
4437 /**
4438 * @brief Enable capture/compare 2 interrupt (CC2IE).
4439 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4440 * @param TIMx Timer instance
4441 * @retval None
4442 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4443 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4444 {
4445 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4446 }
4447
4448 /**
4449 * @brief Disable capture/compare 2 interrupt (CC2IE).
4450 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4451 * @param TIMx Timer instance
4452 * @retval None
4453 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4454 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4455 {
4456 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4457 }
4458
4459 /**
4460 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4461 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4462 * @param TIMx Timer instance
4463 * @retval State of bit (1 or 0).
4464 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4465 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4466 {
4467 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4468 }
4469
4470 /**
4471 * @brief Enable capture/compare 3 interrupt (CC3IE).
4472 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4473 * @param TIMx Timer instance
4474 * @retval None
4475 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4476 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4477 {
4478 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4479 }
4480
4481 /**
4482 * @brief Disable capture/compare 3 interrupt (CC3IE).
4483 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4484 * @param TIMx Timer instance
4485 * @retval None
4486 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4487 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4488 {
4489 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4490 }
4491
4492 /**
4493 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4494 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4495 * @param TIMx Timer instance
4496 * @retval State of bit (1 or 0).
4497 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4498 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4499 {
4500 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4501 }
4502
4503 /**
4504 * @brief Enable capture/compare 4 interrupt (CC4IE).
4505 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4506 * @param TIMx Timer instance
4507 * @retval None
4508 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4509 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4510 {
4511 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4512 }
4513
4514 /**
4515 * @brief Disable capture/compare 4 interrupt (CC4IE).
4516 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4517 * @param TIMx Timer instance
4518 * @retval None
4519 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4520 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4521 {
4522 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4523 }
4524
4525 /**
4526 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4527 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4528 * @param TIMx Timer instance
4529 * @retval State of bit (1 or 0).
4530 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4531 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4532 {
4533 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4534 }
4535
4536 /**
4537 * @brief Enable commutation interrupt (COMIE).
4538 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4539 * @param TIMx Timer instance
4540 * @retval None
4541 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4542 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4543 {
4544 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4545 }
4546
4547 /**
4548 * @brief Disable commutation interrupt (COMIE).
4549 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4550 * @param TIMx Timer instance
4551 * @retval None
4552 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4553 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4554 {
4555 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4556 }
4557
4558 /**
4559 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4560 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4561 * @param TIMx Timer instance
4562 * @retval State of bit (1 or 0).
4563 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4564 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4565 {
4566 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4567 }
4568
4569 /**
4570 * @brief Enable trigger interrupt (TIE).
4571 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4572 * @param TIMx Timer instance
4573 * @retval None
4574 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4575 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4576 {
4577 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4578 }
4579
4580 /**
4581 * @brief Disable trigger interrupt (TIE).
4582 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4583 * @param TIMx Timer instance
4584 * @retval None
4585 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4586 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4587 {
4588 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4589 }
4590
4591 /**
4592 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4593 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4594 * @param TIMx Timer instance
4595 * @retval State of bit (1 or 0).
4596 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4597 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4598 {
4599 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4600 }
4601
4602 /**
4603 * @brief Enable break interrupt (BIE).
4604 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4605 * @param TIMx Timer instance
4606 * @retval None
4607 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4608 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4609 {
4610 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4611 }
4612
4613 /**
4614 * @brief Disable break interrupt (BIE).
4615 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4616 * @param TIMx Timer instance
4617 * @retval None
4618 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4619 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4620 {
4621 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4622 }
4623
4624 /**
4625 * @brief Indicates whether the break interrupt (BIE) is enabled.
4626 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4627 * @param TIMx Timer instance
4628 * @retval State of bit (1 or 0).
4629 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4630 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4631 {
4632 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4633 }
4634
4635 /**
4636 * @}
4637 */
4638
4639 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4640 * @{
4641 */
4642 /**
4643 * @brief Enable update DMA request (UDE).
4644 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4645 * @param TIMx Timer instance
4646 * @retval None
4647 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4648 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4649 {
4650 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4651 }
4652
4653 /**
4654 * @brief Disable update DMA request (UDE).
4655 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4656 * @param TIMx Timer instance
4657 * @retval None
4658 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4659 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4660 {
4661 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4662 }
4663
4664 /**
4665 * @brief Indicates whether the update DMA request (UDE) is enabled.
4666 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4667 * @param TIMx Timer instance
4668 * @retval State of bit (1 or 0).
4669 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4670 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4671 {
4672 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4673 }
4674
4675 /**
4676 * @brief Enable capture/compare 1 DMA request (CC1DE).
4677 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4678 * @param TIMx Timer instance
4679 * @retval None
4680 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4681 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4682 {
4683 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4684 }
4685
4686 /**
4687 * @brief Disable capture/compare 1 DMA request (CC1DE).
4688 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4689 * @param TIMx Timer instance
4690 * @retval None
4691 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4692 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4693 {
4694 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4695 }
4696
4697 /**
4698 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4699 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4700 * @param TIMx Timer instance
4701 * @retval State of bit (1 or 0).
4702 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4703 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4704 {
4705 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4706 }
4707
4708 /**
4709 * @brief Enable capture/compare 2 DMA request (CC2DE).
4710 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4711 * @param TIMx Timer instance
4712 * @retval None
4713 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4714 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4715 {
4716 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4717 }
4718
4719 /**
4720 * @brief Disable capture/compare 2 DMA request (CC2DE).
4721 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4722 * @param TIMx Timer instance
4723 * @retval None
4724 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4725 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4726 {
4727 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4728 }
4729
4730 /**
4731 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4732 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4733 * @param TIMx Timer instance
4734 * @retval State of bit (1 or 0).
4735 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4736 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4737 {
4738 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4739 }
4740
4741 /**
4742 * @brief Enable capture/compare 3 DMA request (CC3DE).
4743 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4744 * @param TIMx Timer instance
4745 * @retval None
4746 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4747 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4748 {
4749 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4750 }
4751
4752 /**
4753 * @brief Disable capture/compare 3 DMA request (CC3DE).
4754 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4755 * @param TIMx Timer instance
4756 * @retval None
4757 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4758 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4759 {
4760 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4761 }
4762
4763 /**
4764 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4765 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4766 * @param TIMx Timer instance
4767 * @retval State of bit (1 or 0).
4768 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4770 {
4771 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4772 }
4773
4774 /**
4775 * @brief Enable capture/compare 4 DMA request (CC4DE).
4776 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4777 * @param TIMx Timer instance
4778 * @retval None
4779 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4780 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4781 {
4782 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4783 }
4784
4785 /**
4786 * @brief Disable capture/compare 4 DMA request (CC4DE).
4787 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4788 * @param TIMx Timer instance
4789 * @retval None
4790 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4791 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4792 {
4793 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4794 }
4795
4796 /**
4797 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4798 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4799 * @param TIMx Timer instance
4800 * @retval State of bit (1 or 0).
4801 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4803 {
4804 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4805 }
4806
4807 /**
4808 * @brief Enable commutation DMA request (COMDE).
4809 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4810 * @param TIMx Timer instance
4811 * @retval None
4812 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4813 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4814 {
4815 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4816 }
4817
4818 /**
4819 * @brief Disable commutation DMA request (COMDE).
4820 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4821 * @param TIMx Timer instance
4822 * @retval None
4823 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4824 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4825 {
4826 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4827 }
4828
4829 /**
4830 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4831 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4832 * @param TIMx Timer instance
4833 * @retval State of bit (1 or 0).
4834 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4835 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4836 {
4837 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4838 }
4839
4840 /**
4841 * @brief Enable trigger interrupt (TDE).
4842 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4843 * @param TIMx Timer instance
4844 * @retval None
4845 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4846 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4847 {
4848 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4849 }
4850
4851 /**
4852 * @brief Disable trigger interrupt (TDE).
4853 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4854 * @param TIMx Timer instance
4855 * @retval None
4856 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4857 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4858 {
4859 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4860 }
4861
4862 /**
4863 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4864 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4865 * @param TIMx Timer instance
4866 * @retval State of bit (1 or 0).
4867 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4868 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4869 {
4870 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4871 }
4872
4873 /**
4874 * @}
4875 */
4876
4877 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4878 * @{
4879 */
4880 /**
4881 * @brief Generate an update event.
4882 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4883 * @param TIMx Timer instance
4884 * @retval None
4885 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4886 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4887 {
4888 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4889 }
4890
4891 /**
4892 * @brief Generate Capture/Compare 1 event.
4893 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4894 * @param TIMx Timer instance
4895 * @retval None
4896 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4897 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4898 {
4899 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4900 }
4901
4902 /**
4903 * @brief Generate Capture/Compare 2 event.
4904 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4905 * @param TIMx Timer instance
4906 * @retval None
4907 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4908 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4909 {
4910 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4911 }
4912
4913 /**
4914 * @brief Generate Capture/Compare 3 event.
4915 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4916 * @param TIMx Timer instance
4917 * @retval None
4918 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4919 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4920 {
4921 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4922 }
4923
4924 /**
4925 * @brief Generate Capture/Compare 4 event.
4926 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4927 * @param TIMx Timer instance
4928 * @retval None
4929 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4930 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4931 {
4932 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4933 }
4934
4935 /**
4936 * @brief Generate commutation event.
4937 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4938 * @param TIMx Timer instance
4939 * @retval None
4940 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4941 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4942 {
4943 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4944 }
4945
4946 /**
4947 * @brief Generate trigger event.
4948 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4949 * @param TIMx Timer instance
4950 * @retval None
4951 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4952 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4953 {
4954 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4955 }
4956
4957 /**
4958 * @brief Generate break event.
4959 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4960 * @param TIMx Timer instance
4961 * @retval None
4962 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4963 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4964 {
4965 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4966 }
4967
4968 /**
4969 * @brief Generate break 2 event.
4970 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4971 * @param TIMx Timer instance
4972 * @retval None
4973 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4974 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4975 {
4976 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4977 }
4978
4979 /**
4980 * @}
4981 */
4982
4983 #if defined(USE_FULL_LL_DRIVER)
4984 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4985 * @{
4986 */
4987
4988 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
4989 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4990 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4991 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4992 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4993 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4994 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4995 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4996 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4997 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4998 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4999 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5000 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5001 /**
5002 * @}
5003 */
5004 #endif /* USE_FULL_LL_DRIVER */
5005
5006 /**
5007 * @}
5008 */
5009
5010 /**
5011 * @}
5012 */
5013
5014 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 */
5015
5016 /**
5017 * @}
5018 */
5019
5020 #ifdef __cplusplus
5021 }
5022 #endif
5023
5024 #endif /* __STM32L5xx_LL_TIM_H */
5025
