1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32L5xx_LL_TIM_H
21 #define __STM32L5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM7)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x3CU, /* 7: TIMx_CH5 */
55 0x3CU /* 8: TIMx_CH6 */
56 };
57
58 static const uint8_t SHIFT_TAB_OCxx[] =
59 {
60 0U, /* 0: OC1M, OC1FE, OC1PE */
61 0U, /* 1: - NA */
62 8U, /* 2: OC2M, OC2FE, OC2PE */
63 0U, /* 3: - NA */
64 0U, /* 4: OC3M, OC3FE, OC3PE */
65 0U, /* 5: - NA */
66 8U, /* 6: OC4M, OC4FE, OC4PE */
67 0U, /* 7: OC5M, OC5FE, OC5PE */
68 8U /* 8: OC6M, OC6FE, OC6PE */
69 };
70
71 static const uint8_t SHIFT_TAB_ICxx[] =
72 {
73 0U, /* 0: CC1S, IC1PSC, IC1F */
74 0U, /* 1: - NA */
75 8U, /* 2: CC2S, IC2PSC, IC2F */
76 0U, /* 3: - NA */
77 0U, /* 4: CC3S, IC3PSC, IC3F */
78 0U, /* 5: - NA */
79 8U, /* 6: CC4S, IC4PSC, IC4F */
80 0U, /* 7: - NA */
81 0U /* 8: - NA */
82 };
83
84 static const uint8_t SHIFT_TAB_CCxP[] =
85 {
86 0U, /* 0: CC1P */
87 2U, /* 1: CC1NP */
88 4U, /* 2: CC2P */
89 6U, /* 3: CC2NP */
90 8U, /* 4: CC3P */
91 10U, /* 5: CC3NP */
92 12U, /* 6: CC4P */
93 16U, /* 7: CC5P */
94 20U /* 8: CC6P */
95 };
96
97 static const uint8_t SHIFT_TAB_OISx[] =
98 {
99 0U, /* 0: OIS1 */
100 1U, /* 1: OIS1N */
101 2U, /* 2: OIS2 */
102 3U, /* 3: OIS2N */
103 4U, /* 4: OIS3 */
104 5U, /* 5: OIS3N */
105 6U, /* 6: OIS4 */
106 8U, /* 7: OIS5 */
107 10U /* 8: OIS6 */
108 };
109 /**
110 * @}
111 */
112
113 /* Private constants ---------------------------------------------------------*/
114 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
115 * @{
116 */
117
118 /* Defines used for the bit position in the register and perform offsets */
119 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
120
121 /* Generic bit definitions for TIMx_OR2 register */
122 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */
123 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */
124
125 /* Remap mask definitions */
126 #define TIMx_OR1_RMP_SHIFT 16U
127 #define TIMx_OR1_RMP_MASK 0x0000FFFFU
128 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
129 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
130 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
131 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
132 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
133 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
134 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
135
136 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
137 #define DT_DELAY_1 ((uint8_t)0x7F)
138 #define DT_DELAY_2 ((uint8_t)0x3F)
139 #define DT_DELAY_3 ((uint8_t)0x1F)
140 #define DT_DELAY_4 ((uint8_t)0x1F)
141
142 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
143 #define DT_RANGE_1 ((uint8_t)0x00)
144 #define DT_RANGE_2 ((uint8_t)0x80)
145 #define DT_RANGE_3 ((uint8_t)0xC0)
146 #define DT_RANGE_4 ((uint8_t)0xE0)
147
148 /** Legacy definitions for compatibility purpose
149 @cond 0
150 */
151 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
152 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
153 /**
154 @endcond
155 */
156
157 #define OCREF_CLEAR_SELECT_Pos (16U)
158 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x00010000 */
159 /**
160 * @}
161 */
162
163 /* Private macros ------------------------------------------------------------*/
164 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
165 * @{
166 */
167 /** @brief Convert channel id into channel index.
168 * @param __CHANNEL__ This parameter can be one of the following values:
169 * @arg @ref LL_TIM_CHANNEL_CH1
170 * @arg @ref LL_TIM_CHANNEL_CH1N
171 * @arg @ref LL_TIM_CHANNEL_CH2
172 * @arg @ref LL_TIM_CHANNEL_CH2N
173 * @arg @ref LL_TIM_CHANNEL_CH3
174 * @arg @ref LL_TIM_CHANNEL_CH3N
175 * @arg @ref LL_TIM_CHANNEL_CH4
176 * @arg @ref LL_TIM_CHANNEL_CH5
177 * @arg @ref LL_TIM_CHANNEL_CH6
178 * @retval none
179 */
180 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
181 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
185 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
186 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
187 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
189
190 /** @brief Calculate the deadtime sampling period(in ps).
191 * @param __TIMCLK__ timer input clock frequency (in Hz).
192 * @param __CKD__ This parameter can be one of the following values:
193 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
194 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
195 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
196 * @retval none
197 */
198 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
199 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
200 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
201 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
202 /**
203 * @}
204 */
205
206
207 /* Exported types ------------------------------------------------------------*/
208 #if defined(USE_FULL_LL_DRIVER)
209 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
210 * @{
211 */
212
213 /**
214 * @brief TIM Time Base configuration structure definition.
215 */
216 typedef struct
217 {
218 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
219 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
220
221 This feature can be modified afterwards using unitary function
222 @ref LL_TIM_SetPrescaler().*/
223
224 uint32_t CounterMode; /*!< Specifies the counter mode.
225 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
226
227 This feature can be modified afterwards using unitary function
228 @ref LL_TIM_SetCounterMode().*/
229
230 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
231 Auto-Reload Register at the next update event.
232 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
233 Some timer instances may support 32 bits counters. In that case this parameter must
234 be a number between 0x0000 and 0xFFFFFFFF.
235
236 This feature can be modified afterwards using unitary function
237 @ref LL_TIM_SetAutoReload().*/
238
239 uint32_t ClockDivision; /*!< Specifies the clock division.
240 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
241
242 This feature can be modified afterwards using unitary function
243 @ref LL_TIM_SetClockDivision().*/
244
245 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
246 reaches zero, an update event is generated and counting restarts
247 from the RCR value (N).
248 This means in PWM mode that (N+1) corresponds to:
249 - the number of PWM periods in edge-aligned mode
250 - the number of half PWM period in center-aligned mode
251 GP timers: this parameter must be a number between Min_Data = 0x00 and
252 Max_Data = 0xFF.
253 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
254 Max_Data = 0xFFFF.
255
256 This feature can be modified afterwards using unitary function
257 @ref LL_TIM_SetRepetitionCounter().*/
258 } LL_TIM_InitTypeDef;
259
260 /**
261 * @brief TIM Output Compare configuration structure definition.
262 */
263 typedef struct
264 {
265 uint32_t OCMode; /*!< Specifies the output mode.
266 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
267
268 This feature can be modified afterwards using unitary function
269 @ref LL_TIM_OC_SetMode().*/
270
271 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
272 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
273
274 This feature can be modified afterwards using unitary functions
275 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
276
277 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
278 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
279
280 This feature can be modified afterwards using unitary functions
281 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
282
283 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
284 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
285
286 This feature can be modified afterwards using unitary function
287 LL_TIM_OC_SetCompareCHx (x=1..6).*/
288
289 uint32_t OCPolarity; /*!< Specifies the output polarity.
290 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_OC_SetPolarity().*/
294
295 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
296 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
297
298 This feature can be modified afterwards using unitary function
299 @ref LL_TIM_OC_SetPolarity().*/
300
301
302 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
303 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetIdleState().*/
307
308 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
309 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
310
311 This feature can be modified afterwards using unitary function
312 @ref LL_TIM_OC_SetIdleState().*/
313 } LL_TIM_OC_InitTypeDef;
314
315 /**
316 * @brief TIM Input Capture configuration structure definition.
317 */
318
319 typedef struct
320 {
321
322 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
323 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetPolarity().*/
327
328 uint32_t ICActiveInput; /*!< Specifies the input.
329 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetActiveInput().*/
333
334 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
335 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
336
337 This feature can be modified afterwards using unitary function
338 @ref LL_TIM_IC_SetPrescaler().*/
339
340 uint32_t ICFilter; /*!< Specifies the input capture filter.
341 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
342
343 This feature can be modified afterwards using unitary function
344 @ref LL_TIM_IC_SetFilter().*/
345 } LL_TIM_IC_InitTypeDef;
346
347
348 /**
349 * @brief TIM Encoder interface configuration structure definition.
350 */
351 typedef struct
352 {
353 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
354 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_SetEncoderMode().*/
358
359 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
360 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetPolarity().*/
364
365 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
366 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetActiveInput().*/
370
371 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
372 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetPrescaler().*/
376
377 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
378 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetFilter().*/
382
383 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
384 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetPolarity().*/
388
389 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
390 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetActiveInput().*/
394
395 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
396 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
397
398 This feature can be modified afterwards using unitary function
399 @ref LL_TIM_IC_SetPrescaler().*/
400
401 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
402 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
403
404 This feature can be modified afterwards using unitary function
405 @ref LL_TIM_IC_SetFilter().*/
406
407 } LL_TIM_ENCODER_InitTypeDef;
408
409 /**
410 * @brief TIM Hall sensor interface configuration structure definition.
411 */
412 typedef struct
413 {
414
415 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
416 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
417
418 This feature can be modified afterwards using unitary function
419 @ref LL_TIM_IC_SetPolarity().*/
420
421 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
422 Prescaler must be set to get a maximum counter period longer than the
423 time interval between 2 consecutive changes on the Hall inputs.
424 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
425
426 This feature can be modified afterwards using unitary function
427 @ref LL_TIM_IC_SetPrescaler().*/
428
429 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
430 This parameter can be a value of
431 @ref TIM_LL_EC_IC_FILTER.
432
433 This feature can be modified afterwards using unitary function
434 @ref LL_TIM_IC_SetFilter().*/
435
436 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
437 A positive pulse (TRGO event) is generated with a programmable delay every time
438 a change occurs on the Hall inputs.
439 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
440
441 This feature can be modified afterwards using unitary function
442 @ref LL_TIM_OC_SetCompareCH2().*/
443 } LL_TIM_HALLSENSOR_InitTypeDef;
444
445 /**
446 * @brief BDTR (Break and Dead Time) structure definition
447 */
448 typedef struct
449 {
450 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
451 This parameter can be a value of @ref TIM_LL_EC_OSSR
452
453 This feature can be modified afterwards using unitary function
454 @ref LL_TIM_SetOffStates()
455
456 @note This bit-field cannot be modified as long as LOCK level 2 has been
457 programmed. */
458
459 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
460 This parameter can be a value of @ref TIM_LL_EC_OSSI
461
462 This feature can be modified afterwards using unitary function
463 @ref LL_TIM_SetOffStates()
464
465 @note This bit-field cannot be modified as long as LOCK level 2 has been
466 programmed. */
467
468 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
469 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
470
471 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
472 register has been written, their content is frozen until the next reset.*/
473
474 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
475 switching-on of the outputs.
476 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
477
478 This feature can be modified afterwards using unitary function
479 @ref LL_TIM_OC_SetDeadTime()
480
481 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
482 programmed. */
483
484 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
485 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
486
487 This feature can be modified afterwards using unitary functions
488 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
489
490 @note This bit-field can not be modified as long as LOCK level 1 has been
491 programmed. */
492
493 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
494 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
495
496 This feature can be modified afterwards using unitary function
497 @ref LL_TIM_ConfigBRK()
498
499 @note This bit-field can not be modified as long as LOCK level 1 has been
500 programmed. */
501
502 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
503 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
504
505 This feature can be modified afterwards using unitary function
506 @ref LL_TIM_ConfigBRK()
507
508 @note This bit-field can not be modified as long as LOCK level 1 has been
509 programmed. */
510
511 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
512 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
513
514 This feature can be modified afterwards using unitary functions
515 @ref LL_TIM_ConfigBRK()
516
517 @note Bidirectional break input is only supported by advanced timers instances.
518
519 @note This bit-field can not be modified as long as LOCK level 1 has been
520 programmed. */
521
522 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
523 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
524
525 This feature can be modified afterwards using unitary functions
526 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
527
528 @note This bit-field can not be modified as long as LOCK level 1 has been
529 programmed. */
530
531 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
532 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
533
534 This feature can be modified afterwards using unitary function
535 @ref LL_TIM_ConfigBRK2()
536
537 @note This bit-field can not be modified as long as LOCK level 1 has been
538 programmed. */
539
540 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
541 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
542
543 This feature can be modified afterwards using unitary function
544 @ref LL_TIM_ConfigBRK2()
545
546 @note This bit-field can not be modified as long as LOCK level 1 has been
547 programmed. */
548
549 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
550 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
551
552 This feature can be modified afterwards using unitary functions
553 @ref LL_TIM_ConfigBRK2()
554
555 @note Bidirectional break input is only supported by advanced timers instances.
556
557 @note This bit-field can not be modified as long as LOCK level 1 has been
558 programmed. */
559
560 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
561 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
562
563 This feature can be modified afterwards using unitary functions
564 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
565
566 @note This bit-field can not be modified as long as LOCK level 1 has been
567 programmed. */
568 } LL_TIM_BDTR_InitTypeDef;
569
570 /**
571 * @}
572 */
573 #endif /* USE_FULL_LL_DRIVER */
574
575 /* Exported constants --------------------------------------------------------*/
576 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
577 * @{
578 */
579
580 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
581 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
582 * @{
583 */
584 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
585 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
586 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
587 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
588 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
589 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
590 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
591 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
592 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
593 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
594 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
595 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
596 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
597 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
598 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
599 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
606 * @{
607 */
608 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
609 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
615 * @{
616 */
617 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
618 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
624 * @{
625 */
626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
628 /**
629 * @}
630 */
631 #endif /* USE_FULL_LL_DRIVER */
632
633 /** @defgroup TIM_LL_EC_IT IT Defines
634 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
635 * @{
636 */
637 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
638 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
639 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
640 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
641 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
642 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
643 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
644 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
645 /**
646 * @}
647 */
648
649 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
650 * @{
651 */
652 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
653 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
654 /**
655 * @}
656 */
657
658 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
659 * @{
660 */
661 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
662 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
668 * @{
669 */
670 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
671 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
672 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
673 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
674 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
675 /**
676 * @}
677 */
678
679 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
680 * @{
681 */
682 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
683 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
684 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
685 /**
686 * @}
687 */
688
689 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
690 * @{
691 */
692 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
693 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
694 /**
695 * @}
696 */
697
698 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
699 * @{
700 */
701 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
702 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
703 /**
704 * @}
705 */
706
707 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
708 * @{
709 */
710 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
711 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
712 /**
713 * @}
714 */
715
716 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
717 * @{
718 */
719 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
720 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
721 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
722 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
723 /**
724 * @}
725 */
726
727 /** @defgroup TIM_LL_EC_CHANNEL Channel
728 * @{
729 */
730 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
731 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
732 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
733 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
734 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
735 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
736 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
737 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
738 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
739 /**
740 * @}
741 */
742
743 #if defined(USE_FULL_LL_DRIVER)
744 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
745 * @{
746 */
747 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
748 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
749 /**
750 * @}
751 */
752 #endif /* USE_FULL_LL_DRIVER */
753
754 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
755 * @{
756 */
757 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
758 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
759 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
760 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
761 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
762 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
763 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
764 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
765 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
766 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
767 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
768 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
769 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
770 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
771 /**
772 * @}
773 */
774
775 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
776 * @{
777 */
778 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
779 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
780 /**
781 * @}
782 */
783
784 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
785 * @{
786 */
787 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
788 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
794 * @{
795 */
796 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
797 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
798 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
799 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
800 /**
801 * @}
802 */
803
804 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
805 * @{
806 */
807 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
808 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
809 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
810 /**
811 * @}
812 */
813
814 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
815 * @{
816 */
817 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
818 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
819 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
820 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
821 /**
822 * @}
823 */
824
825 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
826 * @{
827 */
828 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
829 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
830 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
831 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
832 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
833 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
834 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
835 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
836 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
837 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
838 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
839 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
840 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
841 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
842 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
843 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
844 /**
845 * @}
846 */
847
848 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
849 * @{
850 */
851 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
852 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
853 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
854 /**
855 * @}
856 */
857
858 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
859 * @{
860 */
861 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
862 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
863 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
864 /**
865 * @}
866 */
867
868 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
869 * @{
870 */
871 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
872 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
873 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
874 /**
875 * @}
876 */
877
878 /** @defgroup TIM_LL_EC_TRGO Trigger Output
879 * @{
880 */
881 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
882 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
883 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
884 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
885 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
886 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
887 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
888 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
889 /**
890 * @}
891 */
892
893 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
894 * @{
895 */
896 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
897 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
898 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
899 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
907 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
908 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
909 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
910 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
911 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
912 /**
913 * @}
914 */
915
916 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
917 * @{
918 */
919 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
920 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
921 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
922 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
923 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
924 /**
925 * @}
926 */
927
928 /** @defgroup TIM_LL_EC_TS Trigger Selection
929 * @{
930 */
931 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
932 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
933 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
934 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
935 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
936 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
937 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
938 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
939 /**
940 * @}
941 */
942
943 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
944 * @{
945 */
946 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
947 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
948 /**
949 * @}
950 */
951
952 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
953 * @{
954 */
955 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
956 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
957 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
958 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
959 /**
960 * @}
961 */
962
963 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
964 * @{
965 */
966 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
967 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
968 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
969 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
970 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
971 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
972 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
973 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
974 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
975 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
976 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
977 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
978 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
979 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
980 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
981 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
982 /**
983 * @}
984 */
985
986 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
987 * @{
988 */
989 #define LL_TIM_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
990 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
991 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
992 #define LL_TIM_ETRSOURCE_ADC1_AWD1 (TIM1_OR2_ETRSEL_1 | TIM1_OR2_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 1 */
993 #define LL_TIM_ETRSOURCE_ADC1_AWD2 TIM1_OR2_ETRSEL_2 /*!< ETR input is connected to ADC1 analog watchdog 2 */
994 #define LL_TIM_ETRSOURCE_ADC1_AWD3 (TIM1_OR2_ETRSEL_2 | TIM1_OR2_ETRSEL_0) /*!< ETR input is connected to ADC1 analog watchdog 3 */
995 /**
996 * @}
997 */
998
999 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1000 * @{
1001 */
1002 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1003 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1009 * @{
1010 */
1011 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1012 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1013 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1014 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1015 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1016 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1017 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1018 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1019 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1020 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1021 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1022 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1023 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1024 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1025 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1026 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1032 * @{
1033 */
1034 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1035 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1036 /**
1037 * @}
1038 */
1039
1040 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1041 * @{
1042 */
1043 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1044 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1045 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1046 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1047 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1048 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1049 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1050 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1051 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1052 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1053 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1054 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1055 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1056 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1057 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1058 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup TIM_LL_EC_OSSI OSSI
1064 * @{
1065 */
1066 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1067 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1068 /**
1069 * @}
1070 */
1071
1072 /** @defgroup TIM_LL_EC_OSSR OSSR
1073 * @{
1074 */
1075 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1076 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1082 * @{
1083 */
1084 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1085 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1091 * @{
1092 */
1093 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */
1094 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */
1095 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */
1096 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1102 * @{
1103 */
1104 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */
1105 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1111 * @{
1112 */
1113 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1114 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1120 * @{
1121 */
1122 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1123 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1124 /**
1125 * @}
1126 */
1127
1128 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1129 * @{
1130 */
1131 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1132 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1133 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1134 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1135 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1136 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1137 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1138 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1139 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1140 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1141 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1142 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1143 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1144 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1145 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1146 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1147 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1148 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1149 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1150 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1151 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1152 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1153 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_OR2 register is the DMA base address for DMA burst */
1154 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1160 * @{
1161 */
1162 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1163 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1164 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1165 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1166 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1167 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1168 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1169 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1170 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1171 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1172 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1173 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1174 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1175 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1176 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1177 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1178 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1179 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
1185 * @{
1186 */
1187 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */
1188 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */
1189 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */
1190 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1196 * @{
1197 */
1198 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */
1199 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
1205 * @{
1206 */
1207 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1208 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1209 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */
1210 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1216 * @{
1217 */
1218 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */
1219 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */
1220 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */
1221 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1227 * @{
1228 */
1229 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */
1230 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */
1231 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */
1232 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */
1233 /**
1234 * @}
1235 */
1236
1237 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1238 * @{
1239 */
1240 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */
1241 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1247 * @{
1248 */
1249 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */
1250 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */
1251 /**
1252 * @}
1253 */
1254
1255 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
1256 * @{
1257 */
1258 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/
1259 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1260 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/
1261 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
1262 /**
1263 * @}
1264 */
1265
1266 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1267 * @{
1268 */
1269 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */
1270 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */
1271 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */
1272 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */
1273 /**
1274 * @}
1275 */
1276
1277 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1278 * @{
1279 */
1280 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */
1281 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */
1282 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */
1283 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */
1284 /**
1285 * @}
1286 */
1287
1288 /** Legacy definitions for compatibility purpose
1289 @cond 0
1290 */
1291 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1292 /**
1293 @endcond
1294 */
1295 /**
1296 * @}
1297 */
1298
1299 /* Exported macro ------------------------------------------------------------*/
1300 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1301 * @{
1302 */
1303
1304 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1305 * @{
1306 */
1307 /**
1308 * @brief Write a value in TIM register.
1309 * @param __INSTANCE__ TIM Instance
1310 * @param __REG__ Register to be written
1311 * @param __VALUE__ Value to be written in the register
1312 * @retval None
1313 */
1314 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1315
1316 /**
1317 * @brief Read a value in TIM register.
1318 * @param __INSTANCE__ TIM Instance
1319 * @param __REG__ Register to be read
1320 * @retval Register value
1321 */
1322 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1323 /**
1324 * @}
1325 */
1326
1327 /**
1328 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1329 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1330 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1331 * to TIMx_CNT register bit 31)
1332 * @param __CNT__ Counter value
1333 * @retval UIF status bit
1334 */
1335 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1336 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1337
1338 /**
1339 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1340 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1341 * @param __TIMCLK__ timer input clock frequency (in Hz)
1342 * @param __CKD__ This parameter can be one of the following values:
1343 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1344 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1345 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1346 * @param __DT__ deadtime duration (in ns)
1347 * @retval DTG[0:7]
1348 */
1349 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1350 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1351 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1352 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1353 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1354 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1355 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1356 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1357 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1358 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1359 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1360 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1361 0U)
1362
1363 /**
1364 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1365 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1366 * @param __TIMCLK__ timer input clock frequency (in Hz)
1367 * @param __CNTCLK__ counter clock frequency (in Hz)
1368 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1369 */
1370 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1371 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1372
1373 /**
1374 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1375 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1376 * @param __TIMCLK__ timer input clock frequency (in Hz)
1377 * @param __PSC__ prescaler
1378 * @param __FREQ__ output signal frequency (in Hz)
1379 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1380 */
1381 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1382 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1383
1384 /**
1385 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1386 * active/inactive delay.
1387 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1388 * @param __TIMCLK__ timer input clock frequency (in Hz)
1389 * @param __PSC__ prescaler
1390 * @param __DELAY__ timer output compare active/inactive delay (in us)
1391 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1392 */
1393 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1394 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1395 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1396
1397 /**
1398 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1399 * (when the timer operates in one pulse mode).
1400 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1401 * @param __TIMCLK__ timer input clock frequency (in Hz)
1402 * @param __PSC__ prescaler
1403 * @param __DELAY__ timer output compare active/inactive delay (in us)
1404 * @param __PULSE__ pulse duration (in us)
1405 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1406 */
1407 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1408 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1409 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1410
1411 /**
1412 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1413 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1414 * @param __ICPSC__ This parameter can be one of the following values:
1415 * @arg @ref LL_TIM_ICPSC_DIV1
1416 * @arg @ref LL_TIM_ICPSC_DIV2
1417 * @arg @ref LL_TIM_ICPSC_DIV4
1418 * @arg @ref LL_TIM_ICPSC_DIV8
1419 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1420 */
1421 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1422 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1423
1424
1425 /**
1426 * @}
1427 */
1428
1429
1430 /**
1431 * @}
1432 */
1433
1434 /* Exported functions --------------------------------------------------------*/
1435 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1436 * @{
1437 */
1438
1439 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1440 * @{
1441 */
1442 /**
1443 * @brief Enable timer counter.
1444 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1445 * @param TIMx Timer instance
1446 * @retval None
1447 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1448 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1449 {
1450 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1451 }
1452
1453 /**
1454 * @brief Disable timer counter.
1455 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1456 * @param TIMx Timer instance
1457 * @retval None
1458 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1459 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1460 {
1461 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1462 }
1463
1464 /**
1465 * @brief Indicates whether the timer counter is enabled.
1466 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1467 * @param TIMx Timer instance
1468 * @retval State of bit (1 or 0).
1469 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1470 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1471 {
1472 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Enable update event generation.
1477 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1478 * @param TIMx Timer instance
1479 * @retval None
1480 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1481 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1482 {
1483 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1484 }
1485
1486 /**
1487 * @brief Disable update event generation.
1488 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1489 * @param TIMx Timer instance
1490 * @retval None
1491 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1492 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1493 {
1494 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1495 }
1496
1497 /**
1498 * @brief Indicates whether update event generation is enabled.
1499 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1500 * @param TIMx Timer instance
1501 * @retval Inverted state of bit (0 or 1).
1502 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1503 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1504 {
1505 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Set update event source
1510 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1511 * generate an update interrupt or DMA request if enabled:
1512 * - Counter overflow/underflow
1513 * - Setting the UG bit
1514 * - Update generation through the slave mode controller
1515 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1516 * overflow/underflow generates an update interrupt or DMA request if enabled.
1517 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1518 * @param TIMx Timer instance
1519 * @param UpdateSource This parameter can be one of the following values:
1520 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1521 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1522 * @retval None
1523 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1524 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1525 {
1526 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1527 }
1528
1529 /**
1530 * @brief Get actual event update source
1531 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1532 * @param TIMx Timer instance
1533 * @retval Returned value can be one of the following values:
1534 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1535 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1536 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1537 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1538 {
1539 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1540 }
1541
1542 /**
1543 * @brief Set one pulse mode (one shot v.s. repetitive).
1544 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1545 * @param TIMx Timer instance
1546 * @param OnePulseMode This parameter can be one of the following values:
1547 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1548 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1549 * @retval None
1550 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1551 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1552 {
1553 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1554 }
1555
1556 /**
1557 * @brief Get actual one pulse mode.
1558 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1559 * @param TIMx Timer instance
1560 * @retval Returned value can be one of the following values:
1561 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1562 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1563 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1564 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1565 {
1566 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1567 }
1568
1569 /**
1570 * @brief Set the timer counter counting mode.
1571 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1572 * check whether or not the counter mode selection feature is supported
1573 * by a timer instance.
1574 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1575 * requires a timer reset to avoid unexpected direction
1576 * due to DIR bit readonly in center aligned mode.
1577 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1578 * CR1 CMS LL_TIM_SetCounterMode
1579 * @param TIMx Timer instance
1580 * @param CounterMode This parameter can be one of the following values:
1581 * @arg @ref LL_TIM_COUNTERMODE_UP
1582 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1583 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1584 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1585 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1586 * @retval None
1587 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1588 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1589 {
1590 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1591 }
1592
1593 /**
1594 * @brief Get actual counter mode.
1595 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1596 * check whether or not the counter mode selection feature is supported
1597 * by a timer instance.
1598 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1599 * CR1 CMS LL_TIM_GetCounterMode
1600 * @param TIMx Timer instance
1601 * @retval Returned value can be one of the following values:
1602 * @arg @ref LL_TIM_COUNTERMODE_UP
1603 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1604 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1605 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1606 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1607 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1608 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1609 {
1610 uint32_t counter_mode;
1611
1612 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1613
1614 if (counter_mode == 0U)
1615 {
1616 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1617 }
1618
1619 return counter_mode;
1620 }
1621
1622 /**
1623 * @brief Enable auto-reload (ARR) preload.
1624 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1625 * @param TIMx Timer instance
1626 * @retval None
1627 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1628 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1629 {
1630 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1631 }
1632
1633 /**
1634 * @brief Disable auto-reload (ARR) preload.
1635 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1636 * @param TIMx Timer instance
1637 * @retval None
1638 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1639 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1640 {
1641 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1642 }
1643
1644 /**
1645 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1646 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1647 * @param TIMx Timer instance
1648 * @retval State of bit (1 or 0).
1649 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1650 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1651 {
1652 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1657 * (when supported) and the digital filters.
1658 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1659 * whether or not the clock division feature is supported by the timer
1660 * instance.
1661 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1662 * @param TIMx Timer instance
1663 * @param ClockDivision This parameter can be one of the following values:
1664 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1665 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1666 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1667 * @retval None
1668 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1669 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1670 {
1671 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1672 }
1673
1674 /**
1675 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1676 * generators (when supported) and the digital filters.
1677 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1678 * whether or not the clock division feature is supported by the timer
1679 * instance.
1680 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1681 * @param TIMx Timer instance
1682 * @retval Returned value can be one of the following values:
1683 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1684 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1685 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1686 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1687 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1688 {
1689 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1690 }
1691
1692 /**
1693 * @brief Set the counter value.
1694 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1695 * whether or not a timer instance supports a 32 bits counter.
1696 * @rmtoll CNT CNT LL_TIM_SetCounter
1697 * @param TIMx Timer instance
1698 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1699 * @retval None
1700 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1701 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1702 {
1703 WRITE_REG(TIMx->CNT, Counter);
1704 }
1705
1706 /**
1707 * @brief Get the counter value.
1708 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1709 * whether or not a timer instance supports a 32 bits counter.
1710 * @rmtoll CNT CNT LL_TIM_GetCounter
1711 * @param TIMx Timer instance
1712 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1713 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1714 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1715 {
1716 return (uint32_t)(READ_REG(TIMx->CNT));
1717 }
1718
1719 /**
1720 * @brief Get the current direction of the counter
1721 * @rmtoll CR1 DIR LL_TIM_GetDirection
1722 * @param TIMx Timer instance
1723 * @retval Returned value can be one of the following values:
1724 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1725 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1726 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1727 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1728 {
1729 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1730 }
1731
1732 /**
1733 * @brief Set the prescaler value.
1734 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1735 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1736 * prescaler ratio is taken into account at the next update event.
1737 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1738 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1739 * @param TIMx Timer instance
1740 * @param Prescaler between Min_Data=0 and Max_Data=65535
1741 * @retval None
1742 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1743 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1744 {
1745 WRITE_REG(TIMx->PSC, Prescaler);
1746 }
1747
1748 /**
1749 * @brief Get the prescaler value.
1750 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1751 * @param TIMx Timer instance
1752 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1753 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1754 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1755 {
1756 return (uint32_t)(READ_REG(TIMx->PSC));
1757 }
1758
1759 /**
1760 * @brief Set the auto-reload value.
1761 * @note The counter is blocked while the auto-reload value is null.
1762 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1763 * whether or not a timer instance supports a 32 bits counter.
1764 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1765 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1766 * @param TIMx Timer instance
1767 * @param AutoReload between Min_Data=0 and Max_Data=65535
1768 * @retval None
1769 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1770 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1771 {
1772 WRITE_REG(TIMx->ARR, AutoReload);
1773 }
1774
1775 /**
1776 * @brief Get the auto-reload value.
1777 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1778 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1779 * whether or not a timer instance supports a 32 bits counter.
1780 * @param TIMx Timer instance
1781 * @retval Auto-reload value
1782 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)1783 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
1784 {
1785 return (uint32_t)(READ_REG(TIMx->ARR));
1786 }
1787
1788 /**
1789 * @brief Set the repetition counter value.
1790 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1791 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1792 * whether or not a timer instance supports a repetition counter.
1793 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1794 * @param TIMx Timer instance
1795 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
1796 * @retval None
1797 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1798 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1799 {
1800 WRITE_REG(TIMx->RCR, RepetitionCounter);
1801 }
1802
1803 /**
1804 * @brief Get the repetition counter value.
1805 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1806 * whether or not a timer instance supports a repetition counter.
1807 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1808 * @param TIMx Timer instance
1809 * @retval Repetition counter value
1810 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)1811 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
1812 {
1813 return (uint32_t)(READ_REG(TIMx->RCR));
1814 }
1815
1816 /**
1817 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1818 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1819 * in an atomic way.
1820 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1821 * @param TIMx Timer instance
1822 * @retval None
1823 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)1824 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1825 {
1826 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1827 }
1828
1829 /**
1830 * @brief Disable update interrupt flag (UIF) remapping.
1831 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1832 * @param TIMx Timer instance
1833 * @retval None
1834 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)1835 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1836 {
1837 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1838 }
1839
1840 /**
1841 * @brief Indicate whether update interrupt flag (UIF) copy is set.
1842 * @param Counter Counter value
1843 * @retval State of bit (1 or 0).
1844 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)1845 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
1846 {
1847 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
1848 }
1849
1850 /**
1851 * @}
1852 */
1853
1854 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1855 * @{
1856 */
1857 /**
1858 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1859 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1860 * they are updated only when a commutation event (COM) occurs.
1861 * @note Only on channels that have a complementary output.
1862 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1863 * whether or not a timer instance is able to generate a commutation event.
1864 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1865 * @param TIMx Timer instance
1866 * @retval None
1867 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1868 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1869 {
1870 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1871 }
1872
1873 /**
1874 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1875 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1876 * whether or not a timer instance is able to generate a commutation event.
1877 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1878 * @param TIMx Timer instance
1879 * @retval None
1880 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1881 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1882 {
1883 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1884 }
1885
1886 /**
1887 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1888 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1889 * whether or not a timer instance is able to generate a commutation event.
1890 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1891 * @param TIMx Timer instance
1892 * @param CCUpdateSource This parameter can be one of the following values:
1893 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1894 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1895 * @retval None
1896 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1897 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1898 {
1899 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1900 }
1901
1902 /**
1903 * @brief Set the trigger of the capture/compare DMA request.
1904 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1905 * @param TIMx Timer instance
1906 * @param DMAReqTrigger This parameter can be one of the following values:
1907 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1908 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1909 * @retval None
1910 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1911 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1912 {
1913 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1914 }
1915
1916 /**
1917 * @brief Get actual trigger of the capture/compare DMA request.
1918 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1919 * @param TIMx Timer instance
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1922 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1923 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)1924 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
1925 {
1926 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1927 }
1928
1929 /**
1930 * @brief Set the lock level to freeze the
1931 * configuration of several capture/compare parameters.
1932 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1933 * the lock mechanism is supported by a timer instance.
1934 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1935 * @param TIMx Timer instance
1936 * @param LockLevel This parameter can be one of the following values:
1937 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1938 * @arg @ref LL_TIM_LOCKLEVEL_1
1939 * @arg @ref LL_TIM_LOCKLEVEL_2
1940 * @arg @ref LL_TIM_LOCKLEVEL_3
1941 * @retval None
1942 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1943 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1944 {
1945 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1946 }
1947
1948 /**
1949 * @brief Enable capture/compare channels.
1950 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1951 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1952 * CCER CC2E LL_TIM_CC_EnableChannel\n
1953 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1954 * CCER CC3E LL_TIM_CC_EnableChannel\n
1955 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1956 * CCER CC4E LL_TIM_CC_EnableChannel\n
1957 * CCER CC5E LL_TIM_CC_EnableChannel\n
1958 * CCER CC6E LL_TIM_CC_EnableChannel
1959 * @param TIMx Timer instance
1960 * @param Channels This parameter can be a combination of the following values:
1961 * @arg @ref LL_TIM_CHANNEL_CH1
1962 * @arg @ref LL_TIM_CHANNEL_CH1N
1963 * @arg @ref LL_TIM_CHANNEL_CH2
1964 * @arg @ref LL_TIM_CHANNEL_CH2N
1965 * @arg @ref LL_TIM_CHANNEL_CH3
1966 * @arg @ref LL_TIM_CHANNEL_CH3N
1967 * @arg @ref LL_TIM_CHANNEL_CH4
1968 * @arg @ref LL_TIM_CHANNEL_CH5
1969 * @arg @ref LL_TIM_CHANNEL_CH6
1970 * @retval None
1971 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1972 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1973 {
1974 SET_BIT(TIMx->CCER, Channels);
1975 }
1976
1977 /**
1978 * @brief Disable capture/compare channels.
1979 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1980 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1981 * CCER CC2E LL_TIM_CC_DisableChannel\n
1982 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1983 * CCER CC3E LL_TIM_CC_DisableChannel\n
1984 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1985 * CCER CC4E LL_TIM_CC_DisableChannel\n
1986 * CCER CC5E LL_TIM_CC_DisableChannel\n
1987 * CCER CC6E LL_TIM_CC_DisableChannel
1988 * @param TIMx Timer instance
1989 * @param Channels This parameter can be a combination of the following values:
1990 * @arg @ref LL_TIM_CHANNEL_CH1
1991 * @arg @ref LL_TIM_CHANNEL_CH1N
1992 * @arg @ref LL_TIM_CHANNEL_CH2
1993 * @arg @ref LL_TIM_CHANNEL_CH2N
1994 * @arg @ref LL_TIM_CHANNEL_CH3
1995 * @arg @ref LL_TIM_CHANNEL_CH3N
1996 * @arg @ref LL_TIM_CHANNEL_CH4
1997 * @arg @ref LL_TIM_CHANNEL_CH5
1998 * @arg @ref LL_TIM_CHANNEL_CH6
1999 * @retval None
2000 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2001 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2002 {
2003 CLEAR_BIT(TIMx->CCER, Channels);
2004 }
2005
2006 /**
2007 * @brief Indicate whether channel(s) is(are) enabled.
2008 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2009 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2010 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2011 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2012 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2013 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2014 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2015 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2016 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2017 * @param TIMx Timer instance
2018 * @param Channels This parameter can be a combination of the following values:
2019 * @arg @ref LL_TIM_CHANNEL_CH1
2020 * @arg @ref LL_TIM_CHANNEL_CH1N
2021 * @arg @ref LL_TIM_CHANNEL_CH2
2022 * @arg @ref LL_TIM_CHANNEL_CH2N
2023 * @arg @ref LL_TIM_CHANNEL_CH3
2024 * @arg @ref LL_TIM_CHANNEL_CH3N
2025 * @arg @ref LL_TIM_CHANNEL_CH4
2026 * @arg @ref LL_TIM_CHANNEL_CH5
2027 * @arg @ref LL_TIM_CHANNEL_CH6
2028 * @retval State of bit (1 or 0).
2029 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)2030 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2031 {
2032 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2033 }
2034
2035 /**
2036 * @}
2037 */
2038
2039 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2040 * @{
2041 */
2042 /**
2043 * @brief Configure an output channel.
2044 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2045 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2046 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2047 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2048 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2049 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2050 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2051 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2052 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2053 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2054 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2055 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2056 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2057 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2058 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2059 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2060 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2061 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2062 * @param TIMx Timer instance
2063 * @param Channel This parameter can be one of the following values:
2064 * @arg @ref LL_TIM_CHANNEL_CH1
2065 * @arg @ref LL_TIM_CHANNEL_CH2
2066 * @arg @ref LL_TIM_CHANNEL_CH3
2067 * @arg @ref LL_TIM_CHANNEL_CH4
2068 * @arg @ref LL_TIM_CHANNEL_CH5
2069 * @arg @ref LL_TIM_CHANNEL_CH6
2070 * @param Configuration This parameter must be a combination of all the following values:
2071 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2072 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2073 * @retval None
2074 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2075 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2076 {
2077 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2078 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2079 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2080 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2081 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2082 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2083 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2084 }
2085
2086 /**
2087 * @brief Define the behavior of the output reference signal OCxREF from which
2088 * OCx and OCxN (when relevant) are derived.
2089 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2090 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2091 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2092 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2093 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2094 * CCMR3 OC6M LL_TIM_OC_SetMode
2095 * @param TIMx Timer instance
2096 * @param Channel This parameter can be one of the following values:
2097 * @arg @ref LL_TIM_CHANNEL_CH1
2098 * @arg @ref LL_TIM_CHANNEL_CH2
2099 * @arg @ref LL_TIM_CHANNEL_CH3
2100 * @arg @ref LL_TIM_CHANNEL_CH4
2101 * @arg @ref LL_TIM_CHANNEL_CH5
2102 * @arg @ref LL_TIM_CHANNEL_CH6
2103 * @param Mode This parameter can be one of the following values:
2104 * @arg @ref LL_TIM_OCMODE_FROZEN
2105 * @arg @ref LL_TIM_OCMODE_ACTIVE
2106 * @arg @ref LL_TIM_OCMODE_INACTIVE
2107 * @arg @ref LL_TIM_OCMODE_TOGGLE
2108 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2109 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2110 * @arg @ref LL_TIM_OCMODE_PWM1
2111 * @arg @ref LL_TIM_OCMODE_PWM2
2112 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2113 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2114 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2115 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2116 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2117 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2118 * @retval None
2119 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2120 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2121 {
2122 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2123 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2124 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2125 }
2126
2127 /**
2128 * @brief Get the output compare mode of an output channel.
2129 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2130 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2131 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2132 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2133 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2134 * CCMR3 OC6M LL_TIM_OC_GetMode
2135 * @param TIMx Timer instance
2136 * @param Channel This parameter can be one of the following values:
2137 * @arg @ref LL_TIM_CHANNEL_CH1
2138 * @arg @ref LL_TIM_CHANNEL_CH2
2139 * @arg @ref LL_TIM_CHANNEL_CH3
2140 * @arg @ref LL_TIM_CHANNEL_CH4
2141 * @arg @ref LL_TIM_CHANNEL_CH5
2142 * @arg @ref LL_TIM_CHANNEL_CH6
2143 * @retval Returned value can be one of the following values:
2144 * @arg @ref LL_TIM_OCMODE_FROZEN
2145 * @arg @ref LL_TIM_OCMODE_ACTIVE
2146 * @arg @ref LL_TIM_OCMODE_INACTIVE
2147 * @arg @ref LL_TIM_OCMODE_TOGGLE
2148 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2149 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2150 * @arg @ref LL_TIM_OCMODE_PWM1
2151 * @arg @ref LL_TIM_OCMODE_PWM2
2152 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2153 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2154 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2155 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2156 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2157 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2158 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2159 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2160 {
2161 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2162 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2163 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2164 }
2165
2166 /**
2167 * @brief Set the polarity of an output channel.
2168 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2169 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2170 * CCER CC2P LL_TIM_OC_SetPolarity\n
2171 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2172 * CCER CC3P LL_TIM_OC_SetPolarity\n
2173 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2174 * CCER CC4P LL_TIM_OC_SetPolarity\n
2175 * CCER CC5P LL_TIM_OC_SetPolarity\n
2176 * CCER CC6P LL_TIM_OC_SetPolarity
2177 * @param TIMx Timer instance
2178 * @param Channel This parameter can be one of the following values:
2179 * @arg @ref LL_TIM_CHANNEL_CH1
2180 * @arg @ref LL_TIM_CHANNEL_CH1N
2181 * @arg @ref LL_TIM_CHANNEL_CH2
2182 * @arg @ref LL_TIM_CHANNEL_CH2N
2183 * @arg @ref LL_TIM_CHANNEL_CH3
2184 * @arg @ref LL_TIM_CHANNEL_CH3N
2185 * @arg @ref LL_TIM_CHANNEL_CH4
2186 * @arg @ref LL_TIM_CHANNEL_CH5
2187 * @arg @ref LL_TIM_CHANNEL_CH6
2188 * @param Polarity This parameter can be one of the following values:
2189 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2190 * @arg @ref LL_TIM_OCPOLARITY_LOW
2191 * @retval None
2192 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2193 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2194 {
2195 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2196 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2197 }
2198
2199 /**
2200 * @brief Get the polarity of an output channel.
2201 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2202 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2203 * CCER CC2P LL_TIM_OC_GetPolarity\n
2204 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2205 * CCER CC3P LL_TIM_OC_GetPolarity\n
2206 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2207 * CCER CC4P LL_TIM_OC_GetPolarity\n
2208 * CCER CC5P LL_TIM_OC_GetPolarity\n
2209 * CCER CC6P LL_TIM_OC_GetPolarity
2210 * @param TIMx Timer instance
2211 * @param Channel This parameter can be one of the following values:
2212 * @arg @ref LL_TIM_CHANNEL_CH1
2213 * @arg @ref LL_TIM_CHANNEL_CH1N
2214 * @arg @ref LL_TIM_CHANNEL_CH2
2215 * @arg @ref LL_TIM_CHANNEL_CH2N
2216 * @arg @ref LL_TIM_CHANNEL_CH3
2217 * @arg @ref LL_TIM_CHANNEL_CH3N
2218 * @arg @ref LL_TIM_CHANNEL_CH4
2219 * @arg @ref LL_TIM_CHANNEL_CH5
2220 * @arg @ref LL_TIM_CHANNEL_CH6
2221 * @retval Returned value can be one of the following values:
2222 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2223 * @arg @ref LL_TIM_OCPOLARITY_LOW
2224 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2225 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2226 {
2227 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2228 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2229 }
2230
2231 /**
2232 * @brief Set the IDLE state of an output channel
2233 * @note This function is significant only for the timer instances
2234 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2235 * can be used to check whether or not a timer instance provides
2236 * a break input.
2237 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2238 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2239 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2240 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2241 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2242 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2243 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2244 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2245 * CR2 OIS6 LL_TIM_OC_SetIdleState
2246 * @param TIMx Timer instance
2247 * @param Channel This parameter can be one of the following values:
2248 * @arg @ref LL_TIM_CHANNEL_CH1
2249 * @arg @ref LL_TIM_CHANNEL_CH1N
2250 * @arg @ref LL_TIM_CHANNEL_CH2
2251 * @arg @ref LL_TIM_CHANNEL_CH2N
2252 * @arg @ref LL_TIM_CHANNEL_CH3
2253 * @arg @ref LL_TIM_CHANNEL_CH3N
2254 * @arg @ref LL_TIM_CHANNEL_CH4
2255 * @arg @ref LL_TIM_CHANNEL_CH5
2256 * @arg @ref LL_TIM_CHANNEL_CH6
2257 * @param IdleState This parameter can be one of the following values:
2258 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2259 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2260 * @retval None
2261 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2262 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2263 {
2264 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2265 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2266 }
2267
2268 /**
2269 * @brief Get the IDLE state of an output channel
2270 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2271 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2272 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2273 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2274 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2275 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2276 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2277 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2278 * CR2 OIS6 LL_TIM_OC_GetIdleState
2279 * @param TIMx Timer instance
2280 * @param Channel This parameter can be one of the following values:
2281 * @arg @ref LL_TIM_CHANNEL_CH1
2282 * @arg @ref LL_TIM_CHANNEL_CH1N
2283 * @arg @ref LL_TIM_CHANNEL_CH2
2284 * @arg @ref LL_TIM_CHANNEL_CH2N
2285 * @arg @ref LL_TIM_CHANNEL_CH3
2286 * @arg @ref LL_TIM_CHANNEL_CH3N
2287 * @arg @ref LL_TIM_CHANNEL_CH4
2288 * @arg @ref LL_TIM_CHANNEL_CH5
2289 * @arg @ref LL_TIM_CHANNEL_CH6
2290 * @retval Returned value can be one of the following values:
2291 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2292 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2293 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2294 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2295 {
2296 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2297 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2298 }
2299
2300 /**
2301 * @brief Enable fast mode for the output channel.
2302 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2303 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2304 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2305 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2306 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2307 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2308 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2309 * @param TIMx Timer instance
2310 * @param Channel This parameter can be one of the following values:
2311 * @arg @ref LL_TIM_CHANNEL_CH1
2312 * @arg @ref LL_TIM_CHANNEL_CH2
2313 * @arg @ref LL_TIM_CHANNEL_CH3
2314 * @arg @ref LL_TIM_CHANNEL_CH4
2315 * @arg @ref LL_TIM_CHANNEL_CH5
2316 * @arg @ref LL_TIM_CHANNEL_CH6
2317 * @retval None
2318 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2319 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2320 {
2321 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2322 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2323 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2324
2325 }
2326
2327 /**
2328 * @brief Disable fast mode for the output channel.
2329 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2330 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2331 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2332 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2333 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2334 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2335 * @param TIMx Timer instance
2336 * @param Channel This parameter can be one of the following values:
2337 * @arg @ref LL_TIM_CHANNEL_CH1
2338 * @arg @ref LL_TIM_CHANNEL_CH2
2339 * @arg @ref LL_TIM_CHANNEL_CH3
2340 * @arg @ref LL_TIM_CHANNEL_CH4
2341 * @arg @ref LL_TIM_CHANNEL_CH5
2342 * @arg @ref LL_TIM_CHANNEL_CH6
2343 * @retval None
2344 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2345 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2346 {
2347 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2348 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2349 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2350
2351 }
2352
2353 /**
2354 * @brief Indicates whether fast mode is enabled for the output channel.
2355 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2356 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2357 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2358 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2359 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2360 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2361 * @param TIMx Timer instance
2362 * @param Channel This parameter can be one of the following values:
2363 * @arg @ref LL_TIM_CHANNEL_CH1
2364 * @arg @ref LL_TIM_CHANNEL_CH2
2365 * @arg @ref LL_TIM_CHANNEL_CH3
2366 * @arg @ref LL_TIM_CHANNEL_CH4
2367 * @arg @ref LL_TIM_CHANNEL_CH5
2368 * @arg @ref LL_TIM_CHANNEL_CH6
2369 * @retval State of bit (1 or 0).
2370 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)2371 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2372 {
2373 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2374 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2375 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2376 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2377 }
2378
2379 /**
2380 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2381 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2382 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2383 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2384 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2385 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2386 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2387 * @param TIMx Timer instance
2388 * @param Channel This parameter can be one of the following values:
2389 * @arg @ref LL_TIM_CHANNEL_CH1
2390 * @arg @ref LL_TIM_CHANNEL_CH2
2391 * @arg @ref LL_TIM_CHANNEL_CH3
2392 * @arg @ref LL_TIM_CHANNEL_CH4
2393 * @arg @ref LL_TIM_CHANNEL_CH5
2394 * @arg @ref LL_TIM_CHANNEL_CH6
2395 * @retval None
2396 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2397 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2398 {
2399 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2400 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2401 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2402 }
2403
2404 /**
2405 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2406 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2407 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2408 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2409 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2410 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2411 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2412 * @param TIMx Timer instance
2413 * @param Channel This parameter can be one of the following values:
2414 * @arg @ref LL_TIM_CHANNEL_CH1
2415 * @arg @ref LL_TIM_CHANNEL_CH2
2416 * @arg @ref LL_TIM_CHANNEL_CH3
2417 * @arg @ref LL_TIM_CHANNEL_CH4
2418 * @arg @ref LL_TIM_CHANNEL_CH5
2419 * @arg @ref LL_TIM_CHANNEL_CH6
2420 * @retval None
2421 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2422 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2423 {
2424 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2425 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2426 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2427 }
2428
2429 /**
2430 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2431 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2432 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2433 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2434 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2435 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2436 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2437 * @param TIMx Timer instance
2438 * @param Channel This parameter can be one of the following values:
2439 * @arg @ref LL_TIM_CHANNEL_CH1
2440 * @arg @ref LL_TIM_CHANNEL_CH2
2441 * @arg @ref LL_TIM_CHANNEL_CH3
2442 * @arg @ref LL_TIM_CHANNEL_CH4
2443 * @arg @ref LL_TIM_CHANNEL_CH5
2444 * @arg @ref LL_TIM_CHANNEL_CH6
2445 * @retval State of bit (1 or 0).
2446 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)2447 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2448 {
2449 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2450 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2451 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2452 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2453 }
2454
2455 /**
2456 * @brief Enable clearing the output channel on an external event.
2457 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2458 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2459 * or not a timer instance can clear the OCxREF signal on an external event.
2460 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2461 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2462 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2463 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2464 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2465 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2466 * @param TIMx Timer instance
2467 * @param Channel This parameter can be one of the following values:
2468 * @arg @ref LL_TIM_CHANNEL_CH1
2469 * @arg @ref LL_TIM_CHANNEL_CH2
2470 * @arg @ref LL_TIM_CHANNEL_CH3
2471 * @arg @ref LL_TIM_CHANNEL_CH4
2472 * @arg @ref LL_TIM_CHANNEL_CH5
2473 * @arg @ref LL_TIM_CHANNEL_CH6
2474 * @retval None
2475 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2476 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2477 {
2478 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2479 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2480 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2481 }
2482
2483 /**
2484 * @brief Disable clearing the output channel on an external event.
2485 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2486 * or not a timer instance can clear the OCxREF signal on an external event.
2487 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2488 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2489 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2490 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2491 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2492 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2493 * @param TIMx Timer instance
2494 * @param Channel This parameter can be one of the following values:
2495 * @arg @ref LL_TIM_CHANNEL_CH1
2496 * @arg @ref LL_TIM_CHANNEL_CH2
2497 * @arg @ref LL_TIM_CHANNEL_CH3
2498 * @arg @ref LL_TIM_CHANNEL_CH4
2499 * @arg @ref LL_TIM_CHANNEL_CH5
2500 * @arg @ref LL_TIM_CHANNEL_CH6
2501 * @retval None
2502 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2503 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2504 {
2505 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2506 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2507 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2508 }
2509
2510 /**
2511 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2512 * @note This function enables clearing the output channel on an external event.
2513 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2514 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2515 * or not a timer instance can clear the OCxREF signal on an external event.
2516 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2517 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2518 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2519 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2520 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2521 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2522 * @param TIMx Timer instance
2523 * @param Channel This parameter can be one of the following values:
2524 * @arg @ref LL_TIM_CHANNEL_CH1
2525 * @arg @ref LL_TIM_CHANNEL_CH2
2526 * @arg @ref LL_TIM_CHANNEL_CH3
2527 * @arg @ref LL_TIM_CHANNEL_CH4
2528 * @arg @ref LL_TIM_CHANNEL_CH5
2529 * @arg @ref LL_TIM_CHANNEL_CH6
2530 * @retval State of bit (1 or 0).
2531 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)2532 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2533 {
2534 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2535 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2536 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2537 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2538 }
2539
2540 /**
2541 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2542 * the Ocx and OCxN signals).
2543 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2544 * dead-time insertion feature is supported by a timer instance.
2545 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2546 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2547 * @param TIMx Timer instance
2548 * @param DeadTime between Min_Data=0 and Max_Data=255
2549 * @retval None
2550 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2551 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2552 {
2553 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2554 }
2555
2556 /**
2557 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2558 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2559 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2560 * whether or not a timer instance supports a 32 bits counter.
2561 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2562 * output channel 1 is supported by a timer instance.
2563 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2564 * @param TIMx Timer instance
2565 * @param CompareValue between Min_Data=0 and Max_Data=65535
2566 * @retval None
2567 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2568 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2569 {
2570 WRITE_REG(TIMx->CCR1, CompareValue);
2571 }
2572
2573 /**
2574 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2575 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2576 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2577 * whether or not a timer instance supports a 32 bits counter.
2578 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2579 * output channel 2 is supported by a timer instance.
2580 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2581 * @param TIMx Timer instance
2582 * @param CompareValue between Min_Data=0 and Max_Data=65535
2583 * @retval None
2584 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2585 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2586 {
2587 WRITE_REG(TIMx->CCR2, CompareValue);
2588 }
2589
2590 /**
2591 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2592 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2593 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2594 * whether or not a timer instance supports a 32 bits counter.
2595 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2596 * output channel is supported by a timer instance.
2597 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2598 * @param TIMx Timer instance
2599 * @param CompareValue between Min_Data=0 and Max_Data=65535
2600 * @retval None
2601 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2602 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2603 {
2604 WRITE_REG(TIMx->CCR3, CompareValue);
2605 }
2606
2607 /**
2608 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2609 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2610 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2611 * whether or not a timer instance supports a 32 bits counter.
2612 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2613 * output channel 4 is supported by a timer instance.
2614 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2615 * @param TIMx Timer instance
2616 * @param CompareValue between Min_Data=0 and Max_Data=65535
2617 * @retval None
2618 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2619 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2620 {
2621 WRITE_REG(TIMx->CCR4, CompareValue);
2622 }
2623
2624 /**
2625 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2626 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2627 * output channel 5 is supported by a timer instance.
2628 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2629 * @param TIMx Timer instance
2630 * @param CompareValue between Min_Data=0 and Max_Data=65535
2631 * @retval None
2632 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2633 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2634 {
2635 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2636 }
2637
2638 /**
2639 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2640 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2641 * output channel 6 is supported by a timer instance.
2642 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2643 * @param TIMx Timer instance
2644 * @param CompareValue between Min_Data=0 and Max_Data=65535
2645 * @retval None
2646 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2647 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2648 {
2649 WRITE_REG(TIMx->CCR6, CompareValue);
2650 }
2651
2652 /**
2653 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2654 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2655 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2656 * whether or not a timer instance supports a 32 bits counter.
2657 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2658 * output channel 1 is supported by a timer instance.
2659 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2660 * @param TIMx Timer instance
2661 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2662 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2663 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2664 {
2665 return (uint32_t)(READ_REG(TIMx->CCR1));
2666 }
2667
2668 /**
2669 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2670 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2671 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2672 * whether or not a timer instance supports a 32 bits counter.
2673 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2674 * output channel 2 is supported by a timer instance.
2675 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2676 * @param TIMx Timer instance
2677 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2678 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2679 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2680 {
2681 return (uint32_t)(READ_REG(TIMx->CCR2));
2682 }
2683
2684 /**
2685 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2686 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2687 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2688 * whether or not a timer instance supports a 32 bits counter.
2689 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2690 * output channel 3 is supported by a timer instance.
2691 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2692 * @param TIMx Timer instance
2693 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2694 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2695 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2696 {
2697 return (uint32_t)(READ_REG(TIMx->CCR3));
2698 }
2699
2700 /**
2701 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2702 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2703 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2704 * whether or not a timer instance supports a 32 bits counter.
2705 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2706 * output channel 4 is supported by a timer instance.
2707 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2708 * @param TIMx Timer instance
2709 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2710 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)2711 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
2712 {
2713 return (uint32_t)(READ_REG(TIMx->CCR4));
2714 }
2715
2716 /**
2717 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2718 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2719 * output channel 5 is supported by a timer instance.
2720 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2721 * @param TIMx Timer instance
2722 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2723 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)2724 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
2725 {
2726 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
2727 }
2728
2729 /**
2730 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2731 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2732 * output channel 6 is supported by a timer instance.
2733 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2734 * @param TIMx Timer instance
2735 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2736 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)2737 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
2738 {
2739 return (uint32_t)(READ_REG(TIMx->CCR6));
2740 }
2741
2742 /**
2743 * @brief Select on which reference signal the OC5REF is combined to.
2744 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2745 * whether or not a timer instance supports the combined 3-phase PWM mode.
2746 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2747 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2748 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2749 * @param TIMx Timer instance
2750 * @param GroupCH5 This parameter can be a combination of the following values:
2751 * @arg @ref LL_TIM_GROUPCH5_NONE
2752 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2753 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2754 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2755 * @retval None
2756 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)2757 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2758 {
2759 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
2760 }
2761
2762 /**
2763 * @}
2764 */
2765
2766 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2767 * @{
2768 */
2769 /**
2770 * @brief Configure input channel.
2771 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2772 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2773 * CCMR1 IC1F LL_TIM_IC_Config\n
2774 * CCMR1 CC2S LL_TIM_IC_Config\n
2775 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2776 * CCMR1 IC2F LL_TIM_IC_Config\n
2777 * CCMR2 CC3S LL_TIM_IC_Config\n
2778 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2779 * CCMR2 IC3F LL_TIM_IC_Config\n
2780 * CCMR2 CC4S LL_TIM_IC_Config\n
2781 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2782 * CCMR2 IC4F LL_TIM_IC_Config\n
2783 * CCER CC1P LL_TIM_IC_Config\n
2784 * CCER CC1NP LL_TIM_IC_Config\n
2785 * CCER CC2P LL_TIM_IC_Config\n
2786 * CCER CC2NP LL_TIM_IC_Config\n
2787 * CCER CC3P LL_TIM_IC_Config\n
2788 * CCER CC3NP LL_TIM_IC_Config\n
2789 * CCER CC4P LL_TIM_IC_Config\n
2790 * CCER CC4NP LL_TIM_IC_Config
2791 * @param TIMx Timer instance
2792 * @param Channel This parameter can be one of the following values:
2793 * @arg @ref LL_TIM_CHANNEL_CH1
2794 * @arg @ref LL_TIM_CHANNEL_CH2
2795 * @arg @ref LL_TIM_CHANNEL_CH3
2796 * @arg @ref LL_TIM_CHANNEL_CH4
2797 * @param Configuration This parameter must be a combination of all the following values:
2798 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2799 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2800 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2801 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2802 * @retval None
2803 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2804 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2805 {
2806 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2807 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2808 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2809 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
2810 << SHIFT_TAB_ICxx[iChannel]);
2811 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2812 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2813 }
2814
2815 /**
2816 * @brief Set the active input.
2817 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2818 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2819 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2820 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2821 * @param TIMx Timer instance
2822 * @param Channel This parameter can be one of the following values:
2823 * @arg @ref LL_TIM_CHANNEL_CH1
2824 * @arg @ref LL_TIM_CHANNEL_CH2
2825 * @arg @ref LL_TIM_CHANNEL_CH3
2826 * @arg @ref LL_TIM_CHANNEL_CH4
2827 * @param ICActiveInput This parameter can be one of the following values:
2828 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2829 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2830 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2831 * @retval None
2832 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2833 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2834 {
2835 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2836 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2837 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2838 }
2839
2840 /**
2841 * @brief Get the current active input.
2842 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2843 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2844 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2845 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2846 * @param TIMx Timer instance
2847 * @param Channel This parameter can be one of the following values:
2848 * @arg @ref LL_TIM_CHANNEL_CH1
2849 * @arg @ref LL_TIM_CHANNEL_CH2
2850 * @arg @ref LL_TIM_CHANNEL_CH3
2851 * @arg @ref LL_TIM_CHANNEL_CH4
2852 * @retval Returned value can be one of the following values:
2853 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2854 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2855 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2856 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)2857 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
2858 {
2859 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2860 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2861 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2862 }
2863
2864 /**
2865 * @brief Set the prescaler of input channel.
2866 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2867 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2868 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2869 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2870 * @param TIMx Timer instance
2871 * @param Channel This parameter can be one of the following values:
2872 * @arg @ref LL_TIM_CHANNEL_CH1
2873 * @arg @ref LL_TIM_CHANNEL_CH2
2874 * @arg @ref LL_TIM_CHANNEL_CH3
2875 * @arg @ref LL_TIM_CHANNEL_CH4
2876 * @param ICPrescaler This parameter can be one of the following values:
2877 * @arg @ref LL_TIM_ICPSC_DIV1
2878 * @arg @ref LL_TIM_ICPSC_DIV2
2879 * @arg @ref LL_TIM_ICPSC_DIV4
2880 * @arg @ref LL_TIM_ICPSC_DIV8
2881 * @retval None
2882 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2883 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2884 {
2885 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2886 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2887 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2888 }
2889
2890 /**
2891 * @brief Get the current prescaler value acting on an input channel.
2892 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2893 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2894 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2895 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2896 * @param TIMx Timer instance
2897 * @param Channel This parameter can be one of the following values:
2898 * @arg @ref LL_TIM_CHANNEL_CH1
2899 * @arg @ref LL_TIM_CHANNEL_CH2
2900 * @arg @ref LL_TIM_CHANNEL_CH3
2901 * @arg @ref LL_TIM_CHANNEL_CH4
2902 * @retval Returned value can be one of the following values:
2903 * @arg @ref LL_TIM_ICPSC_DIV1
2904 * @arg @ref LL_TIM_ICPSC_DIV2
2905 * @arg @ref LL_TIM_ICPSC_DIV4
2906 * @arg @ref LL_TIM_ICPSC_DIV8
2907 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)2908 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
2909 {
2910 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2911 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2912 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2913 }
2914
2915 /**
2916 * @brief Set the input filter duration.
2917 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2918 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2919 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2920 * CCMR2 IC4F LL_TIM_IC_SetFilter
2921 * @param TIMx Timer instance
2922 * @param Channel This parameter can be one of the following values:
2923 * @arg @ref LL_TIM_CHANNEL_CH1
2924 * @arg @ref LL_TIM_CHANNEL_CH2
2925 * @arg @ref LL_TIM_CHANNEL_CH3
2926 * @arg @ref LL_TIM_CHANNEL_CH4
2927 * @param ICFilter This parameter can be one of the following values:
2928 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2929 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2930 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2931 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2932 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2933 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2934 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2935 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2936 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2937 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2938 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2939 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2940 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2941 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2942 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2943 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2944 * @retval None
2945 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2946 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2947 {
2948 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2949 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2950 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2951 }
2952
2953 /**
2954 * @brief Get the input filter duration.
2955 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2956 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2957 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2958 * CCMR2 IC4F LL_TIM_IC_GetFilter
2959 * @param TIMx Timer instance
2960 * @param Channel This parameter can be one of the following values:
2961 * @arg @ref LL_TIM_CHANNEL_CH1
2962 * @arg @ref LL_TIM_CHANNEL_CH2
2963 * @arg @ref LL_TIM_CHANNEL_CH3
2964 * @arg @ref LL_TIM_CHANNEL_CH4
2965 * @retval Returned value can be one of the following values:
2966 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2967 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2968 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2969 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2970 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2971 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2972 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2973 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2974 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2975 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2976 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2977 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2978 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2979 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2980 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2981 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2982 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)2983 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
2984 {
2985 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2986 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2987 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2988 }
2989
2990 /**
2991 * @brief Set the input channel polarity.
2992 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2993 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2994 * CCER CC2P LL_TIM_IC_SetPolarity\n
2995 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2996 * CCER CC3P LL_TIM_IC_SetPolarity\n
2997 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2998 * CCER CC4P LL_TIM_IC_SetPolarity\n
2999 * CCER CC4NP LL_TIM_IC_SetPolarity
3000 * @param TIMx Timer instance
3001 * @param Channel This parameter can be one of the following values:
3002 * @arg @ref LL_TIM_CHANNEL_CH1
3003 * @arg @ref LL_TIM_CHANNEL_CH2
3004 * @arg @ref LL_TIM_CHANNEL_CH3
3005 * @arg @ref LL_TIM_CHANNEL_CH4
3006 * @param ICPolarity This parameter can be one of the following values:
3007 * @arg @ref LL_TIM_IC_POLARITY_RISING
3008 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3009 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3010 * @retval None
3011 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3012 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3013 {
3014 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3015 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3016 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3017 }
3018
3019 /**
3020 * @brief Get the current input channel polarity.
3021 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3022 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3023 * CCER CC2P LL_TIM_IC_GetPolarity\n
3024 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3025 * CCER CC3P LL_TIM_IC_GetPolarity\n
3026 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3027 * CCER CC4P LL_TIM_IC_GetPolarity\n
3028 * CCER CC4NP LL_TIM_IC_GetPolarity
3029 * @param TIMx Timer instance
3030 * @param Channel This parameter can be one of the following values:
3031 * @arg @ref LL_TIM_CHANNEL_CH1
3032 * @arg @ref LL_TIM_CHANNEL_CH2
3033 * @arg @ref LL_TIM_CHANNEL_CH3
3034 * @arg @ref LL_TIM_CHANNEL_CH4
3035 * @retval Returned value can be one of the following values:
3036 * @arg @ref LL_TIM_IC_POLARITY_RISING
3037 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3038 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3039 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3040 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3041 {
3042 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3043 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3044 SHIFT_TAB_CCxP[iChannel]);
3045 }
3046
3047 /**
3048 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3049 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3050 * a timer instance provides an XOR input.
3051 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3052 * @param TIMx Timer instance
3053 * @retval None
3054 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3055 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3056 {
3057 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3058 }
3059
3060 /**
3061 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3062 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3063 * a timer instance provides an XOR input.
3064 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3065 * @param TIMx Timer instance
3066 * @retval None
3067 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3068 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3069 {
3070 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3071 }
3072
3073 /**
3074 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3075 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3076 * a timer instance provides an XOR input.
3077 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3078 * @param TIMx Timer instance
3079 * @retval State of bit (1 or 0).
3080 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)3081 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3082 {
3083 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3084 }
3085
3086 /**
3087 * @brief Get captured value for input channel 1.
3088 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3089 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3090 * whether or not a timer instance supports a 32 bits counter.
3091 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3092 * input channel 1 is supported by a timer instance.
3093 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3094 * @param TIMx Timer instance
3095 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3096 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3097 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3098 {
3099 return (uint32_t)(READ_REG(TIMx->CCR1));
3100 }
3101
3102 /**
3103 * @brief Get captured value for input channel 2.
3104 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3105 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3106 * whether or not a timer instance supports a 32 bits counter.
3107 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3108 * input channel 2 is supported by a timer instance.
3109 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3110 * @param TIMx Timer instance
3111 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3112 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3113 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3114 {
3115 return (uint32_t)(READ_REG(TIMx->CCR2));
3116 }
3117
3118 /**
3119 * @brief Get captured value for input channel 3.
3120 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3121 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3122 * whether or not a timer instance supports a 32 bits counter.
3123 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3124 * input channel 3 is supported by a timer instance.
3125 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3126 * @param TIMx Timer instance
3127 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3128 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3129 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3130 {
3131 return (uint32_t)(READ_REG(TIMx->CCR3));
3132 }
3133
3134 /**
3135 * @brief Get captured value for input channel 4.
3136 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3137 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3138 * whether or not a timer instance supports a 32 bits counter.
3139 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3140 * input channel 4 is supported by a timer instance.
3141 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3142 * @param TIMx Timer instance
3143 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3144 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3145 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3146 {
3147 return (uint32_t)(READ_REG(TIMx->CCR4));
3148 }
3149
3150 /**
3151 * @}
3152 */
3153
3154 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3155 * @{
3156 */
3157 /**
3158 * @brief Enable external clock mode 2.
3159 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3160 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3161 * whether or not a timer instance supports external clock mode2.
3162 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3163 * @param TIMx Timer instance
3164 * @retval None
3165 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3166 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3167 {
3168 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3169 }
3170
3171 /**
3172 * @brief Disable external clock mode 2.
3173 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3174 * whether or not a timer instance supports external clock mode2.
3175 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3176 * @param TIMx Timer instance
3177 * @retval None
3178 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3179 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3180 {
3181 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3182 }
3183
3184 /**
3185 * @brief Indicate whether external clock mode 2 is enabled.
3186 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3187 * whether or not a timer instance supports external clock mode2.
3188 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3189 * @param TIMx Timer instance
3190 * @retval State of bit (1 or 0).
3191 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3192 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3193 {
3194 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3195 }
3196
3197 /**
3198 * @brief Set the clock source of the counter clock.
3199 * @note when selected clock source is external clock mode 1, the timer input
3200 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3201 * function. This timer input must be configured by calling
3202 * the @ref LL_TIM_IC_Config() function.
3203 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3204 * whether or not a timer instance supports external clock mode1.
3205 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3206 * whether or not a timer instance supports external clock mode2.
3207 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3208 * SMCR ECE LL_TIM_SetClockSource
3209 * @param TIMx Timer instance
3210 * @param ClockSource This parameter can be one of the following values:
3211 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3212 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3213 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3214 * @retval None
3215 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3216 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3217 {
3218 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3219 }
3220
3221 /**
3222 * @brief Set the encoder interface mode.
3223 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3224 * whether or not a timer instance supports the encoder mode.
3225 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3226 * @param TIMx Timer instance
3227 * @param EncoderMode This parameter can be one of the following values:
3228 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3229 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3230 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3231 * @retval None
3232 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3233 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3234 {
3235 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3236 }
3237
3238 /**
3239 * @}
3240 */
3241
3242 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3243 * @{
3244 */
3245 /**
3246 * @brief Set the trigger output (TRGO) used for timer synchronization .
3247 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3248 * whether or not a timer instance can operate as a master timer.
3249 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3250 * @param TIMx Timer instance
3251 * @param TimerSynchronization This parameter can be one of the following values:
3252 * @arg @ref LL_TIM_TRGO_RESET
3253 * @arg @ref LL_TIM_TRGO_ENABLE
3254 * @arg @ref LL_TIM_TRGO_UPDATE
3255 * @arg @ref LL_TIM_TRGO_CC1IF
3256 * @arg @ref LL_TIM_TRGO_OC1REF
3257 * @arg @ref LL_TIM_TRGO_OC2REF
3258 * @arg @ref LL_TIM_TRGO_OC3REF
3259 * @arg @ref LL_TIM_TRGO_OC4REF
3260 * @retval None
3261 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3262 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3263 {
3264 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3265 }
3266
3267 /**
3268 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3269 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3270 * whether or not a timer instance can be used for ADC synchronization.
3271 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3272 * @param TIMx Timer Instance
3273 * @param ADCSynchronization This parameter can be one of the following values:
3274 * @arg @ref LL_TIM_TRGO2_RESET
3275 * @arg @ref LL_TIM_TRGO2_ENABLE
3276 * @arg @ref LL_TIM_TRGO2_UPDATE
3277 * @arg @ref LL_TIM_TRGO2_CC1F
3278 * @arg @ref LL_TIM_TRGO2_OC1
3279 * @arg @ref LL_TIM_TRGO2_OC2
3280 * @arg @ref LL_TIM_TRGO2_OC3
3281 * @arg @ref LL_TIM_TRGO2_OC4
3282 * @arg @ref LL_TIM_TRGO2_OC5
3283 * @arg @ref LL_TIM_TRGO2_OC6
3284 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3285 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3286 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3287 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3288 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3289 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3290 * @retval None
3291 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3292 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3293 {
3294 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3295 }
3296
3297 /**
3298 * @brief Set the synchronization mode of a slave timer.
3299 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3300 * a timer instance can operate as a slave timer.
3301 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3302 * @param TIMx Timer instance
3303 * @param SlaveMode This parameter can be one of the following values:
3304 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3305 * @arg @ref LL_TIM_SLAVEMODE_RESET
3306 * @arg @ref LL_TIM_SLAVEMODE_GATED
3307 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3308 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3309 * @retval None
3310 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3311 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3312 {
3313 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3314 }
3315
3316 /**
3317 * @brief Set the selects the trigger input to be used to synchronize the counter.
3318 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3319 * a timer instance can operate as a slave timer.
3320 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3321 * @param TIMx Timer instance
3322 * @param TriggerInput This parameter can be one of the following values:
3323 * @arg @ref LL_TIM_TS_ITR0
3324 * @arg @ref LL_TIM_TS_ITR1
3325 * @arg @ref LL_TIM_TS_ITR2
3326 * @arg @ref LL_TIM_TS_ITR3
3327 * @arg @ref LL_TIM_TS_TI1F_ED
3328 * @arg @ref LL_TIM_TS_TI1FP1
3329 * @arg @ref LL_TIM_TS_TI2FP2
3330 * @arg @ref LL_TIM_TS_ETRF
3331 * @retval None
3332 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3333 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3334 {
3335 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3336 }
3337
3338 /**
3339 * @brief Enable the Master/Slave mode.
3340 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3341 * a timer instance can operate as a slave timer.
3342 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3343 * @param TIMx Timer instance
3344 * @retval None
3345 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3346 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3347 {
3348 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3349 }
3350
3351 /**
3352 * @brief Disable the Master/Slave mode.
3353 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3354 * a timer instance can operate as a slave timer.
3355 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3356 * @param TIMx Timer instance
3357 * @retval None
3358 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3359 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3360 {
3361 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3362 }
3363
3364 /**
3365 * @brief Indicates whether the Master/Slave mode is enabled.
3366 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3367 * a timer instance can operate as a slave timer.
3368 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3369 * @param TIMx Timer instance
3370 * @retval State of bit (1 or 0).
3371 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3372 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3373 {
3374 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3375 }
3376
3377 /**
3378 * @brief Configure the external trigger (ETR) input.
3379 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3380 * a timer instance provides an external trigger input.
3381 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3382 * SMCR ETPS LL_TIM_ConfigETR\n
3383 * SMCR ETF LL_TIM_ConfigETR
3384 * @param TIMx Timer instance
3385 * @param ETRPolarity This parameter can be one of the following values:
3386 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3387 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3388 * @param ETRPrescaler This parameter can be one of the following values:
3389 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3390 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3391 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3392 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3393 * @param ETRFilter This parameter can be one of the following values:
3394 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3395 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3396 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3397 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3398 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3399 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3400 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3401 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3402 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3403 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3404 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3405 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3406 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3407 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3408 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3409 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3410 * @retval None
3411 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3412 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3413 uint32_t ETRFilter)
3414 {
3415 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3416 }
3417
3418 /**
3419 * @brief Select the external trigger (ETR) input source.
3420 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3421 * not a timer instance supports ETR source selection.
3422 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
3423 * @param TIMx Timer instance
3424 * @param ETRSource This parameter can be one of the following values:
3425 * @arg @ref LL_TIM_ETRSOURCE_GPIO
3426 * @arg @ref LL_TIM_ETRSOURCE_COMP1
3427 * @arg @ref LL_TIM_ETRSOURCE_COMP2
3428 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD1
3429 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD2
3430 * @arg @ref LL_TIM_ETRSOURCE_ADC1_AWD3
3431 * @retval None
3432 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3433 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3434 {
3435 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
3436 }
3437
3438 /**
3439 * @}
3440 */
3441
3442 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3443 * @{
3444 */
3445 /**
3446 * @brief Enable the break function.
3447 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3448 * a timer instance provides a break input.
3449 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3450 * @param TIMx Timer instance
3451 * @retval None
3452 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3453 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3454 {
3455 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3456 }
3457
3458 /**
3459 * @brief Disable the break function.
3460 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3461 * @param TIMx Timer instance
3462 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3463 * a timer instance provides a break input.
3464 * @retval None
3465 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3466 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3467 {
3468 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3469 }
3470
3471 /**
3472 * @brief Configure the break input.
3473 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3474 * a timer instance provides a break input.
3475 * @note Bidirectional mode is only supported by advanced timer instances.
3476 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3477 * a timer instance is an advanced-control timer.
3478 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
3479 * in input mode and in open drain output mode. Any active Break event will
3480 * assert a low logic level on the Break input to indicate an internal break
3481 * event to external devices.
3482 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
3483 * LL_TIM_BREAK_AFMODE_INPUT.
3484 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3485 * BDTR BKF LL_TIM_ConfigBRK\n
3486 * BDTR BKBID LL_TIM_ConfigBRK
3487 * @param TIMx Timer instance
3488 * @param BreakPolarity This parameter can be one of the following values:
3489 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3490 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3491 * @param BreakFilter This parameter can be one of the following values:
3492 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3493 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3494 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3495 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3496 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3497 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3498 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3499 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3500 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3501 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3502 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3503 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3504 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3505 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3506 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3507 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3508 * @param BreakAFMode This parameter can be one of the following values:
3509 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
3510 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
3511 * @retval None
3512 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)3513 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
3514 uint32_t BreakAFMode)
3515 {
3516 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
3517 }
3518
3519 /**
3520 * @brief Disarm the break input (when it operates in bidirectional mode).
3521 * @note The break input can be disarmed only when it is configured in
3522 * bidirectional mode and when when MOE is reset.
3523 * @note Purpose is to be able to have the input voltage back to high-state,
3524 * whatever the time constant on the output .
3525 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
3526 * @param TIMx Timer instance
3527 * @retval None
3528 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)3529 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
3530 {
3531 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3532 }
3533
3534 /**
3535 * @brief Re-arm the break input (when it operates in bidirectional mode).
3536 * @note The Break input is automatically armed as soon as MOE bit is set.
3537 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3538 * @param TIMx Timer instance
3539 * @retval None
3540 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)3541 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3542 {
3543 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3544 }
3545
3546 /**
3547 * @brief Enable the break 2 function.
3548 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3549 * a timer instance provides a second break input.
3550 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3551 * @param TIMx Timer instance
3552 * @retval None
3553 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)3554 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3555 {
3556 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3557 }
3558
3559 /**
3560 * @brief Disable the break 2 function.
3561 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3562 * a timer instance provides a second break input.
3563 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3564 * @param TIMx Timer instance
3565 * @retval None
3566 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)3567 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3568 {
3569 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3570 }
3571
3572 /**
3573 * @brief Configure the break 2 input.
3574 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3575 * a timer instance provides a second break input.
3576 * @note Bidirectional mode is only supported by advanced timer instances.
3577 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
3578 * a timer instance is an advanced-control timer.
3579 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
3580 * in input mode and in open drain output mode. Any active Break event will
3581 * assert a low logic level on the Break 2 input to indicate an internal break
3582 * event to external devices.
3583 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
3584 * LL_TIM_BREAK2_AFMODE_INPUT.
3585 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3586 * BDTR BK2F LL_TIM_ConfigBRK2\n
3587 * BDTR BK2BID LL_TIM_ConfigBRK2
3588 * @param TIMx Timer instance
3589 * @param Break2Polarity This parameter can be one of the following values:
3590 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3591 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3592 * @param Break2Filter This parameter can be one of the following values:
3593 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3594 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3595 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3596 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3597 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3598 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3599 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3600 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3601 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3602 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3603 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3604 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3605 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3606 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3607 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3608 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3609 * @param Break2AFMode This parameter can be one of the following values:
3610 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
3611 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
3612 * @retval None
3613 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)3614 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
3615 uint32_t Break2AFMode)
3616 {
3617 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
3618 }
3619
3620 /**
3621 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
3622 * @note The break 2 input can be disarmed only when it is configured in
3623 * bidirectional mode and when when MOE is reset.
3624 * @note Purpose is to be able to have the input voltage back to high-state,
3625 * whatever the time constant on the output.
3626 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
3627 * @param TIMx Timer instance
3628 * @retval None
3629 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)3630 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
3631 {
3632 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3633 }
3634
3635 /**
3636 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3637 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
3638 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3639 * @param TIMx Timer instance
3640 * @retval None
3641 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)3642 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3643 {
3644 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3645 }
3646
3647 /**
3648 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3649 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3650 * a timer instance provides a break input.
3651 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3652 * BDTR OSSR LL_TIM_SetOffStates
3653 * @param TIMx Timer instance
3654 * @param OffStateIdle This parameter can be one of the following values:
3655 * @arg @ref LL_TIM_OSSI_DISABLE
3656 * @arg @ref LL_TIM_OSSI_ENABLE
3657 * @param OffStateRun This parameter can be one of the following values:
3658 * @arg @ref LL_TIM_OSSR_DISABLE
3659 * @arg @ref LL_TIM_OSSR_ENABLE
3660 * @retval None
3661 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)3662 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3663 {
3664 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3665 }
3666
3667 /**
3668 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3669 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3670 * a timer instance provides a break input.
3671 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3672 * @param TIMx Timer instance
3673 * @retval None
3674 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)3675 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3676 {
3677 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3678 }
3679
3680 /**
3681 * @brief Disable automatic output (MOE can be set only by software).
3682 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3683 * a timer instance provides a break input.
3684 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3685 * @param TIMx Timer instance
3686 * @retval None
3687 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)3688 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3689 {
3690 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3691 }
3692
3693 /**
3694 * @brief Indicate whether automatic output is enabled.
3695 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3696 * a timer instance provides a break input.
3697 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3698 * @param TIMx Timer instance
3699 * @retval State of bit (1 or 0).
3700 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)3701 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
3702 {
3703 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
3704 }
3705
3706 /**
3707 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3708 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3709 * software and is reset in case of break or break2 event
3710 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3711 * a timer instance provides a break input.
3712 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3713 * @param TIMx Timer instance
3714 * @retval None
3715 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)3716 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3717 {
3718 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3719 }
3720
3721 /**
3722 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3723 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3724 * software and is reset in case of break or break2 event.
3725 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3726 * a timer instance provides a break input.
3727 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3728 * @param TIMx Timer instance
3729 * @retval None
3730 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)3731 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3732 {
3733 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3734 }
3735
3736 /**
3737 * @brief Indicates whether outputs are enabled.
3738 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3739 * a timer instance provides a break input.
3740 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3741 * @param TIMx Timer instance
3742 * @retval State of bit (1 or 0).
3743 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)3744 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
3745 {
3746 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
3747 }
3748
3749 /**
3750 * @brief Enable the signals connected to the designated timer break input.
3751 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3752 * or not a timer instance allows for break input selection.
3753 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
3754 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
3755 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
3756 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
3757 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n
3758 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
3759 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
3760 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
3761 * @param TIMx Timer instance
3762 * @param BreakInput This parameter can be one of the following values:
3763 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3764 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3765 * @param Source This parameter can be one of the following values:
3766 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3767 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3768 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3769 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3770 * @retval None
3771 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3772 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3773 {
3774 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3775 SET_BIT(*pReg, Source);
3776 }
3777
3778 /**
3779 * @brief Disable the signals connected to the designated timer break input.
3780 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3781 * or not a timer instance allows for break input selection.
3782 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
3783 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
3784 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
3785 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
3786 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n
3787 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
3788 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
3789 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
3790 * @param TIMx Timer instance
3791 * @param BreakInput This parameter can be one of the following values:
3792 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3793 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3794 * @param Source This parameter can be one of the following values:
3795 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3796 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3797 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3798 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3799 * @retval None
3800 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)3801 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3802 {
3803 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3804 CLEAR_BIT(*pReg, Source);
3805 }
3806
3807 /**
3808 * @brief Set the polarity of the break signal for the timer break input.
3809 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3810 * or not a timer instance allows for break input selection.
3811 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
3812 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
3813 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
3814 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
3815 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
3816 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
3817 * @param TIMx Timer instance
3818 * @param BreakInput This parameter can be one of the following values:
3819 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3820 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3821 * @param Source This parameter can be one of the following values:
3822 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3823 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
3824 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
3825 * @param Polarity This parameter can be one of the following values:
3826 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3827 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3828 * @retval None
3829 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)3830 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3831 uint32_t Polarity)
3832 {
3833 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
3834 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
3835 }
3836 /**
3837 * @}
3838 */
3839
3840 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3841 * @{
3842 */
3843 /**
3844 * @brief Configures the timer DMA burst feature.
3845 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3846 * not a timer instance supports the DMA burst mode.
3847 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3848 * DCR DBA LL_TIM_ConfigDMABurst
3849 * @param TIMx Timer instance
3850 * @param DMABurstBaseAddress This parameter can be one of the following values:
3851 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3852 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3853 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3854 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3855 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3856 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3857 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3858 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3859 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3860 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3861 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3862 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3863 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3864 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3865 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3866 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3867 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3868 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3869 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
3870 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3871 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3872 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3873 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
3874 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
3875 * @param DMABurstLength This parameter can be one of the following values:
3876 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3877 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3878 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3879 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3880 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3881 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3882 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3883 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3884 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3885 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3886 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3887 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3888 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3889 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3890 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3891 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3892 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3893 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3894 * @retval None
3895 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)3896 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3897 {
3898 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
3899 }
3900
3901 /**
3902 * @}
3903 */
3904
3905 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3906 * @{
3907 */
3908 /**
3909 * @brief Remap TIM inputs (input channel, internal/external triggers).
3910 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3911 * a some timer inputs can be remapped.
3912 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
3913 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
3914 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
3915 * TIM2_OR1 ETR1_RMP LL_TIM_SetRemap\n
3916 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
3917 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
3918 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
3919 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
3920 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
3921 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
3922 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap
3923 * @param TIMx Timer instance
3924 * @param Remap Remap param depends on the TIMx. Description available only
3925 * in CHM version of the User Manual (not in .pdf).
3926 * Otherwise see Reference Manual description of OR1 registers.
3927 *
3928 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3929 *
3930 * TIM1: any combination of TI1_RMP, ETR_ADC1_RMP where
3931 *
3932 * . . TI1_RMP can be one of the following values
3933 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
3934 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
3935 *
3936 * . . ETR_ADC1_RMP can be one of the following values
3937 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
3938 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
3939 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
3940 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
3941 *
3942 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
3943 *
3944 * . . ITR1_RMP can be one of the following values
3945 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3946 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
3947 *
3948 * . . ETR1_RMP can be one of the following values
3949 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
3950 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
3951 *
3952 * TI4_RMP can be one of the following values
3953 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
3954 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
3955 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
3956 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
3957 *
3958 * TIM3: one of the following values
3959 *
3960 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
3961 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
3962 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
3963 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
3964 *
3965 * TIM8: one of the following values
3966 *
3967 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
3968 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
3969 *
3970 * TIM15: any combination of TI1_RMP, ENCODER_MODE where
3971 *
3972 * . . TI1_RMP can be one of the following values
3973 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
3974 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
3975 *
3976 * . . ENCODER_MODE can be one of the following values
3977 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
3978 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
3979 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
3980 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
3981 *
3982 * TIM16: one of the following values
3983 *
3984 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
3985 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
3986 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
3987 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
3988 *
3989 * TIM17: one of the following values
3990 *
3991 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
3992 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
3993 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
3994 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
3995 * @retval None
3996 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3997 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3998 {
3999 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
4000 }
4001
4002 /**
4003 * @}
4004 */
4005
4006 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4007 * @{
4008 */
4009 /**
4010 * @brief Clear the update interrupt flag (UIF).
4011 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4012 * @param TIMx Timer instance
4013 * @retval None
4014 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4015 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4016 {
4017 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4018 }
4019
4020 /**
4021 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4022 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4023 * @param TIMx Timer instance
4024 * @retval State of bit (1 or 0).
4025 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4026 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4027 {
4028 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4029 }
4030
4031 /**
4032 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4033 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4034 * @param TIMx Timer instance
4035 * @retval None
4036 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4037 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4038 {
4039 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4040 }
4041
4042 /**
4043 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4044 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4045 * @param TIMx Timer instance
4046 * @retval State of bit (1 or 0).
4047 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4048 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4049 {
4050 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4051 }
4052
4053 /**
4054 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4055 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4056 * @param TIMx Timer instance
4057 * @retval None
4058 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4059 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4060 {
4061 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4062 }
4063
4064 /**
4065 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4066 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4067 * @param TIMx Timer instance
4068 * @retval State of bit (1 or 0).
4069 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4070 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4071 {
4072 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4073 }
4074
4075 /**
4076 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4077 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4078 * @param TIMx Timer instance
4079 * @retval None
4080 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4081 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4082 {
4083 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4084 }
4085
4086 /**
4087 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4088 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4089 * @param TIMx Timer instance
4090 * @retval State of bit (1 or 0).
4091 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4092 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4093 {
4094 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4095 }
4096
4097 /**
4098 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4099 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4100 * @param TIMx Timer instance
4101 * @retval None
4102 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4103 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4104 {
4105 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4106 }
4107
4108 /**
4109 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4110 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4111 * @param TIMx Timer instance
4112 * @retval State of bit (1 or 0).
4113 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4114 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4115 {
4116 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4117 }
4118
4119 /**
4120 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4121 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4122 * @param TIMx Timer instance
4123 * @retval None
4124 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4125 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4126 {
4127 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4128 }
4129
4130 /**
4131 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4132 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4133 * @param TIMx Timer instance
4134 * @retval State of bit (1 or 0).
4135 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4136 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4137 {
4138 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4139 }
4140
4141 /**
4142 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4143 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4144 * @param TIMx Timer instance
4145 * @retval None
4146 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4147 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4148 {
4149 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4150 }
4151
4152 /**
4153 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4154 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4155 * @param TIMx Timer instance
4156 * @retval State of bit (1 or 0).
4157 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4158 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4159 {
4160 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4161 }
4162
4163 /**
4164 * @brief Clear the commutation interrupt flag (COMIF).
4165 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4166 * @param TIMx Timer instance
4167 * @retval None
4168 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4169 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4170 {
4171 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4172 }
4173
4174 /**
4175 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4176 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4177 * @param TIMx Timer instance
4178 * @retval State of bit (1 or 0).
4179 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4180 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4181 {
4182 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
4183 }
4184
4185 /**
4186 * @brief Clear the trigger interrupt flag (TIF).
4187 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
4188 * @param TIMx Timer instance
4189 * @retval None
4190 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)4191 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
4192 {
4193 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
4194 }
4195
4196 /**
4197 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
4198 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
4199 * @param TIMx Timer instance
4200 * @retval State of bit (1 or 0).
4201 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)4202 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
4203 {
4204 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
4205 }
4206
4207 /**
4208 * @brief Clear the break interrupt flag (BIF).
4209 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
4210 * @param TIMx Timer instance
4211 * @retval None
4212 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)4213 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
4214 {
4215 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
4216 }
4217
4218 /**
4219 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
4220 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
4221 * @param TIMx Timer instance
4222 * @retval State of bit (1 or 0).
4223 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)4224 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
4225 {
4226 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
4227 }
4228
4229 /**
4230 * @brief Clear the break 2 interrupt flag (B2IF).
4231 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
4232 * @param TIMx Timer instance
4233 * @retval None
4234 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)4235 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
4236 {
4237 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
4238 }
4239
4240 /**
4241 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
4242 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
4243 * @param TIMx Timer instance
4244 * @retval State of bit (1 or 0).
4245 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)4246 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
4247 {
4248 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
4249 }
4250
4251 /**
4252 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
4253 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
4254 * @param TIMx Timer instance
4255 * @retval None
4256 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)4257 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
4258 {
4259 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
4260 }
4261
4262 /**
4263 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
4264 * (Capture/Compare 1 interrupt is pending).
4265 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
4266 * @param TIMx Timer instance
4267 * @retval State of bit (1 or 0).
4268 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)4269 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
4270 {
4271 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
4272 }
4273
4274 /**
4275 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
4276 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
4277 * @param TIMx Timer instance
4278 * @retval None
4279 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)4280 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
4281 {
4282 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
4283 }
4284
4285 /**
4286 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
4287 * (Capture/Compare 2 over-capture interrupt is pending).
4288 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
4289 * @param TIMx Timer instance
4290 * @retval State of bit (1 or 0).
4291 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)4292 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
4293 {
4294 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
4295 }
4296
4297 /**
4298 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
4299 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
4300 * @param TIMx Timer instance
4301 * @retval None
4302 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)4303 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
4304 {
4305 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
4306 }
4307
4308 /**
4309 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
4310 * (Capture/Compare 3 over-capture interrupt is pending).
4311 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
4312 * @param TIMx Timer instance
4313 * @retval State of bit (1 or 0).
4314 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)4315 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
4316 {
4317 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
4318 }
4319
4320 /**
4321 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
4322 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
4323 * @param TIMx Timer instance
4324 * @retval None
4325 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)4326 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
4327 {
4328 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
4329 }
4330
4331 /**
4332 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
4333 * (Capture/Compare 4 over-capture interrupt is pending).
4334 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
4335 * @param TIMx Timer instance
4336 * @retval State of bit (1 or 0).
4337 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)4338 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
4339 {
4340 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
4341 }
4342
4343 /**
4344 * @brief Clear the system break interrupt flag (SBIF).
4345 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
4346 * @param TIMx Timer instance
4347 * @retval None
4348 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)4349 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
4350 {
4351 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
4352 }
4353
4354 /**
4355 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
4356 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
4357 * @param TIMx Timer instance
4358 * @retval State of bit (1 or 0).
4359 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)4360 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
4361 {
4362 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
4363 }
4364
4365 /**
4366 * @}
4367 */
4368
4369 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4370 * @{
4371 */
4372 /**
4373 * @brief Enable update interrupt (UIE).
4374 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4375 * @param TIMx Timer instance
4376 * @retval None
4377 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)4378 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4379 {
4380 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4381 }
4382
4383 /**
4384 * @brief Disable update interrupt (UIE).
4385 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4386 * @param TIMx Timer instance
4387 * @retval None
4388 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)4389 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4390 {
4391 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4392 }
4393
4394 /**
4395 * @brief Indicates whether the update interrupt (UIE) is enabled.
4396 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4397 * @param TIMx Timer instance
4398 * @retval State of bit (1 or 0).
4399 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)4400 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
4401 {
4402 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
4403 }
4404
4405 /**
4406 * @brief Enable capture/compare 1 interrupt (CC1IE).
4407 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4408 * @param TIMx Timer instance
4409 * @retval None
4410 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)4411 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4412 {
4413 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4414 }
4415
4416 /**
4417 * @brief Disable capture/compare 1 interrupt (CC1IE).
4418 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4419 * @param TIMx Timer instance
4420 * @retval None
4421 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)4422 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4423 {
4424 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4425 }
4426
4427 /**
4428 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4429 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4430 * @param TIMx Timer instance
4431 * @retval State of bit (1 or 0).
4432 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)4433 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
4434 {
4435 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
4436 }
4437
4438 /**
4439 * @brief Enable capture/compare 2 interrupt (CC2IE).
4440 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4441 * @param TIMx Timer instance
4442 * @retval None
4443 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)4444 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4445 {
4446 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4447 }
4448
4449 /**
4450 * @brief Disable capture/compare 2 interrupt (CC2IE).
4451 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4452 * @param TIMx Timer instance
4453 * @retval None
4454 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)4455 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4456 {
4457 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4458 }
4459
4460 /**
4461 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4462 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4463 * @param TIMx Timer instance
4464 * @retval State of bit (1 or 0).
4465 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)4466 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
4467 {
4468 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
4469 }
4470
4471 /**
4472 * @brief Enable capture/compare 3 interrupt (CC3IE).
4473 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4474 * @param TIMx Timer instance
4475 * @retval None
4476 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)4477 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4478 {
4479 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4480 }
4481
4482 /**
4483 * @brief Disable capture/compare 3 interrupt (CC3IE).
4484 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4485 * @param TIMx Timer instance
4486 * @retval None
4487 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)4488 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4489 {
4490 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4491 }
4492
4493 /**
4494 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4495 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4496 * @param TIMx Timer instance
4497 * @retval State of bit (1 or 0).
4498 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)4499 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
4500 {
4501 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
4502 }
4503
4504 /**
4505 * @brief Enable capture/compare 4 interrupt (CC4IE).
4506 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4507 * @param TIMx Timer instance
4508 * @retval None
4509 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)4510 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4511 {
4512 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4513 }
4514
4515 /**
4516 * @brief Disable capture/compare 4 interrupt (CC4IE).
4517 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4518 * @param TIMx Timer instance
4519 * @retval None
4520 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)4521 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4522 {
4523 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4524 }
4525
4526 /**
4527 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4528 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4529 * @param TIMx Timer instance
4530 * @retval State of bit (1 or 0).
4531 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)4532 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
4533 {
4534 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
4535 }
4536
4537 /**
4538 * @brief Enable commutation interrupt (COMIE).
4539 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4540 * @param TIMx Timer instance
4541 * @retval None
4542 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)4543 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4544 {
4545 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4546 }
4547
4548 /**
4549 * @brief Disable commutation interrupt (COMIE).
4550 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4551 * @param TIMx Timer instance
4552 * @retval None
4553 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)4554 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4555 {
4556 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4557 }
4558
4559 /**
4560 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4561 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4562 * @param TIMx Timer instance
4563 * @retval State of bit (1 or 0).
4564 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)4565 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
4566 {
4567 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
4568 }
4569
4570 /**
4571 * @brief Enable trigger interrupt (TIE).
4572 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4573 * @param TIMx Timer instance
4574 * @retval None
4575 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)4576 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4577 {
4578 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4579 }
4580
4581 /**
4582 * @brief Disable trigger interrupt (TIE).
4583 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4584 * @param TIMx Timer instance
4585 * @retval None
4586 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)4587 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4588 {
4589 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4590 }
4591
4592 /**
4593 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4594 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4595 * @param TIMx Timer instance
4596 * @retval State of bit (1 or 0).
4597 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)4598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
4599 {
4600 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
4601 }
4602
4603 /**
4604 * @brief Enable break interrupt (BIE).
4605 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4606 * @param TIMx Timer instance
4607 * @retval None
4608 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)4609 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4610 {
4611 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4612 }
4613
4614 /**
4615 * @brief Disable break interrupt (BIE).
4616 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4617 * @param TIMx Timer instance
4618 * @retval None
4619 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)4620 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4621 {
4622 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4623 }
4624
4625 /**
4626 * @brief Indicates whether the break interrupt (BIE) is enabled.
4627 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4628 * @param TIMx Timer instance
4629 * @retval State of bit (1 or 0).
4630 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)4631 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
4632 {
4633 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
4634 }
4635
4636 /**
4637 * @}
4638 */
4639
4640 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
4641 * @{
4642 */
4643 /**
4644 * @brief Enable update DMA request (UDE).
4645 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4646 * @param TIMx Timer instance
4647 * @retval None
4648 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)4649 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4650 {
4651 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4652 }
4653
4654 /**
4655 * @brief Disable update DMA request (UDE).
4656 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4657 * @param TIMx Timer instance
4658 * @retval None
4659 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)4660 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4661 {
4662 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4663 }
4664
4665 /**
4666 * @brief Indicates whether the update DMA request (UDE) is enabled.
4667 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4668 * @param TIMx Timer instance
4669 * @retval State of bit (1 or 0).
4670 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)4671 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
4672 {
4673 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
4674 }
4675
4676 /**
4677 * @brief Enable capture/compare 1 DMA request (CC1DE).
4678 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4679 * @param TIMx Timer instance
4680 * @retval None
4681 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)4682 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4683 {
4684 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4685 }
4686
4687 /**
4688 * @brief Disable capture/compare 1 DMA request (CC1DE).
4689 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4690 * @param TIMx Timer instance
4691 * @retval None
4692 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)4693 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4694 {
4695 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4696 }
4697
4698 /**
4699 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4700 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4701 * @param TIMx Timer instance
4702 * @retval State of bit (1 or 0).
4703 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)4704 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
4705 {
4706 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
4707 }
4708
4709 /**
4710 * @brief Enable capture/compare 2 DMA request (CC2DE).
4711 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4712 * @param TIMx Timer instance
4713 * @retval None
4714 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)4715 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4716 {
4717 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4718 }
4719
4720 /**
4721 * @brief Disable capture/compare 2 DMA request (CC2DE).
4722 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4723 * @param TIMx Timer instance
4724 * @retval None
4725 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)4726 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4727 {
4728 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4729 }
4730
4731 /**
4732 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4733 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4734 * @param TIMx Timer instance
4735 * @retval State of bit (1 or 0).
4736 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)4737 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
4738 {
4739 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
4740 }
4741
4742 /**
4743 * @brief Enable capture/compare 3 DMA request (CC3DE).
4744 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4745 * @param TIMx Timer instance
4746 * @retval None
4747 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)4748 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4749 {
4750 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4751 }
4752
4753 /**
4754 * @brief Disable capture/compare 3 DMA request (CC3DE).
4755 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4756 * @param TIMx Timer instance
4757 * @retval None
4758 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)4759 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4760 {
4761 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4762 }
4763
4764 /**
4765 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4766 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4767 * @param TIMx Timer instance
4768 * @retval State of bit (1 or 0).
4769 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)4770 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
4771 {
4772 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
4773 }
4774
4775 /**
4776 * @brief Enable capture/compare 4 DMA request (CC4DE).
4777 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4778 * @param TIMx Timer instance
4779 * @retval None
4780 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)4781 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4782 {
4783 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4784 }
4785
4786 /**
4787 * @brief Disable capture/compare 4 DMA request (CC4DE).
4788 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4789 * @param TIMx Timer instance
4790 * @retval None
4791 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)4792 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4793 {
4794 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4795 }
4796
4797 /**
4798 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4799 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4800 * @param TIMx Timer instance
4801 * @retval State of bit (1 or 0).
4802 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)4803 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
4804 {
4805 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
4806 }
4807
4808 /**
4809 * @brief Enable commutation DMA request (COMDE).
4810 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4811 * @param TIMx Timer instance
4812 * @retval None
4813 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)4814 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4815 {
4816 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4817 }
4818
4819 /**
4820 * @brief Disable commutation DMA request (COMDE).
4821 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4822 * @param TIMx Timer instance
4823 * @retval None
4824 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)4825 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4826 {
4827 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4828 }
4829
4830 /**
4831 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4832 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4833 * @param TIMx Timer instance
4834 * @retval State of bit (1 or 0).
4835 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)4836 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
4837 {
4838 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
4839 }
4840
4841 /**
4842 * @brief Enable trigger interrupt (TDE).
4843 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4844 * @param TIMx Timer instance
4845 * @retval None
4846 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)4847 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4848 {
4849 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4850 }
4851
4852 /**
4853 * @brief Disable trigger interrupt (TDE).
4854 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4855 * @param TIMx Timer instance
4856 * @retval None
4857 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)4858 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4859 {
4860 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4861 }
4862
4863 /**
4864 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4865 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4866 * @param TIMx Timer instance
4867 * @retval State of bit (1 or 0).
4868 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)4869 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
4870 {
4871 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
4872 }
4873
4874 /**
4875 * @}
4876 */
4877
4878 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4879 * @{
4880 */
4881 /**
4882 * @brief Generate an update event.
4883 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4884 * @param TIMx Timer instance
4885 * @retval None
4886 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)4887 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4888 {
4889 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4890 }
4891
4892 /**
4893 * @brief Generate Capture/Compare 1 event.
4894 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4895 * @param TIMx Timer instance
4896 * @retval None
4897 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)4898 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4899 {
4900 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4901 }
4902
4903 /**
4904 * @brief Generate Capture/Compare 2 event.
4905 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4906 * @param TIMx Timer instance
4907 * @retval None
4908 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)4909 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4910 {
4911 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4912 }
4913
4914 /**
4915 * @brief Generate Capture/Compare 3 event.
4916 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4917 * @param TIMx Timer instance
4918 * @retval None
4919 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)4920 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4921 {
4922 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4923 }
4924
4925 /**
4926 * @brief Generate Capture/Compare 4 event.
4927 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4928 * @param TIMx Timer instance
4929 * @retval None
4930 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)4931 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4932 {
4933 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4934 }
4935
4936 /**
4937 * @brief Generate commutation event.
4938 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4939 * @param TIMx Timer instance
4940 * @retval None
4941 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)4942 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4943 {
4944 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4945 }
4946
4947 /**
4948 * @brief Generate trigger event.
4949 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4950 * @param TIMx Timer instance
4951 * @retval None
4952 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)4953 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4954 {
4955 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4956 }
4957
4958 /**
4959 * @brief Generate break event.
4960 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4961 * @param TIMx Timer instance
4962 * @retval None
4963 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)4964 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4965 {
4966 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4967 }
4968
4969 /**
4970 * @brief Generate break 2 event.
4971 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4972 * @param TIMx Timer instance
4973 * @retval None
4974 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)4975 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4976 {
4977 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4978 }
4979
4980 /**
4981 * @}
4982 */
4983
4984 #if defined(USE_FULL_LL_DRIVER)
4985 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4986 * @{
4987 */
4988
4989 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4990 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4991 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
4992 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4993 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4994 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4995 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4996 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4997 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4998 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4999 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
5000 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5001 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
5002 /**
5003 * @}
5004 */
5005 #endif /* USE_FULL_LL_DRIVER */
5006
5007 /**
5008 * @}
5009 */
5010
5011 /**
5012 * @}
5013 */
5014
5015 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 */
5016
5017 /**
5018 * @}
5019 */
5020
5021 #ifdef __cplusplus
5022 }
5023 #endif
5024
5025 #endif /* __STM32L5xx_LL_TIM_H */
5026
