1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_icache.h
4 * @author MCD Application Team
5 * @brief Header file of ICACHE LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion ------------------------------------*/
20 #ifndef STM32L5xx_LL_ICACHE_H
21 #define STM32L5xx_LL_ICACHE_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes -----------------------------------------------------------------*/
28 #include "stm32l5xx.h"
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined(ICACHE)
35
36 /** @defgroup ICACHE_LL ICACHE
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /* Exported types ------------------------------------------------------------*/
45 /** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
46 * @{
47 */
48
49 /**
50 * @brief LL ICACHE region configuration structure definition
51 */
52 typedef struct
53 {
54 uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
55
56 uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
57
58 uint32_t Size; /*!< Configures the region size.
59 This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
60
61 uint32_t TrafficRoute; /*!< Selects the traffic route.
62 This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
63
64 uint32_t OutputBurstType; /*!< Selects the output burst type.
65 This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
66 } LL_ICACHE_RegionTypeDef;
67
68 /**
69 * @}
70 */
71
72 /* Exported constants -------------------------------------------------------*/
73 /** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
74 * @{
75 */
76
77 /** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
78 * @{
79 */
80 #define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
81 #define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
82 /**
83 * @}
84 */
85
86 /** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
87 * @{
88 */
89 #define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
90 #define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
91 #define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
92 /**
93 * @}
94 */
95
96 /** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
97 * @brief Flags defines which can be used with LL_ICACHE_ReadReg function
98 * @{
99 */
100 #define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
101 #define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
102 #define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
103 /**
104 * @}
105 */
106
107 /** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
108 * @brief Flags defines which can be used with LL_ICACHE_WriteReg function
109 * @{
110 */
111 #define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
112 #define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
113 /**
114 * @}
115 */
116
117 /** @defgroup ICACHE_LL_EC_IT IT Defines
118 * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
119 * @{
120 */
121 #define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
122 #define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
123 /**
124 * @}
125 */
126
127 /** @defgroup ICACHE_LL_EC_Region Remapped Region number
128 * @{
129 */
130 #define LL_ICACHE_REGION_0 0U /*!< Region 0 */
131 #define LL_ICACHE_REGION_1 1U /*!< Region 1 */
132 #define LL_ICACHE_REGION_2 2U /*!< Region 2 */
133 #define LL_ICACHE_REGION_3 3U /*!< Region 3 */
134 /**
135 * @}
136 */
137
138 /** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
139 * @{
140 */
141 #define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
142 #define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
143 #define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
144 #define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
145 #define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
146 #define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
147 #define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
148 /**
149 * @}
150 */
151
152 /** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
153 * @{
154 */
155 #define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
156 #define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
157 /**
158 * @}
159 */
160
161 /** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
162 * @{
163 */
164 #define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
165 #define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
166 /**
167 * @}
168 */
169
170 /**
171 * @}
172 */
173
174 /* Exported macros ----------------------------------------------------------*/
175 /** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
176 * @{
177 */
178
179 /** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
180 * @{
181 */
182
183 /**
184 * @brief Write a value in ICACHE register
185 * @param __REG__ Register to be written
186 * @param __VALUE__ Value to be written in the register
187 * @retval None
188 */
189 #define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
190
191 /**
192 * @brief Read a value in ICACHE register
193 * @param __REG__ Register to be read
194 * @retval Register value
195 */
196 #define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
197 /**
198 * @}
199 */
200
201 /**
202 * @}
203 */
204
205 /* Exported functions --------------------------------------------------------*/
206 /** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
207 * @{
208 */
209
210 /** @defgroup ICACHE_LL_EF_Configuration Configuration
211 * @{
212 */
213
214 /**
215 * @brief Enable the ICACHE.
216 * @rmtoll CR EN LL_ICACHE_Enable
217 * @retval None
218 */
LL_ICACHE_Enable(void)219 __STATIC_INLINE void LL_ICACHE_Enable(void)
220 {
221 SET_BIT(ICACHE->CR, ICACHE_CR_EN);
222 }
223
224 /**
225 * @brief Disable the ICACHE.
226 * @rmtoll CR EN LL_ICACHE_Disable
227 * @retval None
228 */
LL_ICACHE_Disable(void)229 __STATIC_INLINE void LL_ICACHE_Disable(void)
230 {
231 CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
232 }
233
234 /**
235 * @brief Return if ICACHE is enabled or not.
236 * @rmtoll CR EN LL_ICACHE_IsEnabled
237 * @retval State of bit (1 or 0).
238 */
LL_ICACHE_IsEnabled(void)239 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
240 {
241 return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
242 }
243
244 /**
245 * @brief Select the ICACHE operating mode.
246 * @rmtoll CR WAYSEL LL_ICACHE_SetMode
247 * @param Mode This parameter can be one of the following values:
248 * @arg @ref LL_ICACHE_1WAY
249 * @arg @ref LL_ICACHE_2WAYS
250 * @retval None
251 */
LL_ICACHE_SetMode(uint32_t Mode)252 __STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
253 {
254 MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
255 }
256
257 /**
258 * @brief Get the selected ICACHE operating mode.
259 * @rmtoll CR WAYSEL LL_ICACHE_GetMode
260 * @retval Returned value can be one of the following values:
261 * @arg @ref LL_ICACHE_1WAY
262 * @arg @ref LL_ICACHE_2WAYS
263 */
LL_ICACHE_GetMode(void)264 __STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
265 {
266 return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
267 }
268
269 /**
270 * @brief Invalidate the ICACHE.
271 * @note Until the BSYEND flag is set, the cache is bypassed.
272 * @rmtoll CR CACHEINV LL_ICACHE_Invalidate
273 * @retval None
274 */
LL_ICACHE_Invalidate(void)275 __STATIC_INLINE void LL_ICACHE_Invalidate(void)
276 {
277 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
278 }
279
280 /**
281 * @}
282 */
283
284 /** @defgroup ICACHE_LL_EF_Monitors Monitors
285 * @{
286 */
287
288 /**
289 * @brief Enable the hit/miss monitor(s).
290 * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
291 * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
292 * @param Monitors This parameter can be one or a combination of the following values:
293 * @arg @ref LL_ICACHE_MONITOR_HIT
294 * @arg @ref LL_ICACHE_MONITOR_MISS
295 * @arg @ref LL_ICACHE_MONITOR_ALL
296 * @retval None
297 */
LL_ICACHE_EnableMonitors(uint32_t Monitors)298 __STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
299 {
300 SET_BIT(ICACHE->CR, Monitors);
301 }
302
303 /**
304 * @brief Disable the hit/miss monitor(s).
305 * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
306 * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
307 * @param Monitors This parameter can be one or a combination of the following values:
308 * @arg @ref LL_ICACHE_MONITOR_HIT
309 * @arg @ref LL_ICACHE_MONITOR_MISS
310 * @arg @ref LL_ICACHE_MONITOR_ALL
311 * @retval None
312 */
LL_ICACHE_DisableMonitors(uint32_t Monitors)313 __STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
314 {
315 CLEAR_BIT(ICACHE->CR, Monitors);
316 }
317
318 /**
319 * @brief Check if the monitor(s) is(are) enabled or disabled.
320 * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
321 * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
322 * @param Monitors This parameter can be one or a combination of the following values:
323 * @arg @ref LL_ICACHE_MONITOR_HIT
324 * @arg @ref LL_ICACHE_MONITOR_MISS
325 * @arg @ref LL_ICACHE_MONITOR_ALL
326 * @retval State of parameter value (1 or 0).
327 */
LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)328 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
329 {
330 return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
331 }
332
333 /**
334 * @brief Reset the hit/miss monitor(s).
335 * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
336 * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
337 * @param Monitors This parameter can be one or a combination of the following values:
338 * @arg @ref LL_ICACHE_MONITOR_HIT
339 * @arg @ref LL_ICACHE_MONITOR_MISS
340 * @arg @ref LL_ICACHE_MONITOR_ALL
341 * @retval None
342 */
LL_ICACHE_ResetMonitors(uint32_t Monitors)343 __STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
344 {
345 /* Reset */
346 SET_BIT(ICACHE->CR, (Monitors << 2U));
347 /* Release reset */
348 CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
349 }
350
351 /**
352 * @brief Get the Hit monitor.
353 * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
354 * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
355 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
356 */
LL_ICACHE_GetHitMonitor(void)357 __STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
358 {
359 return (ICACHE->HMONR);
360 }
361
362 /**
363 * @brief Get the Miss monitor.
364 * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
365 * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
366 * @retval Value between Min_Data=0 and Max_Data=0xFFFF
367 */
LL_ICACHE_GetMissMonitor(void)368 __STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
369 {
370 return (ICACHE->MMONR);
371 }
372
373 /**
374 * @}
375 */
376
377 /** @defgroup ICACHE_LL_EF_IT_Management IT_Management
378 * @{
379 */
380
381 /**
382 * @brief Enable BSYEND interrupt.
383 * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
384 * @retval None
385 */
LL_ICACHE_EnableIT_BSYEND(void)386 __STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
387 {
388 SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
389 }
390
391 /**
392 * @brief Disable BSYEND interrupt.
393 * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
394 * @retval None
395 */
LL_ICACHE_DisableIT_BSYEND(void)396 __STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
397 {
398 CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
399 }
400
401 /**
402 * @brief Check if the BSYEND Interrupt is enabled or disabled.
403 * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
404 * @retval State of bit (1 or 0).
405 */
LL_ICACHE_IsEnabledIT_BSYEND(void)406 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
407 {
408 return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
409 }
410
411 /**
412 * @brief Enable ERR interrupt.
413 * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
414 * @retval None
415 */
LL_ICACHE_EnableIT_ERR(void)416 __STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
417 {
418 SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
419 }
420
421 /**
422 * @brief Disable ERR interrupt.
423 * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
424 * @retval None
425 */
LL_ICACHE_DisableIT_ERR(void)426 __STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
427 {
428 CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
429 }
430
431 /**
432 * @brief Check if the ERR Interrupt is enabled or disabled.
433 * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
434 * @retval State of bit (1 or 0).
435 */
LL_ICACHE_IsEnabledIT_ERR(void)436 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
437 {
438 return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
439 }
440
441 /**
442 * @}
443 */
444
445 /** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
446 * @{
447 */
448
449 /**
450 * @brief Indicate the status of an ongoing operation flag.
451 * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
452 * @retval State of bit (1 or 0).
453 */
LL_ICACHE_IsActiveFlag_BUSY(void)454 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
455 {
456 return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
457 }
458
459 /**
460 * @brief Indicate the status of an operation end flag.
461 * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
462 * @retval State of bit (1 or 0).
463 */
LL_ICACHE_IsActiveFlag_BSYEND(void)464 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
465 {
466 return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
467 }
468
469 /**
470 * @brief Indicate the status of an error flag.
471 * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
472 * @retval State of bit (1 or 0).
473 */
LL_ICACHE_IsActiveFlag_ERR(void)474 __STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
475 {
476 return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
477 }
478
479 /**
480 * @brief Clear busy end of operation flag.
481 * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
482 * @retval None
483 */
LL_ICACHE_ClearFlag_BSYEND(void)484 __STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
485 {
486 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
487 }
488
489 /**
490 * @brief Clear error flag.
491 * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
492 * @retval None
493 */
LL_ICACHE_ClearFlag_ERR(void)494 __STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
495 {
496 WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
497 }
498
499 /**
500 * @}
501 */
502
503 /** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
504 * @{
505 */
506
507 /**
508 * @brief Enable the remapped memory region.
509 * @note The region must have been already configured.
510 * @rmtoll CRRx REN LL_ICACHE_EnableRegion
511 * @param Region This parameter can be one of the following values:
512 * @arg @ref LL_ICACHE_REGION_0
513 * @arg @ref LL_ICACHE_REGION_1
514 * @arg @ref LL_ICACHE_REGION_2
515 * @arg @ref LL_ICACHE_REGION_3
516 * @retval None
517 */
LL_ICACHE_EnableRegion(uint32_t Region)518 __STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
519 {
520 SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
521 ICACHE_CRRx_REN);
522 }
523
524 /**
525 * @brief Disable the remapped memory region.
526 * @rmtoll CRRx REN LL_ICACHE_DisableRegion
527 * @param Region This parameter can be one of the following values:
528 * @arg @ref LL_ICACHE_REGION_0
529 * @arg @ref LL_ICACHE_REGION_1
530 * @arg @ref LL_ICACHE_REGION_2
531 * @arg @ref LL_ICACHE_REGION_3
532 * @retval None
533 */
LL_ICACHE_DisableRegion(uint32_t Region)534 __STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
535 {
536 CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
537 ICACHE_CRRx_REN);
538 }
539
540 /**
541 * @brief Return if remapped memory region is enabled or not.
542 * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
543 * @param Region This parameter can be one of the following values:
544 * @arg @ref LL_ICACHE_REGION_0
545 * @arg @ref LL_ICACHE_REGION_1
546 * @arg @ref LL_ICACHE_REGION_2
547 * @arg @ref LL_ICACHE_REGION_3
548 * @retval State of bit (1 or 0).
549 */
LL_ICACHE_IsEnabledRegion(uint32_t Region)550 __STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
551 {
552 return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
553 ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
554 }
555
556 /**
557 * @brief Select the memory remapped region base address.
558 * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
559 * @param Region This parameter can be one of the following values:
560 * @arg @ref LL_ICACHE_REGION_0
561 * @arg @ref LL_ICACHE_REGION_1
562 * @arg @ref LL_ICACHE_REGION_2
563 * @arg @ref LL_ICACHE_REGION_3
564 * @param Address Alias address in the Code region
565 * @retval None
566 */
LL_ICACHE_SetRegionBaseAddress(uint32_t Region,uint32_t Address)567 __STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
568 {
569 MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
570 ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR));
571 }
572
573 /**
574 * @brief Get the memory remapped region base address.
575 * @note The base address is the alias in the Code region.
576 * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
577 * @param Region This parameter can be one of the following values:
578 * @arg @ref LL_ICACHE_REGION_0
579 * @arg @ref LL_ICACHE_REGION_1
580 * @arg @ref LL_ICACHE_REGION_2
581 * @arg @ref LL_ICACHE_REGION_3
582 * @retval Address Alias address in the Code region
583 */
LL_ICACHE_GetRegionBaseAddress(uint32_t Region)584 __STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
585 {
586 return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
587 ICACHE_CRRx_BASEADDR));
588 }
589
590 /**
591 * @brief Select the memory remapped region remap address.
592 * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
593 * @param Region This parameter can be one of the following values:
594 * @arg @ref LL_ICACHE_REGION_0
595 * @arg @ref LL_ICACHE_REGION_1
596 * @arg @ref LL_ICACHE_REGION_2
597 * @arg @ref LL_ICACHE_REGION_3
598 * @param Address External memory address
599 * @retval None
600 */
LL_ICACHE_SetRegionRemapAddress(uint32_t Region,uint32_t Address)601 __STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
602 {
603 MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
604 ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
605 }
606
607 /**
608 * @brief Get the memory remapped region base address.
609 * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
610 * @param Region This parameter can be one of the following values:
611 * @arg @ref LL_ICACHE_REGION_0
612 * @arg @ref LL_ICACHE_REGION_1
613 * @arg @ref LL_ICACHE_REGION_2
614 * @arg @ref LL_ICACHE_REGION_3
615 * @retval Address External memory address
616 */
LL_ICACHE_GetRegionRemapAddress(uint32_t Region)617 __STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
618 {
619 return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
620 ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
621 }
622
623 /**
624 * @brief Select the memory remapped region size.
625 * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
626 * @param Region This parameter can be one of the following values:
627 * @arg @ref LL_ICACHE_REGION_0
628 * @arg @ref LL_ICACHE_REGION_1
629 * @arg @ref LL_ICACHE_REGION_2
630 * @arg @ref LL_ICACHE_REGION_3
631 * @param Size This parameter can be one of the following values:
632 * @arg @ref LL_ICACHE_REGIONSIZE_2MB
633 * @arg @ref LL_ICACHE_REGIONSIZE_4MB
634 * @arg @ref LL_ICACHE_REGIONSIZE_8MB
635 * @arg @ref LL_ICACHE_REGIONSIZE_16MB
636 * @arg @ref LL_ICACHE_REGIONSIZE_32MB
637 * @arg @ref LL_ICACHE_REGIONSIZE_64MB
638 * @arg @ref LL_ICACHE_REGIONSIZE_128MB
639 * @retval None
640 */
LL_ICACHE_SetRegionSize(uint32_t Region,uint32_t Size)641 __STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
642 {
643 MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
644 ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
645 }
646
647 /**
648 * @brief Get the selected the memory remapped region size.
649 * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
650 * @param Region This parameter can be one of the following values:
651 * @arg @ref LL_ICACHE_REGION_0
652 * @arg @ref LL_ICACHE_REGION_1
653 * @arg @ref LL_ICACHE_REGION_2
654 * @arg @ref LL_ICACHE_REGION_3
655 * @retval Returned value can be one of the following values:
656 * @arg @ref LL_ICACHE_REGIONSIZE_2MB
657 * @arg @ref LL_ICACHE_REGIONSIZE_4MB
658 * @arg @ref LL_ICACHE_REGIONSIZE_8MB
659 * @arg @ref LL_ICACHE_REGIONSIZE_16MB
660 * @arg @ref LL_ICACHE_REGIONSIZE_32MB
661 * @arg @ref LL_ICACHE_REGIONSIZE_64MB
662 * @arg @ref LL_ICACHE_REGIONSIZE_128MB
663 */
LL_ICACHE_GetRegionSize(uint32_t Region)664 __STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
665 {
666 return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
667 ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
668 }
669
670 /**
671 * @brief Select the memory remapped region output burst type.
672 * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
673 * @param Region This parameter can be one of the following values:
674 * @arg @ref LL_ICACHE_REGION_0
675 * @arg @ref LL_ICACHE_REGION_1
676 * @arg @ref LL_ICACHE_REGION_2
677 * @arg @ref LL_ICACHE_REGION_3
678 * @param Type This parameter can be one of the following values:
679 * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
680 * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
681 * @retval None
682 */
LL_ICACHE_SetRegionOutputBurstType(uint32_t Region,uint32_t Type)683 __STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
684 {
685 MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
686 ICACHE_CRRx_HBURST, Type);
687 }
688
689 /**
690 * @brief Get the selected the memory remapped region output burst type.
691 * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
692 * @param Region This parameter can be one of the following values:
693 * @arg @ref LL_ICACHE_REGION_0
694 * @arg @ref LL_ICACHE_REGION_1
695 * @arg @ref LL_ICACHE_REGION_2
696 * @arg @ref LL_ICACHE_REGION_3
697 * @retval Returned value can be one of the following values:
698 * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
699 * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
700 */
LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)701 __STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
702 {
703 return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
704 ICACHE_CRRx_HBURST));
705 }
706
707 /**
708 * @brief Select the memory remapped region cache master port.
709 * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
710 * @param Region This parameter can be one of the following values:
711 * @arg @ref LL_ICACHE_REGION_0
712 * @arg @ref LL_ICACHE_REGION_1
713 * @arg @ref LL_ICACHE_REGION_2
714 * @arg @ref LL_ICACHE_REGION_3
715 * @param Port This parameter can be one of the following values:
716 * @arg @ref LL_ICACHE_MASTER1_PORT
717 * @arg @ref LL_ICACHE_MASTER2_PORT
718 * @retval None
719 */
LL_ICACHE_SetRegionMasterPort(uint32_t Region,uint32_t Port)720 __STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
721 {
722 MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
723 ICACHE_CRRx_MSTSEL, Port);
724 }
725
726 /**
727 * @brief Get the selected the memory remapped region cache master port.
728 * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
729 * @param Region This parameter can be one of the following values:
730 * @arg @ref LL_ICACHE_REGION_0
731 * @arg @ref LL_ICACHE_REGION_1
732 * @arg @ref LL_ICACHE_REGION_2
733 * @arg @ref LL_ICACHE_REGION_3
734 * @retval Returned value can be one of the following values:
735 * @arg @ref LL_ICACHE_MASTER1_PORT
736 * @arg @ref LL_ICACHE_MASTER2_PORT
737 */
LL_ICACHE_GetRegionMasterPort(uint32_t Region)738 __STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
739 {
740 return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
741 ICACHE_CRRx_MSTSEL));
742 }
743
744 /**
745 * @}
746 */
747
748 #if defined(USE_FULL_LL_DRIVER)
749 /** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
750 * @{
751 */
752
753 void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
754
755 /**
756 * @}
757 */
758 #endif /* USE_FULL_LL_DRIVER */
759
760 /**
761 * @}
762 */
763
764 /**
765 * @}
766 */
767
768 #endif /* ICACHE */
769
770 /**
771 * @}
772 */
773
774 #ifdef __cplusplus
775 }
776 #endif
777
778 #endif /* STM32L5xx_LL_ICACHE_H */
779
