1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_sram.c
4 * @author MCD Application Team
5 * @brief SRAM HAL module driver.
6 * This file provides a generic firmware to drive SRAM memories
7 * mounted as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2019 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SRAM memories. It uses the FMC layer functions to interface
27 with SRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SRAM/PSRAM memories:
30
31 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
32 SRAM_HandleTypeDef hsram; and:
33
34 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SRAM device
39
40 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
41 base register instance for NOR or SRAM extended mode
42
43 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
44 mode timings; for example:
45 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
46 and fill its fields with the allowed values of the structure member.
47
48 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
49 performs the following sequence:
50
51 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
52 (##) Control register configuration using the FMC NORSRAM interface function
53 FMC_NORSRAM_Init()
54 (##) Timing register configuration using the FMC NORSRAM interface function
55 FMC_NORSRAM_Timing_Init()
56 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
57 FMC_NORSRAM_Extended_Timing_Init()
58 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
59
60 (#) At this stage you can perform read/write accesses from/to the memory connected
61 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
62 following APIs:
63 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
64 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
65
66 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
67 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
68
69 (#) You can continuously monitor the SRAM device HAL state by calling the function
70 HAL_SRAM_GetState()
71
72 *** Callback registration ***
73 =============================================
74 [..]
75 The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
76 allows the user to configure dynamically the driver callbacks.
77
78 Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
79 it allows to register following callbacks:
80 (+) MspInitCallback : SRAM MspInit.
81 (+) MspDeInitCallback : SRAM MspDeInit.
82 This function takes as parameters the HAL peripheral handle, the Callback ID
83 and a pointer to the user callback function.
84
85 Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
86 weak (surcharged) function. It allows to reset following callbacks:
87 (+) MspInitCallback : SRAM MspInit.
88 (+) MspDeInitCallback : SRAM MspDeInit.
89 This function) takes as parameters the HAL peripheral handle and the Callback ID.
90
91 By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
92 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
93 Exception done for MspInit and MspDeInit callbacks that are respectively
94 reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
95 and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
96 If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
97 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
98
99 Callbacks can be registered/unregistered in READY state only.
100 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
101 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
102 during the Init/DeInit.
103 In that case first register the MspInit/MspDeInit user callbacks
104 using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
105 or HAL_SRAM_Init function.
106
107 When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
108 not defined, the callback registering feature is not available
109 and weak (surcharged) callbacks are used.
110
111 @endverbatim
112 ******************************************************************************
113 */
114
115 /* Includes ------------------------------------------------------------------*/
116 #include "stm32l5xx_hal.h"
117
118
119 /** @addtogroup STM32L5xx_HAL_Driver
120 * @{
121 */
122
123 #ifdef HAL_SRAM_MODULE_ENABLED
124
125 /** @defgroup SRAM SRAM
126 * @brief SRAM driver modules
127 * @{
128 */
129
130 /* Private typedef -----------------------------------------------------------*/
131 /* Private define ------------------------------------------------------------*/
132 /* Private macro -------------------------------------------------------------*/
133 /* Private variables ---------------------------------------------------------*/
134 /* Private function prototypes -----------------------------------------------*/
135 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
136 * @{
137 */
138 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
139 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
140 static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146
147 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
148 * @{
149 */
150
151 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
152 * @brief Initialization and Configuration functions.
153 *
154 @verbatim
155 ==============================================================================
156 ##### SRAM Initialization and de_initialization functions #####
157 ==============================================================================
158 [..] This section provides functions allowing to initialize/de-initialize
159 the SRAM memory
160
161 @endverbatim
162 * @{
163 */
164
165 /**
166 * @brief Performs the SRAM device initialization sequence
167 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
168 * the configuration information for SRAM module.
169 * @param Timing Pointer to SRAM control timing structure
170 * @param ExtTiming Pointer to SRAM extended mode timing structure
171 * @retval HAL status
172 */
HAL_SRAM_Init(SRAM_HandleTypeDef * hsram,FMC_NORSRAM_TimingTypeDef * Timing,FMC_NORSRAM_TimingTypeDef * ExtTiming)173 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
174 FMC_NORSRAM_TimingTypeDef *ExtTiming)
175 {
176 /* Check the SRAM handle parameter */
177 if (hsram == NULL)
178 {
179 return HAL_ERROR;
180 }
181
182 if (hsram->State == HAL_SRAM_STATE_RESET)
183 {
184 /* Allocate lock resource and initialize it */
185 hsram->Lock = HAL_UNLOCKED;
186
187 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
188 if (hsram->MspInitCallback == NULL)
189 {
190 hsram->MspInitCallback = HAL_SRAM_MspInit;
191 }
192 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
193 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
194
195 /* Init the low level hardware */
196 hsram->MspInitCallback(hsram);
197 #else
198 /* Initialize the low level hardware (MSP) */
199 HAL_SRAM_MspInit(hsram);
200 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
201 }
202
203 /* Initialize SRAM control Interface */
204 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
205
206 /* Initialize SRAM timing Interface */
207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
208
209 /* Initialize SRAM extended mode timing Interface */
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
211 hsram->Init.ExtendedMode);
212
213 /* Enable the NORSRAM device */
214 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
215
216 /* Initialize the SRAM controller state */
217 hsram->State = HAL_SRAM_STATE_READY;
218
219 return HAL_OK;
220 }
221
222 /**
223 * @brief Performs the SRAM device De-initialization sequence.
224 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
225 * the configuration information for SRAM module.
226 * @retval HAL status
227 */
HAL_SRAM_DeInit(SRAM_HandleTypeDef * hsram)228 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
229 {
230 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
231 if (hsram->MspDeInitCallback == NULL)
232 {
233 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
234 }
235
236 /* DeInit the low level hardware */
237 hsram->MspDeInitCallback(hsram);
238 #else
239 /* De-Initialize the low level hardware (MSP) */
240 HAL_SRAM_MspDeInit(hsram);
241 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
242
243 /* Configure the SRAM registers with their reset values */
244 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
245
246 /* Reset the SRAM controller state */
247 hsram->State = HAL_SRAM_STATE_RESET;
248
249 /* Release Lock */
250 __HAL_UNLOCK(hsram);
251
252 return HAL_OK;
253 }
254
255 /**
256 * @brief SRAM MSP Init.
257 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
258 * the configuration information for SRAM module.
259 * @retval None
260 */
HAL_SRAM_MspInit(SRAM_HandleTypeDef * hsram)261 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
262 {
263 /* Prevent unused argument(s) compilation warning */
264 UNUSED(hsram);
265
266 /* NOTE : This function Should not be modified, when the callback is needed,
267 the HAL_SRAM_MspInit could be implemented in the user file
268 */
269 }
270
271 /**
272 * @brief SRAM MSP DeInit.
273 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
274 * the configuration information for SRAM module.
275 * @retval None
276 */
HAL_SRAM_MspDeInit(SRAM_HandleTypeDef * hsram)277 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
278 {
279 /* Prevent unused argument(s) compilation warning */
280 UNUSED(hsram);
281
282 /* NOTE : This function Should not be modified, when the callback is needed,
283 the HAL_SRAM_MspDeInit could be implemented in the user file
284 */
285 }
286
287 /**
288 * @brief DMA transfer complete callback.
289 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
290 * the configuration information for SRAM module.
291 * @retval None
292 */
HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef * hdma)293 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
294 {
295 /* Prevent unused argument(s) compilation warning */
296 UNUSED(hdma);
297
298 /* NOTE : This function Should not be modified, when the callback is needed,
299 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
300 */
301 }
302
303 /**
304 * @brief DMA transfer complete error callback.
305 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
306 * the configuration information for SRAM module.
307 * @retval None
308 */
HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef * hdma)309 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
310 {
311 /* Prevent unused argument(s) compilation warning */
312 UNUSED(hdma);
313
314 /* NOTE : This function Should not be modified, when the callback is needed,
315 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
316 */
317 }
318
319 /**
320 * @}
321 */
322
323 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
324 * @brief Input Output and memory control functions
325 *
326 @verbatim
327 ==============================================================================
328 ##### SRAM Input and Output functions #####
329 ==============================================================================
330 [..]
331 This section provides functions allowing to use and control the SRAM memory
332
333 @endverbatim
334 * @{
335 */
336
337 /**
338 * @brief Reads 8-bit buffer from SRAM memory.
339 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
340 * the configuration information for SRAM module.
341 * @param pAddress Pointer to read start address
342 * @param pDstBuffer Pointer to destination buffer
343 * @param BufferSize Size of the buffer to read from memory
344 * @retval HAL status
345 */
HAL_SRAM_Read_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)346 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
347 uint32_t BufferSize)
348 {
349 uint32_t size;
350 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
351 uint8_t *pdestbuff = pDstBuffer;
352 HAL_SRAM_StateTypeDef state = hsram->State;
353
354 /* Check the SRAM controller state */
355 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
356 {
357 /* Process Locked */
358 __HAL_LOCK(hsram);
359
360 /* Update the SRAM controller state */
361 hsram->State = HAL_SRAM_STATE_BUSY;
362
363 /* Read data from memory */
364 for (size = BufferSize; size != 0U; size--)
365 {
366 *pdestbuff = *psramaddress;
367 pdestbuff++;
368 psramaddress++;
369 }
370
371 /* Update the SRAM controller state */
372 hsram->State = state;
373
374 /* Process unlocked */
375 __HAL_UNLOCK(hsram);
376 }
377 else
378 {
379 return HAL_ERROR;
380 }
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Writes 8-bit buffer to SRAM memory.
387 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
388 * the configuration information for SRAM module.
389 * @param pAddress Pointer to write start address
390 * @param pSrcBuffer Pointer to source buffer to write
391 * @param BufferSize Size of the buffer to write to memory
392 * @retval HAL status
393 */
HAL_SRAM_Write_8b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)394 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
395 uint32_t BufferSize)
396 {
397 uint32_t size;
398 __IO uint8_t *psramaddress = (uint8_t *)pAddress;
399 uint8_t *psrcbuff = pSrcBuffer;
400
401 /* Check the SRAM controller state */
402 if (hsram->State == HAL_SRAM_STATE_READY)
403 {
404 /* Process Locked */
405 __HAL_LOCK(hsram);
406
407 /* Update the SRAM controller state */
408 hsram->State = HAL_SRAM_STATE_BUSY;
409
410 /* Write data to memory */
411 for (size = BufferSize; size != 0U; size--)
412 {
413 *psramaddress = *psrcbuff;
414 psrcbuff++;
415 psramaddress++;
416 }
417
418 /* Update the SRAM controller state */
419 hsram->State = HAL_SRAM_STATE_READY;
420
421 /* Process unlocked */
422 __HAL_UNLOCK(hsram);
423 }
424 else
425 {
426 return HAL_ERROR;
427 }
428
429 return HAL_OK;
430 }
431
432 /**
433 * @brief Reads 16-bit buffer from SRAM memory.
434 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
435 * the configuration information for SRAM module.
436 * @param pAddress Pointer to read start address
437 * @param pDstBuffer Pointer to destination buffer
438 * @param BufferSize Size of the buffer to read from memory
439 * @retval HAL status
440 */
HAL_SRAM_Read_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)441 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
442 uint32_t BufferSize)
443 {
444 uint32_t size;
445 __IO uint32_t *psramaddress = pAddress;
446 uint16_t *pdestbuff = pDstBuffer;
447 uint8_t limit;
448 HAL_SRAM_StateTypeDef state = hsram->State;
449
450 /* Check the SRAM controller state */
451 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
452 {
453 /* Process Locked */
454 __HAL_LOCK(hsram);
455
456 /* Update the SRAM controller state */
457 hsram->State = HAL_SRAM_STATE_BUSY;
458
459 /* Check if the size is a 32-bits multiple */
460 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
461
462 /* Read data from memory */
463 for (size = BufferSize; size != limit; size -= 2U)
464 {
465 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
466 pdestbuff++;
467 *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U);
468 pdestbuff++;
469 psramaddress++;
470 }
471
472 /* Read last 16-bits if size is not 32-bits multiple */
473 if (limit != 0U)
474 {
475 *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
476 }
477
478 /* Update the SRAM controller state */
479 hsram->State = state;
480
481 /* Process unlocked */
482 __HAL_UNLOCK(hsram);
483 }
484 else
485 {
486 return HAL_ERROR;
487 }
488
489 return HAL_OK;
490 }
491
492 /**
493 * @brief Writes 16-bit buffer to SRAM memory.
494 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
495 * the configuration information for SRAM module.
496 * @param pAddress Pointer to write start address
497 * @param pSrcBuffer Pointer to source buffer to write
498 * @param BufferSize Size of the buffer to write to memory
499 * @retval HAL status
500 */
HAL_SRAM_Write_16b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)501 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
502 uint32_t BufferSize)
503 {
504 uint32_t size;
505 __IO uint32_t *psramaddress = pAddress;
506 uint16_t *psrcbuff = pSrcBuffer;
507 uint8_t limit;
508
509 /* Check the SRAM controller state */
510 if (hsram->State == HAL_SRAM_STATE_READY)
511 {
512 /* Process Locked */
513 __HAL_LOCK(hsram);
514
515 /* Update the SRAM controller state */
516 hsram->State = HAL_SRAM_STATE_BUSY;
517
518 /* Check if the size is a 32-bits multiple */
519 limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
520
521 /* Write data to memory */
522 for (size = BufferSize; size != limit; size -= 2U)
523 {
524 *psramaddress = (uint32_t)(*psrcbuff);
525 psrcbuff++;
526 *psramaddress |= ((uint32_t)(*psrcbuff) << 16U);
527 psrcbuff++;
528 psramaddress++;
529 }
530
531 /* Write last 16-bits if size is not 32-bits multiple */
532 if (limit != 0U)
533 {
534 *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U);
535 }
536
537 /* Update the SRAM controller state */
538 hsram->State = HAL_SRAM_STATE_READY;
539
540 /* Process unlocked */
541 __HAL_UNLOCK(hsram);
542 }
543 else
544 {
545 return HAL_ERROR;
546 }
547
548 return HAL_OK;
549 }
550
551 /**
552 * @brief Reads 32-bit buffer from SRAM memory.
553 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
554 * the configuration information for SRAM module.
555 * @param pAddress Pointer to read start address
556 * @param pDstBuffer Pointer to destination buffer
557 * @param BufferSize Size of the buffer to read from memory
558 * @retval HAL status
559 */
HAL_SRAM_Read_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)560 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
561 uint32_t BufferSize)
562 {
563 uint32_t size;
564 __IO uint32_t *psramaddress = pAddress;
565 uint32_t *pdestbuff = pDstBuffer;
566 HAL_SRAM_StateTypeDef state = hsram->State;
567
568 /* Check the SRAM controller state */
569 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
570 {
571 /* Process Locked */
572 __HAL_LOCK(hsram);
573
574 /* Update the SRAM controller state */
575 hsram->State = HAL_SRAM_STATE_BUSY;
576
577 /* Read data from memory */
578 for (size = BufferSize; size != 0U; size--)
579 {
580 *pdestbuff = *psramaddress;
581 pdestbuff++;
582 psramaddress++;
583 }
584
585 /* Update the SRAM controller state */
586 hsram->State = state;
587
588 /* Process unlocked */
589 __HAL_UNLOCK(hsram);
590 }
591 else
592 {
593 return HAL_ERROR;
594 }
595
596 return HAL_OK;
597 }
598
599 /**
600 * @brief Writes 32-bit buffer to SRAM memory.
601 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
602 * the configuration information for SRAM module.
603 * @param pAddress Pointer to write start address
604 * @param pSrcBuffer Pointer to source buffer to write
605 * @param BufferSize Size of the buffer to write to memory
606 * @retval HAL status
607 */
HAL_SRAM_Write_32b(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)608 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
609 uint32_t BufferSize)
610 {
611 uint32_t size;
612 __IO uint32_t *psramaddress = pAddress;
613 uint32_t *psrcbuff = pSrcBuffer;
614
615 /* Check the SRAM controller state */
616 if (hsram->State == HAL_SRAM_STATE_READY)
617 {
618 /* Process Locked */
619 __HAL_LOCK(hsram);
620
621 /* Update the SRAM controller state */
622 hsram->State = HAL_SRAM_STATE_BUSY;
623
624 /* Write data to memory */
625 for (size = BufferSize; size != 0U; size--)
626 {
627 *psramaddress = *psrcbuff;
628 psrcbuff++;
629 psramaddress++;
630 }
631
632 /* Update the SRAM controller state */
633 hsram->State = HAL_SRAM_STATE_READY;
634
635 /* Process unlocked */
636 __HAL_UNLOCK(hsram);
637 }
638 else
639 {
640 return HAL_ERROR;
641 }
642
643 return HAL_OK;
644 }
645
646 /**
647 * @brief Reads a Words data from the SRAM memory using DMA transfer.
648 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
649 * the configuration information for SRAM module.
650 * @param pAddress Pointer to read start address
651 * @param pDstBuffer Pointer to destination buffer
652 * @param BufferSize Size of the buffer to read from memory
653 * @retval HAL status
654 */
HAL_SRAM_Read_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)655 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
656 uint32_t BufferSize)
657 {
658 HAL_StatusTypeDef status;
659 HAL_SRAM_StateTypeDef state = hsram->State;
660
661 /* Check the SRAM controller state */
662 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
663 {
664 /* Process Locked */
665 __HAL_LOCK(hsram);
666
667 /* Update the SRAM controller state */
668 hsram->State = HAL_SRAM_STATE_BUSY;
669
670 /* Configure DMA user callbacks */
671 if (state == HAL_SRAM_STATE_READY)
672 {
673 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
674 }
675 else
676 {
677 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt;
678 }
679 hsram->hdma->XferErrorCallback = SRAM_DMAError;
680
681 /* Enable the DMA Stream */
682 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
683
684 /* Process unlocked */
685 __HAL_UNLOCK(hsram);
686 }
687 else
688 {
689 status = HAL_ERROR;
690 }
691
692 return status;
693 }
694
695 /**
696 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
697 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
698 * the configuration information for SRAM module.
699 * @param pAddress Pointer to write start address
700 * @param pSrcBuffer Pointer to source buffer to write
701 * @param BufferSize Size of the buffer to write to memory
702 * @retval HAL status
703 */
HAL_SRAM_Write_DMA(SRAM_HandleTypeDef * hsram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)704 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
705 uint32_t BufferSize)
706 {
707 HAL_StatusTypeDef status;
708
709 /* Check the SRAM controller state */
710 if (hsram->State == HAL_SRAM_STATE_READY)
711 {
712 /* Process Locked */
713 __HAL_LOCK(hsram);
714
715 /* Update the SRAM controller state */
716 hsram->State = HAL_SRAM_STATE_BUSY;
717
718 /* Configure DMA user callbacks */
719 hsram->hdma->XferCpltCallback = SRAM_DMACplt;
720 hsram->hdma->XferErrorCallback = SRAM_DMAError;
721
722 /* Enable the DMA Stream */
723 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
724
725 /* Process unlocked */
726 __HAL_UNLOCK(hsram);
727 }
728 else
729 {
730 status = HAL_ERROR;
731 }
732
733 return status;
734 }
735
736 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
737 /**
738 * @brief Register a User SRAM Callback
739 * To be used instead of the weak (surcharged) predefined callback
740 * @param hsram : SRAM handle
741 * @param CallbackId : ID of the callback to be registered
742 * This parameter can be one of the following values:
743 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
744 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
745 * @param pCallback : pointer to the Callback function
746 * @retval status
747 */
HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_CallbackTypeDef pCallback)748 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
749 pSRAM_CallbackTypeDef pCallback)
750 {
751 HAL_StatusTypeDef status = HAL_OK;
752 HAL_SRAM_StateTypeDef state;
753
754 if (pCallback == NULL)
755 {
756 return HAL_ERROR;
757 }
758
759 /* Process locked */
760 __HAL_LOCK(hsram);
761
762 state = hsram->State;
763 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
764 {
765 switch (CallbackId)
766 {
767 case HAL_SRAM_MSP_INIT_CB_ID :
768 hsram->MspInitCallback = pCallback;
769 break;
770 case HAL_SRAM_MSP_DEINIT_CB_ID :
771 hsram->MspDeInitCallback = pCallback;
772 break;
773 default :
774 /* update return status */
775 status = HAL_ERROR;
776 break;
777 }
778 }
779 else
780 {
781 /* update return status */
782 status = HAL_ERROR;
783 }
784
785 /* Release Lock */
786 __HAL_UNLOCK(hsram);
787 return status;
788 }
789
790 /**
791 * @brief Unregister a User SRAM Callback
792 * SRAM Callback is redirected to the weak (surcharged) predefined callback
793 * @param hsram : SRAM handle
794 * @param CallbackId : ID of the callback to be unregistered
795 * This parameter can be one of the following values:
796 * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID
797 * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID
798 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
799 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
800 * @retval status
801 */
HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId)802 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
803 {
804 HAL_StatusTypeDef status = HAL_OK;
805 HAL_SRAM_StateTypeDef state;
806
807 /* Process locked */
808 __HAL_LOCK(hsram);
809
810 state = hsram->State;
811 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
812 {
813 switch (CallbackId)
814 {
815 case HAL_SRAM_MSP_INIT_CB_ID :
816 hsram->MspInitCallback = HAL_SRAM_MspInit;
817 break;
818 case HAL_SRAM_MSP_DEINIT_CB_ID :
819 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
820 break;
821 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
822 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
823 break;
824 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
825 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
826 break;
827 default :
828 /* update return status */
829 status = HAL_ERROR;
830 break;
831 }
832 }
833 else if (state == HAL_SRAM_STATE_RESET)
834 {
835 switch (CallbackId)
836 {
837 case HAL_SRAM_MSP_INIT_CB_ID :
838 hsram->MspInitCallback = HAL_SRAM_MspInit;
839 break;
840 case HAL_SRAM_MSP_DEINIT_CB_ID :
841 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
842 break;
843 default :
844 /* update return status */
845 status = HAL_ERROR;
846 break;
847 }
848 }
849 else
850 {
851 /* update return status */
852 status = HAL_ERROR;
853 }
854
855 /* Release Lock */
856 __HAL_UNLOCK(hsram);
857 return status;
858 }
859
860 /**
861 * @brief Register a User SRAM Callback for DMA transfers
862 * To be used instead of the weak (surcharged) predefined callback
863 * @param hsram : SRAM handle
864 * @param CallbackId : ID of the callback to be registered
865 * This parameter can be one of the following values:
866 * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID
867 * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
868 * @param pCallback : pointer to the Callback function
869 * @retval status
870 */
HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef * hsram,HAL_SRAM_CallbackIDTypeDef CallbackId,pSRAM_DmaCallbackTypeDef pCallback)871 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
872 pSRAM_DmaCallbackTypeDef pCallback)
873 {
874 HAL_StatusTypeDef status = HAL_OK;
875 HAL_SRAM_StateTypeDef state;
876
877 if (pCallback == NULL)
878 {
879 return HAL_ERROR;
880 }
881
882 /* Process locked */
883 __HAL_LOCK(hsram);
884
885 state = hsram->State;
886 if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
887 {
888 switch (CallbackId)
889 {
890 case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
891 hsram->DmaXferCpltCallback = pCallback;
892 break;
893 case HAL_SRAM_DMA_XFER_ERR_CB_ID :
894 hsram->DmaXferErrorCallback = pCallback;
895 break;
896 default :
897 /* update return status */
898 status = HAL_ERROR;
899 break;
900 }
901 }
902 else
903 {
904 /* update return status */
905 status = HAL_ERROR;
906 }
907
908 /* Release Lock */
909 __HAL_UNLOCK(hsram);
910 return status;
911 }
912 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
913
914 /**
915 * @}
916 */
917
918 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
919 * @brief Control functions
920 *
921 @verbatim
922 ==============================================================================
923 ##### SRAM Control functions #####
924 ==============================================================================
925 [..]
926 This subsection provides a set of functions allowing to control dynamically
927 the SRAM interface.
928
929 @endverbatim
930 * @{
931 */
932
933 /**
934 * @brief Enables dynamically SRAM write operation.
935 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
936 * the configuration information for SRAM module.
937 * @retval HAL status
938 */
HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef * hsram)939 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
940 {
941 /* Check the SRAM controller state */
942 if (hsram->State == HAL_SRAM_STATE_PROTECTED)
943 {
944 /* Process Locked */
945 __HAL_LOCK(hsram);
946
947 /* Update the SRAM controller state */
948 hsram->State = HAL_SRAM_STATE_BUSY;
949
950 /* Enable write operation */
951 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
952
953 /* Update the SRAM controller state */
954 hsram->State = HAL_SRAM_STATE_READY;
955
956 /* Process unlocked */
957 __HAL_UNLOCK(hsram);
958 }
959 else
960 {
961 return HAL_ERROR;
962 }
963
964 return HAL_OK;
965 }
966
967 /**
968 * @brief Disables dynamically SRAM write operation.
969 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
970 * the configuration information for SRAM module.
971 * @retval HAL status
972 */
HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef * hsram)973 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
974 {
975 /* Check the SRAM controller state */
976 if (hsram->State == HAL_SRAM_STATE_READY)
977 {
978 /* Process Locked */
979 __HAL_LOCK(hsram);
980
981 /* Update the SRAM controller state */
982 hsram->State = HAL_SRAM_STATE_BUSY;
983
984 /* Disable write operation */
985 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
986
987 /* Update the SRAM controller state */
988 hsram->State = HAL_SRAM_STATE_PROTECTED;
989
990 /* Process unlocked */
991 __HAL_UNLOCK(hsram);
992 }
993 else
994 {
995 return HAL_ERROR;
996 }
997
998 return HAL_OK;
999 }
1000
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
1006 * @brief Peripheral State functions
1007 *
1008 @verbatim
1009 ==============================================================================
1010 ##### SRAM State functions #####
1011 ==============================================================================
1012 [..]
1013 This subsection permits to get in run-time the status of the SRAM controller
1014 and the data flow.
1015
1016 @endverbatim
1017 * @{
1018 */
1019
1020 /**
1021 * @brief Returns the SRAM controller state
1022 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
1023 * the configuration information for SRAM module.
1024 * @retval HAL state
1025 */
HAL_SRAM_GetState(SRAM_HandleTypeDef * hsram)1026 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
1027 {
1028 return hsram->State;
1029 }
1030
1031 /**
1032 * @}
1033 */
1034
1035 /**
1036 * @}
1037 */
1038
1039 /** @addtogroup SRAM_Private_Functions SRAM Private Functions
1040 * @{
1041 */
1042
1043 /**
1044 * @brief DMA SRAM process complete callback.
1045 * @param hdma : DMA handle
1046 * @retval None
1047 */
SRAM_DMACplt(DMA_HandleTypeDef * hdma)1048 static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
1049 {
1050 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1051
1052 /* Disable the DMA channel */
1053 __HAL_DMA_DISABLE(hdma);
1054
1055 /* Update the SRAM controller state */
1056 hsram->State = HAL_SRAM_STATE_READY;
1057
1058 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1059 hsram->DmaXferCpltCallback(hdma);
1060 #else
1061 HAL_SRAM_DMA_XferCpltCallback(hdma);
1062 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1063 }
1064
1065 /**
1066 * @brief DMA SRAM process complete callback.
1067 * @param hdma : DMA handle
1068 * @retval None
1069 */
SRAM_DMACpltProt(DMA_HandleTypeDef * hdma)1070 static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
1071 {
1072 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1073
1074 /* Disable the DMA channel */
1075 __HAL_DMA_DISABLE(hdma);
1076
1077 /* Update the SRAM controller state */
1078 hsram->State = HAL_SRAM_STATE_PROTECTED;
1079
1080 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1081 hsram->DmaXferCpltCallback(hdma);
1082 #else
1083 HAL_SRAM_DMA_XferCpltCallback(hdma);
1084 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1085 }
1086
1087 /**
1088 * @brief DMA SRAM error callback.
1089 * @param hdma : DMA handle
1090 * @retval None
1091 */
SRAM_DMAError(DMA_HandleTypeDef * hdma)1092 static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
1093 {
1094 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
1095
1096 /* Disable the DMA channel */
1097 __HAL_DMA_DISABLE(hdma);
1098
1099 /* Update the SRAM controller state */
1100 hsram->State = HAL_SRAM_STATE_ERROR;
1101
1102 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
1103 hsram->DmaXferErrorCallback(hdma);
1104 #else
1105 HAL_SRAM_DMA_XferErrorCallback(hdma);
1106 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
1107 }
1108
1109 /**
1110 * @}
1111 */
1112
1113 /**
1114 * @}
1115 */
1116
1117 #endif /* HAL_SRAM_MODULE_ENABLED */
1118
1119 /**
1120 * @}
1121 */
1122
1123
