1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_RCC_H 22 #define STM32L5xx_HAL_RCC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup RCC_Exported_Types RCC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief RCC PLL configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PLLState; /*!< The new state of the PLL. 50 This parameter can be a value of @ref RCC_PLL_Config */ 51 52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 53 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 54 55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 56 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ 57 58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 59 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 60 61 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 62 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 63 64 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 65 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 66 67 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 68 User has to set the PLLR parameter correctly to not exceed max frequency 110MHZ. 69 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 70 71 } RCC_PLLInitTypeDef; 72 73 /** 74 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 75 */ 76 typedef struct 77 { 78 uint32_t OscillatorType; /*!< The oscillators to be configured. 79 This parameter can be a value of @ref RCC_Oscillator_Type */ 80 81 uint32_t HSEState; /*!< The new state of the HSE. 82 This parameter can be a value of @ref RCC_HSE_Config */ 83 84 uint32_t LSEState; /*!< The new state of the LSE. 85 This parameter can be a value of @ref RCC_LSE_Config */ 86 87 uint32_t HSIState; /*!< The new state of the HSI. 88 This parameter can be a value of @ref RCC_HSI_Config */ 89 90 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 91 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ 92 93 uint32_t LSIState; /*!< The new state of the LSI. 94 This parameter can be a value of @ref RCC_LSI_Config */ 95 96 uint32_t LSIDiv; /*!< The division factor of the LSI. 97 This parameter can be a value of @ref RCC_LSI_Div */ 98 99 uint32_t MSIState; /*!< The new state of the MSI. 100 This parameter can be a value of @ref RCC_MSI_Config */ 101 102 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 103 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 104 105 uint32_t MSIClockRange; /*!< The MSI frequency range. 106 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 107 108 uint32_t HSI48State; /*!< The new state of the HSI48. 109 This parameter can be a value of @ref RCC_HSI48_Config */ 110 111 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 112 113 } RCC_OscInitTypeDef; 114 115 /** 116 * @brief RCC System, AHB and APB buses clock configuration structure definition 117 */ 118 typedef struct 119 { 120 uint32_t ClockType; /*!< The clock to be configured. 121 This parameter can be a value of @ref RCC_System_Clock_Type */ 122 123 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 124 This parameter can be a value of @ref RCC_System_Clock_Source */ 125 126 uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 127 This parameter can be a value of @ref RCC_AHBx_Clock_Source */ 128 129 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 130 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 131 132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 133 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 134 135 } RCC_ClkInitTypeDef; 136 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 /** @defgroup RCC_Exported_Constants RCC Exported Constants 143 * @{ 144 */ 145 146 /** @defgroup RCC_Timeout_Value Timeout Values 147 * @{ 148 */ 149 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 150 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 151 /** 152 * @} 153 */ 154 155 /** @defgroup RCC_Oscillator_Type Oscillator Type 156 * @{ 157 */ 158 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 159 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 160 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 161 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 162 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 163 #define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ 164 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ 165 /** 166 * @} 167 */ 168 169 /** @defgroup RCC_HSE_Config HSE Config 170 * @{ 171 */ 172 #define RCC_HSE_OFF 0U /*!< HSE clock deactivation */ 173 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 174 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup RCC_LSE_Config LSE Config 180 * @{ 181 */ 182 #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ 183 #define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ 184 #define RCC_LSE_ON ((uint32_t)(RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< LSE clock activation for RCC and peripherals */ 185 #define RCC_LSE_BYPASS_RTC_ONLY ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 186 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 187 /** 188 * @} 189 */ 190 191 /** @defgroup RCC_HSI_Config HSI Config 192 * @{ 193 */ 194 #define RCC_HSI_OFF 0U /*!< HSI clock deactivation */ 195 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 196 197 #define RCC_HSICALIBRATION_DEFAULT 0x00000040U /* Default HSI calibration trimming value */ 198 /** 199 * @} 200 */ 201 202 /** @defgroup RCC_LSI_Config LSI Config 203 * @{ 204 */ 205 #define RCC_LSI_OFF 0U /*!< LSI clock deactivation */ 206 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 207 /** 208 * @} 209 */ 210 211 /** @defgroup RCC_LSI_Div LSI Div 212 * @{ 213 */ 214 #define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ 215 #define RCC_LSI_DIV128 RCC_CSR_LSIPRE /*!< LSI clock is divided by 128 */ 216 /** 217 * @} 218 */ 219 220 /** @defgroup RCC_MSI_Config MSI Config 221 * @{ 222 */ 223 #define RCC_MSI_OFF 0U /*!< MSI clock deactivation */ 224 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 225 226 #define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ 227 /** 228 * @} 229 */ 230 231 /** @defgroup RCC_HSI48_Config HSI48 Config 232 * @{ 233 */ 234 #define RCC_HSI48_OFF 0U /*!< HSI48 clock deactivation */ 235 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 236 /** 237 * @} 238 */ 239 240 /** @defgroup RCC_PLL_Config PLL Config 241 * @{ 242 */ 243 #define RCC_PLL_NONE 0U /*!< PLL configuration unchanged */ 244 #define RCC_PLL_OFF 1U /*!< PLL deactivation */ 245 #define RCC_PLL_ON 2U /*!< PLL activation */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider 251 * @{ 252 */ 253 #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */ 254 #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */ 255 #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */ 256 #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */ 257 #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */ 258 #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */ 259 #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */ 260 #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */ 261 #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */ 262 #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */ 263 #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */ 264 #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */ 265 #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */ 266 #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */ 267 #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */ 268 #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */ 269 /** 270 * @} 271 */ 272 273 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 274 * @{ 275 */ 276 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ 277 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ 278 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ 279 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ 280 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ 281 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ 282 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ 283 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ 284 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ 285 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ 286 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ 287 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ 288 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ 289 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ 290 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ 291 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ 292 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ 293 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ 294 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ 295 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ 296 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ 297 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ 298 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ 299 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ 300 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ 301 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ 302 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ 303 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ 304 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ 305 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 311 * @{ 312 */ 313 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ 314 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ 315 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ 316 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 322 * @{ 323 */ 324 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ 325 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ 326 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ 327 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ 328 /** 329 * @} 330 */ 331 332 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 333 * @{ 334 */ 335 #define RCC_PLLSOURCE_NONE 0U /*!< No clock selected as PLL entry clock source */ 336 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */ 337 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */ 338 #define RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */ 339 /** 340 * @} 341 */ 342 343 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 344 * @{ 345 */ 346 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL */ 347 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 348 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup RCC_PLLSAI1_Clock_Source PLLSAI1 Clock Source 354 * @{ 355 */ 356 #define RCC_PLLSAI1SOURCE_NONE 0U /*!< No clock selected as PLLSAI1 entry clock source */ 357 #define RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_0 /*!< MSI clock selected as PLLSAI1 entry clock source */ 358 #define RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_1 /*!< HSI clock selected as PLLSAI1 entry clock source */ 359 #define RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_1 | RCC_PLLSAI1CFGR_PLLSAI1SRC_0) /*!< HSE clock selected as PLLSAI1 entry clock source */ 360 /** 361 * @} 362 */ 363 364 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 365 * @{ 366 */ 367 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 368 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 369 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup RCC_PLLSAI2_Clock_Source PLLSAI2 Clock Source 375 * @{ 376 */ 377 #define RCC_PLLSAI2SOURCE_NONE 0U /*!< No clock selected as PLLSAI2 entry clock source */ 378 #define RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_0 /*!< MSI clock selected as PLLSAI2 entry clock source */ 379 #define RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_1 /*!< HSI clock selected as PLLSAI2 entry clock source */ 380 #define RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_1 | RCC_PLLSAI2CFGR_PLLSAI2SRC_0) /*!< HSE clock selected as PLLSAI2 entry clock source */ 381 /** 382 * @} 383 */ 384 385 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 386 * @{ 387 */ 388 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 394 * @{ 395 */ 396 #define RCC_MSIRANGE_0 0UL /*!< MSI = 100 kHz */ 397 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_0 /*!< MSI = 200 kHz */ 398 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_1 /*!< MSI = 400 kHz */ 399 #define RCC_MSIRANGE_3 (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 800 kHz */ 400 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_2 /*!< MSI = 1 MHz */ 401 #define RCC_MSIRANGE_5 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0) /*!< MSI = 2 MHz */ 402 #define RCC_MSIRANGE_6 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1) /*!< MSI = 4 MHz */ 403 #define RCC_MSIRANGE_7 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 8 MHz */ 404 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_3 /*!< MSI = 16 MHz */ 405 #define RCC_MSIRANGE_9 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0) /*!< MSI = 24 MHz */ 406 #define RCC_MSIRANGE_10 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1) /*!< MSI = 32 MHz */ 407 #define RCC_MSIRANGE_11 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 48 MHz */ 408 /** 409 * @} 410 */ 411 412 /** @defgroup RCC_System_Clock_Type System Clock Type 413 * @{ 414 */ 415 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 416 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 417 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 418 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 419 /** 420 * @} 421 */ 422 423 /** @defgroup RCC_System_Clock_Source System Clock Source 424 * @{ 425 */ 426 #define RCC_SYSCLKSOURCE_MSI 0UL /*!< MSI selection as system clock */ 427 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */ 428 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */ 429 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW /*!< PLL selection as system clock */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 435 * @{ 436 */ 437 #define RCC_SYSCLKSOURCE_STATUS_MSI 0UL /*!< MSI used as system clock */ 438 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */ 439 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */ 440 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS /*!< PLL used as system clock */ 441 /** 442 * @} 443 */ 444 445 /** @defgroup RCC_AHBx_Clock_Source AHBx Clock Source 446 * @{ 447 */ 448 #define RCC_SYSCLK_DIV1 0UL /*!< SYSCLK not divided */ 449 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ 450 #define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ 451 #define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ 452 #define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ 453 #define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ 454 #define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ 455 #define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ 456 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 512 */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 462 * @{ 463 */ 464 #define RCC_HCLK_DIV1 0UL /*!< HCLK not divided */ 465 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_2 /*!< HCLK divided by 2 */ 466 #define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK divided by 4 */ 467 #define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK divided by 8 */ 468 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1 /*!< HCLK divided by 16 */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 474 * @{ 475 */ 476 #define RCC_RTCCLKSOURCE_NONE 0U /*!< No clock used as RTC clock */ 477 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 478 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 479 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 480 /** 481 * @} 482 */ 483 484 /** @defgroup RCC_MCO_Index MCO Index 485 * @{ 486 */ 487 #define RCC_MCO1 0U 488 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 489 /** 490 * @} 491 */ 492 493 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 494 * @{ 495 */ 496 #define RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO1 output disabled, no clock on MCO1 */ 497 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 498 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 499 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 500 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 501 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 502 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 503 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 504 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 510 * @{ 511 */ 512 #define RCC_MCODIV_1 0UL /*!< MCO not divided */ 513 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ 514 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ 515 #define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ 516 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup RCC_Interrupt Interrupts 522 * @{ 523 */ 524 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 525 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 526 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 527 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 528 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 529 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 530 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 531 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 532 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 533 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup RCC_Flag Flags 539 * Elements values convention: XXXYYYYYb 540 * - YYYYY : Flag position in the register 541 * - XXX : Register index 542 * - 001: CR register 543 * - 010: BDCR register 544 * - 011: CSR register 545 * - 100: CRRCR register 546 * @{ 547 */ 548 /* Flags in the CR register */ 549 #define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ 550 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 551 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 552 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ 553 #define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ 554 #define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ 555 556 /* Flags in the BDCR register */ 557 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ 558 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */ 559 560 /* Flags in the CSR register */ 561 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ 562 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 563 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ 564 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ 565 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ 566 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 567 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 568 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 569 570 /* Flags in the CRRCR register */ 571 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 577 * @{ 578 */ 579 #define RCC_LSEDRIVE_LOW 0U /*!< LSE low drive capability */ 580 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 581 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 582 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 583 /** 584 * @} 585 */ 586 587 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 588 * @{ 589 */ 590 #define RCC_STOP_WAKEUPCLOCK_MSI 0U /*!< MSI selection after wake-up from STOP */ 591 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup RCC_items RCC items 597 * @brief RCC items to configure attributes on 598 * @{ 599 */ 600 #define RCC_HSI RCC_SECCFGR_HSISEC 601 #define RCC_HSE RCC_SECCFGR_HSESEC 602 #define RCC_MSI RCC_SECCFGR_MSISEC 603 #define RCC_LSI RCC_SECCFGR_LSISEC 604 #define RCC_LSE RCC_SECCFGR_LSESEC 605 #define RCC_HSI48 RCC_SECCFGR_HSI48SEC 606 #define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC 607 #define RCC_PRESCALER RCC_SECCFGR_PRESCSEC 608 #define RCC_PLL RCC_SECCFGR_PLLSEC 609 #define RCC_PLLSAI1 RCC_SECCFGR_PLLSAI1SEC 610 #define RCC_PLLSAI2 RCC_SECCFGR_PLLSAI2SEC 611 #define RCC_CLK48M RCC_SECCFGR_CLK48MSEC 612 #define RCC_RMVF RCC_SECCFGR_RMVFSEC 613 #define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ 614 RCC_SYSCLK|RCC_PRESCALER|RCC_PLL|RCC_PLLSAI1| \ 615 RCC_PLLSAI2|RCC_CLK48M|RCC_RMVF) 616 /** 617 * @} 618 */ 619 620 /** @defgroup RCC_attributes RCC attributes 621 * @brief RCC secure/non-secure and privilege/non-privilege attributes 622 * @note secure and non-secure attributes are only available from secure state when the system 623 * implement the security (TZEN=1) 624 * @{ 625 */ 626 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 627 #define RCC_SEC (RCC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 628 #define RCC_NSEC (RCC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 629 #endif /* __ARM_FEATURE_CMSE */ 630 #define RCC_PRIV (RCC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 631 #define RCC_NPRIV (RCC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 632 /** 633 * @} 634 */ 635 636 /** 637 * @} 638 */ 639 640 /* Exported macros -----------------------------------------------------------*/ 641 642 /** @defgroup RCC_Exported_Macros RCC Exported Macros 643 * @{ 644 */ 645 646 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 647 * @brief Enable or disable the AHB1 peripheral clock. 648 * @note After reset, the peripheral clock (used for registers read/write access) 649 * is disabled and the application software has to enable this clock before 650 * using it. 651 * @{ 652 */ 653 654 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 655 __IO uint32_t tmpreg; \ 656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 657 /* Delay after an RCC peripheral clock enabling */ \ 658 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 659 UNUSED(tmpreg); \ 660 } while(0) 661 662 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 663 __IO uint32_t tmpreg; \ 664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 665 /* Delay after an RCC peripheral clock enabling */ \ 666 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 667 UNUSED(tmpreg); \ 668 } while(0) 669 670 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ 671 __IO uint32_t tmpreg; \ 672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 673 /* Delay after an RCC peripheral clock enabling */ \ 674 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ 675 UNUSED(tmpreg); \ 676 } while(0) 677 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 678 __IO uint32_t tmpreg; \ 679 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 680 /* Delay after an RCC peripheral clock enabling */ \ 681 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 682 UNUSED(tmpreg); \ 683 } while(0) 684 685 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 686 __IO uint32_t tmpreg; \ 687 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 688 /* Delay after an RCC peripheral clock enabling */ \ 689 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 690 UNUSED(tmpreg); \ 691 } while(0) 692 693 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 694 __IO uint32_t tmpreg; \ 695 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 696 /* Delay after an RCC peripheral clock enabling */ \ 697 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 698 UNUSED(tmpreg); \ 699 } while(0) 700 701 #define __HAL_RCC_GTZC_CLK_ENABLE() do { \ 702 __IO uint32_t tmpreg; \ 703 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ 704 /* Delay after an RCC peripheral clock enabling */ \ 705 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ 706 UNUSED(tmpreg); \ 707 } while(0) 708 709 710 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 711 712 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 713 714 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) 715 716 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 717 718 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 719 720 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 721 722 #define __HAL_RCC_GTZC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) 723 724 /** 725 * @} 726 */ 727 728 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 729 * @brief Enable or disable the AHB2 peripheral clock. 730 * @note After reset, the peripheral clock (used for registers read/write access) 731 * is disabled and the application software has to enable this clock before 732 * using it. 733 * @{ 734 */ 735 736 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 737 __IO uint32_t tmpreg; \ 738 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 739 /* Delay after an RCC peripheral clock enabling */ \ 740 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 741 UNUSED(tmpreg); \ 742 } while(0) 743 744 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 745 __IO uint32_t tmpreg; \ 746 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 747 /* Delay after an RCC peripheral clock enabling */ \ 748 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 749 UNUSED(tmpreg); \ 750 } while(0) 751 752 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 753 __IO uint32_t tmpreg; \ 754 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 755 /* Delay after an RCC peripheral clock enabling */ \ 756 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 757 UNUSED(tmpreg); \ 758 } while(0) 759 760 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 761 __IO uint32_t tmpreg; \ 762 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 763 /* Delay after an RCC peripheral clock enabling */ \ 764 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 765 UNUSED(tmpreg); \ 766 } while(0) 767 768 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 769 __IO uint32_t tmpreg; \ 770 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 771 /* Delay after an RCC peripheral clock enabling */ \ 772 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 773 UNUSED(tmpreg); \ 774 } while(0) 775 776 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 777 __IO uint32_t tmpreg; \ 778 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 779 /* Delay after an RCC peripheral clock enabling */ \ 780 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 781 UNUSED(tmpreg); \ 782 } while(0) 783 784 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 785 __IO uint32_t tmpreg; \ 786 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 787 /* Delay after an RCC peripheral clock enabling */ \ 788 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 789 UNUSED(tmpreg); \ 790 } while(0) 791 792 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 793 __IO uint32_t tmpreg; \ 794 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 795 /* Delay after an RCC peripheral clock enabling */ \ 796 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 797 UNUSED(tmpreg); \ 798 } while(0) 799 800 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 801 __IO uint32_t tmpreg; \ 802 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 803 /* Delay after an RCC peripheral clock enabling */ \ 804 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 805 UNUSED(tmpreg); \ 806 } while(0) 807 808 #if defined(AES) 809 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 810 __IO uint32_t tmpreg; \ 811 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 812 /* Delay after an RCC peripheral clock enabling */ \ 813 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 814 UNUSED(tmpreg); \ 815 } while(0) 816 #endif /* AES */ 817 818 #if defined(HASH) 819 #define __HAL_RCC_HASH_CLK_ENABLE() do { \ 820 __IO uint32_t tmpreg; \ 821 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 822 /* Delay after an RCC peripheral clock enabling */ \ 823 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ 824 UNUSED(tmpreg); \ 825 } while(0) 826 #endif /* HASH */ 827 828 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 829 __IO uint32_t tmpreg; \ 830 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 831 /* Delay after an RCC peripheral clock enabling */ \ 832 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 833 UNUSED(tmpreg); \ 834 } while(0) 835 836 #define __HAL_RCC_PKA_CLK_ENABLE() do { \ 837 __IO uint32_t tmpreg; \ 838 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 839 /* Delay after an RCC peripheral clock enabling */ \ 840 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ 841 UNUSED(tmpreg); \ 842 } while(0) 843 844 #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ 845 __IO uint32_t tmpreg; \ 846 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ 847 /* Delay after an RCC peripheral clock enabling */ \ 848 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ 849 UNUSED(tmpreg); \ 850 } while(0) 851 852 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 853 __IO uint32_t tmpreg; \ 854 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 855 /* Delay after an RCC peripheral clock enabling */ \ 856 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ 857 UNUSED(tmpreg); \ 858 } while(0) 859 860 861 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 862 863 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 864 865 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 866 867 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 868 869 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 870 871 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 872 873 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 874 875 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 876 877 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 878 879 #if defined(AES) 880 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 881 #endif /* AES */ 882 883 #if defined(HASH) 884 #define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) 885 #endif /* HASH */ 886 887 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 888 889 #define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) 890 891 #define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN) 892 893 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) 894 895 /** 896 * @} 897 */ 898 899 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 900 * @brief Enable or disable the AHB3 peripheral clock. 901 * @note After reset, the peripheral clock (used for registers read/write access) 902 * is disabled and the application software has to enable this clock before 903 * using it. 904 * @{ 905 */ 906 907 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 908 __IO uint32_t tmpreg; \ 909 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 910 /* Delay after an RCC peripheral clock enabling */ \ 911 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 912 UNUSED(tmpreg); \ 913 } while(0) 914 915 #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ 916 __IO uint32_t tmpreg; \ 917 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 918 /* Delay after an RCC peripheral clock enabling */ \ 919 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ 920 UNUSED(tmpreg); \ 921 } while(0) 922 923 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 924 925 #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) 926 927 /** 928 * @} 929 */ 930 931 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 932 * @brief Enable or disable the APB1 peripheral clock. 933 * @note After reset, the peripheral clock (used for registers read/write access) 934 * is disabled and the application software has to enable this clock before 935 * using it. 936 * @{ 937 */ 938 939 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 940 __IO uint32_t tmpreg; \ 941 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 942 /* Delay after an RCC peripheral clock enabling */ \ 943 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 944 UNUSED(tmpreg); \ 945 } while(0) 946 947 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 948 __IO uint32_t tmpreg; \ 949 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 950 /* Delay after an RCC peripheral clock enabling */ \ 951 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 952 UNUSED(tmpreg); \ 953 } while(0) 954 955 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 956 __IO uint32_t tmpreg; \ 957 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 958 /* Delay after an RCC peripheral clock enabling */ \ 959 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 960 UNUSED(tmpreg); \ 961 } while(0) 962 963 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 964 __IO uint32_t tmpreg; \ 965 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 966 /* Delay after an RCC peripheral clock enabling */ \ 967 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 968 UNUSED(tmpreg); \ 969 } while(0) 970 971 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 972 __IO uint32_t tmpreg; \ 973 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 974 /* Delay after an RCC peripheral clock enabling */ \ 975 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 976 UNUSED(tmpreg); \ 977 } while(0) 978 979 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 980 __IO uint32_t tmpreg; \ 981 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 982 /* Delay after an RCC peripheral clock enabling */ \ 983 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 984 UNUSED(tmpreg); \ 985 } while(0) 986 987 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 988 __IO uint32_t tmpreg; \ 989 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 990 /* Delay after an RCC peripheral clock enabling */ \ 991 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 992 UNUSED(tmpreg); \ 993 } while(0) 994 995 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 996 __IO uint32_t tmpreg; \ 997 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 998 /* Delay after an RCC peripheral clock enabling */ \ 999 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 1000 UNUSED(tmpreg); \ 1001 } while(0) 1002 1003 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 1004 __IO uint32_t tmpreg; \ 1005 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1006 /* Delay after an RCC peripheral clock enabling */ \ 1007 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 1008 UNUSED(tmpreg); \ 1009 } while(0) 1010 1011 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 1012 __IO uint32_t tmpreg; \ 1013 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1014 /* Delay after an RCC peripheral clock enabling */ \ 1015 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 1016 UNUSED(tmpreg); \ 1017 } while(0) 1018 1019 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 1020 __IO uint32_t tmpreg; \ 1021 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1022 /* Delay after an RCC peripheral clock enabling */ \ 1023 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 1024 UNUSED(tmpreg); \ 1025 } while(0) 1026 1027 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 1028 __IO uint32_t tmpreg; \ 1029 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1030 /* Delay after an RCC peripheral clock enabling */ \ 1031 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 1032 UNUSED(tmpreg); \ 1033 } while(0) 1034 1035 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 1036 __IO uint32_t tmpreg; \ 1037 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1038 /* Delay after an RCC peripheral clock enabling */ \ 1039 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 1040 UNUSED(tmpreg); \ 1041 } while(0) 1042 1043 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 1044 __IO uint32_t tmpreg; \ 1045 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1046 /* Delay after an RCC peripheral clock enabling */ \ 1047 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 1048 UNUSED(tmpreg); \ 1049 } while(0) 1050 1051 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 1052 __IO uint32_t tmpreg; \ 1053 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1054 /* Delay after an RCC peripheral clock enabling */ \ 1055 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 1056 UNUSED(tmpreg); \ 1057 } while(0) 1058 1059 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 1060 __IO uint32_t tmpreg; \ 1061 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1062 /* Delay after an RCC peripheral clock enabling */ \ 1063 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 1064 UNUSED(tmpreg); \ 1065 } while(0) 1066 1067 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 1068 __IO uint32_t tmpreg; \ 1069 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1070 /* Delay after an RCC peripheral clock enabling */ \ 1071 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 1072 UNUSED(tmpreg); \ 1073 } while(0) 1074 1075 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ 1076 __IO uint32_t tmpreg; \ 1077 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1078 /* Delay after an RCC peripheral clock enabling */ \ 1079 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ 1080 UNUSED(tmpreg); \ 1081 } while(0) 1082 1083 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 1084 __IO uint32_t tmpreg; \ 1085 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1086 /* Delay after an RCC peripheral clock enabling */ \ 1087 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 1088 UNUSED(tmpreg); \ 1089 } while(0) 1090 1091 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 1092 __IO uint32_t tmpreg; \ 1093 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1094 /* Delay after an RCC peripheral clock enabling */ \ 1095 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 1096 UNUSED(tmpreg); \ 1097 } while(0) 1098 1099 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 1100 __IO uint32_t tmpreg; \ 1101 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1102 /* Delay after an RCC peripheral clock enabling */ \ 1103 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 1104 UNUSED(tmpreg); \ 1105 } while(0) 1106 1107 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 1108 __IO uint32_t tmpreg; \ 1109 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1110 /* Delay after an RCC peripheral clock enabling */ \ 1111 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 1112 UNUSED(tmpreg); \ 1113 } while(0) 1114 1115 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 1116 __IO uint32_t tmpreg; \ 1117 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1118 /* Delay after an RCC peripheral clock enabling */ \ 1119 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 1120 UNUSED(tmpreg); \ 1121 } while(0) 1122 1123 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 1124 __IO uint32_t tmpreg; \ 1125 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1126 /* Delay after an RCC peripheral clock enabling */ \ 1127 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 1128 UNUSED(tmpreg); \ 1129 } while(0) 1130 1131 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 1132 __IO uint32_t tmpreg; \ 1133 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1134 /* Delay after an RCC peripheral clock enabling */ \ 1135 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 1136 UNUSED(tmpreg); \ 1137 } while(0) 1138 1139 #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ 1140 __IO uint32_t tmpreg; \ 1141 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ 1142 /* Delay after an RCC peripheral clock enabling */ \ 1143 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ 1144 UNUSED(tmpreg); \ 1145 } while(0) 1146 1147 #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ 1148 __IO uint32_t tmpreg; \ 1149 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1150 /* Delay after an RCC peripheral clock enabling */ \ 1151 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ 1152 UNUSED(tmpreg); \ 1153 } while(0) 1154 1155 #if defined(USB) 1156 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 1157 __IO uint32_t tmpreg; \ 1158 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ 1159 /* Delay after an RCC peripheral clock enabling */ \ 1160 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ 1161 UNUSED(tmpreg); \ 1162 } while(0) 1163 #endif /* USB */ 1164 1165 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ 1166 __IO uint32_t tmpreg; \ 1167 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1168 /* Delay after an RCC peripheral clock enabling */ \ 1169 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ 1170 UNUSED(tmpreg); \ 1171 } while(0) 1172 1173 1174 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 1175 1176 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 1177 1178 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 1179 1180 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 1181 1182 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 1183 1184 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 1185 1186 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 1187 1188 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 1189 1190 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 1191 1192 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 1193 1194 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 1195 1196 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 1197 1198 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 1199 1200 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 1201 1202 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 1203 1204 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 1205 1206 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) 1207 1208 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 1209 1210 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 1211 1212 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 1213 1214 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 1215 1216 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 1217 1218 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 1219 1220 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 1221 1222 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) 1223 1224 #define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) 1225 1226 #if defined(USB) 1227 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); 1228 #endif /* USB */ 1229 1230 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); 1231 1232 /** 1233 * @} 1234 */ 1235 1236 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 1237 * @brief Enable or disable the APB2 peripheral clock. 1238 * @note After reset, the peripheral clock (used for registers read/write access) 1239 * is disabled and the application software has to enable this clock before 1240 * using it. 1241 * @{ 1242 */ 1243 1244 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 1245 __IO uint32_t tmpreg; \ 1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1247 /* Delay after an RCC peripheral clock enabling */ \ 1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 1249 UNUSED(tmpreg); \ 1250 } while(0) 1251 1252 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 1253 __IO uint32_t tmpreg; \ 1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1255 /* Delay after an RCC peripheral clock enabling */ \ 1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 1257 UNUSED(tmpreg); \ 1258 } while(0) 1259 1260 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 1261 __IO uint32_t tmpreg; \ 1262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1263 /* Delay after an RCC peripheral clock enabling */ \ 1264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 1265 UNUSED(tmpreg); \ 1266 } while(0) 1267 1268 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1269 __IO uint32_t tmpreg; \ 1270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1271 /* Delay after an RCC peripheral clock enabling */ \ 1272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 1273 UNUSED(tmpreg); \ 1274 } while(0) 1275 1276 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 1277 __IO uint32_t tmpreg; \ 1278 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1279 /* Delay after an RCC peripheral clock enabling */ \ 1280 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 1281 UNUSED(tmpreg); \ 1282 } while(0) 1283 1284 1285 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1286 __IO uint32_t tmpreg; \ 1287 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1288 /* Delay after an RCC peripheral clock enabling */ \ 1289 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 1290 UNUSED(tmpreg); \ 1291 } while(0) 1292 1293 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1294 __IO uint32_t tmpreg; \ 1295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1296 /* Delay after an RCC peripheral clock enabling */ \ 1297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 1298 UNUSED(tmpreg); \ 1299 } while(0) 1300 1301 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1302 __IO uint32_t tmpreg; \ 1303 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1304 /* Delay after an RCC peripheral clock enabling */ \ 1305 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 1306 UNUSED(tmpreg); \ 1307 } while(0) 1308 1309 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 1310 __IO uint32_t tmpreg; \ 1311 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1312 /* Delay after an RCC peripheral clock enabling */ \ 1313 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 1314 UNUSED(tmpreg); \ 1315 } while(0) 1316 1317 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 1318 __IO uint32_t tmpreg; \ 1319 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1320 /* Delay after an RCC peripheral clock enabling */ \ 1321 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 1322 UNUSED(tmpreg); \ 1323 } while(0) 1324 1325 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 1326 __IO uint32_t tmpreg; \ 1327 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1328 /* Delay after an RCC peripheral clock enabling */ \ 1329 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 1330 UNUSED(tmpreg); \ 1331 } while(0) 1332 1333 1334 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 1335 1336 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 1337 1338 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 1339 1340 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 1341 1342 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 1343 1344 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 1345 1346 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 1347 1348 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 1349 1350 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 1351 1352 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 1353 1354 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 1355 1356 /** 1357 * @} 1358 */ 1359 1360 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 1361 * @brief Check whether the AHB1 peripheral clock is enabled or not. 1362 * @note After reset, the peripheral clock (used for registers read/write access) 1363 * is disabled and the application software has to enable this clock before 1364 * using it. 1365 * @{ 1366 */ 1367 1368 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U) 1369 1370 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U) 1371 1372 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U) 1373 1374 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) 1375 1376 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) 1377 1378 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) 1379 1380 #define __HAL_RCC_GTZC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) != 0U) 1381 1382 1383 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U) 1384 1385 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U) 1386 1387 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U) 1388 1389 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) 1390 1391 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) 1392 1393 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) 1394 1395 #define __HAL_RCC_GTZC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN) == 0U) 1396 1397 /** 1398 * @} 1399 */ 1400 1401 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 1402 * @brief Check whether the AHB2 peripheral clock is enabled or not. 1403 * @note After reset, the peripheral clock (used for registers read/write access) 1404 * is disabled and the application software has to enable this clock before 1405 * using it. 1406 * @{ 1407 */ 1408 1409 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) 1410 1411 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1412 1413 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) 1414 1415 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U) 1416 1417 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U) 1418 1419 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U) 1420 1421 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U) 1422 1423 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) 1424 1425 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != 0U) 1426 1427 #if defined(AES) 1428 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) 1429 #endif /* AES */ 1430 1431 #if defined(HASH) 1432 #define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) 1433 #endif /* HASH */ 1434 1435 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) 1436 1437 #define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) 1438 1439 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U) 1440 1441 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U) 1442 1443 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U) 1444 1445 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U) 1446 1447 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U) 1448 1449 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U) 1450 1451 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U) 1452 1453 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == 0U) 1454 1455 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == 0U) 1456 1457 #if defined(AES) 1458 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U) 1459 #endif /* AES */ 1460 1461 #if defined(HASH) 1462 #define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == 0U) 1463 #endif /* HASH */ 1464 1465 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U) 1466 1467 #define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) == 0U) 1468 1469 /** 1470 * @} 1471 */ 1472 1473 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 1474 * @brief Check whether the AHB3 peripheral clock is enabled or not. 1475 * @note After reset, the peripheral clock (used for registers read/write access) 1476 * is disabled and the application software has to enable this clock before 1477 * using it. 1478 * @{ 1479 */ 1480 1481 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U) 1482 1483 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) 1484 1485 /** 1486 * @} 1487 */ 1488 1489 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 1490 * @brief Check whether the APB1 peripheral clock is enabled or not. 1491 * @note After reset, the peripheral clock (used for registers read/write access) 1492 * is disabled and the application software has to enable this clock before 1493 * using it. 1494 * @{ 1495 */ 1496 1497 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) 1498 1499 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) 1500 1501 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) 1502 1503 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) 1504 1505 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) 1506 1507 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) 1508 1509 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U) 1510 1511 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) 1512 1513 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) 1514 1515 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U) 1516 1517 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) 1518 1519 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) 1520 1521 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) 1522 1523 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) 1524 1525 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) 1526 1527 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) 1528 1529 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U) 1530 1531 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) 1532 1533 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) 1534 1535 #if defined(USB) 1536 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U) 1537 #endif /* USB */ 1538 1539 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U) 1540 1541 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != 0U) 1542 1543 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != 0U) 1544 1545 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U) 1546 1547 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U) 1548 1549 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) 1550 1551 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) != 0U) 1552 1553 1554 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) 1555 1556 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) 1557 1558 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) 1559 1560 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) 1561 1562 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) 1563 1564 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) 1565 1566 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U) 1567 1568 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U) 1569 1570 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) 1571 1572 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U) 1573 1574 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) 1575 1576 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) 1577 1578 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) 1579 1580 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) 1581 1582 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) 1583 1584 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) 1585 1586 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U) 1587 1588 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) 1589 1590 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) 1591 1592 #if defined(USB) 1593 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U) 1594 #endif /* USB */ 1595 1596 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U) 1597 1598 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == 0U) 1599 1600 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == 0U) 1601 1602 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U) 1603 1604 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U) 1605 1606 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) 1607 1608 #define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN) == 0U) 1609 1610 /** 1611 * @} 1612 */ 1613 1614 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 1615 * @brief Check whether the APB2 peripheral clock is enabled or not. 1616 * @note After reset, the peripheral clock (used for registers read/write access) 1617 * is disabled and the application software has to enable this clock before 1618 * using it. 1619 * @{ 1620 */ 1621 1622 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U) 1623 1624 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != 0U) 1625 1626 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) 1627 1628 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) 1629 1630 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) 1631 1632 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) 1633 1634 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) 1635 1636 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) 1637 1638 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) 1639 1640 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) 1641 1642 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) 1643 1644 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != 0U) 1645 1646 1647 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U) 1648 1649 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) 1650 1651 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) 1652 1653 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) 1654 1655 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) 1656 1657 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) 1658 1659 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) 1660 1661 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) 1662 1663 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) 1664 1665 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) 1666 1667 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == 0U) 1668 1669 /** 1670 * @} 1671 */ 1672 1673 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 1674 * @brief Force or release AHB1 peripheral reset. 1675 * @{ 1676 */ 1677 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL) 1678 1679 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1680 1681 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1682 1683 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1684 1685 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1686 1687 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1688 1689 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1690 1691 1692 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL) 1693 1694 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 1695 1696 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 1697 1698 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) 1699 1700 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 1701 1702 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 1703 1704 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 1705 1706 /** 1707 * @} 1708 */ 1709 1710 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 1711 * @brief Force or release AHB2 peripheral reset. 1712 * @{ 1713 */ 1714 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL) 1715 1716 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1717 1718 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1719 1720 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1721 1722 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1723 1724 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1725 1726 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1727 1728 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1729 1730 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1731 1732 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 1733 1734 #if defined(AES) 1735 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1736 #endif /* AES */ 1737 1738 #if defined(HASH) 1739 #define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1740 #endif /* HASH */ 1741 1742 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1743 1744 #define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1745 1746 #define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) 1747 1748 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 1749 1750 1751 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL) 1752 1753 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 1754 1755 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 1756 1757 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 1758 1759 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 1760 1761 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 1762 1763 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 1764 1765 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 1766 1767 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 1768 1769 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 1770 1771 #if defined(AES) 1772 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 1773 #endif /* AES */ 1774 1775 #if defined(HASH) 1776 #define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) 1777 #endif /* HASH */ 1778 1779 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 1780 1781 #define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) 1782 1783 #define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTFDEC1RST) 1784 1785 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) 1786 1787 /** 1788 * @} 1789 */ 1790 1791 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 1792 * @brief Force or release AHB3 peripheral reset. 1793 * @{ 1794 */ 1795 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL) 1796 1797 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1798 1799 #define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 1800 1801 1802 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL) 1803 1804 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 1805 1806 #define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) 1807 1808 /** 1809 * @} 1810 */ 1811 1812 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 1813 * @brief Force or release APB1 peripheral reset. 1814 * @{ 1815 */ 1816 #define __HAL_RCC_APB1_FORCE_RESET() do { \ 1817 WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ 1818 WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ 1819 } while(0) 1820 1821 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1822 1823 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1824 1825 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1826 1827 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1828 1829 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1830 1831 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1832 1833 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1834 1835 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1836 1837 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1838 1839 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1840 1841 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1842 1843 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1844 1845 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1846 1847 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1848 1849 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1850 1851 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1852 1853 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1854 1855 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1856 1857 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 1858 1859 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 1860 1861 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1862 1863 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1864 1865 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1866 1867 #define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM3RST) 1868 1869 #define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 1870 1871 #if defined(USB) 1872 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_USBFSRST) 1873 #endif /* USB */ 1874 1875 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1876 1877 1878 #define __HAL_RCC_APB1_RELEASE_RESET() do { \ 1879 WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ 1880 WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ 1881 } while(0) 1882 1883 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 1884 1885 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 1886 1887 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 1888 1889 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 1890 1891 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 1892 1893 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 1894 1895 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 1896 1897 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 1898 1899 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 1900 1901 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 1902 1903 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 1904 1905 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 1906 1907 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 1908 1909 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 1910 1911 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 1912 1913 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) 1914 1915 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 1916 1917 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 1918 1919 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 1920 1921 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 1922 1923 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 1924 1925 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 1926 1927 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 1928 1929 #define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM3RST) 1930 1931 #define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) 1932 1933 #if defined(USB) 1934 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_USBFSRST) 1935 #endif /* USB */ 1936 1937 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) 1938 1939 /** 1940 * @} 1941 */ 1942 1943 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 1944 * @brief Force or release APB2 peripheral reset. 1945 * @{ 1946 */ 1947 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL) 1948 1949 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1950 1951 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1952 1953 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1954 1955 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1956 1957 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1958 1959 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1960 1961 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1962 1963 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1964 1965 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1966 1967 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 1968 1969 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 1970 1971 1972 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL) 1973 1974 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 1975 1976 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 1977 1978 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 1979 1980 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 1981 1982 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 1983 1984 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 1985 1986 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 1987 1988 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 1989 1990 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 1991 1992 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 1993 1994 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 1995 1996 /** 1997 * @} 1998 */ 1999 2000 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 2001 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 2002 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2003 * power consumption. 2004 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2005 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2006 * @{ 2007 */ 2008 2009 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2010 2011 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2012 2013 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2014 2015 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2016 2017 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2018 2019 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2020 2021 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2022 2023 #define __HAL_RCC_GTZC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) 2024 2025 #define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2026 2027 2028 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 2029 2030 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 2031 2032 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) 2033 2034 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 2035 2036 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 2037 2038 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 2039 2040 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 2041 2042 #define __HAL_RCC_GTZC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) 2043 2044 #define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) 2045 2046 /** 2047 * @} 2048 */ 2049 2050 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 2051 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 2052 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2053 * power consumption. 2054 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2055 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2056 * @{ 2057 */ 2058 2059 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2060 2061 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2062 2063 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2064 2065 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2066 2067 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2068 2069 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2070 2071 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2072 2073 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2074 2075 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2076 2077 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2078 2079 #if defined(AES) 2080 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2081 #endif /* AES */ 2082 2083 #if defined(HASH) 2084 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2085 #endif /* HASH */ 2086 2087 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2088 2089 #define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2090 2091 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) 2092 2093 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2094 2095 2096 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 2097 2098 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 2099 2100 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 2101 2102 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 2103 2104 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 2105 2106 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 2107 2108 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 2109 2110 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 2111 2112 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 2113 2114 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 2115 2116 #if defined(AES) 2117 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 2118 #endif /* AES */ 2119 2120 #if defined(HASH) 2121 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) 2122 #endif /* HASH */ 2123 2124 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 2125 2126 #define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) 2127 2128 #define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTFDEC1SMEN) 2129 2130 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) 2131 2132 /** 2133 * @} 2134 */ 2135 2136 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 2137 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 2138 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2139 * power consumption. 2140 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2141 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2142 * @{ 2143 */ 2144 2145 #define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2146 2147 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2148 2149 2150 #define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) 2151 2152 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 2153 2154 /** 2155 * @} 2156 */ 2157 2158 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 2159 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 2160 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2161 * power consumption. 2162 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2163 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2164 * @{ 2165 */ 2166 2167 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2168 2169 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2170 2171 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2172 2173 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2174 2175 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2176 2177 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2178 2179 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2180 2181 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2182 2183 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2184 2185 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2186 2187 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2188 2189 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2190 2191 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2192 2193 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2194 2195 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2196 2197 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2198 2199 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2200 2201 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2202 2203 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2204 2205 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2206 2207 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 2208 2209 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 2210 2211 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2212 2213 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2214 2215 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2216 2217 #define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) 2218 2219 #define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2220 2221 #if defined(USB) 2222 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_USBFSSMEN) 2223 #endif /* USB */ 2224 2225 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2226 2227 2228 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 2229 2230 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 2231 2232 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 2233 2234 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 2235 2236 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 2237 2238 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 2239 2240 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 2241 2242 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 2243 2244 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 2245 2246 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 2247 2248 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 2249 2250 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 2251 2252 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 2253 2254 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 2255 2256 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 2257 2258 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 2259 2260 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 2261 2262 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) 2263 2264 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 2265 2266 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 2267 2268 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 2269 2270 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 2271 2272 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 2273 2274 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 2275 2276 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 2277 2278 #define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) 2279 2280 #define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) 2281 2282 #if defined(USB) 2283 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_USBFSSMEN) 2284 #endif /* USB */ 2285 2286 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) 2287 2288 /** 2289 * @} 2290 */ 2291 2292 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 2293 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 2294 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2295 * power consumption. 2296 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2297 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2298 * @{ 2299 */ 2300 2301 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2302 2303 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2304 2305 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2306 2307 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2308 2309 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2310 2311 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2312 2313 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2314 2315 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2316 2317 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2318 2319 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2320 2321 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 2322 2323 2324 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 2325 2326 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 2327 2328 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 2329 2330 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 2331 2332 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 2333 2334 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 2335 2336 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 2337 2338 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 2339 2340 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 2341 2342 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 2343 2344 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 2345 2346 /** 2347 * @} 2348 */ 2349 2350 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 2351 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2352 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2353 * power consumption. 2354 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2355 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2356 * @{ 2357 */ 2358 2359 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U) 2360 2361 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U) 2362 2363 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U) 2364 2365 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) 2366 2367 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) 2368 2369 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) 2370 2371 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) 2372 2373 #define __HAL_RCC_GTZC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) != 0U) 2374 2375 2376 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U) 2377 2378 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U) 2379 2380 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U) 2381 2382 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U) 2383 2384 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U) 2385 2386 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U) 2387 2388 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == 0U) 2389 2390 #define __HAL_RCC_GTZC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZCSMEN) == 0U) 2391 2392 /** 2393 * @} 2394 */ 2395 2396 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 2397 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2398 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2399 * power consumption. 2400 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2401 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2402 * @{ 2403 */ 2404 2405 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) 2406 2407 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) 2408 2409 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) 2410 2411 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U) 2412 2413 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U) 2414 2415 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U) 2416 2417 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U) 2418 2419 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) 2420 2421 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) 2422 2423 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != 0U) 2424 2425 #if defined(AES) 2426 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) 2427 #endif /* AES */ 2428 2429 #if defined(HASH) 2430 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) 2431 #endif /* HASH */ 2432 2433 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) 2434 2435 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != 0U) 2436 2437 2438 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U) 2439 2440 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U) 2441 2442 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U) 2443 2444 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U) 2445 2446 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U) 2447 2448 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U) 2449 2450 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U) 2451 2452 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == 0U) 2453 2454 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U) 2455 2456 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == 0U) 2457 2458 #if defined(AES) 2459 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U) 2460 #endif /* AES */ 2461 2462 #if defined(HASH) 2463 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == 0U) 2464 #endif /* HASH */ 2465 2466 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U) 2467 2468 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == 0U) 2469 2470 /** 2471 * @} 2472 */ 2473 2474 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 2475 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 2476 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2477 * power consumption. 2478 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2479 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2480 * @{ 2481 */ 2482 2483 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U) 2484 2485 2486 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U) 2487 2488 /** 2489 * @} 2490 */ 2491 2492 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 2493 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 2494 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2495 * power consumption. 2496 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2497 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2498 * @{ 2499 */ 2500 2501 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) 2502 2503 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) 2504 2505 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U) 2506 2507 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U) 2508 2509 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U) 2510 2511 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U) 2512 2513 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U) 2514 2515 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) 2516 2517 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U) 2518 2519 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U) 2520 2521 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) 2522 2523 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U) 2524 2525 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U) 2526 2527 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U) 2528 2529 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) 2530 2531 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U) 2532 2533 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U) 2534 2535 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U) 2536 2537 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U) 2538 2539 #if defined(USB) 2540 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U) 2541 #endif /* USB */ 2542 2543 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U) 2544 2545 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != 0U) 2546 2547 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != 0U) 2548 2549 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U) 2550 2551 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U) 2552 2553 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) 2554 2555 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) != 0U) 2556 2557 2558 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U) 2559 2560 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U) 2561 2562 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U) 2563 2564 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U) 2565 2566 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U) 2567 2568 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U) 2569 2570 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U) 2571 2572 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U) 2573 2574 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U) 2575 2576 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U) 2577 2578 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U) 2579 2580 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U) 2581 2582 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U) 2583 2584 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U) 2585 2586 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U) 2587 2588 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U) 2589 2590 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U) 2591 2592 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U) 2593 2594 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U) 2595 2596 #if defined(USB) 2597 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U) 2598 #endif /* USB */ 2599 2600 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U) 2601 2602 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == 0U) 2603 2604 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == 0U) 2605 2606 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U) 2607 2608 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U) 2609 2610 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == 0U) 2611 2612 #define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM3SMEN) == 0U) 2613 2614 /** 2615 * @} 2616 */ 2617 2618 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 2619 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 2620 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 2621 * power consumption. 2622 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 2623 * @note By default, all peripheral clocks are enabled during SLEEP mode. 2624 * @{ 2625 */ 2626 2627 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U) 2628 2629 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) 2630 2631 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) 2632 2633 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U) 2634 2635 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) 2636 2637 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U) 2638 2639 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) 2640 2641 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) 2642 2643 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) 2644 2645 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != 0U) 2646 2647 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != 0U) 2648 2649 2650 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U) 2651 2652 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U) 2653 2654 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U) 2655 2656 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U) 2657 2658 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U) 2659 2660 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U) 2661 2662 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U) 2663 2664 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U) 2665 2666 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U) 2667 2668 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == 0U) 2669 2670 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == 0U) 2671 2672 /** 2673 * @} 2674 */ 2675 2676 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 2677 * @{ 2678 */ 2679 2680 /** @brief Macros to force or release the Backup domain reset. 2681 * @note This function resets the RTC peripheral (including the backup registers) 2682 * and the RTC clock source selection in RCC_CSR register. 2683 * @note The BKPSRAM is not affected by this reset. 2684 * @retval None 2685 */ 2686 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2687 2688 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 2689 2690 /** 2691 * @} 2692 */ 2693 2694 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 2695 * @{ 2696 */ 2697 2698 /** @brief Macros to enable or disable the RTC clock. 2699 * @note As the RTC is in the Backup domain and write access is denied to 2700 * this domain after reset, you have to enable write access using 2701 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 2702 * (to be done once after reset). 2703 * @note These macros must be used after the RTC clock source was selected. 2704 * @retval None 2705 */ 2706 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2707 2708 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 2709 2710 /** 2711 * @} 2712 */ 2713 2714 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 2715 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 2716 * It is used (enabled by hardware) as system clock source after startup 2717 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 2718 * of the HSE used directly or indirectly as system clock (if the Clock 2719 * Security System CSS is enabled). 2720 * @note HSI can not be stopped if it is used as system clock source. In this case, 2721 * you have to select another source of the system clock then stop the HSI. 2722 * @note After enabling the HSI, the application software should wait on HSIRDY 2723 * flag to be set indicating that HSI clock is stable and can be used as 2724 * system clock source. 2725 * This parameter can be: ENABLE or DISABLE. 2726 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 2727 * clock cycles. 2728 * @retval None 2729 */ 2730 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 2731 2732 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 2733 2734 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 2735 * @note The calibration is used to compensate for the variations in voltage 2736 * and temperature that influence the frequency of the internal HSI RC. 2737 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 2738 * (default is RCC_HSICALIBRATION_DEFAULT). 2739 * This parameter must be a number between 0 and 0x7F. 2740 * @retval None 2741 */ 2742 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 2743 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 2744 2745 /** 2746 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 2747 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 2748 * @note The enable of this function has not effect on the HSION bit. 2749 * This parameter can be: ENABLE or DISABLE. 2750 * @retval None 2751 */ 2752 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 2753 2754 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 2755 2756 /** 2757 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 2758 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 2759 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 2760 * speed because of the HSI startup time. 2761 * @note The enable of this function has not effect on the HSION bit. 2762 * This parameter can be: ENABLE or DISABLE. 2763 * @retval None 2764 */ 2765 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 2766 2767 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 2768 2769 /** 2770 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 2771 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 2772 * It is used (enabled by hardware) as system clock source after 2773 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 2774 * of failure of the HSE used directly or indirectly as system clock 2775 * (if the Clock Security System CSS is enabled). 2776 * @note MSI can not be stopped if it is used as system clock source. 2777 * In this case, you have to select another source of the system 2778 * clock then stop the MSI. 2779 * @note After enabling the MSI, the application software should wait on 2780 * MSIRDY flag to be set indicating that MSI clock is stable and can 2781 * be used as system clock source. 2782 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 2783 * clock cycles. 2784 * @retval None 2785 */ 2786 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 2787 2788 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 2789 2790 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 2791 * @note The calibration is used to compensate for the variations in voltage 2792 * and temperature that influence the frequency of the internal MSI RC. 2793 * Refer to the Application Note AN3300 for more details on how to 2794 * calibrate the MSI. 2795 * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value 2796 * (default is RCC_MSICALIBRATION_DEFAULT). 2797 * This parameter must be a number between 0 and 255. 2798 * @retval None 2799 */ 2800 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 2801 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) 2802 2803 /** 2804 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 2805 * @note After restart from Reset , the MSI clock is around 4 MHz. 2806 * After stop the startup clock can be MSI (at any of its possible 2807 * frequencies, the one that was used before entering stop mode) or HSI. 2808 * After Standby its frequency can be selected between 4 possible values 2809 * (1, 2, 4 or 8 MHz). 2810 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 2811 * (MSIRDY=1). 2812 * @note The MSI clock range after reset can be modified on the fly. 2813 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2814 * This parameter must be one of the following values: 2815 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz 2816 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz 2817 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz 2818 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz 2819 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2820 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2821 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2822 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2823 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2824 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2825 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2826 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2827 * @retval None 2828 */ 2829 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 2830 do { \ 2831 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 2832 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 2833 } while(0) 2834 2835 /** 2836 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 2837 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 2838 * @param __MSIRANGEVALUE__ specifies the MSI clock range. 2839 * This parameter must be one of the following values: 2840 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2841 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2842 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2843 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2844 * @retval None 2845 */ 2846 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 2847 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 2848 2849 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 2850 * @retval MSI clock range. 2851 * This parameter must be one of the following values: 2852 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz 2853 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz 2854 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz 2855 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz 2856 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 2857 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz 2858 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) 2859 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 2860 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 2861 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 2862 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 2863 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 2864 */ 2865 #define __HAL_RCC_GET_MSI_RANGE() \ 2866 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ 2867 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ 2868 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) 2869 2870 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 2871 * @note After enabling the LSI, the application software should wait on 2872 * LSIRDY flag to be set indicating that LSI clock is stable and can 2873 * be used to clock the IWDG and/or the RTC. 2874 * @note LSI can not be disabled if the IWDG is running. 2875 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 2876 * clock cycles. 2877 * @retval None 2878 */ 2879 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 2880 2881 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 2882 2883 /** 2884 * @brief Macro to configure the External High Speed oscillator (HSE). 2885 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 2886 * supported by this macro. User should request a transition to HSE Off 2887 * first and then HSE On or HSE Bypass. 2888 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 2889 * software should wait on HSERDY flag to be set indicating that HSE clock 2890 * is stable and can be used to clock the PLL and/or system clock. 2891 * @note HSE state can not be changed if it is used directly or through the 2892 * PLL as system clock. In this case, you have to select another source 2893 * of the system clock then change the HSE state (ex. disable it). 2894 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 2895 * @note This function reset the CSSON bit, so if the clock security system(CSS) 2896 * was previously enabled you have to enable it again after calling this 2897 * function. 2898 * @param __STATE__ specifies the new state of the HSE. 2899 * This parameter can be one of the following values: 2900 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 2901 * 6 HSE oscillator clock cycles. 2902 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 2903 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 2904 * @retval None 2905 */ 2906 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 2907 do { \ 2908 if((__STATE__) == RCC_HSE_ON) \ 2909 { \ 2910 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2911 } \ 2912 else if((__STATE__) == RCC_HSE_BYPASS) \ 2913 { \ 2914 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2915 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 2916 } \ 2917 else \ 2918 { \ 2919 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 2920 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 2921 } \ 2922 } while(0) 2923 2924 /** 2925 * @brief Macro to configure the External Low Speed oscillator (LSE). 2926 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 2927 * supported by this macro. User should request a transition to LSE Off 2928 * first and then LSE On or LSE Bypass. 2929 * @note As the LSE is in the Backup domain and write access is denied to 2930 * this domain after reset, you have to enable write access using 2931 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 2932 * (to be done once after reset). 2933 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 2934 * software should wait on LSERDY flag to be set indicating that LSE clock 2935 * is stable and can be used to clock the RTC. 2936 * @param __STATE__ specifies the new state of the LSE. 2937 * This parameter can be one of the following values: 2938 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 2939 * 6 LSE oscillator clock cycles. 2940 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 2941 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 2942 * @retval None 2943 */ 2944 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 2945 do { \ 2946 if((__STATE__) == RCC_LSE_ON) \ 2947 { \ 2948 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2949 } \ 2950 else if((__STATE__) == RCC_LSE_BYPASS) \ 2951 { \ 2952 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2953 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2954 } \ 2955 else \ 2956 { \ 2957 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 2958 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 2959 } \ 2960 } while(0) 2961 2962 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 2963 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 2964 * @note After enabling the HSI48, the application software should wait on HSI48RDY 2965 * flag to be set indicating that HSI48 clock is stable. 2966 * This parameter can be: ENABLE or DISABLE. 2967 * @retval None 2968 */ 2969 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2970 2971 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 2972 2973 /** @brief Macros to configure the RTC clock (RTCCLK). 2974 * @note As the RTC clock configuration bits are in the Backup domain and write 2975 * access is denied to this domain after reset, you have to enable write 2976 * access using the Power Backup Access macro before to configure 2977 * the RTC clock source (to be done once after reset). 2978 * @note Once the RTC clock is configured it cannot be changed unless the 2979 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 2980 * a Power On Reset (POR). 2981 * 2982 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 2983 * This parameter can be one of the following values: 2984 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 2985 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 2986 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 2987 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 2988 * 2989 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 2990 * work in STOP and STANDBY modes, and can be used as wakeup source. 2991 * However, when the HSE clock is used as RTC clock source, the RTC 2992 * cannot be used in STOP and STANDBY modes. 2993 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 2994 * RTC clock source). 2995 * @retval None 2996 */ 2997 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 2998 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 2999 3000 3001 /** @brief Macro to get the RTC clock source. 3002 * @retval The returned value can be one of the following: 3003 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 3004 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 3005 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 3006 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 3007 */ 3008 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 3009 3010 /** @brief Macros to enable or disable the main PLL. 3011 * @note After enabling the main PLL, the application software should wait on 3012 * PLLRDY flag to be set indicating that PLL clock is stable and can 3013 * be used as system clock source. 3014 * @note The main PLL can not be disabled if it is used as system clock source 3015 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 3016 * @retval None 3017 */ 3018 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 3019 3020 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 3021 3022 /** @brief Macro to configure the PLL clock source. 3023 * @note This function must be used only when the main PLL is disabled. 3024 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3025 * This parameter can be one of the following values: 3026 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3027 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3028 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3029 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3030 * @retval None 3031 * 3032 */ 3033 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 3034 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 3035 3036 /** @brief Macro to configure the PLL source division factor M. 3037 * @note This function must be used only when the main PLL is disabled. 3038 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3039 * This parameter must be a number between Min_Data = 1 and Max_Data = 16. 3040 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3041 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3042 * of 16 MHz to limit PLL jitter. 3043 * @retval None 3044 * 3045 */ 3046 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 3047 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) 3048 3049 /** 3050 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 3051 * @note This macro must be used only when the main PLL is disabled. 3052 * @note This macro preserves the PLL's output clocks enable state. 3053 * 3054 * @param __PLLSOURCE__ specifies the PLL entry clock source. 3055 * This parameter can be one of the following values: 3056 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 3057 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 3058 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 3059 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 3060 * 3061 * @param __PLLM__ specifies the division factor for PLL VCO input clock. 3062 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider. 3063 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 3064 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 3065 * of 16 MHz to limit PLL jitter. 3066 * 3067 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. 3068 * This parameter must be a number between 8 and 86. 3069 * @note You have to set the PLLN parameter correctly to ensure that the VCO 3070 * output frequency is between 64 and 344 MHz. 3071 * 3072 * @param __PLLP__ specifies the division factor for SAI clock. 3073 * This parameter must be a number in the range (2 to 31). 3074 * 3075 * @param __PLLQ__ specifies the division factor for USB FS, SDMMC1, RNG and FDCAN clocks. 3076 * This parameter must be in the range (2, 4, 6 or 8). 3077 * @note If the USB FS is used in your application, you have to set the 3078 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 3079 * the SDMMC1, RNG and FDCAN need a frequency lower than or equal to 48 MHz 3080 * to work correctly. 3081 * 3082 * @param __PLLR__ specifies the division factor for the main system clock. 3083 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 3084 * This parameter must be in the range (2, 4, 6 or 8). 3085 * @retval None 3086 */ 3087 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 3088 MODIFY_REG(RCC->PLLCFGR, \ 3089 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ 3090 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ 3091 ((__PLLSOURCE__) | \ 3092 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ 3093 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ 3094 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ 3095 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ 3096 ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) 3097 3098 /** @brief Macro to get the oscillator used as PLL clock source. 3099 * @retval The oscillator used as PLL clock source. The returned value can be one 3100 * of the following: 3101 * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. 3102 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source. 3103 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. 3104 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. 3105 */ 3106 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 3107 3108 /** 3109 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 3110 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 3111 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 3112 * be stopped if used as System Clock. 3113 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. 3114 * This parameter can be one or a combination of the following values: 3115 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 3116 * high-quality audio performance on SAI interface in case. 3117 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB FS(48 MHz), 3118 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 3119 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 3120 * @retval None 3121 */ 3122 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3123 3124 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3125 3126 /** 3127 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 3128 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. 3129 * This parameter can be one of the following values: 3130 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 3131 * high-quality audio performance on SAI interface in case. 3132 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB FS (48 MHz), 3133 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 3134 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 3135 * @retval SET / RESET 3136 */ 3137 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 3138 3139 /** 3140 * @brief Macro to configure the system clock source. 3141 * @param __SYSCLKSOURCE__ specifies the system clock source. 3142 * This parameter can be one of the following values: 3143 * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. 3144 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 3145 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 3146 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 3147 * @retval None 3148 */ 3149 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 3150 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 3151 3152 /** @brief Macro to get the clock source used as system clock. 3153 * @retval The clock source used as system clock. The returned value can be one 3154 * of the following: 3155 * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock. 3156 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 3157 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 3158 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. 3159 */ 3160 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 3161 3162 /** 3163 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 3164 * @note As the LSE is in the Backup domain and write access is denied to 3165 * this domain after reset, you have to enable write access using 3166 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 3167 * (to be done once after reset). 3168 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 3169 * This parameter can be one of the following values: 3170 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 3171 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 3172 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 3173 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 3174 * @retval None 3175 */ 3176 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 3177 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 3178 3179 /** 3180 * @brief Macro to configure the wake up from stop clock. 3181 * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. 3182 * This parameter can be one of the following values: 3183 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 3184 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 3185 * @retval None 3186 */ 3187 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 3188 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 3189 3190 3191 /** @brief Macro to configure the MCO clock. 3192 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 3193 * This parameter can be one of the following values: 3194 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 3195 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 3196 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 3197 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 3198 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 3199 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 3200 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 3201 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 3202 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 3203 * @param __MCODIV__ specifies the MCO clock prescaler. 3204 * This parameter can be one of the following values: 3205 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 3206 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 3207 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 3208 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 3209 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 3210 */ 3211 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 3212 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 3213 3214 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 3215 * @brief macros to manage the specified RCC Flags and interrupts. 3216 * @{ 3217 */ 3218 3219 /** @brief Enable RCC interrupt. 3220 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 3221 * This parameter can be any combination of the following values: 3222 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3223 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3224 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3225 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3226 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3227 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3228 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3229 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3230 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3231 * @retval None 3232 */ 3233 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 3234 3235 /** @brief Disable RCC interrupt. 3236 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 3237 * This parameter can be any combination of the following values: 3238 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3239 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3240 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 3241 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3242 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3243 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3244 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3245 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3246 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3247 * @retval None 3248 */ 3249 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 3250 3251 /** @brief Clear the RCC's interrupt pending bits. 3252 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3253 * This parameter can be any combination of the following values: 3254 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3255 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3256 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3257 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3258 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3259 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3260 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3261 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3262 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3263 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3264 * @retval None 3265 */ 3266 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) 3267 3268 /** @brief Check whether the RCC interrupt has occurred or not. 3269 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 3270 * This parameter can be one of the following values: 3271 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 3272 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 3273 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 3274 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 3275 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 3276 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 3277 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 3278 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt 3279 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 3280 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt 3281 * @retval The pending state of __INTERRUPT__ (TRUE or FALSE). 3282 */ 3283 #define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) 3284 3285 /** @brief Set RMVF bit to clear the reset flags. 3286 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 3287 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 3288 * @retval None 3289 */ 3290 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) 3291 3292 /** @brief Check whether the selected RCC flag is set or not. 3293 * @param __FLAG__ specifies the flag to check. 3294 * This parameter can be one of the following values: 3295 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 3296 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 3297 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 3298 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 3299 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready 3300 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready 3301 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready 3302 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 3303 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 3304 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 3305 * @arg @ref RCC_FLAG_BORRST BOR reset 3306 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 3307 * @arg @ref RCC_FLAG_PINRST Pin reset 3308 * @arg @ref RCC_FLAG_SFTRST Software reset 3309 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 3310 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 3311 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 3312 * @retval The new state of __FLAG__ (TRUE or FALSE). 3313 */ 3314 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ 3315 ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ 3316 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ 3317 ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ 3318 (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ 3319 ? 1U : 0U) 3320 3321 /** 3322 * @} 3323 */ 3324 3325 /** 3326 * @} 3327 */ 3328 3329 /* Private constants ---------------------------------------------------------*/ 3330 /** @defgroup RCC_Private_Constants RCC Private Constants 3331 * @{ 3332 */ 3333 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 3334 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 3335 #define MSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 3336 3337 /* Defines used for Flags */ 3338 #define CR_REG_INDEX 1U 3339 #define BDCR_REG_INDEX 2U 3340 #define CSR_REG_INDEX 3U 3341 #define CRRCR_REG_INDEX 4U 3342 3343 #define RCC_FLAG_MASK 0x0000001FU 3344 3345 /* Defines for attributes */ 3346 #define RCC_ATTR_SEC_MASK 0x100U 3347 #define RCC_ATTR_PRIV_MASK 0x200U 3348 /** 3349 * @} 3350 */ 3351 3352 /* Private macros ------------------------------------------------------------*/ 3353 /** @addtogroup RCC_Private_Macros 3354 * @{ 3355 */ 3356 3357 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 3358 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 3359 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 3360 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 3361 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 3362 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 3363 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 3364 3365 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 3366 ((__HSE__) == RCC_HSE_BYPASS)) 3367 3368 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || \ 3369 ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ 3370 ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY)) 3371 3372 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 3373 3374 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ 3375 <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) 3376 3377 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 3378 3379 #define IS_RCC_LSIDIV(__DIV__) (((__DIV__) == RCC_LSI_DIV1) || ((__DIV__) == RCC_LSI_DIV128)) 3380 3381 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 3382 3383 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 3384 3385 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 3386 3387 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 3388 ((__PLL__) == RCC_PLL_ON)) 3389 3390 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 3391 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 3392 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 3393 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 3394 3395 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) 3396 3397 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 3398 3399 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 3400 3401 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3402 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3403 3404 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 3405 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 3406 3407 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 3408 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 3409 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 3410 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 3411 3412 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) ((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) && \ 3413 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK)) == 0U)) 3414 3415 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 3416 ((__RANGE__) == RCC_MSIRANGE_1) || \ 3417 ((__RANGE__) == RCC_MSIRANGE_2) || \ 3418 ((__RANGE__) == RCC_MSIRANGE_3) || \ 3419 ((__RANGE__) == RCC_MSIRANGE_4) || \ 3420 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3421 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3422 ((__RANGE__) == RCC_MSIRANGE_7) || \ 3423 ((__RANGE__) == RCC_MSIRANGE_8) || \ 3424 ((__RANGE__) == RCC_MSIRANGE_9) || \ 3425 ((__RANGE__) == RCC_MSIRANGE_10) || \ 3426 ((__RANGE__) == RCC_MSIRANGE_11)) 3427 3428 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 3429 ((__RANGE__) == RCC_MSIRANGE_5) || \ 3430 ((__RANGE__) == RCC_MSIRANGE_6) || \ 3431 ((__RANGE__) == RCC_MSIRANGE_7)) 3432 3433 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 3434 3435 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 3436 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 3437 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 3438 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 3439 3440 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 3441 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 3442 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 3443 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 3444 ((__HCLK__) == RCC_SYSCLK_DIV512)) 3445 3446 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 3447 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 3448 ((__PCLK__) == RCC_HCLK_DIV16)) 3449 3450 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 3451 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 3452 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 3453 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 3454 3455 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 3456 3457 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 3458 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 3459 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 3460 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 3461 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 3462 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 3463 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 3464 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 3465 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 3466 3467 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 3468 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 3469 ((__DIV__) == RCC_MCODIV_16)) 3470 3471 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 3472 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 3473 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 3474 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 3475 3476 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 3477 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 3478 3479 #define IS_RCC_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & RCC_HSI) == RCC_HSI) || \ 3480 (((__ITEM__) & RCC_HSE) == RCC_HSE) || \ 3481 (((__ITEM__) & RCC_MSI) == RCC_MSI) || \ 3482 (((__ITEM__) & RCC_LSI) == RCC_LSI) || \ 3483 (((__ITEM__) & RCC_LSE) == RCC_LSE) || \ 3484 (((__ITEM__) & RCC_HSI48) == RCC_HSI48) || \ 3485 (((__ITEM__) & RCC_SYSCLK) == RCC_SYSCLK) || \ 3486 (((__ITEM__) & RCC_PRESCALER) == RCC_PRESCALER) || \ 3487 (((__ITEM__) & RCC_PLL) == RCC_PLL) || \ 3488 (((__ITEM__) & RCC_PLLSAI1) == RCC_PLLSAI1) || \ 3489 (((__ITEM__) & RCC_PLLSAI2) == RCC_PLLSAI2) || \ 3490 (((__ITEM__) & RCC_CLK48M) == RCC_CLK48M) || \ 3491 (((__ITEM__) & RCC_RMVF) == RCC_RMVF) || \ 3492 (((__ITEM__) & ~(RCC_ALL)) == 0U)) 3493 3494 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 3495 3496 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & RCC_SEC) == RCC_SEC) || \ 3497 (((__ATTRIBUTES__) & RCC_NSEC) == RCC_NSEC) || \ 3498 (((__ATTRIBUTES__) & RCC_PRIV) == RCC_PRIV) || \ 3499 (((__ATTRIBUTES__) & RCC_NPRIV) == RCC_NPRIV)) && \ 3500 (((__ATTRIBUTES__) & ~(RCC_SEC|RCC_NSEC|RCC_PRIV|RCC_NPRIV)) == 0U)) 3501 3502 #else 3503 3504 #define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & RCC_PRIV) == RCC_PRIV) || \ 3505 (((__ATTRIBUTES__) & RCC_NPRIV) == RCC_NPRIV)) && \ 3506 (((__ATTRIBUTES__) & ~(RCC_PRIV|RCC_NPRIV)) == 0U)) 3507 3508 #endif /* __ARM_FEATURE_CMSE */ 3509 3510 /** 3511 * @} 3512 */ 3513 3514 /* Include RCC HAL Extended module */ 3515 #include "stm32l5xx_hal_rcc_ex.h" 3516 3517 /* Exported functions --------------------------------------------------------*/ 3518 /** @addtogroup RCC_Exported_Functions 3519 * @{ 3520 */ 3521 3522 3523 /** @addtogroup RCC_Exported_Functions_Group1 3524 * @{ 3525 */ 3526 3527 /* Initialization and de-initialization functions ******************************/ 3528 HAL_StatusTypeDef HAL_RCC_DeInit(void); 3529 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3530 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 3531 3532 /** 3533 * @} 3534 */ 3535 3536 /** @addtogroup RCC_Exported_Functions_Group2 3537 * @{ 3538 */ 3539 3540 /* Peripheral Control functions ************************************************/ 3541 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 3542 void HAL_RCC_EnableCSS(void); 3543 uint32_t HAL_RCC_GetSysClockFreq(void); 3544 uint32_t HAL_RCC_GetHCLKFreq(void); 3545 uint32_t HAL_RCC_GetPCLK1Freq(void); 3546 uint32_t HAL_RCC_GetPCLK2Freq(void); 3547 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 3548 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 3549 /* CSS NMI IRQ handler */ 3550 void HAL_RCC_NMI_IRQHandler(void); 3551 /* User Callbacks in non blocking mode (IT mode) */ 3552 void HAL_RCC_CSSCallback(void); 3553 3554 /** 3555 * @} 3556 */ 3557 3558 /** @addtogroup RCC_Exported_Functions_Group3 3559 * @{ 3560 */ 3561 3562 /* Attributes management functions ******************************************/ 3563 void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); 3564 HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 3565 3566 /** 3567 * @} 3568 */ 3569 3570 /** 3571 * @} 3572 */ 3573 3574 /** 3575 * @} 3576 */ 3577 3578 /** 3579 * @} 3580 */ 3581 3582 #ifdef __cplusplus 3583 } 3584 #endif 3585 3586 #endif /* STM32L5xx_HAL_RCC_H */ 3587 3588 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3589
