1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_OSPI_H 22 #define STM32L5xx_HAL_OSPI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 32 33 /** @addtogroup STM32L5xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup OSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup OSPI_Exported_Types OSPI Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief OSPI Init structure definition 48 */ 49 typedef struct 50 { 51 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 52 indicating that data are available in reception or free place 53 is available in transmission. 54 This parameter can be a value between 1 and 32 */ 55 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 56 quad mode on two different devices to increase the throughput. 57 This parameter can be a value of @ref OSPI_DualQuad */ 58 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 59 This parameter can be a value of @ref OSPI_MemoryType */ 60 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 61 it corresponds to the number of address bits required to access 62 the external device. 63 This parameter can be a value between 1 and 32 */ 64 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 65 must remain high between commands. 66 This parameter can be a value between 1 and 8 */ 67 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 68 This parameter can be a value of @ref OSPI_FreeRunningClock */ 69 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 70 This parameter can be a value of @ref OSPI_ClockMode */ 71 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 72 This parameter can be a value of @ref OSPI_WrapSize */ 73 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 74 the external clock based on the AHB clock. 75 This parameter can be a value between 1 and 256 */ 76 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 77 to take in account external signal delays. 78 This parameter can be a value of @ref OSPI_SampleShifting */ 79 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 80 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 81 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 82 defines the boundary of bytes to release the chip select. 83 This parameter can be a value between 0 and 31 */ 84 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 85 by the delay block. 86 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 87 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 88 Refresh+1 clock cycles. 89 This parameter can be a value between 0 and 0xFFFFFFFF */ 90 }OSPI_InitTypeDef; 91 92 /** 93 * @brief HAL OSPI Handle Structure definition 94 */ 95 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 96 typedef struct __OSPI_HandleTypeDef 97 #else 98 typedef struct 99 #endif 100 { 101 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 102 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 103 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 104 __IO uint32_t XferSize; /*!< Number of data to transfer */ 105 __IO uint32_t XferCount; /*!< Counter of data transferred */ 106 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 107 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 108 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 109 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 110 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 111 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 112 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 113 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 114 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 115 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 116 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 117 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 118 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 119 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 120 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 121 122 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 123 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 124 #endif 125 }OSPI_HandleTypeDef; 126 127 /** 128 * @brief HAL OSPI Regular Command Structure definition 129 */ 130 typedef struct 131 { 132 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 133 to the registers for the write operation (these registers are only 134 used for memory-mapped mode). 135 This parameter can be a value of @ref OSPI_OperationType */ 136 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 137 applies only if Dualquad is disabled in the initialization structure). 138 This parameter can be a value of @ref OSPI_FlashID */ 139 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 140 This parameter can be a value between 0 and 0xFFFFFFFF */ 141 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 142 This parameter can be a value of @ref OSPI_InstructionMode */ 143 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 144 This parameter can be a value of @ref OSPI_InstructionSize */ 145 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 146 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 147 uint32_t Address; /*!< It contains the address to be sent to the device. 148 This parameter can be a value between 0 and 0xFFFFFFFF */ 149 uint32_t AddressMode; /*!< It indicates the mode of the address. 150 This parameter can be a value of @ref OSPI_AddressMode */ 151 uint32_t AddressSize; /*!< It indicates the size of the address. 152 This parameter can be a value of @ref OSPI_AddressSize */ 153 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 154 This parameter can be a value of @ref OSPI_AddressDtrMode */ 155 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 156 This parameter can be a value between 0 and 0xFFFFFFFF */ 157 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 158 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 159 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 160 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 161 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 162 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 163 uint32_t DataMode; /*!< It indicates the mode of the data. 164 This parameter can be a value of @ref OSPI_DataMode */ 165 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 166 This field is only used for indirect mode. 167 This parameter can be a value between 1 and 0xFFFFFFFF */ 168 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 169 This parameter can be a value of @ref OSPI_DataDtrMode */ 170 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 171 This parameter can be a value between 0 and 31 */ 172 uint32_t DQSMode; /*!< It enables or not the data strobe management. 173 This parameter can be a value of @ref OSPI_DQSMode */ 174 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 175 This parameter can be a value of @ref OSPI_SIOOMode */ 176 }OSPI_RegularCmdTypeDef; 177 178 /** 179 * @brief HAL OSPI Hyperbus Configuration Structure definition 180 */ 181 typedef struct 182 { 183 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 184 This parameter can be a value between 0 and 255 */ 185 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 186 This parameter can be a value between 0 and 255 */ 187 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 188 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 189 uint32_t LatencyMode; /*!< It configures the latency mode. 190 This parameter can be a value of @ref OSPI_LatencyMode */ 191 }OSPI_HyperbusCfgTypeDef; 192 193 /** 194 * @brief HAL OSPI Hyperbus Command Structure definition 195 */ 196 typedef struct 197 { 198 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 199 This parameter can be a value of @ref OSPI_AddressSpace */ 200 uint32_t Address; /*!< It contains the address to be sent tot he device. 201 This parameter can be a value between 0 and 0xFFFFFFFF */ 202 uint32_t AddressSize; /*!< It indicates the size of the address. 203 This parameter can be a value of @ref OSPI_AddressSize */ 204 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 205 This field is only used for indirect mode. 206 This parameter can be a value between 1 and 0xFFFFFFFF 207 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 208 uint32_t DQSMode; /*!< It enables or not the data strobe management. 209 This parameter can be a value of @ref OSPI_DQSMode */ 210 }OSPI_HyperbusCmdTypeDef; 211 212 /** 213 * @brief HAL OSPI Auto Polling mode configuration structure definition 214 */ 215 typedef struct 216 { 217 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 218 This parameter can be any value between 0 and 0xFFFFFFFF */ 219 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 220 This parameter can be any value between 0 and 0xFFFFFFFF */ 221 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 222 This parameter can be a value of @ref OSPI_MatchMode */ 223 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 224 This parameter can be a value of @ref OSPI_AutomaticStop */ 225 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 226 This parameter can be any value between 0 and 0xFFFF */ 227 }OSPI_AutoPollingTypeDef; 228 229 /** 230 * @brief HAL OSPI Memory Mapped mode configuration structure definition 231 */ 232 typedef struct 233 { 234 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 235 This parameter can be a value of @ref OSPI_TimeOutActivation */ 236 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 237 This parameter can be any value between 0 and 0xFFFF */ 238 }OSPI_MemoryMappedTypeDef; 239 240 241 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 242 /** 243 * @brief HAL OSPI Callback ID enumeration definition 244 */ 245 typedef enum 246 { 247 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 248 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 249 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 250 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 251 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 252 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 253 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 254 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 255 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 256 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 257 258 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 259 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 260 }HAL_OSPI_CallbackIDTypeDef; 261 262 /** 263 * @brief HAL OSPI Callback pointer definition 264 */ 265 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 266 #endif 267 /** 268 * @} 269 */ 270 271 /* Exported constants --------------------------------------------------------*/ 272 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 273 * @{ 274 */ 275 276 /** @defgroup OSPI_State OSPI State 277 * @{ 278 */ 279 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 280 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 281 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 282 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 283 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 284 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 285 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 286 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 287 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 288 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 289 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 290 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 291 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup OSPI_ErrorCode OSPI Error Code 297 * @{ 298 */ 299 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 300 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 301 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 302 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 303 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 304 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 305 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 306 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 307 #endif 308 /** 309 * @} 310 */ 311 312 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 313 * @{ 314 */ 315 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 316 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup OSPI_MemoryType OSPI Memory Type 322 * @{ 323 */ 324 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 325 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 326 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 327 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 328 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 334 * @{ 335 */ 336 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 337 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup OSPI_ClockMode OSPI Clock Mode 343 * @{ 344 */ 345 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 346 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 352 * @{ 353 */ 354 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 355 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 356 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 357 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 358 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 364 * @{ 365 */ 366 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 367 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 373 * @{ 374 */ 375 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 376 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 377 /** 378 * @} 379 */ 380 381 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 382 * @{ 383 */ 384 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 385 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 386 /** 387 * @} 388 */ 389 390 /** @defgroup OSPI_OperationType OSPI Operation Type 391 * @{ 392 */ 393 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 394 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 395 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 396 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 397 /** 398 * @} 399 */ 400 401 /** @defgroup OSPI_FlashID OSPI Flash Id 402 * @{ 403 */ 404 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 405 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 411 * @{ 412 */ 413 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 414 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 415 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 416 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 417 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 418 /** 419 * @} 420 */ 421 422 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 423 * @{ 424 */ 425 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 426 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 427 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 428 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 429 /** 430 * @} 431 */ 432 433 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 434 * @{ 435 */ 436 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 437 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 438 /** 439 * @} 440 */ 441 442 /** @defgroup OSPI_AddressMode OSPI Address Mode 443 * @{ 444 */ 445 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 446 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 447 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 448 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 449 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 450 /** 451 * @} 452 */ 453 454 /** @defgroup OSPI_AddressSize OSPI Address Size 455 * @{ 456 */ 457 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 458 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 459 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 460 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 466 * @{ 467 */ 468 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 469 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 470 /** 471 * @} 472 */ 473 474 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 475 * @{ 476 */ 477 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 478 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 479 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 480 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 481 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 487 * @{ 488 */ 489 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 490 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 491 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 492 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 493 /** 494 * @} 495 */ 496 497 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 498 * @{ 499 */ 500 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 501 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 502 /** 503 * @} 504 */ 505 506 /** @defgroup OSPI_DataMode OSPI Data Mode 507 * @{ 508 */ 509 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 510 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 511 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 512 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 513 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 514 /** 515 * @} 516 */ 517 518 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 519 * @{ 520 */ 521 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 522 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 523 /** 524 * @} 525 */ 526 527 /** @defgroup OSPI_DQSMode OSPI DQS Mode 528 * @{ 529 */ 530 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 531 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 537 * @{ 538 */ 539 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 540 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 546 * @{ 547 */ 548 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 549 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 550 /** 551 * @} 552 */ 553 554 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 555 * @{ 556 */ 557 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 558 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 564 * @{ 565 */ 566 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 567 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup OSPI_MatchMode OSPI Match Mode 573 * @{ 574 */ 575 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 576 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 577 /** 578 * @} 579 */ 580 581 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 582 * @{ 583 */ 584 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 585 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 586 /** 587 * @} 588 */ 589 590 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 591 * @{ 592 */ 593 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 594 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup OSPI_Flags OSPI Flags 600 * @{ 601 */ 602 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 603 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 604 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 605 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 606 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 607 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup OSPI_Interrupts OSPI Interrupts 613 * @{ 614 */ 615 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 616 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 617 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 618 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 619 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 625 * @{ 626 */ 627 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 628 /** 629 * @} 630 */ 631 632 /** 633 * @} 634 */ 635 636 /* Exported macros -----------------------------------------------------------*/ 637 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 638 * @{ 639 */ 640 /** @brief Reset OSPI handle state. 641 * @param __HANDLE__ specifies the OSPI Handle. 642 * @retval None 643 */ 644 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 645 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 646 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 647 (__HANDLE__)->MspInitCallback = NULL; \ 648 (__HANDLE__)->MspDeInitCallback = NULL; \ 649 } while(0) 650 #else 651 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 652 #endif 653 654 /** @brief Enable the OSPI peripheral. 655 * @param __HANDLE__ specifies the OSPI Handle. 656 * @retval None 657 */ 658 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 659 660 /** @brief Disable the OSPI peripheral. 661 * @param __HANDLE__ specifies the OSPI Handle. 662 * @retval None 663 */ 664 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 665 666 /** @brief Enable the specified OSPI interrupt. 667 * @param __HANDLE__ specifies the OSPI Handle. 668 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 669 * This parameter can be one of the following values: 670 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 671 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 672 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 673 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 674 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 675 * @retval None 676 */ 677 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 678 679 680 /** @brief Disable the specified OSPI interrupt. 681 * @param __HANDLE__ specifies the OSPI Handle. 682 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 683 * This parameter can be one of the following values: 684 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 685 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 686 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 687 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 688 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 689 * @retval None 690 */ 691 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 692 693 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 694 * @param __HANDLE__ specifies the OSPI Handle. 695 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 696 * This parameter can be one of the following values: 697 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 698 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 699 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 700 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 701 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 702 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 703 */ 704 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 705 706 /** 707 * @brief Check whether the selected OSPI flag is set or not. 708 * @param __HANDLE__ specifies the OSPI Handle. 709 * @param __FLAG__ specifies the OSPI flag to check. 710 * This parameter can be one of the following values: 711 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 712 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 713 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 714 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 715 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 716 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 717 * @retval None 718 */ 719 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 720 721 /** @brief Clears the specified OSPI's flag status. 722 * @param __HANDLE__ specifies the OSPI Handle. 723 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 724 * This parameter can be one of the following values: 725 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 726 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 727 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 728 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 729 * @retval None 730 */ 731 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 732 733 /** 734 * @} 735 */ 736 737 /* Exported functions --------------------------------------------------------*/ 738 /** @addtogroup OSPI_Exported_Functions 739 * @{ 740 */ 741 742 /* Initialization/de-initialization functions ********************************/ 743 /** @addtogroup OSPI_Exported_Functions_Group1 744 * @{ 745 */ 746 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 747 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 748 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 749 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 750 751 /** 752 * @} 753 */ 754 755 /* IO operation functions *****************************************************/ 756 /** @addtogroup OSPI_Exported_Functions_Group2 757 * @{ 758 */ 759 /* OSPI IRQ handler function */ 760 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 761 762 /* OSPI command configuration functions */ 763 HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 764 HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 765 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 766 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 767 768 /* OSPI indirect mode functions */ 769 HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 770 HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 771 HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 772 HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 773 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 774 HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 775 776 /* OSPI status flag polling mode functions */ 777 HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 778 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 779 780 /* OSPI memory-mapped mode functions */ 781 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 782 783 /* Callback functions in non-blocking modes ***********************************/ 784 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 785 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 786 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 787 788 /* OSPI indirect mode functions */ 789 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 790 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 791 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 792 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 793 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 794 795 /* OSPI status flag polling mode functions */ 796 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 797 798 /* OSPI memory-mapped mode functions */ 799 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 800 801 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 802 /* OSPI callback registering/unregistering */ 803 HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); 804 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 805 #endif 806 /** 807 * @} 808 */ 809 810 /* Peripheral Control and State functions ************************************/ 811 /** @addtogroup OSPI_Exported_Functions_Group3 812 * @{ 813 */ 814 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 815 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 816 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 817 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 818 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 819 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 820 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 821 822 /** 823 * @} 824 */ 825 826 /** 827 * @} 828 */ 829 /* End of exported functions -------------------------------------------------*/ 830 831 /* Private macros ------------------------------------------------------------*/ 832 /** 833 @cond 0 834 */ 835 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 836 837 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 838 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 839 840 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 841 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 842 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 843 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 844 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 845 846 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 847 848 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 849 850 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 851 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 852 853 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 854 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 855 856 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 857 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 858 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 859 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 860 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 861 862 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 863 864 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 865 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 866 867 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 868 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 869 870 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 871 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 872 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ 873 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) 874 875 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 876 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 877 878 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 879 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 880 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 881 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 882 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 883 884 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 885 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 886 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 887 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 888 889 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 890 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 891 892 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 893 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 894 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 895 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 896 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 897 898 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 899 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 900 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 901 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 902 903 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 904 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 905 906 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 907 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 908 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 909 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 910 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 911 912 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 913 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 914 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 915 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 916 917 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 918 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 919 920 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 921 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 922 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 923 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 924 ((MODE) == HAL_OSPI_DATA_8_LINES)) 925 926 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 927 928 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 929 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 930 931 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 932 933 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 934 ((MODE) == HAL_OSPI_DQS_ENABLE)) 935 936 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 937 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 938 939 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 940 941 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 942 943 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 944 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 945 946 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 947 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 948 949 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 950 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 951 952 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 953 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 954 955 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 956 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 957 958 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 959 960 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 961 962 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 963 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 964 965 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 966 967 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 968 969 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 970 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 971 /** 972 @endcond 973 */ 974 975 /* End of private macros -----------------------------------------------------*/ 976 977 /** 978 * @} 979 */ 980 981 /** 982 * @} 983 */ 984 985 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 986 987 #ifdef __cplusplus 988 } 989 #endif 990 991 #endif /* STM32L5xx_HAL_OSPI_H */ 992 993 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 994
