1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32l5xx_hal.h"
324
325 /** @addtogroup STM32L5xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 /* Macro to get remaining data to transfer on DMA side */
405 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
406
407 /* Private variables ---------------------------------------------------------*/
408 /* Private function prototypes -----------------------------------------------*/
409
410 /** @defgroup I2C_Private_Functions I2C Private Functions
411 * @{
412 */
413 /* Private functions to handle DMA transfer */
414 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
415 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
416 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
417 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
418 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
419 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
420
421 /* Private functions to handle IT transfer */
422 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
423 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
424 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
425 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
426 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
427 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
428 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
429
430 /* Private functions to handle IT transfer */
431 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
432 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
433 uint32_t Tickstart);
434 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
435 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
436 uint32_t Tickstart);
437
438 /* Private functions for I2C transfer IRQ handler */
439 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
440 uint32_t ITSources);
441 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
442 uint32_t ITSources);
443 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
444 uint32_t ITSources);
445 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
446 uint32_t ITSources);
447 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
448 uint32_t ITSources);
449 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
450 uint32_t ITSources);
451
452 /* Private functions to handle flags during polling transfer */
453 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
454 uint32_t Timeout, uint32_t Tickstart);
455 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
456 uint32_t Tickstart);
457 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
458 uint32_t Tickstart);
459 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
460 uint32_t Tickstart);
461 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
462 uint32_t Tickstart);
463
464 /* Private functions to centralize the enable/disable of Interrupts */
465 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
466 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
467
468 /* Private function to treat different error callback */
469 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
470
471 /* Private function to flush TXDR register */
472 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
473
474 /* Private function to handle start, restart or stop a transfer */
475 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
476 uint32_t Request);
477
478 /* Private function to Convert Specific options */
479 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
480 /**
481 * @}
482 */
483
484 /* Exported functions --------------------------------------------------------*/
485
486 /** @defgroup I2C_Exported_Functions I2C Exported Functions
487 * @{
488 */
489
490 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
491 * @brief Initialization and Configuration functions
492 *
493 @verbatim
494 ===============================================================================
495 ##### Initialization and de-initialization functions #####
496 ===============================================================================
497 [..] This subsection provides a set of functions allowing to initialize and
498 deinitialize the I2Cx peripheral:
499
500 (+) User must Implement HAL_I2C_MspInit() function in which he configures
501 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
502
503 (+) Call the function HAL_I2C_Init() to configure the selected device with
504 the selected configuration:
505 (++) Clock Timing
506 (++) Own Address 1
507 (++) Addressing mode (Master, Slave)
508 (++) Dual Addressing mode
509 (++) Own Address 2
510 (++) Own Address 2 Mask
511 (++) General call mode
512 (++) Nostretch mode
513
514 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
515 of the selected I2Cx peripheral.
516
517 @endverbatim
518 * @{
519 */
520
521 /**
522 * @brief Initializes the I2C according to the specified parameters
523 * in the I2C_InitTypeDef and initialize the associated handle.
524 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
525 * the configuration information for the specified I2C.
526 * @retval HAL status
527 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)528 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
529 {
530 /* Check the I2C handle allocation */
531 if (hi2c == NULL)
532 {
533 return HAL_ERROR;
534 }
535
536 /* Check the parameters */
537 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
538 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
539 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
540 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
541 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
542 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
543 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
544 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
545
546 if (hi2c->State == HAL_I2C_STATE_RESET)
547 {
548 /* Allocate lock resource and initialize it */
549 hi2c->Lock = HAL_UNLOCKED;
550
551 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
552 /* Init the I2C Callback settings */
553 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
554 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
555 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
556 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
557 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
558 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
559 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
560 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
561 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
562 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
563
564 if (hi2c->MspInitCallback == NULL)
565 {
566 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
567 }
568
569 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
570 hi2c->MspInitCallback(hi2c);
571 #else
572 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
573 HAL_I2C_MspInit(hi2c);
574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
575 }
576
577 hi2c->State = HAL_I2C_STATE_BUSY;
578
579 /* Disable the selected I2C peripheral */
580 __HAL_I2C_DISABLE(hi2c);
581
582 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
583 /* Configure I2Cx: Frequency range */
584 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
585
586 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
587 /* Disable Own Address1 before set the Own Address1 configuration */
588 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
589
590 /* Configure I2Cx: Own Address1 and ack own address1 mode */
591 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
592 {
593 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
594 }
595 else /* I2C_ADDRESSINGMODE_10BIT */
596 {
597 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
598 }
599
600 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
601 /* Configure I2Cx: Addressing Master mode */
602 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
603 {
604 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
605 }
606 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
607 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
608
609 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
610 /* Disable Own Address2 before set the Own Address2 configuration */
611 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
612
613 /* Configure I2Cx: Dual mode and Own Address2 */
614 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
615 (hi2c->Init.OwnAddress2Masks << 8));
616
617 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
618 /* Configure I2Cx: Generalcall and NoStretch mode */
619 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
620
621 /* Enable the selected I2C peripheral */
622 __HAL_I2C_ENABLE(hi2c);
623
624 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
625 hi2c->State = HAL_I2C_STATE_READY;
626 hi2c->PreviousState = I2C_STATE_NONE;
627 hi2c->Mode = HAL_I2C_MODE_NONE;
628
629 return HAL_OK;
630 }
631
632 /**
633 * @brief DeInitialize the I2C peripheral.
634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
635 * the configuration information for the specified I2C.
636 * @retval HAL status
637 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)638 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
639 {
640 /* Check the I2C handle allocation */
641 if (hi2c == NULL)
642 {
643 return HAL_ERROR;
644 }
645
646 /* Check the parameters */
647 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
648
649 hi2c->State = HAL_I2C_STATE_BUSY;
650
651 /* Disable the I2C Peripheral Clock */
652 __HAL_I2C_DISABLE(hi2c);
653
654 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
655 if (hi2c->MspDeInitCallback == NULL)
656 {
657 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
658 }
659
660 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
661 hi2c->MspDeInitCallback(hi2c);
662 #else
663 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
664 HAL_I2C_MspDeInit(hi2c);
665 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
666
667 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
668 hi2c->State = HAL_I2C_STATE_RESET;
669 hi2c->PreviousState = I2C_STATE_NONE;
670 hi2c->Mode = HAL_I2C_MODE_NONE;
671
672 /* Release Lock */
673 __HAL_UNLOCK(hi2c);
674
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Initialize the I2C MSP.
680 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
681 * the configuration information for the specified I2C.
682 * @retval None
683 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)684 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
685 {
686 /* Prevent unused argument(s) compilation warning */
687 UNUSED(hi2c);
688
689 /* NOTE : This function should not be modified, when the callback is needed,
690 the HAL_I2C_MspInit could be implemented in the user file
691 */
692 }
693
694 /**
695 * @brief DeInitialize the I2C MSP.
696 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
697 * the configuration information for the specified I2C.
698 * @retval None
699 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)700 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
701 {
702 /* Prevent unused argument(s) compilation warning */
703 UNUSED(hi2c);
704
705 /* NOTE : This function should not be modified, when the callback is needed,
706 the HAL_I2C_MspDeInit could be implemented in the user file
707 */
708 }
709
710 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
711 /**
712 * @brief Register a User I2C Callback
713 * To be used instead of the weak predefined callback
714 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
715 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
716 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
717 * the configuration information for the specified I2C.
718 * @param CallbackID ID of the callback to be registered
719 * This parameter can be one of the following values:
720 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
721 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
722 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
723 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
724 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
725 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
726 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
727 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
728 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
729 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
730 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
731 * @param pCallback pointer to the Callback function
732 * @retval HAL status
733 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)734 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
735 pI2C_CallbackTypeDef pCallback)
736 {
737 HAL_StatusTypeDef status = HAL_OK;
738
739 if (pCallback == NULL)
740 {
741 /* Update the error code */
742 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
743
744 return HAL_ERROR;
745 }
746
747 if (HAL_I2C_STATE_READY == hi2c->State)
748 {
749 switch (CallbackID)
750 {
751 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
752 hi2c->MasterTxCpltCallback = pCallback;
753 break;
754
755 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
756 hi2c->MasterRxCpltCallback = pCallback;
757 break;
758
759 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
760 hi2c->SlaveTxCpltCallback = pCallback;
761 break;
762
763 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
764 hi2c->SlaveRxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
768 hi2c->ListenCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
772 hi2c->MemTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
776 hi2c->MemRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_ERROR_CB_ID :
780 hi2c->ErrorCallback = pCallback;
781 break;
782
783 case HAL_I2C_ABORT_CB_ID :
784 hi2c->AbortCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MSPINIT_CB_ID :
788 hi2c->MspInitCallback = pCallback;
789 break;
790
791 case HAL_I2C_MSPDEINIT_CB_ID :
792 hi2c->MspDeInitCallback = pCallback;
793 break;
794
795 default :
796 /* Update the error code */
797 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
798
799 /* Return error status */
800 status = HAL_ERROR;
801 break;
802 }
803 }
804 else if (HAL_I2C_STATE_RESET == hi2c->State)
805 {
806 switch (CallbackID)
807 {
808 case HAL_I2C_MSPINIT_CB_ID :
809 hi2c->MspInitCallback = pCallback;
810 break;
811
812 case HAL_I2C_MSPDEINIT_CB_ID :
813 hi2c->MspDeInitCallback = pCallback;
814 break;
815
816 default :
817 /* Update the error code */
818 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
819
820 /* Return error status */
821 status = HAL_ERROR;
822 break;
823 }
824 }
825 else
826 {
827 /* Update the error code */
828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
829
830 /* Return error status */
831 status = HAL_ERROR;
832 }
833
834 return status;
835 }
836
837 /**
838 * @brief Unregister an I2C Callback
839 * I2C callback is redirected to the weak predefined callback
840 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
841 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
842 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
843 * the configuration information for the specified I2C.
844 * @param CallbackID ID of the callback to be unregistered
845 * This parameter can be one of the following values:
846 * This parameter can be one of the following values:
847 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
848 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
849 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
850 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
851 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
852 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
853 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
854 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
855 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
856 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
857 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
858 * @retval HAL status
859 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)860 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
861 {
862 HAL_StatusTypeDef status = HAL_OK;
863
864 if (HAL_I2C_STATE_READY == hi2c->State)
865 {
866 switch (CallbackID)
867 {
868 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
869 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
870 break;
871
872 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
873 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
874 break;
875
876 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
877 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
878 break;
879
880 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
881 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
882 break;
883
884 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
885 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
886 break;
887
888 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
889 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
890 break;
891
892 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
893 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
894 break;
895
896 case HAL_I2C_ERROR_CB_ID :
897 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
898 break;
899
900 case HAL_I2C_ABORT_CB_ID :
901 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
902 break;
903
904 case HAL_I2C_MSPINIT_CB_ID :
905 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
906 break;
907
908 case HAL_I2C_MSPDEINIT_CB_ID :
909 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
910 break;
911
912 default :
913 /* Update the error code */
914 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
915
916 /* Return error status */
917 status = HAL_ERROR;
918 break;
919 }
920 }
921 else if (HAL_I2C_STATE_RESET == hi2c->State)
922 {
923 switch (CallbackID)
924 {
925 case HAL_I2C_MSPINIT_CB_ID :
926 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
927 break;
928
929 case HAL_I2C_MSPDEINIT_CB_ID :
930 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
931 break;
932
933 default :
934 /* Update the error code */
935 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
936
937 /* Return error status */
938 status = HAL_ERROR;
939 break;
940 }
941 }
942 else
943 {
944 /* Update the error code */
945 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
946
947 /* Return error status */
948 status = HAL_ERROR;
949 }
950
951 return status;
952 }
953
954 /**
955 * @brief Register the Slave Address Match I2C Callback
956 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
958 * the configuration information for the specified I2C.
959 * @param pCallback pointer to the Address Match Callback function
960 * @retval HAL status
961 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)962 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
963 {
964 HAL_StatusTypeDef status = HAL_OK;
965
966 if (pCallback == NULL)
967 {
968 /* Update the error code */
969 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
970
971 return HAL_ERROR;
972 }
973
974 if (HAL_I2C_STATE_READY == hi2c->State)
975 {
976 hi2c->AddrCallback = pCallback;
977 }
978 else
979 {
980 /* Update the error code */
981 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
982
983 /* Return error status */
984 status = HAL_ERROR;
985 }
986
987 return status;
988 }
989
990 /**
991 * @brief UnRegister the Slave Address Match I2C Callback
992 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
993 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
994 * the configuration information for the specified I2C.
995 * @retval HAL status
996 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)997 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
998 {
999 HAL_StatusTypeDef status = HAL_OK;
1000
1001 if (HAL_I2C_STATE_READY == hi2c->State)
1002 {
1003 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1004 }
1005 else
1006 {
1007 /* Update the error code */
1008 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1009
1010 /* Return error status */
1011 status = HAL_ERROR;
1012 }
1013
1014 return status;
1015 }
1016
1017 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1018
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1024 * @brief Data transfers functions
1025 *
1026 @verbatim
1027 ===============================================================================
1028 ##### IO operation functions #####
1029 ===============================================================================
1030 [..]
1031 This subsection provides a set of functions allowing to manage the I2C data
1032 transfers.
1033
1034 (#) There are two modes of transfer:
1035 (++) Blocking mode : The communication is performed in the polling mode.
1036 The status of all data processing is returned by the same function
1037 after finishing transfer.
1038 (++) No-Blocking mode : The communication is performed using Interrupts
1039 or DMA. These functions return the status of the transfer startup.
1040 The end of the data processing will be indicated through the
1041 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1042 using DMA mode.
1043
1044 (#) Blocking mode functions are :
1045 (++) HAL_I2C_Master_Transmit()
1046 (++) HAL_I2C_Master_Receive()
1047 (++) HAL_I2C_Slave_Transmit()
1048 (++) HAL_I2C_Slave_Receive()
1049 (++) HAL_I2C_Mem_Write()
1050 (++) HAL_I2C_Mem_Read()
1051 (++) HAL_I2C_IsDeviceReady()
1052
1053 (#) No-Blocking mode functions with Interrupt are :
1054 (++) HAL_I2C_Master_Transmit_IT()
1055 (++) HAL_I2C_Master_Receive_IT()
1056 (++) HAL_I2C_Slave_Transmit_IT()
1057 (++) HAL_I2C_Slave_Receive_IT()
1058 (++) HAL_I2C_Mem_Write_IT()
1059 (++) HAL_I2C_Mem_Read_IT()
1060 (++) HAL_I2C_Master_Seq_Transmit_IT()
1061 (++) HAL_I2C_Master_Seq_Receive_IT()
1062 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1063 (++) HAL_I2C_Slave_Seq_Receive_IT()
1064 (++) HAL_I2C_EnableListen_IT()
1065 (++) HAL_I2C_DisableListen_IT()
1066 (++) HAL_I2C_Master_Abort_IT()
1067
1068 (#) No-Blocking mode functions with DMA are :
1069 (++) HAL_I2C_Master_Transmit_DMA()
1070 (++) HAL_I2C_Master_Receive_DMA()
1071 (++) HAL_I2C_Slave_Transmit_DMA()
1072 (++) HAL_I2C_Slave_Receive_DMA()
1073 (++) HAL_I2C_Mem_Write_DMA()
1074 (++) HAL_I2C_Mem_Read_DMA()
1075 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1076 (++) HAL_I2C_Master_Seq_Receive_DMA()
1077 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1078 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1079
1080 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1081 (++) HAL_I2C_MasterTxCpltCallback()
1082 (++) HAL_I2C_MasterRxCpltCallback()
1083 (++) HAL_I2C_SlaveTxCpltCallback()
1084 (++) HAL_I2C_SlaveRxCpltCallback()
1085 (++) HAL_I2C_MemTxCpltCallback()
1086 (++) HAL_I2C_MemRxCpltCallback()
1087 (++) HAL_I2C_AddrCallback()
1088 (++) HAL_I2C_ListenCpltCallback()
1089 (++) HAL_I2C_ErrorCallback()
1090 (++) HAL_I2C_AbortCpltCallback()
1091
1092 @endverbatim
1093 * @{
1094 */
1095
1096 /**
1097 * @brief Transmits in master mode an amount of data in blocking mode.
1098 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1099 * the configuration information for the specified I2C.
1100 * @param DevAddress Target device address: The device 7 bits address value
1101 * in datasheet must be shifted to the left before calling the interface
1102 * @param pData Pointer to data buffer
1103 * @param Size Amount of data to be sent
1104 * @param Timeout Timeout duration
1105 * @retval HAL status
1106 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1107 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1108 uint16_t Size, uint32_t Timeout)
1109 {
1110 uint32_t tickstart;
1111
1112 if (hi2c->State == HAL_I2C_STATE_READY)
1113 {
1114 /* Process Locked */
1115 __HAL_LOCK(hi2c);
1116
1117 /* Init tickstart for timeout management*/
1118 tickstart = HAL_GetTick();
1119
1120 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1121 {
1122 return HAL_ERROR;
1123 }
1124
1125 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1126 hi2c->Mode = HAL_I2C_MODE_MASTER;
1127 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1128
1129 /* Prepare transfer parameters */
1130 hi2c->pBuffPtr = pData;
1131 hi2c->XferCount = Size;
1132 hi2c->XferISR = NULL;
1133
1134 /* Send Slave Address */
1135 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1136 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1137 {
1138 hi2c->XferSize = MAX_NBYTE_SIZE;
1139 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1140 I2C_GENERATE_START_WRITE);
1141 }
1142 else
1143 {
1144 hi2c->XferSize = hi2c->XferCount;
1145 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1146 I2C_GENERATE_START_WRITE);
1147 }
1148
1149 while (hi2c->XferCount > 0U)
1150 {
1151 /* Wait until TXIS flag is set */
1152 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1153 {
1154 return HAL_ERROR;
1155 }
1156 /* Write data to TXDR */
1157 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1158
1159 /* Increment Buffer pointer */
1160 hi2c->pBuffPtr++;
1161
1162 hi2c->XferCount--;
1163 hi2c->XferSize--;
1164
1165 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1166 {
1167 /* Wait until TCR flag is set */
1168 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1169 {
1170 return HAL_ERROR;
1171 }
1172
1173 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1174 {
1175 hi2c->XferSize = MAX_NBYTE_SIZE;
1176 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1177 I2C_NO_STARTSTOP);
1178 }
1179 else
1180 {
1181 hi2c->XferSize = hi2c->XferCount;
1182 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1183 I2C_NO_STARTSTOP);
1184 }
1185 }
1186 }
1187
1188 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1189 /* Wait until STOPF flag is set */
1190 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1191 {
1192 return HAL_ERROR;
1193 }
1194
1195 /* Clear STOP Flag */
1196 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1197
1198 /* Clear Configuration Register 2 */
1199 I2C_RESET_CR2(hi2c);
1200
1201 hi2c->State = HAL_I2C_STATE_READY;
1202 hi2c->Mode = HAL_I2C_MODE_NONE;
1203
1204 /* Process Unlocked */
1205 __HAL_UNLOCK(hi2c);
1206
1207 return HAL_OK;
1208 }
1209 else
1210 {
1211 return HAL_BUSY;
1212 }
1213 }
1214
1215 /**
1216 * @brief Receives in master mode an amount of data in blocking mode.
1217 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1218 * the configuration information for the specified I2C.
1219 * @param DevAddress Target device address: The device 7 bits address value
1220 * in datasheet must be shifted to the left before calling the interface
1221 * @param pData Pointer to data buffer
1222 * @param Size Amount of data to be sent
1223 * @param Timeout Timeout duration
1224 * @retval HAL status
1225 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1226 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1227 uint16_t Size, uint32_t Timeout)
1228 {
1229 uint32_t tickstart;
1230
1231 if (hi2c->State == HAL_I2C_STATE_READY)
1232 {
1233 /* Process Locked */
1234 __HAL_LOCK(hi2c);
1235
1236 /* Init tickstart for timeout management*/
1237 tickstart = HAL_GetTick();
1238
1239 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1240 {
1241 return HAL_ERROR;
1242 }
1243
1244 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1245 hi2c->Mode = HAL_I2C_MODE_MASTER;
1246 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1247
1248 /* Prepare transfer parameters */
1249 hi2c->pBuffPtr = pData;
1250 hi2c->XferCount = Size;
1251 hi2c->XferISR = NULL;
1252
1253 /* Send Slave Address */
1254 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1255 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1256 {
1257 hi2c->XferSize = MAX_NBYTE_SIZE;
1258 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1259 I2C_GENERATE_START_READ);
1260 }
1261 else
1262 {
1263 hi2c->XferSize = hi2c->XferCount;
1264 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1265 I2C_GENERATE_START_READ);
1266 }
1267
1268 while (hi2c->XferCount > 0U)
1269 {
1270 /* Wait until RXNE flag is set */
1271 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1272 {
1273 return HAL_ERROR;
1274 }
1275
1276 /* Read data from RXDR */
1277 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1278
1279 /* Increment Buffer pointer */
1280 hi2c->pBuffPtr++;
1281
1282 hi2c->XferSize--;
1283 hi2c->XferCount--;
1284
1285 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1286 {
1287 /* Wait until TCR flag is set */
1288 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1289 {
1290 return HAL_ERROR;
1291 }
1292
1293 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1294 {
1295 hi2c->XferSize = MAX_NBYTE_SIZE;
1296 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1297 I2C_NO_STARTSTOP);
1298 }
1299 else
1300 {
1301 hi2c->XferSize = hi2c->XferCount;
1302 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1303 I2C_NO_STARTSTOP);
1304 }
1305 }
1306 }
1307
1308 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1309 /* Wait until STOPF flag is set */
1310 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1311 {
1312 return HAL_ERROR;
1313 }
1314
1315 /* Clear STOP Flag */
1316 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1317
1318 /* Clear Configuration Register 2 */
1319 I2C_RESET_CR2(hi2c);
1320
1321 hi2c->State = HAL_I2C_STATE_READY;
1322 hi2c->Mode = HAL_I2C_MODE_NONE;
1323
1324 /* Process Unlocked */
1325 __HAL_UNLOCK(hi2c);
1326
1327 return HAL_OK;
1328 }
1329 else
1330 {
1331 return HAL_BUSY;
1332 }
1333 }
1334
1335 /**
1336 * @brief Transmits in slave mode an amount of data in blocking mode.
1337 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1338 * the configuration information for the specified I2C.
1339 * @param pData Pointer to data buffer
1340 * @param Size Amount of data to be sent
1341 * @param Timeout Timeout duration
1342 * @retval HAL status
1343 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1344 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1345 uint32_t Timeout)
1346 {
1347 uint32_t tickstart;
1348
1349 if (hi2c->State == HAL_I2C_STATE_READY)
1350 {
1351 if ((pData == NULL) || (Size == 0U))
1352 {
1353 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1354 return HAL_ERROR;
1355 }
1356 /* Process Locked */
1357 __HAL_LOCK(hi2c);
1358
1359 /* Init tickstart for timeout management*/
1360 tickstart = HAL_GetTick();
1361
1362 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1363 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1364 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1365
1366 /* Prepare transfer parameters */
1367 hi2c->pBuffPtr = pData;
1368 hi2c->XferCount = Size;
1369 hi2c->XferISR = NULL;
1370
1371 /* Enable Address Acknowledge */
1372 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1373
1374 /* Wait until ADDR flag is set */
1375 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1376 {
1377 /* Disable Address Acknowledge */
1378 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1379 return HAL_ERROR;
1380 }
1381
1382 /* Preload TX data if no stretch enable */
1383 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1384 {
1385 /* Preload TX register */
1386 /* Write data to TXDR */
1387 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1388
1389 /* Increment Buffer pointer */
1390 hi2c->pBuffPtr++;
1391
1392 hi2c->XferCount--;
1393 }
1394
1395 /* Clear ADDR flag */
1396 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1397
1398 /* If 10bit addressing mode is selected */
1399 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1400 {
1401 /* Wait until ADDR flag is set */
1402 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1403 {
1404 /* Disable Address Acknowledge */
1405 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1406 return HAL_ERROR;
1407 }
1408
1409 /* Clear ADDR flag */
1410 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1411 }
1412
1413 /* Wait until DIR flag is set Transmitter mode */
1414 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1415 {
1416 /* Disable Address Acknowledge */
1417 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1418 return HAL_ERROR;
1419 }
1420
1421 while (hi2c->XferCount > 0U)
1422 {
1423 /* Wait until TXIS flag is set */
1424 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1425 {
1426 /* Disable Address Acknowledge */
1427 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1428 return HAL_ERROR;
1429 }
1430
1431 /* Write data to TXDR */
1432 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1433
1434 /* Increment Buffer pointer */
1435 hi2c->pBuffPtr++;
1436
1437 hi2c->XferCount--;
1438 }
1439
1440 /* Wait until AF flag is set */
1441 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1442 {
1443 /* Disable Address Acknowledge */
1444 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1445 return HAL_ERROR;
1446 }
1447
1448 /* Flush TX register */
1449 I2C_Flush_TXDR(hi2c);
1450
1451 /* Clear AF flag */
1452 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1453
1454 /* Wait until STOP flag is set */
1455 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1456 {
1457 /* Disable Address Acknowledge */
1458 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1459
1460 return HAL_ERROR;
1461 }
1462
1463 /* Clear STOP flag */
1464 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1465
1466 /* Wait until BUSY flag is reset */
1467 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1468 {
1469 /* Disable Address Acknowledge */
1470 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1471 return HAL_ERROR;
1472 }
1473
1474 /* Disable Address Acknowledge */
1475 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1476
1477 hi2c->State = HAL_I2C_STATE_READY;
1478 hi2c->Mode = HAL_I2C_MODE_NONE;
1479
1480 /* Process Unlocked */
1481 __HAL_UNLOCK(hi2c);
1482
1483 return HAL_OK;
1484 }
1485 else
1486 {
1487 return HAL_BUSY;
1488 }
1489 }
1490
1491 /**
1492 * @brief Receive in slave mode an amount of data in blocking mode
1493 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1494 * the configuration information for the specified I2C.
1495 * @param pData Pointer to data buffer
1496 * @param Size Amount of data to be sent
1497 * @param Timeout Timeout duration
1498 * @retval HAL status
1499 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1500 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1501 uint32_t Timeout)
1502 {
1503 uint32_t tickstart;
1504
1505 if (hi2c->State == HAL_I2C_STATE_READY)
1506 {
1507 if ((pData == NULL) || (Size == 0U))
1508 {
1509 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1510 return HAL_ERROR;
1511 }
1512 /* Process Locked */
1513 __HAL_LOCK(hi2c);
1514
1515 /* Init tickstart for timeout management*/
1516 tickstart = HAL_GetTick();
1517
1518 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1519 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1520 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1521
1522 /* Prepare transfer parameters */
1523 hi2c->pBuffPtr = pData;
1524 hi2c->XferCount = Size;
1525 hi2c->XferSize = hi2c->XferCount;
1526 hi2c->XferISR = NULL;
1527
1528 /* Enable Address Acknowledge */
1529 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1530
1531 /* Wait until ADDR flag is set */
1532 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1533 {
1534 /* Disable Address Acknowledge */
1535 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1536 return HAL_ERROR;
1537 }
1538
1539 /* Clear ADDR flag */
1540 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1541
1542 /* Wait until DIR flag is reset Receiver mode */
1543 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1544 {
1545 /* Disable Address Acknowledge */
1546 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1547 return HAL_ERROR;
1548 }
1549
1550 while (hi2c->XferCount > 0U)
1551 {
1552 /* Wait until RXNE flag is set */
1553 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1554 {
1555 /* Disable Address Acknowledge */
1556 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1557
1558 /* Store Last receive data if any */
1559 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1560 {
1561 /* Read data from RXDR */
1562 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1563
1564 /* Increment Buffer pointer */
1565 hi2c->pBuffPtr++;
1566
1567 hi2c->XferCount--;
1568 hi2c->XferSize--;
1569 }
1570
1571 return HAL_ERROR;
1572 }
1573
1574 /* Read data from RXDR */
1575 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1576
1577 /* Increment Buffer pointer */
1578 hi2c->pBuffPtr++;
1579
1580 hi2c->XferCount--;
1581 hi2c->XferSize--;
1582 }
1583
1584 /* Wait until STOP flag is set */
1585 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1586 {
1587 /* Disable Address Acknowledge */
1588 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1589 return HAL_ERROR;
1590 }
1591
1592 /* Clear STOP flag */
1593 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1594
1595 /* Wait until BUSY flag is reset */
1596 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1597 {
1598 /* Disable Address Acknowledge */
1599 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1600 return HAL_ERROR;
1601 }
1602
1603 /* Disable Address Acknowledge */
1604 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1605
1606 hi2c->State = HAL_I2C_STATE_READY;
1607 hi2c->Mode = HAL_I2C_MODE_NONE;
1608
1609 /* Process Unlocked */
1610 __HAL_UNLOCK(hi2c);
1611
1612 return HAL_OK;
1613 }
1614 else
1615 {
1616 return HAL_BUSY;
1617 }
1618 }
1619
1620 /**
1621 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1622 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1623 * the configuration information for the specified I2C.
1624 * @param DevAddress Target device address: The device 7 bits address value
1625 * in datasheet must be shifted to the left before calling the interface
1626 * @param pData Pointer to data buffer
1627 * @param Size Amount of data to be sent
1628 * @retval HAL status
1629 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1630 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1631 uint16_t Size)
1632 {
1633 uint32_t xfermode;
1634
1635 if (hi2c->State == HAL_I2C_STATE_READY)
1636 {
1637 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1638 {
1639 return HAL_BUSY;
1640 }
1641
1642 /* Process Locked */
1643 __HAL_LOCK(hi2c);
1644
1645 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1646 hi2c->Mode = HAL_I2C_MODE_MASTER;
1647 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1648
1649 /* Prepare transfer parameters */
1650 hi2c->pBuffPtr = pData;
1651 hi2c->XferCount = Size;
1652 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1653 hi2c->XferISR = I2C_Master_ISR_IT;
1654
1655 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1656 {
1657 hi2c->XferSize = MAX_NBYTE_SIZE;
1658 xfermode = I2C_RELOAD_MODE;
1659 }
1660 else
1661 {
1662 hi2c->XferSize = hi2c->XferCount;
1663 xfermode = I2C_AUTOEND_MODE;
1664 }
1665
1666 /* Send Slave Address */
1667 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1668 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1669
1670 /* Process Unlocked */
1671 __HAL_UNLOCK(hi2c);
1672
1673 /* Note : The I2C interrupts must be enabled after unlocking current process
1674 to avoid the risk of I2C interrupt handle execution before current
1675 process unlock */
1676
1677 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1678 /* possible to enable all of these */
1679 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1680 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1681 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1682
1683 return HAL_OK;
1684 }
1685 else
1686 {
1687 return HAL_BUSY;
1688 }
1689 }
1690
1691 /**
1692 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1693 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1694 * the configuration information for the specified I2C.
1695 * @param DevAddress Target device address: The device 7 bits address value
1696 * in datasheet must be shifted to the left before calling the interface
1697 * @param pData Pointer to data buffer
1698 * @param Size Amount of data to be sent
1699 * @retval HAL status
1700 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1701 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1702 uint16_t Size)
1703 {
1704 uint32_t xfermode;
1705
1706 if (hi2c->State == HAL_I2C_STATE_READY)
1707 {
1708 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1709 {
1710 return HAL_BUSY;
1711 }
1712
1713 /* Process Locked */
1714 __HAL_LOCK(hi2c);
1715
1716 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1717 hi2c->Mode = HAL_I2C_MODE_MASTER;
1718 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1719
1720 /* Prepare transfer parameters */
1721 hi2c->pBuffPtr = pData;
1722 hi2c->XferCount = Size;
1723 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1724 hi2c->XferISR = I2C_Master_ISR_IT;
1725
1726 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1727 {
1728 hi2c->XferSize = MAX_NBYTE_SIZE;
1729 xfermode = I2C_RELOAD_MODE;
1730 }
1731 else
1732 {
1733 hi2c->XferSize = hi2c->XferCount;
1734 xfermode = I2C_AUTOEND_MODE;
1735 }
1736
1737 /* Send Slave Address */
1738 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1739 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1740
1741 /* Process Unlocked */
1742 __HAL_UNLOCK(hi2c);
1743
1744 /* Note : The I2C interrupts must be enabled after unlocking current process
1745 to avoid the risk of I2C interrupt handle execution before current
1746 process unlock */
1747
1748 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1749 /* possible to enable all of these */
1750 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1751 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1752 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1753
1754 return HAL_OK;
1755 }
1756 else
1757 {
1758 return HAL_BUSY;
1759 }
1760 }
1761
1762 /**
1763 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1764 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1765 * the configuration information for the specified I2C.
1766 * @param pData Pointer to data buffer
1767 * @param Size Amount of data to be sent
1768 * @retval HAL status
1769 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1770 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1771 {
1772 if (hi2c->State == HAL_I2C_STATE_READY)
1773 {
1774 /* Process Locked */
1775 __HAL_LOCK(hi2c);
1776
1777 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1778 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1779 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1780
1781 /* Enable Address Acknowledge */
1782 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1783
1784 /* Prepare transfer parameters */
1785 hi2c->pBuffPtr = pData;
1786 hi2c->XferCount = Size;
1787 hi2c->XferSize = hi2c->XferCount;
1788 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1789 hi2c->XferISR = I2C_Slave_ISR_IT;
1790
1791 /* Preload TX data if no stretch enable */
1792 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1793 {
1794 /* Preload TX register */
1795 /* Write data to TXDR */
1796 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1797
1798 /* Increment Buffer pointer */
1799 hi2c->pBuffPtr++;
1800
1801 hi2c->XferCount--;
1802 hi2c->XferSize--;
1803 }
1804
1805 /* Process Unlocked */
1806 __HAL_UNLOCK(hi2c);
1807
1808 /* Note : The I2C interrupts must be enabled after unlocking current process
1809 to avoid the risk of I2C interrupt handle execution before current
1810 process unlock */
1811
1812 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1813 /* possible to enable all of these */
1814 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1815 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1816 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1817
1818 return HAL_OK;
1819 }
1820 else
1821 {
1822 return HAL_BUSY;
1823 }
1824 }
1825
1826 /**
1827 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1829 * the configuration information for the specified I2C.
1830 * @param pData Pointer to data buffer
1831 * @param Size Amount of data to be sent
1832 * @retval HAL status
1833 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1834 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1835 {
1836 if (hi2c->State == HAL_I2C_STATE_READY)
1837 {
1838 /* Process Locked */
1839 __HAL_LOCK(hi2c);
1840
1841 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1842 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1843 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1844
1845 /* Enable Address Acknowledge */
1846 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1847
1848 /* Prepare transfer parameters */
1849 hi2c->pBuffPtr = pData;
1850 hi2c->XferCount = Size;
1851 hi2c->XferSize = hi2c->XferCount;
1852 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1853 hi2c->XferISR = I2C_Slave_ISR_IT;
1854
1855 /* Process Unlocked */
1856 __HAL_UNLOCK(hi2c);
1857
1858 /* Note : The I2C interrupts must be enabled after unlocking current process
1859 to avoid the risk of I2C interrupt handle execution before current
1860 process unlock */
1861
1862 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1863 /* possible to enable all of these */
1864 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1865 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1866 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1867
1868 return HAL_OK;
1869 }
1870 else
1871 {
1872 return HAL_BUSY;
1873 }
1874 }
1875
1876 /**
1877 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1878 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1879 * the configuration information for the specified I2C.
1880 * @param DevAddress Target device address: The device 7 bits address value
1881 * in datasheet must be shifted to the left before calling the interface
1882 * @param pData Pointer to data buffer
1883 * @param Size Amount of data to be sent
1884 * @retval HAL status
1885 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1886 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1887 uint16_t Size)
1888 {
1889 uint32_t xfermode;
1890 HAL_StatusTypeDef dmaxferstatus;
1891
1892 if (hi2c->State == HAL_I2C_STATE_READY)
1893 {
1894 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1895 {
1896 return HAL_BUSY;
1897 }
1898
1899 /* Process Locked */
1900 __HAL_LOCK(hi2c);
1901
1902 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1903 hi2c->Mode = HAL_I2C_MODE_MASTER;
1904 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1905
1906 /* Prepare transfer parameters */
1907 hi2c->pBuffPtr = pData;
1908 hi2c->XferCount = Size;
1909 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1910 hi2c->XferISR = I2C_Master_ISR_DMA;
1911
1912 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1913 {
1914 hi2c->XferSize = MAX_NBYTE_SIZE;
1915 xfermode = I2C_RELOAD_MODE;
1916 }
1917 else
1918 {
1919 hi2c->XferSize = hi2c->XferCount;
1920 xfermode = I2C_AUTOEND_MODE;
1921 }
1922
1923 if (hi2c->XferSize > 0U)
1924 {
1925 if (hi2c->hdmatx != NULL)
1926 {
1927 /* Set the I2C DMA transfer complete callback */
1928 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1929
1930 /* Set the DMA error callback */
1931 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1932
1933 /* Set the unused DMA callbacks to NULL */
1934 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1935 hi2c->hdmatx->XferAbortCallback = NULL;
1936
1937 /* Enable the DMA channel */
1938 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1939 hi2c->XferSize);
1940 }
1941 else
1942 {
1943 /* Update I2C state */
1944 hi2c->State = HAL_I2C_STATE_READY;
1945 hi2c->Mode = HAL_I2C_MODE_NONE;
1946
1947 /* Update I2C error code */
1948 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1949
1950 /* Process Unlocked */
1951 __HAL_UNLOCK(hi2c);
1952
1953 return HAL_ERROR;
1954 }
1955
1956 if (dmaxferstatus == HAL_OK)
1957 {
1958 /* Send Slave Address */
1959 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1960 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1961
1962 /* Update XferCount value */
1963 hi2c->XferCount -= hi2c->XferSize;
1964
1965 /* Process Unlocked */
1966 __HAL_UNLOCK(hi2c);
1967
1968 /* Note : The I2C interrupts must be enabled after unlocking current process
1969 to avoid the risk of I2C interrupt handle execution before current
1970 process unlock */
1971 /* Enable ERR and NACK interrupts */
1972 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1973
1974 /* Enable DMA Request */
1975 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1976 }
1977 else
1978 {
1979 /* Update I2C state */
1980 hi2c->State = HAL_I2C_STATE_READY;
1981 hi2c->Mode = HAL_I2C_MODE_NONE;
1982
1983 /* Update I2C error code */
1984 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
1985
1986 /* Process Unlocked */
1987 __HAL_UNLOCK(hi2c);
1988
1989 return HAL_ERROR;
1990 }
1991 }
1992 else
1993 {
1994 /* Update Transfer ISR function pointer */
1995 hi2c->XferISR = I2C_Master_ISR_IT;
1996
1997 /* Send Slave Address */
1998 /* Set NBYTES to write and generate START condition */
1999 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2000 I2C_GENERATE_START_WRITE);
2001
2002 /* Process Unlocked */
2003 __HAL_UNLOCK(hi2c);
2004
2005 /* Note : The I2C interrupts must be enabled after unlocking current process
2006 to avoid the risk of I2C interrupt handle execution before current
2007 process unlock */
2008 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2009 /* possible to enable all of these */
2010 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2011 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2012 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2013 }
2014
2015 return HAL_OK;
2016 }
2017 else
2018 {
2019 return HAL_BUSY;
2020 }
2021 }
2022
2023 /**
2024 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2025 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2026 * the configuration information for the specified I2C.
2027 * @param DevAddress Target device address: The device 7 bits address value
2028 * in datasheet must be shifted to the left before calling the interface
2029 * @param pData Pointer to data buffer
2030 * @param Size Amount of data to be sent
2031 * @retval HAL status
2032 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2033 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2034 uint16_t Size)
2035 {
2036 uint32_t xfermode;
2037 HAL_StatusTypeDef dmaxferstatus;
2038
2039 if (hi2c->State == HAL_I2C_STATE_READY)
2040 {
2041 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2042 {
2043 return HAL_BUSY;
2044 }
2045
2046 /* Process Locked */
2047 __HAL_LOCK(hi2c);
2048
2049 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2050 hi2c->Mode = HAL_I2C_MODE_MASTER;
2051 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2052
2053 /* Prepare transfer parameters */
2054 hi2c->pBuffPtr = pData;
2055 hi2c->XferCount = Size;
2056 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2057 hi2c->XferISR = I2C_Master_ISR_DMA;
2058
2059 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2060 {
2061 hi2c->XferSize = MAX_NBYTE_SIZE;
2062 xfermode = I2C_RELOAD_MODE;
2063 }
2064 else
2065 {
2066 hi2c->XferSize = hi2c->XferCount;
2067 xfermode = I2C_AUTOEND_MODE;
2068 }
2069
2070 if (hi2c->XferSize > 0U)
2071 {
2072 if (hi2c->hdmarx != NULL)
2073 {
2074 /* Set the I2C DMA transfer complete callback */
2075 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2076
2077 /* Set the DMA error callback */
2078 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2079
2080 /* Set the unused DMA callbacks to NULL */
2081 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2082 hi2c->hdmarx->XferAbortCallback = NULL;
2083
2084 /* Enable the DMA channel */
2085 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2086 hi2c->XferSize);
2087 }
2088 else
2089 {
2090 /* Update I2C state */
2091 hi2c->State = HAL_I2C_STATE_READY;
2092 hi2c->Mode = HAL_I2C_MODE_NONE;
2093
2094 /* Update I2C error code */
2095 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2096
2097 /* Process Unlocked */
2098 __HAL_UNLOCK(hi2c);
2099
2100 return HAL_ERROR;
2101 }
2102
2103 if (dmaxferstatus == HAL_OK)
2104 {
2105 /* Send Slave Address */
2106 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2107 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2108
2109 /* Update XferCount value */
2110 hi2c->XferCount -= hi2c->XferSize;
2111
2112 /* Process Unlocked */
2113 __HAL_UNLOCK(hi2c);
2114
2115 /* Note : The I2C interrupts must be enabled after unlocking current process
2116 to avoid the risk of I2C interrupt handle execution before current
2117 process unlock */
2118 /* Enable ERR and NACK interrupts */
2119 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2120
2121 /* Enable DMA Request */
2122 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2123 }
2124 else
2125 {
2126 /* Update I2C state */
2127 hi2c->State = HAL_I2C_STATE_READY;
2128 hi2c->Mode = HAL_I2C_MODE_NONE;
2129
2130 /* Update I2C error code */
2131 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2132
2133 /* Process Unlocked */
2134 __HAL_UNLOCK(hi2c);
2135
2136 return HAL_ERROR;
2137 }
2138 }
2139 else
2140 {
2141 /* Update Transfer ISR function pointer */
2142 hi2c->XferISR = I2C_Master_ISR_IT;
2143
2144 /* Send Slave Address */
2145 /* Set NBYTES to read and generate START condition */
2146 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2147 I2C_GENERATE_START_READ);
2148
2149 /* Process Unlocked */
2150 __HAL_UNLOCK(hi2c);
2151
2152 /* Note : The I2C interrupts must be enabled after unlocking current process
2153 to avoid the risk of I2C interrupt handle execution before current
2154 process unlock */
2155 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2156 /* possible to enable all of these */
2157 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2158 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2159 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2160 }
2161
2162 return HAL_OK;
2163 }
2164 else
2165 {
2166 return HAL_BUSY;
2167 }
2168 }
2169
2170 /**
2171 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2172 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2173 * the configuration information for the specified I2C.
2174 * @param pData Pointer to data buffer
2175 * @param Size Amount of data to be sent
2176 * @retval HAL status
2177 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2178 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2179 {
2180 HAL_StatusTypeDef dmaxferstatus;
2181
2182 if (hi2c->State == HAL_I2C_STATE_READY)
2183 {
2184 if ((pData == NULL) || (Size == 0U))
2185 {
2186 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2187 return HAL_ERROR;
2188 }
2189 /* Process Locked */
2190 __HAL_LOCK(hi2c);
2191
2192 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2193 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2194 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2195
2196 /* Prepare transfer parameters */
2197 hi2c->pBuffPtr = pData;
2198 hi2c->XferCount = Size;
2199 hi2c->XferSize = hi2c->XferCount;
2200 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2201 hi2c->XferISR = I2C_Slave_ISR_DMA;
2202
2203 /* Preload TX data if no stretch enable */
2204 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2205 {
2206 /* Preload TX register */
2207 /* Write data to TXDR */
2208 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2209
2210 /* Increment Buffer pointer */
2211 hi2c->pBuffPtr++;
2212
2213 hi2c->XferCount--;
2214 hi2c->XferSize--;
2215 }
2216
2217 if (hi2c->XferCount != 0U)
2218 {
2219 if (hi2c->hdmatx != NULL)
2220 {
2221 /* Set the I2C DMA transfer complete callback */
2222 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2223
2224 /* Set the DMA error callback */
2225 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2226
2227 /* Set the unused DMA callbacks to NULL */
2228 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2229 hi2c->hdmatx->XferAbortCallback = NULL;
2230
2231 /* Enable the DMA channel */
2232 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2233 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2234 hi2c->XferSize);
2235 }
2236 else
2237 {
2238 /* Update I2C state */
2239 hi2c->State = HAL_I2C_STATE_LISTEN;
2240 hi2c->Mode = HAL_I2C_MODE_NONE;
2241
2242 /* Update I2C error code */
2243 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2244
2245 /* Process Unlocked */
2246 __HAL_UNLOCK(hi2c);
2247
2248 return HAL_ERROR;
2249 }
2250
2251 if (dmaxferstatus == HAL_OK)
2252 {
2253 /* Enable Address Acknowledge */
2254 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2255
2256 /* Process Unlocked */
2257 __HAL_UNLOCK(hi2c);
2258
2259 /* Note : The I2C interrupts must be enabled after unlocking current process
2260 to avoid the risk of I2C interrupt handle execution before current
2261 process unlock */
2262 /* Enable ERR, STOP, NACK, ADDR interrupts */
2263 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2264
2265 /* Enable DMA Request */
2266 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2267 }
2268 else
2269 {
2270 /* Update I2C state */
2271 hi2c->State = HAL_I2C_STATE_LISTEN;
2272 hi2c->Mode = HAL_I2C_MODE_NONE;
2273
2274 /* Update I2C error code */
2275 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2276
2277 /* Process Unlocked */
2278 __HAL_UNLOCK(hi2c);
2279
2280 return HAL_ERROR;
2281 }
2282 }
2283 else
2284 {
2285 /* Enable Address Acknowledge */
2286 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2287
2288 /* Process Unlocked */
2289 __HAL_UNLOCK(hi2c);
2290
2291 /* Note : The I2C interrupts must be enabled after unlocking current process
2292 to avoid the risk of I2C interrupt handle execution before current
2293 process unlock */
2294 /* Enable ERR, STOP, NACK, ADDR interrupts */
2295 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2296 }
2297
2298 return HAL_OK;
2299 }
2300 else
2301 {
2302 return HAL_BUSY;
2303 }
2304 }
2305
2306 /**
2307 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2308 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2309 * the configuration information for the specified I2C.
2310 * @param pData Pointer to data buffer
2311 * @param Size Amount of data to be sent
2312 * @retval HAL status
2313 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2314 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2315 {
2316 HAL_StatusTypeDef dmaxferstatus;
2317
2318 if (hi2c->State == HAL_I2C_STATE_READY)
2319 {
2320 if ((pData == NULL) || (Size == 0U))
2321 {
2322 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2323 return HAL_ERROR;
2324 }
2325 /* Process Locked */
2326 __HAL_LOCK(hi2c);
2327
2328 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2329 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2330 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2331
2332 /* Prepare transfer parameters */
2333 hi2c->pBuffPtr = pData;
2334 hi2c->XferCount = Size;
2335 hi2c->XferSize = hi2c->XferCount;
2336 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2337 hi2c->XferISR = I2C_Slave_ISR_DMA;
2338
2339 if (hi2c->hdmarx != NULL)
2340 {
2341 /* Set the I2C DMA transfer complete callback */
2342 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2343
2344 /* Set the DMA error callback */
2345 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2346
2347 /* Set the unused DMA callbacks to NULL */
2348 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2349 hi2c->hdmarx->XferAbortCallback = NULL;
2350
2351 /* Enable the DMA channel */
2352 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2353 hi2c->XferSize);
2354 }
2355 else
2356 {
2357 /* Update I2C state */
2358 hi2c->State = HAL_I2C_STATE_LISTEN;
2359 hi2c->Mode = HAL_I2C_MODE_NONE;
2360
2361 /* Update I2C error code */
2362 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2363
2364 /* Process Unlocked */
2365 __HAL_UNLOCK(hi2c);
2366
2367 return HAL_ERROR;
2368 }
2369
2370 if (dmaxferstatus == HAL_OK)
2371 {
2372 /* Enable Address Acknowledge */
2373 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2374
2375 /* Process Unlocked */
2376 __HAL_UNLOCK(hi2c);
2377
2378 /* Note : The I2C interrupts must be enabled after unlocking current process
2379 to avoid the risk of I2C interrupt handle execution before current
2380 process unlock */
2381 /* Enable ERR, STOP, NACK, ADDR interrupts */
2382 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2383
2384 /* Enable DMA Request */
2385 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2386 }
2387 else
2388 {
2389 /* Update I2C state */
2390 hi2c->State = HAL_I2C_STATE_LISTEN;
2391 hi2c->Mode = HAL_I2C_MODE_NONE;
2392
2393 /* Update I2C error code */
2394 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2395
2396 /* Process Unlocked */
2397 __HAL_UNLOCK(hi2c);
2398
2399 return HAL_ERROR;
2400 }
2401
2402 return HAL_OK;
2403 }
2404 else
2405 {
2406 return HAL_BUSY;
2407 }
2408 }
2409 /**
2410 * @brief Write an amount of data in blocking mode to a specific memory address
2411 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2412 * the configuration information for the specified I2C.
2413 * @param DevAddress Target device address: The device 7 bits address value
2414 * in datasheet must be shifted to the left before calling the interface
2415 * @param MemAddress Internal memory address
2416 * @param MemAddSize Size of internal memory address
2417 * @param pData Pointer to data buffer
2418 * @param Size Amount of data to be sent
2419 * @param Timeout Timeout duration
2420 * @retval HAL status
2421 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2422 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2423 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2424 {
2425 uint32_t tickstart;
2426
2427 /* Check the parameters */
2428 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2429
2430 if (hi2c->State == HAL_I2C_STATE_READY)
2431 {
2432 if ((pData == NULL) || (Size == 0U))
2433 {
2434 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2435 return HAL_ERROR;
2436 }
2437
2438 /* Process Locked */
2439 __HAL_LOCK(hi2c);
2440
2441 /* Init tickstart for timeout management*/
2442 tickstart = HAL_GetTick();
2443
2444 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2445 {
2446 return HAL_ERROR;
2447 }
2448
2449 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2450 hi2c->Mode = HAL_I2C_MODE_MEM;
2451 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2452
2453 /* Prepare transfer parameters */
2454 hi2c->pBuffPtr = pData;
2455 hi2c->XferCount = Size;
2456 hi2c->XferISR = NULL;
2457
2458 /* Send Slave Address and Memory Address */
2459 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2460 {
2461 /* Process Unlocked */
2462 __HAL_UNLOCK(hi2c);
2463 return HAL_ERROR;
2464 }
2465
2466 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2467 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2468 {
2469 hi2c->XferSize = MAX_NBYTE_SIZE;
2470 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2471 }
2472 else
2473 {
2474 hi2c->XferSize = hi2c->XferCount;
2475 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2476 }
2477
2478 do
2479 {
2480 /* Wait until TXIS flag is set */
2481 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2482 {
2483 return HAL_ERROR;
2484 }
2485
2486 /* Write data to TXDR */
2487 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2488
2489 /* Increment Buffer pointer */
2490 hi2c->pBuffPtr++;
2491
2492 hi2c->XferCount--;
2493 hi2c->XferSize--;
2494
2495 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2496 {
2497 /* Wait until TCR flag is set */
2498 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2499 {
2500 return HAL_ERROR;
2501 }
2502
2503 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2504 {
2505 hi2c->XferSize = MAX_NBYTE_SIZE;
2506 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2507 I2C_NO_STARTSTOP);
2508 }
2509 else
2510 {
2511 hi2c->XferSize = hi2c->XferCount;
2512 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2513 I2C_NO_STARTSTOP);
2514 }
2515 }
2516
2517 } while (hi2c->XferCount > 0U);
2518
2519 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2520 /* Wait until STOPF flag is reset */
2521 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2522 {
2523 return HAL_ERROR;
2524 }
2525
2526 /* Clear STOP Flag */
2527 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2528
2529 /* Clear Configuration Register 2 */
2530 I2C_RESET_CR2(hi2c);
2531
2532 hi2c->State = HAL_I2C_STATE_READY;
2533 hi2c->Mode = HAL_I2C_MODE_NONE;
2534
2535 /* Process Unlocked */
2536 __HAL_UNLOCK(hi2c);
2537
2538 return HAL_OK;
2539 }
2540 else
2541 {
2542 return HAL_BUSY;
2543 }
2544 }
2545
2546 /**
2547 * @brief Read an amount of data in blocking mode from a specific memory address
2548 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2549 * the configuration information for the specified I2C.
2550 * @param DevAddress Target device address: The device 7 bits address value
2551 * in datasheet must be shifted to the left before calling the interface
2552 * @param MemAddress Internal memory address
2553 * @param MemAddSize Size of internal memory address
2554 * @param pData Pointer to data buffer
2555 * @param Size Amount of data to be sent
2556 * @param Timeout Timeout duration
2557 * @retval HAL status
2558 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2559 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2560 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2561 {
2562 uint32_t tickstart;
2563
2564 /* Check the parameters */
2565 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2566
2567 if (hi2c->State == HAL_I2C_STATE_READY)
2568 {
2569 if ((pData == NULL) || (Size == 0U))
2570 {
2571 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2572 return HAL_ERROR;
2573 }
2574
2575 /* Process Locked */
2576 __HAL_LOCK(hi2c);
2577
2578 /* Init tickstart for timeout management*/
2579 tickstart = HAL_GetTick();
2580
2581 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2582 {
2583 return HAL_ERROR;
2584 }
2585
2586 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2587 hi2c->Mode = HAL_I2C_MODE_MEM;
2588 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2589
2590 /* Prepare transfer parameters */
2591 hi2c->pBuffPtr = pData;
2592 hi2c->XferCount = Size;
2593 hi2c->XferISR = NULL;
2594
2595 /* Send Slave Address and Memory Address */
2596 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2597 {
2598 /* Process Unlocked */
2599 __HAL_UNLOCK(hi2c);
2600 return HAL_ERROR;
2601 }
2602
2603 /* Send Slave Address */
2604 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2605 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2606 {
2607 hi2c->XferSize = MAX_NBYTE_SIZE;
2608 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2609 I2C_GENERATE_START_READ);
2610 }
2611 else
2612 {
2613 hi2c->XferSize = hi2c->XferCount;
2614 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2615 I2C_GENERATE_START_READ);
2616 }
2617
2618 do
2619 {
2620 /* Wait until RXNE flag is set */
2621 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2622 {
2623 return HAL_ERROR;
2624 }
2625
2626 /* Read data from RXDR */
2627 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2628
2629 /* Increment Buffer pointer */
2630 hi2c->pBuffPtr++;
2631
2632 hi2c->XferSize--;
2633 hi2c->XferCount--;
2634
2635 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2636 {
2637 /* Wait until TCR flag is set */
2638 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2639 {
2640 return HAL_ERROR;
2641 }
2642
2643 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2644 {
2645 hi2c->XferSize = MAX_NBYTE_SIZE;
2646 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2647 I2C_NO_STARTSTOP);
2648 }
2649 else
2650 {
2651 hi2c->XferSize = hi2c->XferCount;
2652 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2653 I2C_NO_STARTSTOP);
2654 }
2655 }
2656 } while (hi2c->XferCount > 0U);
2657
2658 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2659 /* Wait until STOPF flag is reset */
2660 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2661 {
2662 return HAL_ERROR;
2663 }
2664
2665 /* Clear STOP Flag */
2666 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2667
2668 /* Clear Configuration Register 2 */
2669 I2C_RESET_CR2(hi2c);
2670
2671 hi2c->State = HAL_I2C_STATE_READY;
2672 hi2c->Mode = HAL_I2C_MODE_NONE;
2673
2674 /* Process Unlocked */
2675 __HAL_UNLOCK(hi2c);
2676
2677 return HAL_OK;
2678 }
2679 else
2680 {
2681 return HAL_BUSY;
2682 }
2683 }
2684 /**
2685 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2686 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2687 * the configuration information for the specified I2C.
2688 * @param DevAddress Target device address: The device 7 bits address value
2689 * in datasheet must be shifted to the left before calling the interface
2690 * @param MemAddress Internal memory address
2691 * @param MemAddSize Size of internal memory address
2692 * @param pData Pointer to data buffer
2693 * @param Size Amount of data to be sent
2694 * @retval HAL status
2695 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2696 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2697 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2698 {
2699 /* Check the parameters */
2700 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2701
2702 if (hi2c->State == HAL_I2C_STATE_READY)
2703 {
2704 if ((pData == NULL) || (Size == 0U))
2705 {
2706 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2707 return HAL_ERROR;
2708 }
2709
2710 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2711 {
2712 return HAL_BUSY;
2713 }
2714
2715 /* Process Locked */
2716 __HAL_LOCK(hi2c);
2717
2718 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2719 hi2c->Mode = HAL_I2C_MODE_MEM;
2720 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2721
2722 /* Prepare transfer parameters */
2723 hi2c->pBuffPtr = pData;
2724 hi2c->XferCount = Size;
2725 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2726 hi2c->XferISR = I2C_Mem_ISR_IT;
2727 hi2c->Devaddress = DevAddress;
2728
2729 /* If Memory address size is 8Bit */
2730 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2731 {
2732 /* Prefetch Memory Address */
2733 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2734
2735 /* Reset Memaddress content */
2736 hi2c->Memaddress = 0xFFFFFFFFU;
2737 }
2738 /* If Memory address size is 16Bit */
2739 else
2740 {
2741 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2742 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2743
2744 /* Prepare Memaddress buffer for LSB part */
2745 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2746 }
2747 /* Send Slave Address and Memory Address */
2748 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2749
2750 /* Process Unlocked */
2751 __HAL_UNLOCK(hi2c);
2752
2753 /* Note : The I2C interrupts must be enabled after unlocking current process
2754 to avoid the risk of I2C interrupt handle execution before current
2755 process unlock */
2756
2757 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2758 /* possible to enable all of these */
2759 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2760 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2761 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2762
2763 return HAL_OK;
2764 }
2765 else
2766 {
2767 return HAL_BUSY;
2768 }
2769 }
2770
2771 /**
2772 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2773 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2774 * the configuration information for the specified I2C.
2775 * @param DevAddress Target device address: The device 7 bits address value
2776 * in datasheet must be shifted to the left before calling the interface
2777 * @param MemAddress Internal memory address
2778 * @param MemAddSize Size of internal memory address
2779 * @param pData Pointer to data buffer
2780 * @param Size Amount of data to be sent
2781 * @retval HAL status
2782 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2783 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2784 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2785 {
2786 /* Check the parameters */
2787 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2788
2789 if (hi2c->State == HAL_I2C_STATE_READY)
2790 {
2791 if ((pData == NULL) || (Size == 0U))
2792 {
2793 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2794 return HAL_ERROR;
2795 }
2796
2797 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2798 {
2799 return HAL_BUSY;
2800 }
2801
2802 /* Process Locked */
2803 __HAL_LOCK(hi2c);
2804
2805 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2806 hi2c->Mode = HAL_I2C_MODE_MEM;
2807 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2808
2809 /* Prepare transfer parameters */
2810 hi2c->pBuffPtr = pData;
2811 hi2c->XferCount = Size;
2812 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2813 hi2c->XferISR = I2C_Mem_ISR_IT;
2814 hi2c->Devaddress = DevAddress;
2815
2816 /* If Memory address size is 8Bit */
2817 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2818 {
2819 /* Prefetch Memory Address */
2820 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2821
2822 /* Reset Memaddress content */
2823 hi2c->Memaddress = 0xFFFFFFFFU;
2824 }
2825 /* If Memory address size is 16Bit */
2826 else
2827 {
2828 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2829 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2830
2831 /* Prepare Memaddress buffer for LSB part */
2832 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2833 }
2834 /* Send Slave Address and Memory Address */
2835 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2836
2837 /* Process Unlocked */
2838 __HAL_UNLOCK(hi2c);
2839
2840 /* Note : The I2C interrupts must be enabled after unlocking current process
2841 to avoid the risk of I2C interrupt handle execution before current
2842 process unlock */
2843
2844 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2845 /* possible to enable all of these */
2846 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2847 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2848 I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
2849
2850 return HAL_OK;
2851 }
2852 else
2853 {
2854 return HAL_BUSY;
2855 }
2856 }
2857 /**
2858 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2859 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2860 * the configuration information for the specified I2C.
2861 * @param DevAddress Target device address: The device 7 bits address value
2862 * in datasheet must be shifted to the left before calling the interface
2863 * @param MemAddress Internal memory address
2864 * @param MemAddSize Size of internal memory address
2865 * @param pData Pointer to data buffer
2866 * @param Size Amount of data to be sent
2867 * @retval HAL status
2868 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2869 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2870 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2871 {
2872 HAL_StatusTypeDef dmaxferstatus;
2873
2874 /* Check the parameters */
2875 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2876
2877 if (hi2c->State == HAL_I2C_STATE_READY)
2878 {
2879 if ((pData == NULL) || (Size == 0U))
2880 {
2881 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2882 return HAL_ERROR;
2883 }
2884
2885 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2886 {
2887 return HAL_BUSY;
2888 }
2889
2890 /* Process Locked */
2891 __HAL_LOCK(hi2c);
2892
2893 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2894 hi2c->Mode = HAL_I2C_MODE_MEM;
2895 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2896
2897 /* Prepare transfer parameters */
2898 hi2c->pBuffPtr = pData;
2899 hi2c->XferCount = Size;
2900 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2901 hi2c->XferISR = I2C_Mem_ISR_DMA;
2902 hi2c->Devaddress = DevAddress;
2903
2904 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2905 {
2906 hi2c->XferSize = MAX_NBYTE_SIZE;
2907 }
2908 else
2909 {
2910 hi2c->XferSize = hi2c->XferCount;
2911 }
2912
2913 /* If Memory address size is 8Bit */
2914 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2915 {
2916 /* Prefetch Memory Address */
2917 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2918
2919 /* Reset Memaddress content */
2920 hi2c->Memaddress = 0xFFFFFFFFU;
2921 }
2922 /* If Memory address size is 16Bit */
2923 else
2924 {
2925 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2926 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2927
2928 /* Prepare Memaddress buffer for LSB part */
2929 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2930 }
2931
2932 if (hi2c->hdmatx != NULL)
2933 {
2934 /* Set the I2C DMA transfer complete callback */
2935 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2936
2937 /* Set the DMA error callback */
2938 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2939
2940 /* Set the unused DMA callbacks to NULL */
2941 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2942 hi2c->hdmatx->XferAbortCallback = NULL;
2943
2944 /* Enable the DMA channel */
2945 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2946 hi2c->XferSize);
2947 }
2948 else
2949 {
2950 /* Update I2C state */
2951 hi2c->State = HAL_I2C_STATE_READY;
2952 hi2c->Mode = HAL_I2C_MODE_NONE;
2953
2954 /* Update I2C error code */
2955 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2956
2957 /* Process Unlocked */
2958 __HAL_UNLOCK(hi2c);
2959
2960 return HAL_ERROR;
2961 }
2962
2963 if (dmaxferstatus == HAL_OK)
2964 {
2965 /* Send Slave Address and Memory Address */
2966 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2967
2968 /* Process Unlocked */
2969 __HAL_UNLOCK(hi2c);
2970
2971 /* Note : The I2C interrupts must be enabled after unlocking current process
2972 to avoid the risk of I2C interrupt handle execution before current
2973 process unlock */
2974 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2975 /* possible to enable all of these */
2976 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2977 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2978 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2979 }
2980 else
2981 {
2982 /* Update I2C state */
2983 hi2c->State = HAL_I2C_STATE_READY;
2984 hi2c->Mode = HAL_I2C_MODE_NONE;
2985
2986 /* Update I2C error code */
2987 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2988
2989 /* Process Unlocked */
2990 __HAL_UNLOCK(hi2c);
2991
2992 return HAL_ERROR;
2993 }
2994
2995 return HAL_OK;
2996 }
2997 else
2998 {
2999 return HAL_BUSY;
3000 }
3001 }
3002
3003 /**
3004 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3005 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3006 * the configuration information for the specified I2C.
3007 * @param DevAddress Target device address: The device 7 bits address value
3008 * in datasheet must be shifted to the left before calling the interface
3009 * @param MemAddress Internal memory address
3010 * @param MemAddSize Size of internal memory address
3011 * @param pData Pointer to data buffer
3012 * @param Size Amount of data to be read
3013 * @retval HAL status
3014 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3015 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3016 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3017 {
3018 HAL_StatusTypeDef dmaxferstatus;
3019
3020 /* Check the parameters */
3021 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3022
3023 if (hi2c->State == HAL_I2C_STATE_READY)
3024 {
3025 if ((pData == NULL) || (Size == 0U))
3026 {
3027 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3028 return HAL_ERROR;
3029 }
3030
3031 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3032 {
3033 return HAL_BUSY;
3034 }
3035
3036 /* Process Locked */
3037 __HAL_LOCK(hi2c);
3038
3039 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3040 hi2c->Mode = HAL_I2C_MODE_MEM;
3041 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3042
3043 /* Prepare transfer parameters */
3044 hi2c->pBuffPtr = pData;
3045 hi2c->XferCount = Size;
3046 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3047 hi2c->XferISR = I2C_Mem_ISR_DMA;
3048 hi2c->Devaddress = DevAddress;
3049
3050 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3051 {
3052 hi2c->XferSize = MAX_NBYTE_SIZE;
3053 }
3054 else
3055 {
3056 hi2c->XferSize = hi2c->XferCount;
3057 }
3058
3059 /* If Memory address size is 8Bit */
3060 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3061 {
3062 /* Prefetch Memory Address */
3063 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3064
3065 /* Reset Memaddress content */
3066 hi2c->Memaddress = 0xFFFFFFFFU;
3067 }
3068 /* If Memory address size is 16Bit */
3069 else
3070 {
3071 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3072 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3073
3074 /* Prepare Memaddress buffer for LSB part */
3075 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3076 }
3077
3078 if (hi2c->hdmarx != NULL)
3079 {
3080 /* Set the I2C DMA transfer complete callback */
3081 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3082
3083 /* Set the DMA error callback */
3084 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3085
3086 /* Set the unused DMA callbacks to NULL */
3087 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3088 hi2c->hdmarx->XferAbortCallback = NULL;
3089
3090 /* Enable the DMA channel */
3091 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3092 hi2c->XferSize);
3093 }
3094 else
3095 {
3096 /* Update I2C state */
3097 hi2c->State = HAL_I2C_STATE_READY;
3098 hi2c->Mode = HAL_I2C_MODE_NONE;
3099
3100 /* Update I2C error code */
3101 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3102
3103 /* Process Unlocked */
3104 __HAL_UNLOCK(hi2c);
3105
3106 return HAL_ERROR;
3107 }
3108
3109 if (dmaxferstatus == HAL_OK)
3110 {
3111 /* Send Slave Address and Memory Address */
3112 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3113
3114 /* Process Unlocked */
3115 __HAL_UNLOCK(hi2c);
3116
3117 /* Note : The I2C interrupts must be enabled after unlocking current process
3118 to avoid the risk of I2C interrupt handle execution before current
3119 process unlock */
3120 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3121 /* possible to enable all of these */
3122 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3123 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3124 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3125 }
3126 else
3127 {
3128 /* Update I2C state */
3129 hi2c->State = HAL_I2C_STATE_READY;
3130 hi2c->Mode = HAL_I2C_MODE_NONE;
3131
3132 /* Update I2C error code */
3133 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3134
3135 /* Process Unlocked */
3136 __HAL_UNLOCK(hi2c);
3137
3138 return HAL_ERROR;
3139 }
3140
3141 return HAL_OK;
3142 }
3143 else
3144 {
3145 return HAL_BUSY;
3146 }
3147 }
3148
3149 /**
3150 * @brief Checks if target device is ready for communication.
3151 * @note This function is used with Memory devices
3152 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3153 * the configuration information for the specified I2C.
3154 * @param DevAddress Target device address: The device 7 bits address value
3155 * in datasheet must be shifted to the left before calling the interface
3156 * @param Trials Number of trials
3157 * @param Timeout Timeout duration
3158 * @retval HAL status
3159 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3160 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3161 uint32_t Timeout)
3162 {
3163 uint32_t tickstart;
3164
3165 __IO uint32_t I2C_Trials = 0UL;
3166
3167 FlagStatus tmp1;
3168 FlagStatus tmp2;
3169
3170 if (hi2c->State == HAL_I2C_STATE_READY)
3171 {
3172 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3173 {
3174 return HAL_BUSY;
3175 }
3176
3177 /* Process Locked */
3178 __HAL_LOCK(hi2c);
3179
3180 hi2c->State = HAL_I2C_STATE_BUSY;
3181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3182
3183 do
3184 {
3185 /* Generate Start */
3186 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3187
3188 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3189 /* Wait until STOPF flag is set or a NACK flag is set*/
3190 tickstart = HAL_GetTick();
3191
3192 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3193 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3194
3195 while ((tmp1 == RESET) && (tmp2 == RESET))
3196 {
3197 if (Timeout != HAL_MAX_DELAY)
3198 {
3199 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3200 {
3201 /* Update I2C state */
3202 hi2c->State = HAL_I2C_STATE_READY;
3203
3204 /* Update I2C error code */
3205 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3206
3207 /* Process Unlocked */
3208 __HAL_UNLOCK(hi2c);
3209
3210 return HAL_ERROR;
3211 }
3212 }
3213
3214 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3215 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3216 }
3217
3218 /* Check if the NACKF flag has not been set */
3219 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3220 {
3221 /* Wait until STOPF flag is reset */
3222 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3223 {
3224 return HAL_ERROR;
3225 }
3226
3227 /* Clear STOP Flag */
3228 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3229
3230 /* Device is ready */
3231 hi2c->State = HAL_I2C_STATE_READY;
3232
3233 /* Process Unlocked */
3234 __HAL_UNLOCK(hi2c);
3235
3236 return HAL_OK;
3237 }
3238 else
3239 {
3240 /* Wait until STOPF flag is reset */
3241 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3242 {
3243 return HAL_ERROR;
3244 }
3245
3246 /* Clear NACK Flag */
3247 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3248
3249 /* Clear STOP Flag, auto generated with autoend*/
3250 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3251 }
3252
3253 /* Check if the maximum allowed number of trials has been reached */
3254 if (I2C_Trials == Trials)
3255 {
3256 /* Generate Stop */
3257 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3258
3259 /* Wait until STOPF flag is reset */
3260 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3261 {
3262 return HAL_ERROR;
3263 }
3264
3265 /* Clear STOP Flag */
3266 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3267 }
3268
3269 /* Increment Trials */
3270 I2C_Trials++;
3271 } while (I2C_Trials < Trials);
3272
3273 /* Update I2C state */
3274 hi2c->State = HAL_I2C_STATE_READY;
3275
3276 /* Update I2C error code */
3277 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3278
3279 /* Process Unlocked */
3280 __HAL_UNLOCK(hi2c);
3281
3282 return HAL_ERROR;
3283 }
3284 else
3285 {
3286 return HAL_BUSY;
3287 }
3288 }
3289
3290 /**
3291 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3292 * @note This interface allow to manage repeated start condition when a direction change during transfer
3293 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3294 * the configuration information for the specified I2C.
3295 * @param DevAddress Target device address: The device 7 bits address value
3296 * in datasheet must be shifted to the left before calling the interface
3297 * @param pData Pointer to data buffer
3298 * @param Size Amount of data to be sent
3299 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3300 * @retval HAL status
3301 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3302 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3303 uint16_t Size, uint32_t XferOptions)
3304 {
3305 uint32_t xfermode;
3306 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3307
3308 /* Check the parameters */
3309 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3310
3311 if (hi2c->State == HAL_I2C_STATE_READY)
3312 {
3313 /* Process Locked */
3314 __HAL_LOCK(hi2c);
3315
3316 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3317 hi2c->Mode = HAL_I2C_MODE_MASTER;
3318 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3319
3320 /* Prepare transfer parameters */
3321 hi2c->pBuffPtr = pData;
3322 hi2c->XferCount = Size;
3323 hi2c->XferOptions = XferOptions;
3324 hi2c->XferISR = I2C_Master_ISR_IT;
3325
3326 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3327 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3328 {
3329 hi2c->XferSize = MAX_NBYTE_SIZE;
3330 xfermode = I2C_RELOAD_MODE;
3331 }
3332 else
3333 {
3334 hi2c->XferSize = hi2c->XferCount;
3335 xfermode = hi2c->XferOptions;
3336 }
3337
3338 /* If transfer direction not change and there is no request to start another frame,
3339 do not generate Restart Condition */
3340 /* Mean Previous state is same as current state */
3341 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3342 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3343 {
3344 xferrequest = I2C_NO_STARTSTOP;
3345 }
3346 else
3347 {
3348 /* Convert OTHER_xxx XferOptions if any */
3349 I2C_ConvertOtherXferOptions(hi2c);
3350
3351 /* Update xfermode accordingly if no reload is necessary */
3352 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3353 {
3354 xfermode = hi2c->XferOptions;
3355 }
3356 }
3357
3358 /* Send Slave Address and set NBYTES to write */
3359 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3360
3361 /* Process Unlocked */
3362 __HAL_UNLOCK(hi2c);
3363
3364 /* Note : The I2C interrupts must be enabled after unlocking current process
3365 to avoid the risk of I2C interrupt handle execution before current
3366 process unlock */
3367 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3368 /* possible to enable all of these */
3369 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3370 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3371 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3372
3373 return HAL_OK;
3374 }
3375 else
3376 {
3377 return HAL_BUSY;
3378 }
3379 }
3380
3381 /**
3382 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3383 * @note This interface allow to manage repeated start condition when a direction change during transfer
3384 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3385 * the configuration information for the specified I2C.
3386 * @param DevAddress Target device address: The device 7 bits address value
3387 * in datasheet must be shifted to the left before calling the interface
3388 * @param pData Pointer to data buffer
3389 * @param Size Amount of data to be sent
3390 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3391 * @retval HAL status
3392 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3393 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3394 uint16_t Size, uint32_t XferOptions)
3395 {
3396 uint32_t xfermode;
3397 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3398 HAL_StatusTypeDef dmaxferstatus;
3399
3400 /* Check the parameters */
3401 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3402
3403 if (hi2c->State == HAL_I2C_STATE_READY)
3404 {
3405 /* Process Locked */
3406 __HAL_LOCK(hi2c);
3407
3408 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3409 hi2c->Mode = HAL_I2C_MODE_MASTER;
3410 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3411
3412 /* Prepare transfer parameters */
3413 hi2c->pBuffPtr = pData;
3414 hi2c->XferCount = Size;
3415 hi2c->XferOptions = XferOptions;
3416 hi2c->XferISR = I2C_Master_ISR_DMA;
3417
3418 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3419 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3420 {
3421 hi2c->XferSize = MAX_NBYTE_SIZE;
3422 xfermode = I2C_RELOAD_MODE;
3423 }
3424 else
3425 {
3426 hi2c->XferSize = hi2c->XferCount;
3427 xfermode = hi2c->XferOptions;
3428 }
3429
3430 /* If transfer direction not change and there is no request to start another frame,
3431 do not generate Restart Condition */
3432 /* Mean Previous state is same as current state */
3433 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3434 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3435 {
3436 xferrequest = I2C_NO_STARTSTOP;
3437 }
3438 else
3439 {
3440 /* Convert OTHER_xxx XferOptions if any */
3441 I2C_ConvertOtherXferOptions(hi2c);
3442
3443 /* Update xfermode accordingly if no reload is necessary */
3444 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3445 {
3446 xfermode = hi2c->XferOptions;
3447 }
3448 }
3449
3450 if (hi2c->XferSize > 0U)
3451 {
3452 if (hi2c->hdmatx != NULL)
3453 {
3454 /* Set the I2C DMA transfer complete callback */
3455 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3456
3457 /* Set the DMA error callback */
3458 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3459
3460 /* Set the unused DMA callbacks to NULL */
3461 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3462 hi2c->hdmatx->XferAbortCallback = NULL;
3463
3464 /* Enable the DMA channel */
3465 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3466 hi2c->XferSize);
3467 }
3468 else
3469 {
3470 /* Update I2C state */
3471 hi2c->State = HAL_I2C_STATE_READY;
3472 hi2c->Mode = HAL_I2C_MODE_NONE;
3473
3474 /* Update I2C error code */
3475 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3476
3477 /* Process Unlocked */
3478 __HAL_UNLOCK(hi2c);
3479
3480 return HAL_ERROR;
3481 }
3482
3483 if (dmaxferstatus == HAL_OK)
3484 {
3485 /* Send Slave Address and set NBYTES to write */
3486 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3487
3488 /* Update XferCount value */
3489 hi2c->XferCount -= hi2c->XferSize;
3490
3491 /* Process Unlocked */
3492 __HAL_UNLOCK(hi2c);
3493
3494 /* Note : The I2C interrupts must be enabled after unlocking current process
3495 to avoid the risk of I2C interrupt handle execution before current
3496 process unlock */
3497 /* Enable ERR and NACK interrupts */
3498 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3499
3500 /* Enable DMA Request */
3501 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3502 }
3503 else
3504 {
3505 /* Update I2C state */
3506 hi2c->State = HAL_I2C_STATE_READY;
3507 hi2c->Mode = HAL_I2C_MODE_NONE;
3508
3509 /* Update I2C error code */
3510 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3511
3512 /* Process Unlocked */
3513 __HAL_UNLOCK(hi2c);
3514
3515 return HAL_ERROR;
3516 }
3517 }
3518 else
3519 {
3520 /* Update Transfer ISR function pointer */
3521 hi2c->XferISR = I2C_Master_ISR_IT;
3522
3523 /* Send Slave Address */
3524 /* Set NBYTES to write and generate START condition */
3525 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3526 I2C_GENERATE_START_WRITE);
3527
3528 /* Process Unlocked */
3529 __HAL_UNLOCK(hi2c);
3530
3531 /* Note : The I2C interrupts must be enabled after unlocking current process
3532 to avoid the risk of I2C interrupt handle execution before current
3533 process unlock */
3534 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3535 /* possible to enable all of these */
3536 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3537 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3538 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3539 }
3540
3541 return HAL_OK;
3542 }
3543 else
3544 {
3545 return HAL_BUSY;
3546 }
3547 }
3548
3549 /**
3550 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3551 * @note This interface allow to manage repeated start condition when a direction change during transfer
3552 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3553 * the configuration information for the specified I2C.
3554 * @param DevAddress Target device address: The device 7 bits address value
3555 * in datasheet must be shifted to the left before calling the interface
3556 * @param pData Pointer to data buffer
3557 * @param Size Amount of data to be sent
3558 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3559 * @retval HAL status
3560 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3561 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3562 uint16_t Size, uint32_t XferOptions)
3563 {
3564 uint32_t xfermode;
3565 uint32_t xferrequest = I2C_GENERATE_START_READ;
3566
3567 /* Check the parameters */
3568 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3569
3570 if (hi2c->State == HAL_I2C_STATE_READY)
3571 {
3572 /* Process Locked */
3573 __HAL_LOCK(hi2c);
3574
3575 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3576 hi2c->Mode = HAL_I2C_MODE_MASTER;
3577 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3578
3579 /* Prepare transfer parameters */
3580 hi2c->pBuffPtr = pData;
3581 hi2c->XferCount = Size;
3582 hi2c->XferOptions = XferOptions;
3583 hi2c->XferISR = I2C_Master_ISR_IT;
3584
3585 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3586 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3587 {
3588 hi2c->XferSize = MAX_NBYTE_SIZE;
3589 xfermode = I2C_RELOAD_MODE;
3590 }
3591 else
3592 {
3593 hi2c->XferSize = hi2c->XferCount;
3594 xfermode = hi2c->XferOptions;
3595 }
3596
3597 /* If transfer direction not change and there is no request to start another frame,
3598 do not generate Restart Condition */
3599 /* Mean Previous state is same as current state */
3600 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3601 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3602 {
3603 xferrequest = I2C_NO_STARTSTOP;
3604 }
3605 else
3606 {
3607 /* Convert OTHER_xxx XferOptions if any */
3608 I2C_ConvertOtherXferOptions(hi2c);
3609
3610 /* Update xfermode accordingly if no reload is necessary */
3611 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3612 {
3613 xfermode = hi2c->XferOptions;
3614 }
3615 }
3616
3617 /* Send Slave Address and set NBYTES to read */
3618 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3619
3620 /* Process Unlocked */
3621 __HAL_UNLOCK(hi2c);
3622
3623 /* Note : The I2C interrupts must be enabled after unlocking current process
3624 to avoid the risk of I2C interrupt handle execution before current
3625 process unlock */
3626 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3627
3628 return HAL_OK;
3629 }
3630 else
3631 {
3632 return HAL_BUSY;
3633 }
3634 }
3635
3636 /**
3637 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3638 * @note This interface allow to manage repeated start condition when a direction change during transfer
3639 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3640 * the configuration information for the specified I2C.
3641 * @param DevAddress Target device address: The device 7 bits address value
3642 * in datasheet must be shifted to the left before calling the interface
3643 * @param pData Pointer to data buffer
3644 * @param Size Amount of data to be sent
3645 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3646 * @retval HAL status
3647 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3648 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3649 uint16_t Size, uint32_t XferOptions)
3650 {
3651 uint32_t xfermode;
3652 uint32_t xferrequest = I2C_GENERATE_START_READ;
3653 HAL_StatusTypeDef dmaxferstatus;
3654
3655 /* Check the parameters */
3656 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3657
3658 if (hi2c->State == HAL_I2C_STATE_READY)
3659 {
3660 /* Process Locked */
3661 __HAL_LOCK(hi2c);
3662
3663 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3664 hi2c->Mode = HAL_I2C_MODE_MASTER;
3665 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3666
3667 /* Prepare transfer parameters */
3668 hi2c->pBuffPtr = pData;
3669 hi2c->XferCount = Size;
3670 hi2c->XferOptions = XferOptions;
3671 hi2c->XferISR = I2C_Master_ISR_DMA;
3672
3673 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3674 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3675 {
3676 hi2c->XferSize = MAX_NBYTE_SIZE;
3677 xfermode = I2C_RELOAD_MODE;
3678 }
3679 else
3680 {
3681 hi2c->XferSize = hi2c->XferCount;
3682 xfermode = hi2c->XferOptions;
3683 }
3684
3685 /* If transfer direction not change and there is no request to start another frame,
3686 do not generate Restart Condition */
3687 /* Mean Previous state is same as current state */
3688 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3689 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3690 {
3691 xferrequest = I2C_NO_STARTSTOP;
3692 }
3693 else
3694 {
3695 /* Convert OTHER_xxx XferOptions if any */
3696 I2C_ConvertOtherXferOptions(hi2c);
3697
3698 /* Update xfermode accordingly if no reload is necessary */
3699 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3700 {
3701 xfermode = hi2c->XferOptions;
3702 }
3703 }
3704
3705 if (hi2c->XferSize > 0U)
3706 {
3707 if (hi2c->hdmarx != NULL)
3708 {
3709 /* Set the I2C DMA transfer complete callback */
3710 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3711
3712 /* Set the DMA error callback */
3713 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3714
3715 /* Set the unused DMA callbacks to NULL */
3716 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3717 hi2c->hdmarx->XferAbortCallback = NULL;
3718
3719 /* Enable the DMA channel */
3720 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3721 hi2c->XferSize);
3722 }
3723 else
3724 {
3725 /* Update I2C state */
3726 hi2c->State = HAL_I2C_STATE_READY;
3727 hi2c->Mode = HAL_I2C_MODE_NONE;
3728
3729 /* Update I2C error code */
3730 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3731
3732 /* Process Unlocked */
3733 __HAL_UNLOCK(hi2c);
3734
3735 return HAL_ERROR;
3736 }
3737
3738 if (dmaxferstatus == HAL_OK)
3739 {
3740 /* Send Slave Address and set NBYTES to read */
3741 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3742
3743 /* Update XferCount value */
3744 hi2c->XferCount -= hi2c->XferSize;
3745
3746 /* Process Unlocked */
3747 __HAL_UNLOCK(hi2c);
3748
3749 /* Note : The I2C interrupts must be enabled after unlocking current process
3750 to avoid the risk of I2C interrupt handle execution before current
3751 process unlock */
3752 /* Enable ERR and NACK interrupts */
3753 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3754
3755 /* Enable DMA Request */
3756 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3757 }
3758 else
3759 {
3760 /* Update I2C state */
3761 hi2c->State = HAL_I2C_STATE_READY;
3762 hi2c->Mode = HAL_I2C_MODE_NONE;
3763
3764 /* Update I2C error code */
3765 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3766
3767 /* Process Unlocked */
3768 __HAL_UNLOCK(hi2c);
3769
3770 return HAL_ERROR;
3771 }
3772 }
3773 else
3774 {
3775 /* Update Transfer ISR function pointer */
3776 hi2c->XferISR = I2C_Master_ISR_IT;
3777
3778 /* Send Slave Address */
3779 /* Set NBYTES to read and generate START condition */
3780 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3781 I2C_GENERATE_START_READ);
3782
3783 /* Process Unlocked */
3784 __HAL_UNLOCK(hi2c);
3785
3786 /* Note : The I2C interrupts must be enabled after unlocking current process
3787 to avoid the risk of I2C interrupt handle execution before current
3788 process unlock */
3789 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3790 /* possible to enable all of these */
3791 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3792 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3793 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3794 }
3795
3796 return HAL_OK;
3797 }
3798 else
3799 {
3800 return HAL_BUSY;
3801 }
3802 }
3803
3804 /**
3805 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3806 * @note This interface allow to manage repeated start condition when a direction change during transfer
3807 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3808 * the configuration information for the specified I2C.
3809 * @param pData Pointer to data buffer
3810 * @param Size Amount of data to be sent
3811 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3812 * @retval HAL status
3813 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3814 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3815 uint32_t XferOptions)
3816 {
3817 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3818 FlagStatus tmp;
3819
3820 /* Check the parameters */
3821 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3822
3823 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3824 {
3825 if ((pData == NULL) || (Size == 0U))
3826 {
3827 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3828 return HAL_ERROR;
3829 }
3830
3831 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3832 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3833
3834 /* Process Locked */
3835 __HAL_LOCK(hi2c);
3836
3837 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3838 /* and then toggle the HAL slave RX state to TX state */
3839 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3840 {
3841 /* Disable associated Interrupts */
3842 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3843
3844 /* Abort DMA Xfer if any */
3845 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3846 {
3847 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3848
3849 if (hi2c->hdmarx != NULL)
3850 {
3851 /* Set the I2C DMA Abort callback :
3852 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3853 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3854
3855 /* Abort DMA RX */
3856 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3857 {
3858 /* Call Directly XferAbortCallback function in case of error */
3859 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3860 }
3861 }
3862 }
3863 }
3864
3865 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3866 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3867 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3868
3869 /* Enable Address Acknowledge */
3870 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3871
3872 /* Prepare transfer parameters */
3873 hi2c->pBuffPtr = pData;
3874 hi2c->XferCount = Size;
3875 hi2c->XferSize = hi2c->XferCount;
3876 hi2c->XferOptions = XferOptions;
3877 hi2c->XferISR = I2C_Slave_ISR_IT;
3878
3879 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3880 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
3881 {
3882 /* Clear ADDR flag after prepare the transfer parameters */
3883 /* This action will generate an acknowledge to the Master */
3884 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3885 }
3886
3887 /* Process Unlocked */
3888 __HAL_UNLOCK(hi2c);
3889
3890 /* Note : The I2C interrupts must be enabled after unlocking current process
3891 to avoid the risk of I2C interrupt handle execution before current
3892 process unlock */
3893 /* REnable ADDR interrupt */
3894 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
3895
3896 return HAL_OK;
3897 }
3898 else
3899 {
3900 return HAL_ERROR;
3901 }
3902 }
3903
3904 /**
3905 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
3906 * @note This interface allow to manage repeated start condition when a direction change during transfer
3907 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3908 * the configuration information for the specified I2C.
3909 * @param pData Pointer to data buffer
3910 * @param Size Amount of data to be sent
3911 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3912 * @retval HAL status
3913 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3914 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3915 uint32_t XferOptions)
3916 {
3917 /* Declaration of tmp to prevent undefined behavior of volatile usage */
3918 FlagStatus tmp;
3919 HAL_StatusTypeDef dmaxferstatus;
3920
3921 /* Check the parameters */
3922 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3923
3924 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3925 {
3926 if ((pData == NULL) || (Size == 0U))
3927 {
3928 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3929 return HAL_ERROR;
3930 }
3931
3932 /* Process Locked */
3933 __HAL_LOCK(hi2c);
3934
3935 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3936 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3937
3938 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3939 /* and then toggle the HAL slave RX state to TX state */
3940 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3941 {
3942 /* Disable associated Interrupts */
3943 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3944
3945 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3946 {
3947 /* Abort DMA Xfer if any */
3948 if (hi2c->hdmarx != NULL)
3949 {
3950 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3951
3952 /* Set the I2C DMA Abort callback :
3953 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3954 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3955
3956 /* Abort DMA RX */
3957 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3958 {
3959 /* Call Directly XferAbortCallback function in case of error */
3960 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3961 }
3962 }
3963 }
3964 }
3965 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3966 {
3967 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3968 {
3969 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3970
3971 /* Abort DMA Xfer if any */
3972 if (hi2c->hdmatx != NULL)
3973 {
3974 /* Set the I2C DMA Abort callback :
3975 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3976 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3977
3978 /* Abort DMA TX */
3979 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3980 {
3981 /* Call Directly XferAbortCallback function in case of error */
3982 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3983 }
3984 }
3985 }
3986 }
3987 else
3988 {
3989 /* Nothing to do */
3990 }
3991
3992 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3993 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3994 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3995
3996 /* Enable Address Acknowledge */
3997 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3998
3999 /* Prepare transfer parameters */
4000 hi2c->pBuffPtr = pData;
4001 hi2c->XferCount = Size;
4002 hi2c->XferSize = hi2c->XferCount;
4003 hi2c->XferOptions = XferOptions;
4004 hi2c->XferISR = I2C_Slave_ISR_DMA;
4005
4006 if (hi2c->hdmatx != NULL)
4007 {
4008 /* Set the I2C DMA transfer complete callback */
4009 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4010
4011 /* Set the DMA error callback */
4012 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4013
4014 /* Set the unused DMA callbacks to NULL */
4015 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4016 hi2c->hdmatx->XferAbortCallback = NULL;
4017
4018 /* Enable the DMA channel */
4019 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4020 hi2c->XferSize);
4021 }
4022 else
4023 {
4024 /* Update I2C state */
4025 hi2c->State = HAL_I2C_STATE_LISTEN;
4026 hi2c->Mode = HAL_I2C_MODE_NONE;
4027
4028 /* Update I2C error code */
4029 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4030
4031 /* Process Unlocked */
4032 __HAL_UNLOCK(hi2c);
4033
4034 return HAL_ERROR;
4035 }
4036
4037 if (dmaxferstatus == HAL_OK)
4038 {
4039 /* Update XferCount value */
4040 hi2c->XferCount -= hi2c->XferSize;
4041
4042 /* Reset XferSize */
4043 hi2c->XferSize = 0;
4044 }
4045 else
4046 {
4047 /* Update I2C state */
4048 hi2c->State = HAL_I2C_STATE_LISTEN;
4049 hi2c->Mode = HAL_I2C_MODE_NONE;
4050
4051 /* Update I2C error code */
4052 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4053
4054 /* Process Unlocked */
4055 __HAL_UNLOCK(hi2c);
4056
4057 return HAL_ERROR;
4058 }
4059
4060 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4061 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4062 {
4063 /* Clear ADDR flag after prepare the transfer parameters */
4064 /* This action will generate an acknowledge to the Master */
4065 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4066 }
4067
4068 /* Process Unlocked */
4069 __HAL_UNLOCK(hi2c);
4070
4071 /* Enable DMA Request */
4072 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4073
4074 /* Note : The I2C interrupts must be enabled after unlocking current process
4075 to avoid the risk of I2C interrupt handle execution before current
4076 process unlock */
4077 /* Enable ERR, STOP, NACK, ADDR interrupts */
4078 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4079
4080 return HAL_OK;
4081 }
4082 else
4083 {
4084 return HAL_ERROR;
4085 }
4086 }
4087
4088 /**
4089 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4090 * @note This interface allow to manage repeated start condition when a direction change during transfer
4091 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4092 * the configuration information for the specified I2C.
4093 * @param pData Pointer to data buffer
4094 * @param Size Amount of data to be sent
4095 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4096 * @retval HAL status
4097 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4098 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4099 uint32_t XferOptions)
4100 {
4101 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4102 FlagStatus tmp;
4103
4104 /* Check the parameters */
4105 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4106
4107 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4108 {
4109 if ((pData == NULL) || (Size == 0U))
4110 {
4111 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4112 return HAL_ERROR;
4113 }
4114
4115 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4116 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4117
4118 /* Process Locked */
4119 __HAL_LOCK(hi2c);
4120
4121 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4122 /* and then toggle the HAL slave TX state to RX state */
4123 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4124 {
4125 /* Disable associated Interrupts */
4126 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4127
4128 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4129 {
4130 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4131
4132 /* Abort DMA Xfer if any */
4133 if (hi2c->hdmatx != NULL)
4134 {
4135 /* Set the I2C DMA Abort callback :
4136 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4137 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4138
4139 /* Abort DMA TX */
4140 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4141 {
4142 /* Call Directly XferAbortCallback function in case of error */
4143 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4144 }
4145 }
4146 }
4147 }
4148
4149 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4150 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4151 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4152
4153 /* Enable Address Acknowledge */
4154 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4155
4156 /* Prepare transfer parameters */
4157 hi2c->pBuffPtr = pData;
4158 hi2c->XferCount = Size;
4159 hi2c->XferSize = hi2c->XferCount;
4160 hi2c->XferOptions = XferOptions;
4161 hi2c->XferISR = I2C_Slave_ISR_IT;
4162
4163 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4164 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4165 {
4166 /* Clear ADDR flag after prepare the transfer parameters */
4167 /* This action will generate an acknowledge to the Master */
4168 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4169 }
4170
4171 /* Process Unlocked */
4172 __HAL_UNLOCK(hi2c);
4173
4174 /* Note : The I2C interrupts must be enabled after unlocking current process
4175 to avoid the risk of I2C interrupt handle execution before current
4176 process unlock */
4177 /* REnable ADDR interrupt */
4178 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4179
4180 return HAL_OK;
4181 }
4182 else
4183 {
4184 return HAL_ERROR;
4185 }
4186 }
4187
4188 /**
4189 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4190 * @note This interface allow to manage repeated start condition when a direction change during transfer
4191 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4192 * the configuration information for the specified I2C.
4193 * @param pData Pointer to data buffer
4194 * @param Size Amount of data to be sent
4195 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4196 * @retval HAL status
4197 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4198 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4199 uint32_t XferOptions)
4200 {
4201 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4202 FlagStatus tmp;
4203 HAL_StatusTypeDef dmaxferstatus;
4204
4205 /* Check the parameters */
4206 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4207
4208 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4209 {
4210 if ((pData == NULL) || (Size == 0U))
4211 {
4212 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4213 return HAL_ERROR;
4214 }
4215
4216 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4217 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4218
4219 /* Process Locked */
4220 __HAL_LOCK(hi2c);
4221
4222 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4223 /* and then toggle the HAL slave TX state to RX state */
4224 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4225 {
4226 /* Disable associated Interrupts */
4227 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4228
4229 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4230 {
4231 /* Abort DMA Xfer if any */
4232 if (hi2c->hdmatx != NULL)
4233 {
4234 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4235
4236 /* Set the I2C DMA Abort callback :
4237 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4238 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4239
4240 /* Abort DMA TX */
4241 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4242 {
4243 /* Call Directly XferAbortCallback function in case of error */
4244 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4245 }
4246 }
4247 }
4248 }
4249 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4250 {
4251 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4252 {
4253 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4254
4255 /* Abort DMA Xfer if any */
4256 if (hi2c->hdmarx != NULL)
4257 {
4258 /* Set the I2C DMA Abort callback :
4259 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4260 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4261
4262 /* Abort DMA RX */
4263 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4264 {
4265 /* Call Directly XferAbortCallback function in case of error */
4266 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4267 }
4268 }
4269 }
4270 }
4271 else
4272 {
4273 /* Nothing to do */
4274 }
4275
4276 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4277 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4278 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4279
4280 /* Enable Address Acknowledge */
4281 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4282
4283 /* Prepare transfer parameters */
4284 hi2c->pBuffPtr = pData;
4285 hi2c->XferCount = Size;
4286 hi2c->XferSize = hi2c->XferCount;
4287 hi2c->XferOptions = XferOptions;
4288 hi2c->XferISR = I2C_Slave_ISR_DMA;
4289
4290 if (hi2c->hdmarx != NULL)
4291 {
4292 /* Set the I2C DMA transfer complete callback */
4293 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4294
4295 /* Set the DMA error callback */
4296 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4297
4298 /* Set the unused DMA callbacks to NULL */
4299 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4300 hi2c->hdmarx->XferAbortCallback = NULL;
4301
4302 /* Enable the DMA channel */
4303 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4304 (uint32_t)pData, hi2c->XferSize);
4305 }
4306 else
4307 {
4308 /* Update I2C state */
4309 hi2c->State = HAL_I2C_STATE_LISTEN;
4310 hi2c->Mode = HAL_I2C_MODE_NONE;
4311
4312 /* Update I2C error code */
4313 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4314
4315 /* Process Unlocked */
4316 __HAL_UNLOCK(hi2c);
4317
4318 return HAL_ERROR;
4319 }
4320
4321 if (dmaxferstatus == HAL_OK)
4322 {
4323 /* Update XferCount value */
4324 hi2c->XferCount -= hi2c->XferSize;
4325
4326 /* Reset XferSize */
4327 hi2c->XferSize = 0;
4328 }
4329 else
4330 {
4331 /* Update I2C state */
4332 hi2c->State = HAL_I2C_STATE_LISTEN;
4333 hi2c->Mode = HAL_I2C_MODE_NONE;
4334
4335 /* Update I2C error code */
4336 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4337
4338 /* Process Unlocked */
4339 __HAL_UNLOCK(hi2c);
4340
4341 return HAL_ERROR;
4342 }
4343
4344 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4345 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4346 {
4347 /* Clear ADDR flag after prepare the transfer parameters */
4348 /* This action will generate an acknowledge to the Master */
4349 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4350 }
4351
4352 /* Process Unlocked */
4353 __HAL_UNLOCK(hi2c);
4354
4355 /* Enable DMA Request */
4356 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4357
4358 /* Note : The I2C interrupts must be enabled after unlocking current process
4359 to avoid the risk of I2C interrupt handle execution before current
4360 process unlock */
4361 /* REnable ADDR interrupt */
4362 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4363
4364 return HAL_OK;
4365 }
4366 else
4367 {
4368 return HAL_ERROR;
4369 }
4370 }
4371
4372 /**
4373 * @brief Enable the Address listen mode with Interrupt.
4374 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4375 * the configuration information for the specified I2C.
4376 * @retval HAL status
4377 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4378 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4379 {
4380 if (hi2c->State == HAL_I2C_STATE_READY)
4381 {
4382 hi2c->State = HAL_I2C_STATE_LISTEN;
4383 hi2c->XferISR = I2C_Slave_ISR_IT;
4384
4385 /* Enable the Address Match interrupt */
4386 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4387
4388 return HAL_OK;
4389 }
4390 else
4391 {
4392 return HAL_BUSY;
4393 }
4394 }
4395
4396 /**
4397 * @brief Disable the Address listen mode with Interrupt.
4398 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4399 * the configuration information for the specified I2C
4400 * @retval HAL status
4401 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4402 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4403 {
4404 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4405 uint32_t tmp;
4406
4407 /* Disable Address listen mode only if a transfer is not ongoing */
4408 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4409 {
4410 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4411 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4412 hi2c->State = HAL_I2C_STATE_READY;
4413 hi2c->Mode = HAL_I2C_MODE_NONE;
4414 hi2c->XferISR = NULL;
4415
4416 /* Disable the Address Match interrupt */
4417 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4418
4419 return HAL_OK;
4420 }
4421 else
4422 {
4423 return HAL_BUSY;
4424 }
4425 }
4426
4427 /**
4428 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4429 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4430 * the configuration information for the specified I2C.
4431 * @param DevAddress Target device address: The device 7 bits address value
4432 * in datasheet must be shifted to the left before calling the interface
4433 * @retval HAL status
4434 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4435 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4436 {
4437 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4438 {
4439 /* Process Locked */
4440 __HAL_LOCK(hi2c);
4441
4442 /* Disable Interrupts and Store Previous state */
4443 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4444 {
4445 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4446 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4447 }
4448 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4449 {
4450 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4451 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4452 }
4453 else
4454 {
4455 /* Do nothing */
4456 }
4457
4458 /* Set State at HAL_I2C_STATE_ABORT */
4459 hi2c->State = HAL_I2C_STATE_ABORT;
4460
4461 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4462 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4463 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4464
4465 /* Process Unlocked */
4466 __HAL_UNLOCK(hi2c);
4467
4468 /* Note : The I2C interrupts must be enabled after unlocking current process
4469 to avoid the risk of I2C interrupt handle execution before current
4470 process unlock */
4471 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4472
4473 return HAL_OK;
4474 }
4475 else
4476 {
4477 /* Wrong usage of abort function */
4478 /* This function should be used only in case of abort monitored by master device */
4479 return HAL_ERROR;
4480 }
4481 }
4482
4483 /**
4484 * @}
4485 */
4486
4487 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4488 * @{
4489 */
4490
4491 /**
4492 * @brief This function handles I2C event interrupt request.
4493 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4494 * the configuration information for the specified I2C.
4495 * @retval None
4496 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4497 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4498 {
4499 /* Get current IT Flags and IT sources value */
4500 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4501 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4502
4503 /* I2C events treatment -------------------------------------*/
4504 if (hi2c->XferISR != NULL)
4505 {
4506 hi2c->XferISR(hi2c, itflags, itsources);
4507 }
4508 }
4509
4510 /**
4511 * @brief This function handles I2C error interrupt request.
4512 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4513 * the configuration information for the specified I2C.
4514 * @retval None
4515 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4516 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4517 {
4518 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4519 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4520 uint32_t tmperror;
4521
4522 /* I2C Bus error interrupt occurred ------------------------------------*/
4523 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4524 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4525 {
4526 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4527
4528 /* Clear BERR flag */
4529 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4530 }
4531
4532 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4533 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4534 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4535 {
4536 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4537
4538 /* Clear OVR flag */
4539 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4540 }
4541
4542 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4543 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4544 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4545 {
4546 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4547
4548 /* Clear ARLO flag */
4549 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4550 }
4551
4552 /* Store current volatile hi2c->ErrorCode, misra rule */
4553 tmperror = hi2c->ErrorCode;
4554
4555 /* Call the Error Callback in case of Error detected */
4556 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4557 {
4558 I2C_ITError(hi2c, tmperror);
4559 }
4560 }
4561
4562 /**
4563 * @brief Master Tx Transfer completed callback.
4564 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4565 * the configuration information for the specified I2C.
4566 * @retval None
4567 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4568 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4569 {
4570 /* Prevent unused argument(s) compilation warning */
4571 UNUSED(hi2c);
4572
4573 /* NOTE : This function should not be modified, when the callback is needed,
4574 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4575 */
4576 }
4577
4578 /**
4579 * @brief Master Rx Transfer completed callback.
4580 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4581 * the configuration information for the specified I2C.
4582 * @retval None
4583 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4584 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4585 {
4586 /* Prevent unused argument(s) compilation warning */
4587 UNUSED(hi2c);
4588
4589 /* NOTE : This function should not be modified, when the callback is needed,
4590 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4591 */
4592 }
4593
4594 /** @brief Slave Tx Transfer completed callback.
4595 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4596 * the configuration information for the specified I2C.
4597 * @retval None
4598 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4599 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4600 {
4601 /* Prevent unused argument(s) compilation warning */
4602 UNUSED(hi2c);
4603
4604 /* NOTE : This function should not be modified, when the callback is needed,
4605 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4606 */
4607 }
4608
4609 /**
4610 * @brief Slave Rx Transfer completed callback.
4611 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4612 * the configuration information for the specified I2C.
4613 * @retval None
4614 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4615 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4616 {
4617 /* Prevent unused argument(s) compilation warning */
4618 UNUSED(hi2c);
4619
4620 /* NOTE : This function should not be modified, when the callback is needed,
4621 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4622 */
4623 }
4624
4625 /**
4626 * @brief Slave Address Match callback.
4627 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4628 * the configuration information for the specified I2C.
4629 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4630 * @param AddrMatchCode Address Match Code
4631 * @retval None
4632 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4633 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4634 {
4635 /* Prevent unused argument(s) compilation warning */
4636 UNUSED(hi2c);
4637 UNUSED(TransferDirection);
4638 UNUSED(AddrMatchCode);
4639
4640 /* NOTE : This function should not be modified, when the callback is needed,
4641 the HAL_I2C_AddrCallback() could be implemented in the user file
4642 */
4643 }
4644
4645 /**
4646 * @brief Listen Complete callback.
4647 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4648 * the configuration information for the specified I2C.
4649 * @retval None
4650 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4651 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4652 {
4653 /* Prevent unused argument(s) compilation warning */
4654 UNUSED(hi2c);
4655
4656 /* NOTE : This function should not be modified, when the callback is needed,
4657 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4658 */
4659 }
4660
4661 /**
4662 * @brief Memory Tx Transfer completed callback.
4663 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4664 * the configuration information for the specified I2C.
4665 * @retval None
4666 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4667 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4668 {
4669 /* Prevent unused argument(s) compilation warning */
4670 UNUSED(hi2c);
4671
4672 /* NOTE : This function should not be modified, when the callback is needed,
4673 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4674 */
4675 }
4676
4677 /**
4678 * @brief Memory Rx Transfer completed callback.
4679 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4680 * the configuration information for the specified I2C.
4681 * @retval None
4682 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4683 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4684 {
4685 /* Prevent unused argument(s) compilation warning */
4686 UNUSED(hi2c);
4687
4688 /* NOTE : This function should not be modified, when the callback is needed,
4689 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4690 */
4691 }
4692
4693 /**
4694 * @brief I2C error callback.
4695 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4696 * the configuration information for the specified I2C.
4697 * @retval None
4698 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4699 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4700 {
4701 /* Prevent unused argument(s) compilation warning */
4702 UNUSED(hi2c);
4703
4704 /* NOTE : This function should not be modified, when the callback is needed,
4705 the HAL_I2C_ErrorCallback could be implemented in the user file
4706 */
4707 }
4708
4709 /**
4710 * @brief I2C abort callback.
4711 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4712 * the configuration information for the specified I2C.
4713 * @retval None
4714 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4715 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4716 {
4717 /* Prevent unused argument(s) compilation warning */
4718 UNUSED(hi2c);
4719
4720 /* NOTE : This function should not be modified, when the callback is needed,
4721 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4722 */
4723 }
4724
4725 /**
4726 * @}
4727 */
4728
4729 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4730 * @brief Peripheral State, Mode and Error functions
4731 *
4732 @verbatim
4733 ===============================================================================
4734 ##### Peripheral State, Mode and Error functions #####
4735 ===============================================================================
4736 [..]
4737 This subsection permit to get in run-time the status of the peripheral
4738 and the data flow.
4739
4740 @endverbatim
4741 * @{
4742 */
4743
4744 /**
4745 * @brief Return the I2C handle state.
4746 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4747 * the configuration information for the specified I2C.
4748 * @retval HAL state
4749 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)4750 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
4751 {
4752 /* Return I2C handle state */
4753 return hi2c->State;
4754 }
4755
4756 /**
4757 * @brief Returns the I2C Master, Slave, Memory or no mode.
4758 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4759 * the configuration information for I2C module
4760 * @retval HAL mode
4761 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)4762 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
4763 {
4764 return hi2c->Mode;
4765 }
4766
4767 /**
4768 * @brief Return the I2C error code.
4769 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4770 * the configuration information for the specified I2C.
4771 * @retval I2C Error Code
4772 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)4773 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
4774 {
4775 return hi2c->ErrorCode;
4776 }
4777
4778 /**
4779 * @}
4780 */
4781
4782 /**
4783 * @}
4784 */
4785
4786 /** @addtogroup I2C_Private_Functions
4787 * @{
4788 */
4789
4790 /**
4791 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4792 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4793 * the configuration information for the specified I2C.
4794 * @param ITFlags Interrupt flags to handle.
4795 * @param ITSources Interrupt sources enabled.
4796 * @retval HAL status
4797 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4798 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4799 uint32_t ITSources)
4800 {
4801 uint16_t devaddress;
4802 uint32_t tmpITFlags = ITFlags;
4803
4804 /* Process Locked */
4805 __HAL_LOCK(hi2c);
4806
4807 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4808 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4809 {
4810 /* Clear NACK Flag */
4811 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4812
4813 /* Set corresponding Error Code */
4814 /* No need to generate STOP, it is automatically done */
4815 /* Error callback will be send during stop flag treatment */
4816 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4817
4818 /* Flush TX register */
4819 I2C_Flush_TXDR(hi2c);
4820 }
4821 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4822 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4823 {
4824 /* Remove RXNE flag on temporary variable as read done */
4825 tmpITFlags &= ~I2C_FLAG_RXNE;
4826
4827 /* Read data from RXDR */
4828 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4829
4830 /* Increment Buffer pointer */
4831 hi2c->pBuffPtr++;
4832
4833 hi2c->XferSize--;
4834 hi2c->XferCount--;
4835 }
4836 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4837 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4838 {
4839 /* Write data to TXDR */
4840 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4841
4842 /* Increment Buffer pointer */
4843 hi2c->pBuffPtr++;
4844
4845 hi2c->XferSize--;
4846 hi2c->XferCount--;
4847 }
4848 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4849 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4850 {
4851 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4852 {
4853 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4854
4855 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4856 {
4857 hi2c->XferSize = MAX_NBYTE_SIZE;
4858 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4859 }
4860 else
4861 {
4862 hi2c->XferSize = hi2c->XferCount;
4863 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4864 {
4865 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4866 hi2c->XferOptions, I2C_NO_STARTSTOP);
4867 }
4868 else
4869 {
4870 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4871 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4872 }
4873 }
4874 }
4875 else
4876 {
4877 /* Call TxCpltCallback() if no stop mode is set */
4878 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4879 {
4880 /* Call I2C Master Sequential complete process */
4881 I2C_ITMasterSeqCplt(hi2c);
4882 }
4883 else
4884 {
4885 /* Wrong size Status regarding TCR flag event */
4886 /* Call the corresponding callback to inform upper layer of End of Transfer */
4887 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4888 }
4889 }
4890 }
4891 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4892 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4893 {
4894 if (hi2c->XferCount == 0U)
4895 {
4896 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4897 {
4898 /* Generate a stop condition in case of no transfer option */
4899 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4900 {
4901 /* Generate Stop */
4902 hi2c->Instance->CR2 |= I2C_CR2_STOP;
4903 }
4904 else
4905 {
4906 /* Call I2C Master Sequential complete process */
4907 I2C_ITMasterSeqCplt(hi2c);
4908 }
4909 }
4910 }
4911 else
4912 {
4913 /* Wrong size Status regarding TC flag event */
4914 /* Call the corresponding callback to inform upper layer of End of Transfer */
4915 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4916 }
4917 }
4918 else
4919 {
4920 /* Nothing to do */
4921 }
4922
4923 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
4924 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4925 {
4926 /* Call I2C Master complete process */
4927 I2C_ITMasterCplt(hi2c, tmpITFlags);
4928 }
4929
4930 /* Process Unlocked */
4931 __HAL_UNLOCK(hi2c);
4932
4933 return HAL_OK;
4934 }
4935
4936 /**
4937 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
4938 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4939 * the configuration information for the specified I2C.
4940 * @param ITFlags Interrupt flags to handle.
4941 * @param ITSources Interrupt sources enabled.
4942 * @retval HAL status
4943 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4944 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4945 uint32_t ITSources)
4946 {
4947 uint32_t direction = I2C_GENERATE_START_WRITE;
4948 uint32_t tmpITFlags = ITFlags;
4949
4950 /* Process Locked */
4951 __HAL_LOCK(hi2c);
4952
4953 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4954 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4955 {
4956 /* Clear NACK Flag */
4957 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4958
4959 /* Set corresponding Error Code */
4960 /* No need to generate STOP, it is automatically done */
4961 /* Error callback will be send during stop flag treatment */
4962 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4963
4964 /* Flush TX register */
4965 I2C_Flush_TXDR(hi2c);
4966 }
4967 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4968 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4969 {
4970 /* Remove RXNE flag on temporary variable as read done */
4971 tmpITFlags &= ~I2C_FLAG_RXNE;
4972
4973 /* Read data from RXDR */
4974 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4975
4976 /* Increment Buffer pointer */
4977 hi2c->pBuffPtr++;
4978
4979 hi2c->XferSize--;
4980 hi2c->XferCount--;
4981 }
4982 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4983 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4984 {
4985 if (hi2c->Memaddress == 0xFFFFFFFFU)
4986 {
4987 /* Write data to TXDR */
4988 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4989
4990 /* Increment Buffer pointer */
4991 hi2c->pBuffPtr++;
4992
4993 hi2c->XferSize--;
4994 hi2c->XferCount--;
4995 }
4996 else
4997 {
4998 /* Write LSB part of Memory Address */
4999 hi2c->Instance->TXDR = hi2c->Memaddress;
5000
5001 /* Reset Memaddress content */
5002 hi2c->Memaddress = 0xFFFFFFFFU;
5003 }
5004 }
5005 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5006 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5007 {
5008 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5009 {
5010 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5011 {
5012 hi2c->XferSize = MAX_NBYTE_SIZE;
5013 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5014 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5015 }
5016 else
5017 {
5018 hi2c->XferSize = hi2c->XferCount;
5019 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5020 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5021 }
5022 }
5023 else
5024 {
5025 /* Wrong size Status regarding TCR flag event */
5026 /* Call the corresponding callback to inform upper layer of End of Transfer */
5027 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5028 }
5029 }
5030 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5031 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5032 {
5033 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5034 {
5035 direction = I2C_GENERATE_START_READ;
5036 }
5037
5038 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5039 {
5040 hi2c->XferSize = MAX_NBYTE_SIZE;
5041
5042 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5043 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5044 I2C_RELOAD_MODE, direction);
5045 }
5046 else
5047 {
5048 hi2c->XferSize = hi2c->XferCount;
5049
5050 /* Set NBYTES to write and generate RESTART */
5051 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5052 I2C_AUTOEND_MODE, direction);
5053 }
5054 }
5055 else
5056 {
5057 /* Nothing to do */
5058 }
5059
5060 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5061 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5062 {
5063 /* Call I2C Master complete process */
5064 I2C_ITMasterCplt(hi2c, tmpITFlags);
5065 }
5066
5067 /* Process Unlocked */
5068 __HAL_UNLOCK(hi2c);
5069
5070 return HAL_OK;
5071 }
5072
5073 /**
5074 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5075 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5076 * the configuration information for the specified I2C.
5077 * @param ITFlags Interrupt flags to handle.
5078 * @param ITSources Interrupt sources enabled.
5079 * @retval HAL status
5080 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5081 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5082 uint32_t ITSources)
5083 {
5084 uint32_t tmpoptions = hi2c->XferOptions;
5085 uint32_t tmpITFlags = ITFlags;
5086
5087 /* Process locked */
5088 __HAL_LOCK(hi2c);
5089
5090 /* Check if STOPF is set */
5091 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5092 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5093 {
5094 /* Call I2C Slave complete process */
5095 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5096 }
5097
5098 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5099 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5100 {
5101 /* Check that I2C transfer finished */
5102 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5103 /* Mean XferCount == 0*/
5104 /* So clear Flag NACKF only */
5105 if (hi2c->XferCount == 0U)
5106 {
5107 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5108 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5109 Warning[Pa134]: left and right operands are identical */
5110 {
5111 /* Call I2C Listen complete process */
5112 I2C_ITListenCplt(hi2c, tmpITFlags);
5113 }
5114 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5115 {
5116 /* Clear NACK Flag */
5117 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5118
5119 /* Flush TX register */
5120 I2C_Flush_TXDR(hi2c);
5121
5122 /* Last Byte is Transmitted */
5123 /* Call I2C Slave Sequential complete process */
5124 I2C_ITSlaveSeqCplt(hi2c);
5125 }
5126 else
5127 {
5128 /* Clear NACK Flag */
5129 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5130 }
5131 }
5132 else
5133 {
5134 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5135 /* Clear NACK Flag */
5136 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5137
5138 /* Set ErrorCode corresponding to a Non-Acknowledge */
5139 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5140
5141 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5142 {
5143 /* Call the corresponding callback to inform upper layer of End of Transfer */
5144 I2C_ITError(hi2c, hi2c->ErrorCode);
5145 }
5146 }
5147 }
5148 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5149 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5150 {
5151 if (hi2c->XferCount > 0U)
5152 {
5153 /* Read data from RXDR */
5154 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5155
5156 /* Increment Buffer pointer */
5157 hi2c->pBuffPtr++;
5158
5159 hi2c->XferSize--;
5160 hi2c->XferCount--;
5161 }
5162
5163 if ((hi2c->XferCount == 0U) && \
5164 (tmpoptions != I2C_NO_OPTION_FRAME))
5165 {
5166 /* Call I2C Slave Sequential complete process */
5167 I2C_ITSlaveSeqCplt(hi2c);
5168 }
5169 }
5170 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5171 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5172 {
5173 I2C_ITAddrCplt(hi2c, tmpITFlags);
5174 }
5175 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5176 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5177 {
5178 /* Write data to TXDR only if XferCount not reach "0" */
5179 /* A TXIS flag can be set, during STOP treatment */
5180 /* Check if all Data have already been sent */
5181 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5182 if (hi2c->XferCount > 0U)
5183 {
5184 /* Write data to TXDR */
5185 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5186
5187 /* Increment Buffer pointer */
5188 hi2c->pBuffPtr++;
5189
5190 hi2c->XferCount--;
5191 hi2c->XferSize--;
5192 }
5193 else
5194 {
5195 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5196 {
5197 /* Last Byte is Transmitted */
5198 /* Call I2C Slave Sequential complete process */
5199 I2C_ITSlaveSeqCplt(hi2c);
5200 }
5201 }
5202 }
5203 else
5204 {
5205 /* Nothing to do */
5206 }
5207
5208 /* Process Unlocked */
5209 __HAL_UNLOCK(hi2c);
5210
5211 return HAL_OK;
5212 }
5213
5214 /**
5215 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5216 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5217 * the configuration information for the specified I2C.
5218 * @param ITFlags Interrupt flags to handle.
5219 * @param ITSources Interrupt sources enabled.
5220 * @retval HAL status
5221 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5222 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5223 uint32_t ITSources)
5224 {
5225 uint16_t devaddress;
5226 uint32_t xfermode;
5227
5228 /* Process Locked */
5229 __HAL_LOCK(hi2c);
5230
5231 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5232 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5233 {
5234 /* Clear NACK Flag */
5235 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5236
5237 /* Set corresponding Error Code */
5238 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5239
5240 /* No need to generate STOP, it is automatically done */
5241 /* But enable STOP interrupt, to treat it */
5242 /* Error callback will be send during stop flag treatment */
5243 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5244
5245 /* Flush TX register */
5246 I2C_Flush_TXDR(hi2c);
5247 }
5248 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5249 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5250 {
5251 /* Disable TC interrupt */
5252 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5253
5254 if (hi2c->XferCount != 0U)
5255 {
5256 /* Recover Slave address */
5257 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5258
5259 /* Prepare the new XferSize to transfer */
5260 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5261 {
5262 hi2c->XferSize = MAX_NBYTE_SIZE;
5263 xfermode = I2C_RELOAD_MODE;
5264 }
5265 else
5266 {
5267 hi2c->XferSize = hi2c->XferCount;
5268 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5269 {
5270 xfermode = hi2c->XferOptions;
5271 }
5272 else
5273 {
5274 xfermode = I2C_AUTOEND_MODE;
5275 }
5276 }
5277
5278 /* Set the new XferSize in Nbytes register */
5279 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5280
5281 /* Update XferCount value */
5282 hi2c->XferCount -= hi2c->XferSize;
5283
5284 /* Enable DMA Request */
5285 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5286 {
5287 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5288 }
5289 else
5290 {
5291 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5292 }
5293 }
5294 else
5295 {
5296 /* Call TxCpltCallback() if no stop mode is set */
5297 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5298 {
5299 /* Call I2C Master Sequential complete process */
5300 I2C_ITMasterSeqCplt(hi2c);
5301 }
5302 else
5303 {
5304 /* Wrong size Status regarding TCR flag event */
5305 /* Call the corresponding callback to inform upper layer of End of Transfer */
5306 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5307 }
5308 }
5309 }
5310 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5311 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5312 {
5313 if (hi2c->XferCount == 0U)
5314 {
5315 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5316 {
5317 /* Generate a stop condition in case of no transfer option */
5318 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5319 {
5320 /* Generate Stop */
5321 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5322 }
5323 else
5324 {
5325 /* Call I2C Master Sequential complete process */
5326 I2C_ITMasterSeqCplt(hi2c);
5327 }
5328 }
5329 }
5330 else
5331 {
5332 /* Wrong size Status regarding TC flag event */
5333 /* Call the corresponding callback to inform upper layer of End of Transfer */
5334 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5335 }
5336 }
5337 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5338 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5339 {
5340 /* Call I2C Master complete process */
5341 I2C_ITMasterCplt(hi2c, ITFlags);
5342 }
5343 else
5344 {
5345 /* Nothing to do */
5346 }
5347
5348 /* Process Unlocked */
5349 __HAL_UNLOCK(hi2c);
5350
5351 return HAL_OK;
5352 }
5353
5354 /**
5355 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5356 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5357 * the configuration information for the specified I2C.
5358 * @param ITFlags Interrupt flags to handle.
5359 * @param ITSources Interrupt sources enabled.
5360 * @retval HAL status
5361 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5362 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5363 uint32_t ITSources)
5364 {
5365 uint32_t direction = I2C_GENERATE_START_WRITE;
5366
5367 /* Process Locked */
5368 __HAL_LOCK(hi2c);
5369
5370 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5371 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5372 {
5373 /* Clear NACK Flag */
5374 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5375
5376 /* Set corresponding Error Code */
5377 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5378
5379 /* No need to generate STOP, it is automatically done */
5380 /* But enable STOP interrupt, to treat it */
5381 /* Error callback will be send during stop flag treatment */
5382 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5383
5384 /* Flush TX register */
5385 I2C_Flush_TXDR(hi2c);
5386 }
5387 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5388 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5389 {
5390 /* Write LSB part of Memory Address */
5391 hi2c->Instance->TXDR = hi2c->Memaddress;
5392
5393 /* Reset Memaddress content */
5394 hi2c->Memaddress = 0xFFFFFFFFU;
5395 }
5396 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5397 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5398 {
5399 /* Enable only Error interrupt */
5400 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5401
5402 if (hi2c->XferCount != 0U)
5403 {
5404 /* Prepare the new XferSize to transfer */
5405 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5406 {
5407 hi2c->XferSize = MAX_NBYTE_SIZE;
5408 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5409 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5410 }
5411 else
5412 {
5413 hi2c->XferSize = hi2c->XferCount;
5414 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5415 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5416 }
5417
5418 /* Update XferCount value */
5419 hi2c->XferCount -= hi2c->XferSize;
5420
5421 /* Enable DMA Request */
5422 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5423 {
5424 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5425 }
5426 else
5427 {
5428 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5429 }
5430 }
5431 else
5432 {
5433 /* Wrong size Status regarding TCR flag event */
5434 /* Call the corresponding callback to inform upper layer of End of Transfer */
5435 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5436 }
5437 }
5438 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5439 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5440 {
5441 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5442 {
5443 direction = I2C_GENERATE_START_READ;
5444 }
5445
5446 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5447 {
5448 hi2c->XferSize = MAX_NBYTE_SIZE;
5449
5450 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5451 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5452 I2C_RELOAD_MODE, direction);
5453 }
5454 else
5455 {
5456 hi2c->XferSize = hi2c->XferCount;
5457
5458 /* Set NBYTES to write and generate RESTART */
5459 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5460 I2C_AUTOEND_MODE, direction);
5461 }
5462
5463 /* Update XferCount value */
5464 hi2c->XferCount -= hi2c->XferSize;
5465
5466 /* Enable DMA Request */
5467 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5468 {
5469 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5470 }
5471 else
5472 {
5473 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5474 }
5475 }
5476 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5477 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5478 {
5479 /* Call I2C Master complete process */
5480 I2C_ITMasterCplt(hi2c, ITFlags);
5481 }
5482 else
5483 {
5484 /* Nothing to do */
5485 }
5486
5487 /* Process Unlocked */
5488 __HAL_UNLOCK(hi2c);
5489
5490 return HAL_OK;
5491 }
5492
5493 /**
5494 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5495 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5496 * the configuration information for the specified I2C.
5497 * @param ITFlags Interrupt flags to handle.
5498 * @param ITSources Interrupt sources enabled.
5499 * @retval HAL status
5500 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5501 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5502 uint32_t ITSources)
5503 {
5504 uint32_t tmpoptions = hi2c->XferOptions;
5505 uint32_t treatdmanack = 0U;
5506 HAL_I2C_StateTypeDef tmpstate;
5507
5508 /* Process locked */
5509 __HAL_LOCK(hi2c);
5510
5511 /* Check if STOPF is set */
5512 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5513 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5514 {
5515 /* Call I2C Slave complete process */
5516 I2C_ITSlaveCplt(hi2c, ITFlags);
5517 }
5518
5519 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5520 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5521 {
5522 /* Check that I2C transfer finished */
5523 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5524 /* Mean XferCount == 0 */
5525 /* So clear Flag NACKF only */
5526 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5527 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5528 {
5529 /* Split check of hdmarx, for MISRA compliance */
5530 if (hi2c->hdmarx != NULL)
5531 {
5532 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5533 {
5534 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5535 {
5536 treatdmanack = 1U;
5537 }
5538 }
5539 }
5540
5541 /* Split check of hdmatx, for MISRA compliance */
5542 if (hi2c->hdmatx != NULL)
5543 {
5544 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5545 {
5546 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5547 {
5548 treatdmanack = 1U;
5549 }
5550 }
5551 }
5552
5553 if (treatdmanack == 1U)
5554 {
5555 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5556 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5557 Warning[Pa134]: left and right operands are identical */
5558 {
5559 /* Call I2C Listen complete process */
5560 I2C_ITListenCplt(hi2c, ITFlags);
5561 }
5562 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5563 {
5564 /* Clear NACK Flag */
5565 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5566
5567 /* Flush TX register */
5568 I2C_Flush_TXDR(hi2c);
5569
5570 /* Last Byte is Transmitted */
5571 /* Call I2C Slave Sequential complete process */
5572 I2C_ITSlaveSeqCplt(hi2c);
5573 }
5574 else
5575 {
5576 /* Clear NACK Flag */
5577 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5578 }
5579 }
5580 else
5581 {
5582 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5583 /* Clear NACK Flag */
5584 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5585
5586 /* Set ErrorCode corresponding to a Non-Acknowledge */
5587 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5588
5589 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5590 tmpstate = hi2c->State;
5591
5592 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5593 {
5594 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5595 {
5596 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5597 }
5598 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5599 {
5600 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5601 }
5602 else
5603 {
5604 /* Do nothing */
5605 }
5606
5607 /* Call the corresponding callback to inform upper layer of End of Transfer */
5608 I2C_ITError(hi2c, hi2c->ErrorCode);
5609 }
5610 }
5611 }
5612 else
5613 {
5614 /* Only Clear NACK Flag, no DMA treatment is pending */
5615 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5616 }
5617 }
5618 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5619 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5620 {
5621 I2C_ITAddrCplt(hi2c, ITFlags);
5622 }
5623 else
5624 {
5625 /* Nothing to do */
5626 }
5627
5628 /* Process Unlocked */
5629 __HAL_UNLOCK(hi2c);
5630
5631 return HAL_OK;
5632 }
5633
5634 /**
5635 * @brief Master sends target device address followed by internal memory address for write request.
5636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5637 * the configuration information for the specified I2C.
5638 * @param DevAddress Target device address: The device 7 bits address value
5639 * in datasheet must be shifted to the left before calling the interface
5640 * @param MemAddress Internal memory address
5641 * @param MemAddSize Size of internal memory address
5642 * @param Timeout Timeout duration
5643 * @param Tickstart Tick start value
5644 * @retval HAL status
5645 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5646 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5647 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5648 uint32_t Tickstart)
5649 {
5650 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5651
5652 /* Wait until TXIS flag is set */
5653 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5654 {
5655 return HAL_ERROR;
5656 }
5657
5658 /* If Memory address size is 8Bit */
5659 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5660 {
5661 /* Send Memory Address */
5662 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5663 }
5664 /* If Memory address size is 16Bit */
5665 else
5666 {
5667 /* Send MSB of Memory Address */
5668 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5669
5670 /* Wait until TXIS flag is set */
5671 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5672 {
5673 return HAL_ERROR;
5674 }
5675
5676 /* Send LSB of Memory Address */
5677 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5678 }
5679
5680 /* Wait until TCR flag is set */
5681 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5682 {
5683 return HAL_ERROR;
5684 }
5685
5686 return HAL_OK;
5687 }
5688
5689 /**
5690 * @brief Master sends target device address followed by internal memory address for read request.
5691 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5692 * the configuration information for the specified I2C.
5693 * @param DevAddress Target device address: The device 7 bits address value
5694 * in datasheet must be shifted to the left before calling the interface
5695 * @param MemAddress Internal memory address
5696 * @param MemAddSize Size of internal memory address
5697 * @param Timeout Timeout duration
5698 * @param Tickstart Tick start value
5699 * @retval HAL status
5700 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5701 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5702 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5703 uint32_t Tickstart)
5704 {
5705 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5706
5707 /* Wait until TXIS flag is set */
5708 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5709 {
5710 return HAL_ERROR;
5711 }
5712
5713 /* If Memory address size is 8Bit */
5714 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5715 {
5716 /* Send Memory Address */
5717 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5718 }
5719 /* If Memory address size is 16Bit */
5720 else
5721 {
5722 /* Send MSB of Memory Address */
5723 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5724
5725 /* Wait until TXIS flag is set */
5726 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5727 {
5728 return HAL_ERROR;
5729 }
5730
5731 /* Send LSB of Memory Address */
5732 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5733 }
5734
5735 /* Wait until TC flag is set */
5736 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5737 {
5738 return HAL_ERROR;
5739 }
5740
5741 return HAL_OK;
5742 }
5743
5744 /**
5745 * @brief I2C Address complete process callback.
5746 * @param hi2c I2C handle.
5747 * @param ITFlags Interrupt flags to handle.
5748 * @retval None
5749 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5750 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5751 {
5752 uint8_t transferdirection;
5753 uint16_t slaveaddrcode;
5754 uint16_t ownadd1code;
5755 uint16_t ownadd2code;
5756
5757 /* Prevent unused argument(s) compilation warning */
5758 UNUSED(ITFlags);
5759
5760 /* In case of Listen state, need to inform upper layer of address match code event */
5761 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5762 {
5763 transferdirection = I2C_GET_DIR(hi2c);
5764 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5765 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5766 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5767
5768 /* If 10bits addressing mode is selected */
5769 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5770 {
5771 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5772 {
5773 slaveaddrcode = ownadd1code;
5774 hi2c->AddrEventCount++;
5775 if (hi2c->AddrEventCount == 2U)
5776 {
5777 /* Reset Address Event counter */
5778 hi2c->AddrEventCount = 0U;
5779
5780 /* Clear ADDR flag */
5781 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5782
5783 /* Process Unlocked */
5784 __HAL_UNLOCK(hi2c);
5785
5786 /* Call Slave Addr callback */
5787 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5788 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5789 #else
5790 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5791 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5792 }
5793 }
5794 else
5795 {
5796 slaveaddrcode = ownadd2code;
5797
5798 /* Disable ADDR Interrupts */
5799 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5800
5801 /* Process Unlocked */
5802 __HAL_UNLOCK(hi2c);
5803
5804 /* Call Slave Addr callback */
5805 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5806 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5807 #else
5808 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5809 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5810 }
5811 }
5812 /* else 7 bits addressing mode is selected */
5813 else
5814 {
5815 /* Disable ADDR Interrupts */
5816 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5817
5818 /* Process Unlocked */
5819 __HAL_UNLOCK(hi2c);
5820
5821 /* Call Slave Addr callback */
5822 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5823 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5824 #else
5825 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5826 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5827 }
5828 }
5829 /* Else clear address flag only */
5830 else
5831 {
5832 /* Clear ADDR flag */
5833 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5834
5835 /* Process Unlocked */
5836 __HAL_UNLOCK(hi2c);
5837 }
5838 }
5839
5840 /**
5841 * @brief I2C Master sequential complete process.
5842 * @param hi2c I2C handle.
5843 * @retval None
5844 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5845 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5846 {
5847 /* Reset I2C handle mode */
5848 hi2c->Mode = HAL_I2C_MODE_NONE;
5849
5850 /* No Generate Stop, to permit restart mode */
5851 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5852 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5853 {
5854 hi2c->State = HAL_I2C_STATE_READY;
5855 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5856 hi2c->XferISR = NULL;
5857
5858 /* Disable Interrupts */
5859 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5860
5861 /* Process Unlocked */
5862 __HAL_UNLOCK(hi2c);
5863
5864 /* Call the corresponding callback to inform upper layer of End of Transfer */
5865 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5866 hi2c->MasterTxCpltCallback(hi2c);
5867 #else
5868 HAL_I2C_MasterTxCpltCallback(hi2c);
5869 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5870 }
5871 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5872 else
5873 {
5874 hi2c->State = HAL_I2C_STATE_READY;
5875 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5876 hi2c->XferISR = NULL;
5877
5878 /* Disable Interrupts */
5879 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5880
5881 /* Process Unlocked */
5882 __HAL_UNLOCK(hi2c);
5883
5884 /* Call the corresponding callback to inform upper layer of End of Transfer */
5885 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5886 hi2c->MasterRxCpltCallback(hi2c);
5887 #else
5888 HAL_I2C_MasterRxCpltCallback(hi2c);
5889 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5890 }
5891 }
5892
5893 /**
5894 * @brief I2C Slave sequential complete process.
5895 * @param hi2c I2C handle.
5896 * @retval None
5897 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)5898 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5899 {
5900 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5901
5902 /* Reset I2C handle mode */
5903 hi2c->Mode = HAL_I2C_MODE_NONE;
5904
5905 /* If a DMA is ongoing, Update handle size context */
5906 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5907 {
5908 /* Disable DMA Request */
5909 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5910 }
5911 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5912 {
5913 /* Disable DMA Request */
5914 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5915 }
5916 else
5917 {
5918 /* Do nothing */
5919 }
5920
5921 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5922 {
5923 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5924 hi2c->State = HAL_I2C_STATE_LISTEN;
5925 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5926
5927 /* Disable Interrupts */
5928 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5929
5930 /* Process Unlocked */
5931 __HAL_UNLOCK(hi2c);
5932
5933 /* Call the corresponding callback to inform upper layer of End of Transfer */
5934 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5935 hi2c->SlaveTxCpltCallback(hi2c);
5936 #else
5937 HAL_I2C_SlaveTxCpltCallback(hi2c);
5938 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5939 }
5940
5941 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5942 {
5943 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5944 hi2c->State = HAL_I2C_STATE_LISTEN;
5945 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5946
5947 /* Disable Interrupts */
5948 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5949
5950 /* Process Unlocked */
5951 __HAL_UNLOCK(hi2c);
5952
5953 /* Call the corresponding callback to inform upper layer of End of Transfer */
5954 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5955 hi2c->SlaveRxCpltCallback(hi2c);
5956 #else
5957 HAL_I2C_SlaveRxCpltCallback(hi2c);
5958 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5959 }
5960 else
5961 {
5962 /* Nothing to do */
5963 }
5964 }
5965
5966 /**
5967 * @brief I2C Master complete process.
5968 * @param hi2c I2C handle.
5969 * @param ITFlags Interrupt flags to handle.
5970 * @retval None
5971 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5972 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5973 {
5974 uint32_t tmperror;
5975 uint32_t tmpITFlags = ITFlags;
5976 __IO uint32_t tmpreg;
5977
5978 /* Clear STOP Flag */
5979 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5980
5981 /* Disable Interrupts and Store Previous state */
5982 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5983 {
5984 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5985 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5986 }
5987 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5988 {
5989 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5990 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5991 }
5992 else
5993 {
5994 /* Do nothing */
5995 }
5996
5997 /* Clear Configuration Register 2 */
5998 I2C_RESET_CR2(hi2c);
5999
6000 /* Reset handle parameters */
6001 hi2c->XferISR = NULL;
6002 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6003
6004 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6005 {
6006 /* Clear NACK Flag */
6007 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6008
6009 /* Set acknowledge error code */
6010 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6011 }
6012
6013 /* Fetch Last receive data if any */
6014 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6015 {
6016 /* Read data from RXDR */
6017 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6018 UNUSED(tmpreg);
6019 }
6020
6021 /* Flush TX register */
6022 I2C_Flush_TXDR(hi2c);
6023
6024 /* Store current volatile hi2c->ErrorCode, misra rule */
6025 tmperror = hi2c->ErrorCode;
6026
6027 /* Call the corresponding callback to inform upper layer of End of Transfer */
6028 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6029 {
6030 /* Call the corresponding callback to inform upper layer of End of Transfer */
6031 I2C_ITError(hi2c, hi2c->ErrorCode);
6032 }
6033 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6034 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6035 {
6036 hi2c->State = HAL_I2C_STATE_READY;
6037 hi2c->PreviousState = I2C_STATE_NONE;
6038
6039 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6040 {
6041 hi2c->Mode = HAL_I2C_MODE_NONE;
6042
6043 /* Process Unlocked */
6044 __HAL_UNLOCK(hi2c);
6045
6046 /* Call the corresponding callback to inform upper layer of End of Transfer */
6047 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6048 hi2c->MemTxCpltCallback(hi2c);
6049 #else
6050 HAL_I2C_MemTxCpltCallback(hi2c);
6051 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6052 }
6053 else
6054 {
6055 hi2c->Mode = HAL_I2C_MODE_NONE;
6056
6057 /* Process Unlocked */
6058 __HAL_UNLOCK(hi2c);
6059
6060 /* Call the corresponding callback to inform upper layer of End of Transfer */
6061 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6062 hi2c->MasterTxCpltCallback(hi2c);
6063 #else
6064 HAL_I2C_MasterTxCpltCallback(hi2c);
6065 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6066 }
6067 }
6068 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6069 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6070 {
6071 hi2c->State = HAL_I2C_STATE_READY;
6072 hi2c->PreviousState = I2C_STATE_NONE;
6073
6074 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6075 {
6076 hi2c->Mode = HAL_I2C_MODE_NONE;
6077
6078 /* Process Unlocked */
6079 __HAL_UNLOCK(hi2c);
6080
6081 /* Call the corresponding callback to inform upper layer of End of Transfer */
6082 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6083 hi2c->MemRxCpltCallback(hi2c);
6084 #else
6085 HAL_I2C_MemRxCpltCallback(hi2c);
6086 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6087 }
6088 else
6089 {
6090 hi2c->Mode = HAL_I2C_MODE_NONE;
6091
6092 /* Process Unlocked */
6093 __HAL_UNLOCK(hi2c);
6094
6095 /* Call the corresponding callback to inform upper layer of End of Transfer */
6096 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6097 hi2c->MasterRxCpltCallback(hi2c);
6098 #else
6099 HAL_I2C_MasterRxCpltCallback(hi2c);
6100 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6101 }
6102 }
6103 else
6104 {
6105 /* Nothing to do */
6106 }
6107 }
6108
6109 /**
6110 * @brief I2C Slave complete process.
6111 * @param hi2c I2C handle.
6112 * @param ITFlags Interrupt flags to handle.
6113 * @retval None
6114 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6115 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6116 {
6117 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6118 uint32_t tmpITFlags = ITFlags;
6119 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6120
6121 /* Clear STOP Flag */
6122 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6123
6124 /* Disable Interrupts and Store Previous state */
6125 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6126 {
6127 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6128 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6129 }
6130 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6131 {
6132 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6133 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6134 }
6135 else
6136 {
6137 /* Do nothing */
6138 }
6139
6140 /* Disable Address Acknowledge */
6141 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6142
6143 /* Clear Configuration Register 2 */
6144 I2C_RESET_CR2(hi2c);
6145
6146 /* Flush TX register */
6147 I2C_Flush_TXDR(hi2c);
6148
6149 /* If a DMA is ongoing, Update handle size context */
6150 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6151 {
6152 /* Disable DMA Request */
6153 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6154
6155 if (hi2c->hdmatx != NULL)
6156 {
6157 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6158 }
6159 }
6160 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6161 {
6162 /* Disable DMA Request */
6163 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6164
6165 if (hi2c->hdmarx != NULL)
6166 {
6167 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6168 }
6169 }
6170 else
6171 {
6172 /* Do nothing */
6173 }
6174
6175 /* Store Last receive data if any */
6176 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6177 {
6178 /* Remove RXNE flag on temporary variable as read done */
6179 tmpITFlags &= ~I2C_FLAG_RXNE;
6180
6181 /* Read data from RXDR */
6182 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6183
6184 /* Increment Buffer pointer */
6185 hi2c->pBuffPtr++;
6186
6187 if ((hi2c->XferSize > 0U))
6188 {
6189 hi2c->XferSize--;
6190 hi2c->XferCount--;
6191 }
6192 }
6193
6194 /* All data are not transferred, so set error code accordingly */
6195 if (hi2c->XferCount != 0U)
6196 {
6197 /* Set ErrorCode corresponding to a Non-Acknowledge */
6198 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6199 }
6200
6201 hi2c->Mode = HAL_I2C_MODE_NONE;
6202 hi2c->XferISR = NULL;
6203
6204 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6205 {
6206 /* Call the corresponding callback to inform upper layer of End of Transfer */
6207 I2C_ITError(hi2c, hi2c->ErrorCode);
6208
6209 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6210 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6211 {
6212 /* Call I2C Listen complete process */
6213 I2C_ITListenCplt(hi2c, tmpITFlags);
6214 }
6215 }
6216 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6217 {
6218 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6219 I2C_ITSlaveSeqCplt(hi2c);
6220
6221 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6222 hi2c->State = HAL_I2C_STATE_READY;
6223 hi2c->PreviousState = I2C_STATE_NONE;
6224
6225 /* Process Unlocked */
6226 __HAL_UNLOCK(hi2c);
6227
6228 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6229 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6230 hi2c->ListenCpltCallback(hi2c);
6231 #else
6232 HAL_I2C_ListenCpltCallback(hi2c);
6233 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6234 }
6235 /* Call the corresponding callback to inform upper layer of End of Transfer */
6236 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6237 {
6238 hi2c->State = HAL_I2C_STATE_READY;
6239 hi2c->PreviousState = I2C_STATE_NONE;
6240
6241 /* Process Unlocked */
6242 __HAL_UNLOCK(hi2c);
6243
6244 /* Call the corresponding callback to inform upper layer of End of Transfer */
6245 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6246 hi2c->SlaveRxCpltCallback(hi2c);
6247 #else
6248 HAL_I2C_SlaveRxCpltCallback(hi2c);
6249 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6250 }
6251 else
6252 {
6253 hi2c->State = HAL_I2C_STATE_READY;
6254 hi2c->PreviousState = I2C_STATE_NONE;
6255
6256 /* Process Unlocked */
6257 __HAL_UNLOCK(hi2c);
6258
6259 /* Call the corresponding callback to inform upper layer of End of Transfer */
6260 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6261 hi2c->SlaveTxCpltCallback(hi2c);
6262 #else
6263 HAL_I2C_SlaveTxCpltCallback(hi2c);
6264 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6265 }
6266 }
6267
6268 /**
6269 * @brief I2C Listen complete process.
6270 * @param hi2c I2C handle.
6271 * @param ITFlags Interrupt flags to handle.
6272 * @retval None
6273 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6274 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6275 {
6276 /* Reset handle parameters */
6277 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6278 hi2c->PreviousState = I2C_STATE_NONE;
6279 hi2c->State = HAL_I2C_STATE_READY;
6280 hi2c->Mode = HAL_I2C_MODE_NONE;
6281 hi2c->XferISR = NULL;
6282
6283 /* Store Last receive data if any */
6284 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6285 {
6286 /* Read data from RXDR */
6287 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6288
6289 /* Increment Buffer pointer */
6290 hi2c->pBuffPtr++;
6291
6292 if ((hi2c->XferSize > 0U))
6293 {
6294 hi2c->XferSize--;
6295 hi2c->XferCount--;
6296
6297 /* Set ErrorCode corresponding to a Non-Acknowledge */
6298 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6299 }
6300 }
6301
6302 /* Disable all Interrupts*/
6303 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6304
6305 /* Clear NACK Flag */
6306 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6307
6308 /* Process Unlocked */
6309 __HAL_UNLOCK(hi2c);
6310
6311 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6312 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6313 hi2c->ListenCpltCallback(hi2c);
6314 #else
6315 HAL_I2C_ListenCpltCallback(hi2c);
6316 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6317 }
6318
6319 /**
6320 * @brief I2C interrupts error process.
6321 * @param hi2c I2C handle.
6322 * @param ErrorCode Error code to handle.
6323 * @retval None
6324 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6325 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6326 {
6327 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6328 uint32_t tmppreviousstate;
6329
6330 /* Reset handle parameters */
6331 hi2c->Mode = HAL_I2C_MODE_NONE;
6332 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6333 hi2c->XferCount = 0U;
6334
6335 /* Set new error code */
6336 hi2c->ErrorCode |= ErrorCode;
6337
6338 /* Disable Interrupts */
6339 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6340 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6341 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6342 {
6343 /* Disable all interrupts, except interrupts related to LISTEN state */
6344 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6345
6346 /* keep HAL_I2C_STATE_LISTEN if set */
6347 hi2c->State = HAL_I2C_STATE_LISTEN;
6348 hi2c->XferISR = I2C_Slave_ISR_IT;
6349 }
6350 else
6351 {
6352 /* Disable all interrupts */
6353 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6354
6355 /* Flush TX register */
6356 I2C_Flush_TXDR(hi2c);
6357
6358 /* If state is an abort treatment on going, don't change state */
6359 /* This change will be do later */
6360 if (hi2c->State != HAL_I2C_STATE_ABORT)
6361 {
6362 /* Set HAL_I2C_STATE_READY */
6363 hi2c->State = HAL_I2C_STATE_READY;
6364
6365 /* Check if a STOPF is detected */
6366 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6367 {
6368 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6369 {
6370 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6371 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6372 }
6373
6374 /* Clear STOP Flag */
6375 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6376 }
6377
6378 }
6379 hi2c->XferISR = NULL;
6380 }
6381
6382 /* Abort DMA TX transfer if any */
6383 tmppreviousstate = hi2c->PreviousState;
6384 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6385 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6386 {
6387 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6388 {
6389 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6390 }
6391
6392 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6393 {
6394 /* Set the I2C DMA Abort callback :
6395 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6396 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6397
6398 /* Process Unlocked */
6399 __HAL_UNLOCK(hi2c);
6400
6401 /* Abort DMA TX */
6402 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6403 {
6404 /* Call Directly XferAbortCallback function in case of error */
6405 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6406 }
6407 }
6408 else
6409 {
6410 I2C_TreatErrorCallback(hi2c);
6411 }
6412 }
6413 /* Abort DMA RX transfer if any */
6414 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6415 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6416 {
6417 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6418 {
6419 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6420 }
6421
6422 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6423 {
6424 /* Set the I2C DMA Abort callback :
6425 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6426 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6427
6428 /* Process Unlocked */
6429 __HAL_UNLOCK(hi2c);
6430
6431 /* Abort DMA RX */
6432 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6433 {
6434 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6435 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6436 }
6437 }
6438 else
6439 {
6440 I2C_TreatErrorCallback(hi2c);
6441 }
6442 }
6443 else
6444 {
6445 I2C_TreatErrorCallback(hi2c);
6446 }
6447 }
6448
6449 /**
6450 * @brief I2C Error callback treatment.
6451 * @param hi2c I2C handle.
6452 * @retval None
6453 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6454 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6455 {
6456 if (hi2c->State == HAL_I2C_STATE_ABORT)
6457 {
6458 hi2c->State = HAL_I2C_STATE_READY;
6459 hi2c->PreviousState = I2C_STATE_NONE;
6460
6461 /* Process Unlocked */
6462 __HAL_UNLOCK(hi2c);
6463
6464 /* Call the corresponding callback to inform upper layer of End of Transfer */
6465 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6466 hi2c->AbortCpltCallback(hi2c);
6467 #else
6468 HAL_I2C_AbortCpltCallback(hi2c);
6469 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6470 }
6471 else
6472 {
6473 hi2c->PreviousState = I2C_STATE_NONE;
6474
6475 /* Process Unlocked */
6476 __HAL_UNLOCK(hi2c);
6477
6478 /* Call the corresponding callback to inform upper layer of End of Transfer */
6479 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6480 hi2c->ErrorCallback(hi2c);
6481 #else
6482 HAL_I2C_ErrorCallback(hi2c);
6483 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6484 }
6485 }
6486
6487 /**
6488 * @brief I2C Tx data register flush process.
6489 * @param hi2c I2C handle.
6490 * @retval None
6491 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6492 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6493 {
6494 /* If a pending TXIS flag is set */
6495 /* Write a dummy data in TXDR to clear it */
6496 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6497 {
6498 hi2c->Instance->TXDR = 0x00U;
6499 }
6500
6501 /* Flush TX register if not empty */
6502 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6503 {
6504 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6505 }
6506 }
6507
6508 /**
6509 * @brief DMA I2C master transmit process complete callback.
6510 * @param hdma DMA handle
6511 * @retval None
6512 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6513 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6514 {
6515 /* Derogation MISRAC2012-Rule-11.5 */
6516 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6517
6518 /* Disable DMA Request */
6519 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6520
6521 /* If last transfer, enable STOP interrupt */
6522 if (hi2c->XferCount == 0U)
6523 {
6524 /* Enable STOP interrupt */
6525 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6526 }
6527 /* else prepare a new DMA transfer and enable TCReload interrupt */
6528 else
6529 {
6530 /* Update Buffer pointer */
6531 hi2c->pBuffPtr += hi2c->XferSize;
6532
6533 /* Set the XferSize to transfer */
6534 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6535 {
6536 hi2c->XferSize = MAX_NBYTE_SIZE;
6537 }
6538 else
6539 {
6540 hi2c->XferSize = hi2c->XferCount;
6541 }
6542
6543 /* Enable the DMA channel */
6544 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6545 hi2c->XferSize) != HAL_OK)
6546 {
6547 /* Call the corresponding callback to inform upper layer of End of Transfer */
6548 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6549 }
6550 else
6551 {
6552 /* Enable TC interrupts */
6553 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6554 }
6555 }
6556 }
6557
6558 /**
6559 * @brief DMA I2C slave transmit process complete callback.
6560 * @param hdma DMA handle
6561 * @retval None
6562 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6563 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6564 {
6565 /* Derogation MISRAC2012-Rule-11.5 */
6566 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6567 uint32_t tmpoptions = hi2c->XferOptions;
6568
6569 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6570 {
6571 /* Disable DMA Request */
6572 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6573
6574 /* Last Byte is Transmitted */
6575 /* Call I2C Slave Sequential complete process */
6576 I2C_ITSlaveSeqCplt(hi2c);
6577 }
6578 else
6579 {
6580 /* No specific action, Master fully manage the generation of STOP condition */
6581 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6582 /* So STOP condition should be manage through Interrupt treatment */
6583 }
6584 }
6585
6586 /**
6587 * @brief DMA I2C master receive process complete callback.
6588 * @param hdma DMA handle
6589 * @retval None
6590 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6591 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6592 {
6593 /* Derogation MISRAC2012-Rule-11.5 */
6594 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6595
6596 /* Disable DMA Request */
6597 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6598
6599 /* If last transfer, enable STOP interrupt */
6600 if (hi2c->XferCount == 0U)
6601 {
6602 /* Enable STOP interrupt */
6603 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6604 }
6605 /* else prepare a new DMA transfer and enable TCReload interrupt */
6606 else
6607 {
6608 /* Update Buffer pointer */
6609 hi2c->pBuffPtr += hi2c->XferSize;
6610
6611 /* Set the XferSize to transfer */
6612 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6613 {
6614 hi2c->XferSize = MAX_NBYTE_SIZE;
6615 }
6616 else
6617 {
6618 hi2c->XferSize = hi2c->XferCount;
6619 }
6620
6621 /* Enable the DMA channel */
6622 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6623 hi2c->XferSize) != HAL_OK)
6624 {
6625 /* Call the corresponding callback to inform upper layer of End of Transfer */
6626 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6627 }
6628 else
6629 {
6630 /* Enable TC interrupts */
6631 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6632 }
6633 }
6634 }
6635
6636 /**
6637 * @brief DMA I2C slave receive process complete callback.
6638 * @param hdma DMA handle
6639 * @retval None
6640 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6641 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6642 {
6643 /* Derogation MISRAC2012-Rule-11.5 */
6644 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6645 uint32_t tmpoptions = hi2c->XferOptions;
6646
6647 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6648 (tmpoptions != I2C_NO_OPTION_FRAME))
6649 {
6650 /* Disable DMA Request */
6651 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6652
6653 /* Call I2C Slave Sequential complete process */
6654 I2C_ITSlaveSeqCplt(hi2c);
6655 }
6656 else
6657 {
6658 /* No specific action, Master fully manage the generation of STOP condition */
6659 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6660 /* So STOP condition should be manage through Interrupt treatment */
6661 }
6662 }
6663
6664 /**
6665 * @brief DMA I2C communication error callback.
6666 * @param hdma DMA handle
6667 * @retval None
6668 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6669 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6670 {
6671 /* Derogation MISRAC2012-Rule-11.5 */
6672 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6673
6674 /* Disable Acknowledge */
6675 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6676
6677 /* Call the corresponding callback to inform upper layer of End of Transfer */
6678 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6679 }
6680
6681 /**
6682 * @brief DMA I2C communication abort callback
6683 * (To be called at end of DMA Abort procedure).
6684 * @param hdma DMA handle.
6685 * @retval None
6686 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6687 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6688 {
6689 /* Derogation MISRAC2012-Rule-11.5 */
6690 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6691
6692 /* Reset AbortCpltCallback */
6693 if (hi2c->hdmatx != NULL)
6694 {
6695 hi2c->hdmatx->XferAbortCallback = NULL;
6696 }
6697 if (hi2c->hdmarx != NULL)
6698 {
6699 hi2c->hdmarx->XferAbortCallback = NULL;
6700 }
6701
6702 I2C_TreatErrorCallback(hi2c);
6703 }
6704
6705 /**
6706 * @brief This function handles I2C Communication Timeout. It waits
6707 * until a flag is no longer in the specified status.
6708 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6709 * the configuration information for the specified I2C.
6710 * @param Flag Specifies the I2C flag to check.
6711 * @param Status The actual Flag status (SET or RESET).
6712 * @param Timeout Timeout duration
6713 * @param Tickstart Tick start value
6714 * @retval HAL status
6715 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6716 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6717 uint32_t Timeout, uint32_t Tickstart)
6718 {
6719 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6720 {
6721 /* Check for the Timeout */
6722 if (Timeout != HAL_MAX_DELAY)
6723 {
6724 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6725 {
6726 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
6727 {
6728 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6729 hi2c->State = HAL_I2C_STATE_READY;
6730 hi2c->Mode = HAL_I2C_MODE_NONE;
6731
6732 /* Process Unlocked */
6733 __HAL_UNLOCK(hi2c);
6734 return HAL_ERROR;
6735 }
6736 }
6737 }
6738 }
6739 return HAL_OK;
6740 }
6741
6742 /**
6743 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6744 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6745 * the configuration information for the specified I2C.
6746 * @param Timeout Timeout duration
6747 * @param Tickstart Tick start value
6748 * @retval HAL status
6749 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6750 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6751 uint32_t Tickstart)
6752 {
6753 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6754 {
6755 /* Check if an error is detected */
6756 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6757 {
6758 return HAL_ERROR;
6759 }
6760
6761 /* Check for the Timeout */
6762 if (Timeout != HAL_MAX_DELAY)
6763 {
6764 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6765 {
6766 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
6767 {
6768 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6769 hi2c->State = HAL_I2C_STATE_READY;
6770 hi2c->Mode = HAL_I2C_MODE_NONE;
6771
6772 /* Process Unlocked */
6773 __HAL_UNLOCK(hi2c);
6774
6775 return HAL_ERROR;
6776 }
6777 }
6778 }
6779 }
6780 return HAL_OK;
6781 }
6782
6783 /**
6784 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6785 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6786 * the configuration information for the specified I2C.
6787 * @param Timeout Timeout duration
6788 * @param Tickstart Tick start value
6789 * @retval HAL status
6790 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6791 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6792 uint32_t Tickstart)
6793 {
6794 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6795 {
6796 /* Check if an error is detected */
6797 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6798 {
6799 return HAL_ERROR;
6800 }
6801
6802 /* Check for the Timeout */
6803 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6804 {
6805 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
6806 {
6807 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6808 hi2c->State = HAL_I2C_STATE_READY;
6809 hi2c->Mode = HAL_I2C_MODE_NONE;
6810
6811 /* Process Unlocked */
6812 __HAL_UNLOCK(hi2c);
6813
6814 return HAL_ERROR;
6815 }
6816 }
6817 }
6818 return HAL_OK;
6819 }
6820
6821 /**
6822 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
6823 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6824 * the configuration information for the specified I2C.
6825 * @param Timeout Timeout duration
6826 * @param Tickstart Tick start value
6827 * @retval HAL status
6828 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6829 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6830 uint32_t Tickstart)
6831 {
6832 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6833 {
6834 /* Check if an error is detected */
6835 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6836 {
6837 return HAL_ERROR;
6838 }
6839
6840 /* Check if a STOPF is detected */
6841 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6842 {
6843 /* Check if an RXNE is pending */
6844 /* Store Last receive data if any */
6845 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
6846 {
6847 /* Return HAL_OK */
6848 /* The Reading of data from RXDR will be done in caller function */
6849 return HAL_OK;
6850 }
6851 else
6852 {
6853 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6854 {
6855 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6856 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
6857 }
6858 else
6859 {
6860 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6861 }
6862
6863 /* Clear STOP Flag */
6864 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6865
6866 /* Clear Configuration Register 2 */
6867 I2C_RESET_CR2(hi2c);
6868
6869 hi2c->State = HAL_I2C_STATE_READY;
6870 hi2c->Mode = HAL_I2C_MODE_NONE;
6871
6872 /* Process Unlocked */
6873 __HAL_UNLOCK(hi2c);
6874
6875 return HAL_ERROR;
6876 }
6877 }
6878
6879 /* Check for the Timeout */
6880 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6881 {
6882 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
6883 {
6884 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6885 hi2c->State = HAL_I2C_STATE_READY;
6886
6887 /* Process Unlocked */
6888 __HAL_UNLOCK(hi2c);
6889
6890 return HAL_ERROR;
6891 }
6892 }
6893 }
6894 return HAL_OK;
6895 }
6896
6897 /**
6898 * @brief This function handles errors detection during an I2C Communication.
6899 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6900 * the configuration information for the specified I2C.
6901 * @param Timeout Timeout duration
6902 * @param Tickstart Tick start value
6903 * @retval HAL status
6904 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6905 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6906 {
6907 HAL_StatusTypeDef status = HAL_OK;
6908 uint32_t itflag = hi2c->Instance->ISR;
6909 uint32_t error_code = 0;
6910 uint32_t tickstart = Tickstart;
6911 uint32_t tmp1;
6912 HAL_I2C_ModeTypeDef tmp2;
6913
6914 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
6915 {
6916 /* Clear NACKF Flag */
6917 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6918
6919 /* Wait until STOP Flag is set or timeout occurred */
6920 /* AutoEnd should be initiate after AF */
6921 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
6922 {
6923 /* Check for the Timeout */
6924 if (Timeout != HAL_MAX_DELAY)
6925 {
6926 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6927 {
6928 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
6929 tmp2 = hi2c->Mode;
6930
6931 /* In case of I2C still busy, try to regenerate a STOP manually */
6932 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
6933 (tmp1 != I2C_CR2_STOP) && \
6934 (tmp2 != HAL_I2C_MODE_SLAVE))
6935 {
6936 /* Generate Stop */
6937 hi2c->Instance->CR2 |= I2C_CR2_STOP;
6938
6939 /* Update Tick with new reference */
6940 tickstart = HAL_GetTick();
6941 }
6942
6943 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6944 {
6945 /* Check for the Timeout */
6946 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
6947 {
6948 error_code |= HAL_I2C_ERROR_TIMEOUT;
6949
6950 status = HAL_ERROR;
6951
6952 break;
6953 }
6954 }
6955 }
6956 }
6957 }
6958
6959 /* In case STOP Flag is detected, clear it */
6960 if (status == HAL_OK)
6961 {
6962 /* Clear STOP Flag */
6963 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6964 }
6965
6966 error_code |= HAL_I2C_ERROR_AF;
6967
6968 status = HAL_ERROR;
6969 }
6970
6971 /* Refresh Content of Status register */
6972 itflag = hi2c->Instance->ISR;
6973
6974 /* Then verify if an additional errors occurs */
6975 /* Check if a Bus error occurred */
6976 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
6977 {
6978 error_code |= HAL_I2C_ERROR_BERR;
6979
6980 /* Clear BERR flag */
6981 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
6982
6983 status = HAL_ERROR;
6984 }
6985
6986 /* Check if an Over-Run/Under-Run error occurred */
6987 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
6988 {
6989 error_code |= HAL_I2C_ERROR_OVR;
6990
6991 /* Clear OVR flag */
6992 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
6993
6994 status = HAL_ERROR;
6995 }
6996
6997 /* Check if an Arbitration Loss error occurred */
6998 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
6999 {
7000 error_code |= HAL_I2C_ERROR_ARLO;
7001
7002 /* Clear ARLO flag */
7003 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7004
7005 status = HAL_ERROR;
7006 }
7007
7008 if (status != HAL_OK)
7009 {
7010 /* Flush TX register */
7011 I2C_Flush_TXDR(hi2c);
7012
7013 /* Clear Configuration Register 2 */
7014 I2C_RESET_CR2(hi2c);
7015
7016 hi2c->ErrorCode |= error_code;
7017 hi2c->State = HAL_I2C_STATE_READY;
7018 hi2c->Mode = HAL_I2C_MODE_NONE;
7019
7020 /* Process Unlocked */
7021 __HAL_UNLOCK(hi2c);
7022 }
7023
7024 return status;
7025 }
7026
7027 /**
7028 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7029 * @param hi2c I2C handle.
7030 * @param DevAddress Specifies the slave address to be programmed.
7031 * @param Size Specifies the number of bytes to be programmed.
7032 * This parameter must be a value between 0 and 255.
7033 * @param Mode New state of the I2C START condition generation.
7034 * This parameter can be one of the following values:
7035 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7036 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7037 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7038 * @param Request New state of the I2C START condition generation.
7039 * This parameter can be one of the following values:
7040 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7041 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7042 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7043 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7044 * @retval None
7045 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7046 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7047 uint32_t Request)
7048 {
7049 /* Check the parameters */
7050 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7051 assert_param(IS_TRANSFER_MODE(Mode));
7052 assert_param(IS_TRANSFER_REQUEST(Request));
7053
7054 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7055 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7056 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7057 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7058
7059 /* update CR2 register */
7060 MODIFY_REG(hi2c->Instance->CR2, \
7061 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7062 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7063 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7064 }
7065
7066 /**
7067 * @brief Manage the enabling of Interrupts.
7068 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7069 * the configuration information for the specified I2C.
7070 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7071 * @retval None
7072 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7073 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7074 {
7075 uint32_t tmpisr = 0U;
7076
7077 if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
7078 (hi2c->XferISR == I2C_Slave_ISR_DMA))
7079 {
7080 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7081 {
7082 /* Enable ERR, STOP, NACK and ADDR interrupts */
7083 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7084 }
7085
7086 if (InterruptRequest == I2C_XFER_ERROR_IT)
7087 {
7088 /* Enable ERR and NACK interrupts */
7089 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7090 }
7091
7092 if (InterruptRequest == I2C_XFER_CPLT_IT)
7093 {
7094 /* Enable STOP interrupts */
7095 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7096 }
7097
7098 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7099 {
7100 /* Enable TC interrupts */
7101 tmpisr |= I2C_IT_TCI;
7102 }
7103 }
7104 else
7105 {
7106 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7107 {
7108 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7109 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7110 }
7111
7112 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7113 {
7114 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7115 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7116 }
7117
7118 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7119 {
7120 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7121 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7122 }
7123
7124 if (InterruptRequest == I2C_XFER_ERROR_IT)
7125 {
7126 /* Enable ERR and NACK interrupts */
7127 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7128 }
7129
7130 if (InterruptRequest == I2C_XFER_CPLT_IT)
7131 {
7132 /* Enable STOP interrupts */
7133 tmpisr |= I2C_IT_STOPI;
7134 }
7135 }
7136
7137 /* Enable interrupts only at the end */
7138 /* to avoid the risk of I2C interrupt handle execution before */
7139 /* all interrupts requested done */
7140 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7141 }
7142
7143 /**
7144 * @brief Manage the disabling of Interrupts.
7145 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7146 * the configuration information for the specified I2C.
7147 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7148 * @retval None
7149 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7150 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7151 {
7152 uint32_t tmpisr = 0U;
7153
7154 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7155 {
7156 /* Disable TC and TXI interrupts */
7157 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7158
7159 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7160 {
7161 /* Disable NACK and STOP interrupts */
7162 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7163 }
7164 }
7165
7166 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7167 {
7168 /* Disable TC and RXI interrupts */
7169 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7170
7171 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7172 {
7173 /* Disable NACK and STOP interrupts */
7174 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7175 }
7176 }
7177
7178 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7179 {
7180 /* Disable ADDR, NACK and STOP interrupts */
7181 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7182 }
7183
7184 if (InterruptRequest == I2C_XFER_ERROR_IT)
7185 {
7186 /* Enable ERR and NACK interrupts */
7187 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7188 }
7189
7190 if (InterruptRequest == I2C_XFER_CPLT_IT)
7191 {
7192 /* Enable STOP interrupts */
7193 tmpisr |= I2C_IT_STOPI;
7194 }
7195
7196 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7197 {
7198 /* Enable TC interrupts */
7199 tmpisr |= I2C_IT_TCI;
7200 }
7201
7202 /* Disable interrupts only at the end */
7203 /* to avoid a breaking situation like at "t" time */
7204 /* all disable interrupts request are not done */
7205 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7206 }
7207
7208 /**
7209 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7210 * @param hi2c I2C handle.
7211 * @retval None
7212 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7213 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7214 {
7215 /* if user set XferOptions to I2C_OTHER_FRAME */
7216 /* it request implicitly to generate a restart condition */
7217 /* set XferOptions to I2C_FIRST_FRAME */
7218 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7219 {
7220 hi2c->XferOptions = I2C_FIRST_FRAME;
7221 }
7222 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7223 /* it request implicitly to generate a restart condition */
7224 /* then generate a stop condition at the end of transfer */
7225 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7226 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7227 {
7228 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7229 }
7230 else
7231 {
7232 /* Nothing to do */
7233 }
7234 }
7235
7236 /**
7237 * @}
7238 */
7239
7240 #endif /* HAL_I2C_MODULE_ENABLED */
7241 /**
7242 * @}
7243 */
7244
7245 /**
7246 * @}
7247 */
7248
