1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L5xx_HAL_GTZC_H 21 #define STM32L5xx_HAL_GTZC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l5xx_hal_def.h" 29 30 /** @addtogroup STM32L5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup GTZC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup GTZC_Exported_Types GTZC Exported Types 41 * @{ 42 */ 43 44 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing. */ 45 #define GTZC_MCPBB_NB_VCTR_REG_MAX (24U) 46 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 47 typedef struct 48 { 49 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. 50 Each bit corresponds to a block inside the super block. 51 0 means non-secure, 1 means secure */ 52 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). 53 0 means unlocked, 1 means locked */ 54 } MPCBB_Attribute_ConfigTypeDef; 55 56 typedef struct 57 { 58 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access field. 59 It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 60 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 61 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 62 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 63 } MPCBB_ConfigTypeDef; 64 65 typedef struct 66 { 67 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 68 GTZC_MPCWM_AreaId */ 69 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 70 memory base address. It must aligned on 128KB for FMC 71 and OCTOSPI memories */ 72 uint32_t Length; /*!< Length of the watermark area, starting from the selected 73 Offset. It must aligned on 128KB for FMC and OCTOSPI 74 memories */ 75 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 76 of @ref GTZC_MPCWM_Attribute */ 77 } MPCWM_ConfigTypeDef; 78 79 /** 80 * @} 81 */ 82 83 /* Private constants ---------------------------------------------------------*/ 84 85 /** @defgroup GTZC_Private_Constants GTZC Private Constants 86 * @{ 87 */ 88 89 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 90 * @{ 91 */ 92 93 /* composition definition for Peripheral identifier parameter (PeriphId) used in 94 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 95 * functions and also in all HAL_GTZC_TZIC relative functions. 96 * Bitmap Definition 97 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 98 * Each bit is dedicated to a single register. 99 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 100 * all peripherals within all registers. 101 * bits[4:0] Field "bit position". Define the bit position within the 102 * register dedicated to the peripheral, value from 0 to 31. 103 */ 104 #define GTZC_PERIPH_REG_SHIFT (28U) 105 #define GTZC_PERIPH_REG (0xF0000000UL) 106 #define GTZC_PERIPH_REG1 (0x00000000UL) 107 #define GTZC_PERIPH_REG2 (0x10000000UL) 108 #define GTZC_PERIPH_REG3 (0x20000000UL) 109 #define GTZC_PERIPH_BIT_POSITION (0x0000001FUL) 110 111 /** 112 * @} 113 */ 114 115 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 116 * @{ 117 */ 118 #define GTZC_ATTR_SEC_MASK 0x100U 119 #define GTZC_ATTR_PRIV_MASK 0x200U 120 121 /** 122 * @} 123 */ 124 125 /** 126 * @} 127 */ 128 129 /* Exported constants --------------------------------------------------------*/ 130 131 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 132 * @{ 133 */ 134 135 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 136 * @{ 137 */ 138 139 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 140 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 141 142 /** 143 * @} 144 */ 145 146 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 147 * @{ 148 */ 149 150 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 151 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 152 153 /** 154 * @} 155 */ 156 157 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 158 * @{ 159 */ 160 161 #define GTZC_TZSC_MPCWM_ID1 (0U) 162 #define GTZC_TZSC_MPCWM_ID2 (1U) 163 164 /** 165 * @} 166 */ 167 168 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 169 * @{ 170 */ 171 #define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 172 #define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 173 #define GTZC_PERIPH_TIM4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 174 #define GTZC_PERIPH_TIM5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 175 #define GTZC_PERIPH_TIM6 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 176 #define GTZC_PERIPH_TIM7 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 177 #define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 178 #define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 179 #define GTZC_PERIPH_SPI2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 180 #define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 181 #define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 182 #define GTZC_PERIPH_USART3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 183 #define GTZC_PERIPH_UART4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 184 #define GTZC_PERIPH_UART5 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 185 #define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 186 #define GTZC_PERIPH_I2C2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 187 #define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) 188 #define GTZC_PERIPH_CRS (GTZC_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 189 #define GTZC_PERIPH_DAC1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) 190 #define GTZC_PERIPH_OPAMP (GTZC_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) 191 #define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) 192 #define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) 193 #define GTZC_PERIPH_I2C4 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) 194 #define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 195 #define GTZC_PERIPH_LPTIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) 196 #define GTZC_PERIPH_FDCAN1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) 197 #define GTZC_PERIPH_USBFS (GTZC_PERIPH_REG1 | GTZC_CFGR1_USBFS_Pos) 198 #define GTZC_PERIPH_UCPD1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) 199 #define GTZC_PERIPH_VREFBUF (GTZC_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) 200 #define GTZC_PERIPH_COMP (GTZC_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) 201 #define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM1_Pos) 202 #define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_SPI1_Pos) 203 #define GTZC_PERIPH_TIM8 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 204 #define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 205 #define GTZC_PERIPH_TIM15 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 206 #define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 207 #define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 208 #define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 209 #define GTZC_PERIPH_SAI2 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 210 #define GTZC_PERIPH_DFSDM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DFSDM1_Pos) 211 #define GTZC_PERIPH_CRC (GTZC_PERIPH_REG2 | GTZC_CFGR2_CRC_Pos) 212 #define GTZC_PERIPH_TSC (GTZC_PERIPH_REG2 | GTZC_CFGR2_TSC_Pos) 213 #define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_ICACHE_REG_Pos) 214 #define GTZC_PERIPH_ADC (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC_Pos) 215 #define GTZC_PERIPH_AES (GTZC_PERIPH_REG2 | GTZC_CFGR2_AES_Pos) 216 #define GTZC_PERIPH_HASH (GTZC_PERIPH_REG2 | GTZC_CFGR2_HASH_Pos) 217 #define GTZC_PERIPH_RNG (GTZC_PERIPH_REG2 | GTZC_CFGR2_RNG_Pos) 218 #define GTZC_PERIPH_PKA (GTZC_PERIPH_REG2 | GTZC_CFGR2_PKA_Pos) 219 #define GTZC_PERIPH_SDMMC1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SDMMC1_Pos) 220 #define GTZC_PERIPH_FMC_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_FMC_REG_Pos) 221 #define GTZC_PERIPH_OCTOSPI1_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_OCTOSPI1_REG_Pos) 222 #define GTZC_PERIPH_RTC (GTZC_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) 223 #define GTZC_PERIPH_PWR (GTZC_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) 224 #define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) 225 #define GTZC_PERIPH_DMA1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMA1_Pos) 226 #define GTZC_PERIPH_DMA2 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMA2_Pos) 227 #define GTZC_PERIPH_DMAMUX1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_DMAMUX1_Pos) 228 #define GTZC_PERIPH_RCC (GTZC_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) 229 #define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG2 | GTZC_CFGR2_FLASH_Pos) 230 #define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG2 | GTZC_CFGR2_FLASH_REG_Pos) 231 #define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) 232 #define GTZC_PERIPH_OTFDEC1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_OTFDEC1_Pos) 233 #define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TZSC_Pos) 234 #define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TZIC_Pos) 235 #define GTZC_PERIPH_FMC_MEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_FMC_MEM_Pos) 236 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_MEM_Pos) 237 #define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG3 | GTZC_CFGR3_SRAM1_Pos) 238 #define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_MPCBB1_REG_Pos) 239 #define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG3 | GTZC_CFGR3_SRAM2_Pos) 240 #define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_MPCBB2_REG_Pos) 241 242 #define GTZC_PERIPH_ALL (0x00000020U) 243 244 /* Note that two maximum values are also defined here: 245 * - max number of securable AHB/APB peripherals or masters 246 * (used in TZSC sub-block) 247 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 248 * (used in TZIC sub-block) 249 */ 250 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_OCTOSPI1_REG + 1U)) 251 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB2_REG + 1U)) 252 253 /** 254 * @} 255 */ 256 257 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 258 * @note secure and non-secure attributes are only available from secure state when the system 259 * implement the security (TZEN=1) 260 * @{ 261 */ 262 263 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 264 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 265 * functions 266 */ 267 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 268 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 269 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 270 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 271 272 /** 273 * @} 274 */ 275 276 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 277 * @{ 278 */ 279 280 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 281 #define GTZC_TZSC_LOCK_OFF (0U) 282 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 283 284 /** 285 * @} 286 */ 287 288 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 289 * @{ 290 */ 291 292 /* user-oriented definitions for TZSC_MPCWM */ 293 #define GTZC_TZSC_MPCWM_GRANULARITY 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 294 295 /** 296 * @} 297 */ 298 299 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 300 * @{ 301 */ 302 303 /* user-oriented definitions for TZSC_MPCWM */ 304 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 305 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 306 307 /** 308 * @} 309 */ 310 311 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 312 * @{ 313 */ 314 315 /* user-oriented definitions for MPCBB */ 316 #define GTZC_MPCBB_BLOCK_SIZE 0x100U /* 256 Bytes */ 317 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 8 KBytes */ 318 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 319 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 320 321 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 322 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 323 324 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 325 #define GTZC_MCPBB_LOCK_OFF (0U) 326 #define GTZC_MCPBB_LOCK_ON (1U) 327 328 /** 329 * @} 330 */ 331 332 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 333 * @{ 334 */ 335 336 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 337 #define GTZC_TZIC_NO_ILA_EVENT (0U) 338 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 339 340 /** 341 * @} 342 */ 343 344 /** 345 * @} 346 */ 347 348 /* Private macros ------------------------------------------------------------*/ 349 350 /** @defgroup GTZC_Private_Macros GTZC Private Macros 351 * @{ 352 */ 353 354 /* retrieve information to access register for a specific PeriphId */ 355 #define GTZC_GET_REG_INDEX(periph_id)\ 356 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 357 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 358 359 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 360 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 361 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 362 363 #define GTZC_MEM_SIZE(mem)\ 364 ( mem ## _SIZE ) 365 366 #define GTZC_BASE_ADDRESS_S(mem)\ 367 ( mem ## _BASE_S ) 368 369 #define GTZC_BASE_ADDRESS_NS(mem)\ 370 ( mem ## _BASE_NS ) 371 372 /** 373 * @} 374 */ 375 376 /* Exported macros -----------------------------------------------------------*/ 377 378 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 379 * @{ 380 */ 381 382 /* user-oriented macro to get array index of a specific PeriphId 383 * in case of GTZC_PERIPH_ALL usage in the two following functions: 384 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 385 */ 386 #define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\ 387 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 388 389 /** 390 * @} 391 */ 392 393 /* Exported functions --------------------------------------------------------*/ 394 395 /** @addtogroup GTZC_Exported_Functions 396 * @{ 397 */ 398 399 /** @addtogroup GTZC_Exported_Functions_Group1 400 * @brief TZSC Initialization and Configuration functions 401 * @{ 402 */ 403 404 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 405 uint32_t PeriphAttributes); 406 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 407 uint32_t *PeriphAttributes); 408 409 /** 410 * @} 411 */ 412 413 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 414 415 /** @addtogroup GTZC_Exported_Functions_Group2 416 * @brief MPCWM Initialization and Configuration functions 417 * @{ 418 */ 419 420 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 421 MPCWM_ConfigTypeDef *pMPCWM_Desc); 422 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 423 MPCWM_ConfigTypeDef *pMPCWM_Desc); 424 /** 425 * @} 426 */ 427 428 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 429 430 /** @addtogroup GTZC_Exported_Functions_Group3 431 * @brief TZSC and TZSC-MPCWM Lock functions 432 * @{ 433 */ 434 435 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 436 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 437 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 438 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance); 439 440 /** 441 * @} 442 */ 443 444 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 445 446 /** @addtogroup GTZC_Exported_Functions_Group4 447 * @brief MPCBB Initialization and Configuration functions 448 * @{ 449 */ 450 451 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 452 MPCBB_ConfigTypeDef *pMPCBB_desc); 453 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 454 MPCBB_ConfigTypeDef *pMPCBB_desc); 455 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 456 uint32_t NbBlocks, 457 uint32_t *pMemAttributes); 458 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 459 uint32_t NbBlocks, 460 uint32_t *pMemAttributes); 461 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 462 uint32_t NbSuperBlocks, 463 uint32_t *pLockAttributes); 464 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 465 uint32_t NbSuperBlocks, 466 uint32_t *pLockAttributes); 467 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 468 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 469 uint32_t *pLockState); 470 471 /** 472 * @} 473 */ 474 475 /** @addtogroup GTZC_Exported_Functions_Group5 476 * @brief TZIC functions 477 * @{ 478 */ 479 480 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 481 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 482 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 483 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 484 485 /** 486 * @} 487 */ 488 489 /** @addtogroup GTZC_Exported_Functions_Group6 490 * @brief IRQ related Functions 491 * @{ 492 */ 493 494 void HAL_GTZC_IRQHandler(void); 495 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 496 497 /** 498 * @} 499 */ 500 501 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 502 503 /** 504 * @} 505 */ 506 507 /** 508 * @} 509 */ 510 511 /** 512 * @} 513 */ 514 515 #ifdef __cplusplus 516 } 517 #endif 518 519 #endif /* STM32L5xx_HAL_GTZC_H */ 520 521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 522
