1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_flash.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_FLASH_H 22 #define STM32L5xx_HAL_FLASH_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASH 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASH_Exported_Types FLASH Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or page erase. 50 This parameter can be a value of @ref FLASH_Type_Erase */ 51 uint32_t Banks; /*!< Select bank to erase. 52 This parameter must be a value of @ref FLASH_Banks 53 (FLASH_BANK_BOTH should be used only for mass erase) */ 54 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled 55 This parameter must be a value between 0 and (max number of pages in the bank - 1) 56 (eg : 127 for 512kB dual bank) */ 57 uint32_t NbPages; /*!< Number of pages to be erased. 58 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ 59 } FLASH_EraseInitTypeDef; 60 61 /** 62 * @brief FLASH Option Bytes Program structure definition 63 */ 64 typedef struct 65 { 66 uint32_t OptionType; /*!< Option byte to be configured. 67 This parameter can be a combination of the values of @ref FLASH_OB_Type */ 68 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). 69 Only one WRP area could be programmed at the same time. 70 This parameter can be value of @ref FLASH_OB_WRP_Area */ 71 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). 72 This parameter must be a value between 0 and (max number of pages in the bank - 1) 73 (eg : 127 for 512kB dual bank) */ 74 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). 75 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ 76 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). 77 This parameter can be a value of @ref FLASH_OB_Read_Protection */ 78 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 79 This parameter can be a combination of @ref FLASH_OB_USER_Type */ 80 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). 81 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, 82 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, 83 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 84 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 85 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SWAP_BANK, 86 @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK, 87 @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST, 88 @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, 89 @ref FLASH_OB_USER_PA15_PUPEN and @ref FLASH_OB_USER_TZEN */ 90 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 91 uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). 92 This parameter must be a value of @ref FLASH_OB_WMSEC */ 93 uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). 94 This parameter must be a value between 0 and (max number of pages in the bank - 1) */ 95 uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). 96 This parameter must be a value between WMSecStartPage and (max number of pages in the bank - 1) */ 97 uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). 98 This parameter must be a value between WMSecStartPage and WMPCROPStartPage 99 (if PCROP area activated) or WMSecEndPage */ 100 uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). 101 This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ 102 #endif 103 uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). 104 This parameter must be a value of @ref FLASH_OB_BOOTADDR */ 105 uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). 106 This parameter must be a value between 0x0 and 0xFFFFFF00 */ 107 } FLASH_OBProgramInitTypeDef; 108 109 /** 110 * @brief FLASH handle Structure definition 111 */ 112 typedef struct 113 { 114 HAL_LockTypeDef Lock; /*!< FLASH locking object */ 115 uint32_t ErrorCode; /*!< FLASH error code */ 116 uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 117 uint32_t Address; /*!< Internal variable to save address selected for program in IT context */ 118 uint32_t Bank; /*!< Internal variable to save current bank selected during erase in IT context */ 119 uint32_t Page; /*!< Internal variable to define the current page which is being erased in IT context */ 120 uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */ 121 }FLASH_ProcessTypeDef; 122 123 /** 124 * @} 125 */ 126 127 /* Exported constants --------------------------------------------------------*/ 128 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 129 * @{ 130 */ 131 132 /** @defgroup FLASH_Flags FLASH Flags Definition 133 * @{ 134 */ 135 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 136 #define FLASH_FLAG_EOP FLASH_SECSR_SECEOP /*!< FLASH End of operation flag */ 137 #define FLASH_FLAG_OPERR FLASH_SECSR_SECOPERR /*!< FLASH Operation error flag */ 138 #define FLASH_FLAG_PROGERR FLASH_SECSR_SECPROGERR /*!< FLASH Programming error flag */ 139 #define FLASH_FLAG_WRPERR FLASH_SECSR_SECWRPERR /*!< FLASH Write protection error flag */ 140 #define FLASH_FLAG_PGAERR FLASH_SECSR_SECPGAERR /*!< FLASH Programming alignment error flag */ 141 #define FLASH_FLAG_SIZERR FLASH_SECSR_SECSIZERR /*!< FLASH Size error flag */ 142 #define FLASH_FLAG_PGSERR FLASH_SECSR_SECPGSERR /*!< FLASH Programming sequence error flag */ 143 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 144 #define FLASH_FLAG_BSY FLASH_SECSR_SECBSY /*!< FLASH Busy flag */ 145 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 146 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 147 148 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 149 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) /*!< Flash all flags from Status Register */ 150 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 151 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 152 #else 153 #define FLASH_FLAG_EOP FLASH_NSSR_NSEOP /*!< FLASH End of operation flag */ 154 #define FLASH_FLAG_OPERR FLASH_NSSR_NSOPERR /*!< FLASH Operation error flag */ 155 #define FLASH_FLAG_PROGERR FLASH_NSSR_NSPROGERR /*!< FLASH Programming error flag */ 156 #define FLASH_FLAG_WRPERR FLASH_NSSR_NSWRPERR /*!< FLASH Write protection error flag */ 157 #define FLASH_FLAG_PGAERR FLASH_NSSR_NSPGAERR /*!< FLASH Programming alignment error flag */ 158 #define FLASH_FLAG_SIZERR FLASH_NSSR_NSSIZERR /*!< FLASH Size error flag */ 159 #define FLASH_FLAG_PGSERR FLASH_NSSR_NSPGSERR /*!< FLASH Programming sequence error flag */ 160 #define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ 161 #define FLASH_FLAG_BSY FLASH_NSSR_NSBSY /*!< FLASH Busy flag */ 162 #define FLASH_FLAG_ECCC (FLASH_ECCR_ECCC | FLASH_ECCR_ECCC2) /*!< FLASH ECC correction */ 163 #define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */ 164 165 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ 166 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ 167 FLASH_FLAG_OPTWERR) /*!< Flash all flags from Status Register */ 168 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ 169 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ 170 #endif 171 /** 172 * @} 173 */ 174 175 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition 176 * @brief FLASH Interrupt definition 177 * @{ 178 */ 179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 180 #define FLASH_IT_EOP FLASH_SECCR_SECEOPIE /*!< End of FLASH Operation Interrupt source */ 181 #define FLASH_IT_OPERR FLASH_SECCR_SECERRIE /*!< Error Interrupt source */ 182 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 183 #else 184 #define FLASH_IT_EOP FLASH_NSCR_NSEOPIE /*!< End of FLASH Operation Interrupt source */ 185 #define FLASH_IT_OPERR FLASH_NSCR_NSERRIE /*!< Error Interrupt source */ 186 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ 187 #endif 188 /** 189 * @} 190 */ 191 192 /** @defgroup FLASH_Error FLASH Error 193 * @{ 194 */ 195 #define HAL_FLASH_ERROR_NONE 0x00000000U /*!< Flash no error */ 196 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR /*!< Flash operation error */ 197 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR /*!< Flash programming error */ 198 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Flash write protection error */ 199 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR /*!< Flash programming alignment error */ 200 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR /*!< Flash size error */ 201 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Flash programming sequence error */ 202 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 203 #else 204 #define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR /*!< Flash option modification error */ 205 #endif 206 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< Flash ECC correction error */ 207 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< Flash ECC detection error */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup FLASH_Type_Erase FLASH Erase Type 213 * @{ 214 */ 215 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 216 #define FLASH_TYPEERASE_PAGES FLASH_SECCR_SECPER /*!<Secure pages erase only*/ 217 #define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_NSPER | FLASH_NON_SECURE_MASK) /*!<Non-secure pages erase only*/ 218 #define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_SECMER1 | FLASH_SECCR_SECMER2) /*!<Secure flash mass erase activation*/ 219 #define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_NSMER1 | FLASH_NSCR_NSMER2 | FLASH_NON_SECURE_MASK) /*!<Non-secure flash mass erase activation*/ 220 #else 221 #define FLASH_TYPEERASE_PAGES FLASH_NSCR_NSPER /*!<Pages erase only*/ 222 #define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_NSMER1 | FLASH_NSCR_NSMER2) /*!<Flash mass erase activation*/ 223 #endif 224 /** 225 * @} 226 */ 227 228 /** @defgroup FLASH_Banks FLASH Banks 229 * @{ 230 */ 231 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ 232 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ 233 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup FLASH_Type_Program FLASH Program Type 239 * @{ 240 */ 241 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 242 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_SECCR_SECPG /*!<Program a double-word (64-bit) at a specified secure address.*/ 243 #define FLASH_TYPEPROGRAM_DOUBLEWORD_NS (FLASH_NSCR_NSPG | FLASH_NON_SECURE_MASK) /*!<Program a double-word (64-bit) at a specified non-secure address.*/ 244 #else 245 #define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_NSCR_NSPG /*!<Program a double-word (64-bit) at a specified address.*/ 246 #endif 247 /** 248 * @} 249 */ 250 251 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type 252 * @{ 253 */ 254 #define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ 255 #define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ 256 #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ 257 #define OPTIONBYTE_BOOTADDR 0x00000008U /*!< Boot address option byte configuration */ 258 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 259 #define OPTIONBYTE_WMSEC 0x00000010U /*!< Watermark-based secure area option byte configuration */ 260 #define OPTIONBYTE_BOOT_LOCK 0x00000020U /*!< Boot lock option byte configuration */ 261 #endif 262 /** 263 * @} 264 */ 265 266 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area 267 * @{ 268 */ 269 #define OB_WRPAREA_BANK1_AREAA 0x00000001U /*!< Flash Bank 1 Area A */ 270 #define OB_WRPAREA_BANK1_AREAB 0x00000002U /*!< Flash Bank 1 Area B */ 271 #define OB_WRPAREA_BANK2_AREAA 0x00000004U /*!< Flash Bank 2 Area A */ 272 #define OB_WRPAREA_BANK2_AREAB 0x00000008U /*!< Flash Bank 2 Area B */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection 278 * @{ 279 */ 280 #define OB_RDP_LEVEL_0 ((uint32_t)0xAA) /*!< RDP level 0 code */ 281 #define OB_RDP_LEVEL_0_5 ((uint32_t)0x55) /*!< RDP level 0.5 code */ 282 #define OB_RDP_LEVEL_1 ((uint32_t)0xBB) /*!< RDP level 1 code */ 283 #define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< RDP level 2 code. 284 Warning: When enabling read protection level 2 285 it's no more possible to go back to level 1 or 0. */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type 291 * @{ 292 */ 293 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */ 294 #define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */ 295 #define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */ 296 #define OB_USER_nRST_SHDW 0x00000008U /*!< Reset generated when entering the shutdown mode */ 297 #define OB_USER_IWDG_SW 0x00000010U /*!< Independent watchdog selection */ 298 #define OB_USER_IWDG_STOP 0x00000020U /*!< Independent watchdog counter freeze in stop mode */ 299 #define OB_USER_IWDG_STDBY 0x00000040U /*!< Independent watchdog counter freeze in standby mode */ 300 #define OB_USER_WWDG_SW 0x00000080U /*!< Window watchdog selection */ 301 #define OB_USER_SWAP_BANK 0x00000100U /*!< Swap banks */ 302 #define OB_USER_DUALBANK 0x00000200U /*!< Dual-Bank on 256kB Flash memory devices */ 303 #define OB_USER_DBANK 0x00000400U /*!< Single bank with 128-bits data or two banks with 64-bits data */ 304 #define OB_USER_SRAM2_PE 0x00000800U /*!< SRAM2 parity error enable */ 305 #define OB_USER_SRAM2_RST 0x00001000U /*!< SRAM2 Erase when system reset */ 306 #define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */ 307 #define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */ 308 #define OB_USER_PA15_PUPEN 0x00008000U /*!< PA15 pull-up enable option bit */ 309 #define OB_USER_TZEN 0x00010000U /*!< Global TrustZone enable */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level 315 * @{ 316 */ 317 #define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */ 318 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */ 319 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */ 320 #define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */ 321 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */ 322 /** 323 * @} 324 */ 325 326 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 327 * @{ 328 */ 329 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ 330 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby 336 * @{ 337 */ 338 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ 339 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ 340 /** 341 * @} 342 */ 343 344 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown 345 * @{ 346 */ 347 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ 348 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type 354 * @{ 355 */ 356 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ 357 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ 358 /** 359 * @} 360 */ 361 362 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop 363 * @{ 364 */ 365 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ 366 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ 367 /** 368 * @} 369 */ 370 371 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby 372 * @{ 373 */ 374 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ 375 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ 376 /** 377 * @} 378 */ 379 380 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type 381 * @{ 382 */ 383 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ 384 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ 385 /** 386 * @} 387 */ 388 389 /** @defgroup FLASH_OB_USER_SWAP_BANK FLASH Option Bytes User Swap banks 390 * @{ 391 */ 392 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank 1 is located at AHB address 0x0, Bank 2 is located at 0x40000 */ 393 #define OB_SWAP_BANK_ENABLE FLASH_OPTR_SWAP_BANK /*!< Bank 1 is located at AHB address 0x40000, Bank 2 is located at 0x0 */ 394 /** 395 * @} 396 */ 397 398 /** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type 399 * @{ 400 */ 401 #define OB_DUALBANK_SINGLE 0x00000000U /*!< 256 kB Single-bank Flash */ 402 #define OB_DUALBANK_DUAL FLASH_OPTR_DB256K /*!< 256 kB Dual-bank Flash */ 403 /** 404 * @} 405 */ 406 407 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type 408 * @{ 409 */ 410 #define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */ 411 #define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */ 412 /** 413 * @} 414 */ 415 416 /** @defgroup FLASH_OB_USER_SRAM2_PAR FLASH Option Bytes User SRAM2 Parity error enable 417 * @{ 418 */ 419 #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity error generation enable */ 420 #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2_PE /*!< SRAM2 parity check disable */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type 426 * @{ 427 */ 428 #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset occurs */ 429 #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2_RST /*!< SRAM2 is not erased when a system reset occurs */ 430 /** 431 * @} 432 */ 433 434 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 435 * @{ 436 */ 437 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ 438 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from BOOT0 pin */ 439 /** 440 * @} 441 */ 442 443 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit 444 * @{ 445 */ 446 #define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ 447 #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup FLASH_OB_USER_PA15_PUPEN FLASH Option Bytes User PA15 pull-up enable option bit 453 * @{ 454 */ 455 #define OB_PA15_PUP_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */ 456 #define OB_PA15_PUP_ENABLE FLASH_OPTR_PA15_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */ 457 /** 458 * @} 459 */ 460 461 /** @defgroup FLASH_OB_USER_TZEN FLASH Option Bytes User Global TrustZone 462 * @{ 463 */ 464 #define OB_TZEN_DISABLE 0x00000000U /*!< no TrustZone */ 465 #define OB_TZEN_ENABLE FLASH_OPTR_TZEN /*!< TrustZone */ 466 /** 467 * @} 468 */ 469 470 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 471 /** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock 472 * @{ 473 */ 474 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */ 475 #define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup FLASH_OB_WMSEC FLASH Option Bytes Watermarked-based security configuration 481 * @{ 482 */ 483 #define OB_WMSEC_AREA1 FLASH_BANK_1 /*!< Watermarked-based security area for bank 1 */ 484 #define OB_WMSEC_AREA2 FLASH_BANK_2 /*!< Watermarked-based security area for bank 2 */ 485 486 #define OB_WMSEC_SECURE_AREA_CONFIG 0x00000010U /*!< Configure Watermarked-based security area */ 487 #define OB_WMSEC_HDP_AREA_CONFIG 0x00000020U /*!< Configure Watermarked-based secure hide area */ 488 #define OB_WMSEC_HDP_AREA_ENABLE 0x00000080U /*!< Enable Watermarked-based secure hide area */ 489 #define OB_WMSEC_HDP_AREA_DISABLE 0x00000100U /*!< Disable Watermarked-based secure hide area */ 490 /** 491 * @} 492 */ 493 #endif 494 495 /** @defgroup FLASH_OB_BOOTADDR FLASH Option Bytes Boot address 496 * @{ 497 */ 498 #define OB_BOOTADDR_NS0 0x00000001U /*!< Non-secure boot address 0 */ 499 #define OB_BOOTADDR_NS1 0x00000002U /*!< Non-secure boot address 1 */ 500 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 501 #define OB_BOOTADDR_SEC0 0x00000004U /*!< Secure boot address 0 */ 502 #endif 503 /** 504 * @} 505 */ 506 507 /** @defgroup FLASH_Latency FLASH Latency 508 * @{ 509 */ 510 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 511 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 512 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 513 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 514 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 515 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */ 516 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */ 517 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ 518 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ 519 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */ 520 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */ 521 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */ 522 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */ 523 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */ 524 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */ 525 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */ 526 /** 527 * @} 528 */ 529 530 /** @defgroup FLASH_Keys FLASH Keys 531 * @{ 532 */ 533 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */ 534 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 535 to unlock the FLASH registers access */ 536 537 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ 538 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 539 to unlock the RUN_PD bit in FLASH_ACR */ 540 541 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ 542 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 543 to allow option bytes operations */ 544 545 #define FLASH_LVEKEY1 0xF4F5F6F7U /*!< Flash LVE key1 */ 546 #define FLASH_LVEKEY2 0x0A1B2C3DU /*!< Flash LVE key2: used with FLASH_LVEKEY1 547 to unblock the LVEN bit in FLASH_ACR */ 548 /** 549 * @} 550 */ 551 552 /** 553 * @} 554 */ 555 556 /* Exported macros -----------------------------------------------------------*/ 557 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros 558 * @brief macros to control FLASH features 559 * @{ 560 */ 561 562 /** 563 * @brief Set the FLASH Latency. 564 * @param __LATENCY__ FLASH Latency. 565 * This parameter can be one of the following values : 566 * @arg FLASH_LATENCY_0: FLASH Zero wait state 567 * @arg FLASH_LATENCY_1: FLASH One wait state 568 * @arg FLASH_LATENCY_2: FLASH Two wait states 569 * @arg FLASH_LATENCY_3: FLASH Three wait states 570 * @arg FLASH_LATENCY_4: FLASH Four wait states 571 * @arg FLASH_LATENCY_5: FLASH Five wait states 572 * @arg FLASH_LATENCY_6: FLASH Six wait states 573 * @arg FLASH_LATENCY_7: FLASH Seven wait states 574 * @arg FLASH_LATENCY_8: FLASH Eight wait states 575 * @arg FLASH_LATENCY_9: FLASH Nine wait states 576 * @arg FLASH_LATENCY_10: FLASH Ten wait states 577 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 578 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 579 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 580 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 581 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 582 * @retval None 583 */ 584 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) 585 586 /** 587 * @brief Get the FLASH Latency. 588 * @retval FLASH Latency 589 * This parameter can be one of the following values : 590 * @arg FLASH_LATENCY_0: FLASH Zero wait state 591 * @arg FLASH_LATENCY_1: FLASH One wait state 592 * @arg FLASH_LATENCY_2: FLASH Two wait states 593 * @arg FLASH_LATENCY_3: FLASH Three wait states 594 * @arg FLASH_LATENCY_4: FLASH Four wait states 595 * @arg FLASH_LATENCY_5: FLASH Five wait states 596 * @arg FLASH_LATENCY_6: FLASH Six wait states 597 * @arg FLASH_LATENCY_7: FLASH Seven wait states 598 * @arg FLASH_LATENCY_8: FLASH Eight wait states 599 * @arg FLASH_LATENCY_9: FLASH Nine wait states 600 * @arg FLASH_LATENCY_10: FLASH Ten wait states 601 * @arg FLASH_LATENCY_11: FLASH Eleven wait states 602 * @arg FLASH_LATENCY_12: FLASH Twelve wait states 603 * @arg FLASH_LATENCY_13: FLASH Thirteen wait states 604 * @arg FLASH_LATENCY_14: FLASH Fourteen wait states 605 * @arg FLASH_LATENCY_15: FLASH Fifteen wait states 606 */ 607 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) 608 609 /** 610 * @brief Enable the FLASH power down during Low-power run mode. 611 * @retval None 612 * @note Writing this bit to 0, automatically the keys are 613 * lost and a new unlock sequence is necessary to re-write it to 1. 614 */ 615 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 616 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 617 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 618 } while (0) 619 620 /** 621 * @brief Disable the FLASH power down during Low-power run mode. 622 * @retval None 623 * @note Writing this bit to 1, automatically the keys are 624 * loss and a new unlock sequence is necessary to re-write it to 0. 625 */ 626 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ 627 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ 628 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ 629 } while (0) 630 631 /** 632 * @brief Enable the FLASH power down during Low-Power sleep mode 633 * @retval None 634 */ 635 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 636 637 /** 638 * @brief Disable the FLASH power down during Low-Power sleep mode 639 * @retval None 640 */ 641 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) 642 643 /** 644 * @} 645 */ 646 647 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros 648 * @brief macros to handle FLASH interrupts 649 * @{ 650 */ 651 652 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 653 /** 654 * @brief Enable secure FLASH interrupts from the secure world. 655 * @param __INTERRUPT__ FLASH interrupt. 656 * This parameter can be any combination of the following values: 657 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 658 * @arg FLASH_IT_OPERR: Error Interrupt 659 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 660 * @retval None 661 */ 662 /* Enable secure FLASH interrupts from the secure world */ 663 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 664 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 665 } while(0) 666 /** 667 * @brief Enable non-secure FLASH interrupts from the secure world. 668 * @param __INTERRUPT__ FLASH interrupt. 669 * This parameter can be any combination of the following values: 670 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 671 * @arg FLASH_IT_OPERR: Error Interrupt 672 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 673 * @retval None 674 */ 675 #define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 676 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 677 } while(0) 678 #else 679 /** 680 * @brief Enable non-secure FLASH interrupts from the non-secure world. 681 * @param __INTERRUPT__ FLASH interrupt. 682 * This parameter can be any combination of the following values: 683 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 684 * @arg FLASH_IT_OPERR: Error Interrupt 685 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 686 * @retval None 687 */ 688 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 689 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 690 } while(0) 691 #endif /* __ARM_FEATURE_CMSE */ 692 693 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 694 /** 695 * @brief Disable secure FLASH interrupts from the secure world. 696 * @param __INTERRUPT__ FLASH interrupt. 697 * This parameter can be any combination of the following values: 698 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 699 * @arg FLASH_IT_OPERR: Error Interrupt 700 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 701 * @retval None 702 */ 703 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 704 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 705 } while(0) 706 /** 707 * @brief Disable non-secure FLASH interrupts from the secure world. 708 * @param __INTERRUPT__ FLASH interrupt. 709 * This parameter can be any combination of the following values: 710 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 711 * @arg FLASH_IT_OPERR: Error Interrupt 712 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 713 * @retval None 714 */ 715 #define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 716 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 717 } while(0) 718 #else 719 /** 720 * @brief Disable non-secure FLASH interrupts from the non-secure world. 721 * @param __INTERRUPT__ FLASH interrupt. 722 * This parameter can be any combination of the following values: 723 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt 724 * @arg FLASH_IT_OPERR: Error Interrupt 725 * @arg FLASH_IT_ECCC: ECC Correction Interrupt 726 * @retval None 727 */ 728 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ 729 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ 730 } while(0) 731 #endif /* __ARM_FEATURE_CMSE */ 732 733 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 734 /** 735 * @brief Check whether the specified secure FLASH flags from the secure world is set or not. 736 * @param __FLAG__ specifies the FLASH flag to check. 737 * This parameter can be one of the following values: 738 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 739 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 740 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 741 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 742 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 743 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 744 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 745 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 746 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 747 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 748 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 749 * @retval The new state of FLASH_FLAG (SET or RESET). 750 */ 751 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 752 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 753 ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ 754 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ 755 (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) 756 /** 757 * @brief Check whether the specified non-secure FLASH flags from the secure world is set or not. 758 * @param __FLAG__ specifies the FLASH flag to check. 759 * This parameter can be one of the following values: 760 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 761 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 762 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 763 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 764 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 765 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 766 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 767 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 768 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 769 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 770 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 771 * @retval The new state of FLASH_FLAG (SET or RESET). 772 */ 773 #define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 774 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 775 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 776 #else 777 /** 778 * @brief Check whether the specified non-secure FLASH flags from the non-secure world is set or not. 779 * @param __FLAG__ specifies the FLASH flag to check. 780 * This parameter can be one of the following values: 781 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 782 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 783 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 784 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 785 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 786 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 787 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 788 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag 789 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 790 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 791 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 792 * @retval The new state of FLASH_FLAG (SET or RESET). 793 */ 794 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ 795 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ 796 (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) 797 #endif /* __ARM_FEATURE_CMSE */ 798 799 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 800 /** 801 * @brief Clear secure FLASH flags from the secure world. 802 * @param __FLAG__ specifies the FLASH flags to clear. 803 * This parameter can be any combination of the following values: 804 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 805 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 806 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 807 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 808 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 809 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 810 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 811 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 812 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 813 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 814 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 815 * @retval None 816 */ 817 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 818 if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ 819 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR)) != 0U) { WRITE_REG(FLASH->SECSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); } \ 820 } while(0) 821 /** 822 * @brief Clear non-secure FLASH flags from the secure world. 823 * @param __FLAG__ specifies the FLASH flags to clear. 824 * This parameter can be any combination of the following values: 825 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 826 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 827 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 828 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 829 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 830 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 831 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 832 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 833 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 834 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 835 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 836 * @retval None 837 */ 838 #define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 839 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 840 } while(0) 841 #else 842 /** 843 * @brief Clear non-secure FLASH flags from the non-secure world. 844 * @param __FLAG__ specifies the FLASH flags to clear. 845 * This parameter can be any combination of the following values: 846 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag 847 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag 848 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag 849 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 850 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag 851 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag 852 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag 853 * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) 854 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected 855 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected 856 * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags 857 * @retval None 858 */ 859 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ 860 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ 861 } while(0) 862 #endif /* __ARM_FEATURE_CMSE */ 863 /** 864 * @} 865 */ 866 867 /* Include FLASH HAL Extended module */ 868 #include "stm32l5xx_hal_flash_ex.h" 869 #include "stm32l5xx_hal_flash_ramfunc.h" 870 871 /* Exported functions --------------------------------------------------------*/ 872 /** @addtogroup FLASH_Exported_Functions 873 * @{ 874 */ 875 876 /* Program operation functions ***********************************************/ 877 /** @addtogroup FLASH_Exported_Functions_Group1 878 * @{ 879 */ 880 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 881 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 882 /* FLASH IRQ handler method */ 883 void HAL_FLASH_IRQHandler(void); 884 /* Callbacks in non blocking modes */ 885 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 886 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 887 /** 888 * @} 889 */ 890 891 /* Peripheral Control functions **********************************************/ 892 /** @addtogroup FLASH_Exported_Functions_Group2 893 * @{ 894 */ 895 HAL_StatusTypeDef HAL_FLASH_Unlock(void); 896 HAL_StatusTypeDef HAL_FLASH_Lock(void); 897 /* Option bytes control */ 898 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 899 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 900 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 901 /** 902 * @} 903 */ 904 905 /* Peripheral State functions ************************************************/ 906 /** @addtogroup FLASH_Exported_Functions_Group3 907 * @{ 908 */ 909 uint32_t HAL_FLASH_GetError(void); 910 /** 911 * @} 912 */ 913 914 /** 915 * @} 916 */ 917 918 /* Private variables ---------------------------------------------------------*/ 919 /** @addtogroup FLASH_Private_Variables FLASH Private Variables 920 * @{ 921 */ 922 extern FLASH_ProcessTypeDef pFlash; 923 /** 924 * @} 925 */ 926 927 /* Private function ----------------------------------------------------------*/ 928 /** @addtogroup FLASH_Private_Functions FLASH Private Functions 929 * @{ 930 */ 931 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 932 /** 933 * @} 934 */ 935 936 /* Private constants ---------------------------------------------------------*/ 937 /** @defgroup FLASH_Private_Constants FLASH Private Constants 938 * @{ 939 */ 940 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) 941 942 #define FLASH_PAGE_SIZE 0x00000800U 943 #define FLASH_PAGE_SIZE_128_BITS 0x00001000U 944 945 #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) 946 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) 947 #define FLASH_PAGE_NB_128_BITS (FLASH_SIZE / FLASH_PAGE_SIZE_128_BITS) 948 949 #define FLASH_TIMEOUT_VALUE 1000u /* 1 s */ 950 951 #define FLASH_NON_SECURE_MASK 0x80000000U 952 /** 953 * @} 954 */ 955 956 /* Private macros ------------------------------------------------------------*/ 957 /** @defgroup FLASH_Private_Macros FLASH Private Macros 958 * @{ 959 */ 960 961 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 962 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 963 ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ 964 ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ 965 ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) 966 #else 967 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ 968 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 969 #endif 970 971 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ 972 ((BANK) == FLASH_BANK_2) || \ 973 ((BANK) == FLASH_BANK_BOTH)) 974 975 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ 976 ((BANK) == FLASH_BANK_2)) 977 978 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 979 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ 980 ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD_NS)) 981 #else 982 #define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) 983 #endif 984 985 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 986 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ 987 (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) 988 #else 989 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) 990 #endif 991 992 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= OTP_BASE) && ((ADDRESS) < (OTP_BASE+OTP_SIZE))) 993 994 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) 995 996 #define IS_FLASH_PAGE(PAGE) ((PAGE) < 128U) 997 998 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 999 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 1000 OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR))) 1001 #else 1002 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ 1003 OPTIONBYTE_BOOTADDR))) 1004 #endif 1005 1006 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ 1007 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) 1008 1009 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 1010 ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ 1011 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 1012 ((LEVEL) == OB_RDP_LEVEL_2)) 1013 1014 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFFFU) && ((TYPE) != 0U)) 1015 1016 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ 1017 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ 1018 ((LEVEL) == OB_BOR_LEVEL_4)) 1019 1020 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) 1021 1022 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) 1023 1024 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) 1025 1026 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) 1027 1028 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) 1029 1030 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) 1031 1032 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) 1033 1034 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 1035 1036 #define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) 1037 1038 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) 1039 1040 #define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) 1041 1042 #define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) 1043 1044 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) 1045 1046 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) 1047 1048 #define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) 1049 1050 #define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) 1051 1052 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1053 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) 1054 1055 #define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x1B3U) != 0U) && (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFFE4CU) == 0U)) 1056 1057 #define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ 1058 ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && (((WMSEC) & OB_WMSEC_AREA1) == 0U))) 1059 #endif 1060 1061 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1062 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ 1063 ((CFG) == OB_BOOTADDR_SEC0)) 1064 #else 1065 #define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) 1066 #endif 1067 1068 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ 1069 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ 1070 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ 1071 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ 1072 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ 1073 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ 1074 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ 1075 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) 1076 1077 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1078 #define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) 1079 #else 1080 #define IS_FLASH_SECURE_OPERATION() (0U) 1081 #endif /* __ARM_FEATURE_CMSE */ 1082 /** 1083 * @} 1084 */ 1085 1086 /** 1087 * @} 1088 */ 1089 1090 /** 1091 * @} 1092 */ 1093 1094 #ifdef __cplusplus 1095 } 1096 #endif 1097 1098 #endif /* STM32L5xx_HAL_FLASH_H */ 1099 1100 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1101
