1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_CORTEX_H 22 #define STM32L5xx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup CORTEX CORTEX 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint8_t Enable; /*!< Specifies the status of the region. 51 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 52 uint8_t Number; /*!< Specifies the number of the region to protect. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 54 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 55 uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ 56 uint8_t AttributesIndex; /*!< Specifies the memory attributes index. 57 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 58 uint8_t AccessPermission; /*!< Specifies the region access permission type. 59 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 60 uint8_t DisableExec; /*!< Specifies the instruction access status. 61 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 62 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 63 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 64 } MPU_Region_InitTypeDef; 65 /** 66 * @} 67 */ 68 69 /** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition 70 * @{ 71 */ 72 typedef struct 73 { 74 uint8_t Number; /*!< Specifies the number of the memory attributes to configure. 75 This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ 76 77 uint8_t Attributes; /*!< Specifies the memory attributes vue. 78 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 79 80 } MPU_Attributes_InitTypeDef; 81 /** 82 * @} 83 */ 84 85 #endif /* __MPU_PRESENT */ 86 87 /** 88 * @} 89 */ 90 91 /* Exported constants --------------------------------------------------------*/ 92 93 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 94 * @{ 95 */ 96 97 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 98 * @{ 99 */ 100 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 101 3 bits for subpriority */ 102 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 103 2 bits for subpriority */ 104 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 105 1 bits for subpriority */ 106 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 107 0 bit for subpriority */ 108 /** 109 * @} 110 */ 111 112 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 113 * @{ 114 */ 115 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 116 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 117 /** 118 * @} 119 */ 120 121 #if (__MPU_PRESENT == 1) 122 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 123 * @{ 124 */ 125 #define MPU_HFNMI_PRIVDEF_NONE 0U 126 #define MPU_HARDFAULT_NMI 2U 127 #define MPU_PRIVILEGED_DEFAULT 4U 128 #define MPU_HFNMI_PRIVDEF 6U 129 /** 130 * @} 131 */ 132 133 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 134 * @{ 135 */ 136 #define MPU_REGION_ENABLE 1U 137 #define MPU_REGION_DISABLE 0U 138 /** 139 * @} 140 */ 141 142 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 143 * @{ 144 */ 145 #define MPU_INSTRUCTION_ACCESS_ENABLE 0U 146 #define MPU_INSTRUCTION_ACCESS_DISABLE 1U 147 /** 148 * @} 149 */ 150 151 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 152 * @{ 153 */ 154 #define MPU_ACCESS_NOT_SHAREABLE 0U 155 #define MPU_ACCESS_OUTER_SHAREABLE 1U 156 #define MPU_ACCESS_INNER_SHAREABLE 3U 157 /** 158 * @} 159 */ 160 161 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 162 * @{ 163 */ 164 #define MPU_REGION_PRIV_RW 0U 165 #define MPU_REGION_ALL_RW 1U 166 #define MPU_REGION_PRIV_RO 2U 167 #define MPU_REGION_ALL_RO 3U 168 /** 169 * @} 170 */ 171 172 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 173 * @{ 174 */ 175 #define MPU_REGION_NUMBER0 0U 176 #define MPU_REGION_NUMBER1 1U 177 #define MPU_REGION_NUMBER2 2U 178 #define MPU_REGION_NUMBER3 3U 179 #define MPU_REGION_NUMBER4 4U 180 #define MPU_REGION_NUMBER5 5U 181 #define MPU_REGION_NUMBER6 6U 182 #define MPU_REGION_NUMBER7 7U 183 /** 184 * @} 185 */ 186 187 /** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number 188 * @{ 189 */ 190 #define MPU_ATTRIBUTES_NUMBER0 0U 191 #define MPU_ATTRIBUTES_NUMBER1 1U 192 #define MPU_ATTRIBUTES_NUMBER2 2U 193 #define MPU_ATTRIBUTES_NUMBER3 3U 194 #define MPU_ATTRIBUTES_NUMBER4 4U 195 #define MPU_ATTRIBUTES_NUMBER5 5U 196 #define MPU_ATTRIBUTES_NUMBER6 6U 197 #define MPU_ATTRIBUTES_NUMBER7 7U 198 /** 199 * @} 200 */ 201 202 /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes 203 * @{ 204 */ 205 #define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ 206 #define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ 207 #define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ 208 #define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ 209 210 #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ 211 #define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ 212 #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ 213 214 #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ 215 #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ 216 217 #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ 218 #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ 219 #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ 220 #define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ 221 222 #define OUTER(__ATTR__) ((__ATTR__) << 4U) 223 #define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) 224 /** 225 * @} 226 */ 227 228 #endif /* __MPU_PRESENT */ 229 230 /** 231 * @} 232 */ 233 234 /* Exported macros -----------------------------------------------------------*/ 235 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 236 * @{ 237 */ 238 239 /** 240 * @} 241 */ 242 243 /* Exported functions --------------------------------------------------------*/ 244 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 245 * @{ 246 */ 247 248 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 249 * @brief Initialization and Configuration functions 250 * @{ 251 */ 252 /* Initialization and Configuration functions *****************************/ 253 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 254 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 255 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 256 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 257 void HAL_NVIC_SystemReset(void); 258 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 259 /** 260 * @} 261 */ 262 263 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 264 * @brief Cortex control functions 265 * @{ 266 */ 267 /* Peripheral Control functions ***********************************************/ 268 uint32_t HAL_NVIC_GetPriorityGrouping(void); 269 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 270 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 271 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 272 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 273 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 274 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 275 void HAL_SYSTICK_IRQHandler(void); 276 void HAL_SYSTICK_Callback(void); 277 278 #if (__MPU_PRESENT == 1) 279 void HAL_MPU_Enable(uint32_t MPU_Control); 280 void HAL_MPU_Disable(void); 281 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); 282 void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 283 #ifdef MPU_NS 284 void HAL_MPU_Enable_NS(uint32_t MPU_Control); 285 void HAL_MPU_Disable_NS(void); 286 void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); 287 void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); 288 #endif /* MPU_NS */ 289 #endif /* __MPU_PRESENT */ 290 /** 291 * @} 292 */ 293 294 /** 295 * @} 296 */ 297 298 /* Private types -------------------------------------------------------------*/ 299 /* Private variables ---------------------------------------------------------*/ 300 /* Private constants ---------------------------------------------------------*/ 301 /* Private macros ------------------------------------------------------------*/ 302 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 303 * @{ 304 */ 305 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 306 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 307 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 308 ((GROUP) == NVIC_PRIORITYGROUP_3)) 309 310 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 311 312 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) 313 314 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) 315 316 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 317 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 318 319 #if (__MPU_PRESENT == 1) 320 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 321 ((STATE) == MPU_REGION_DISABLE)) 322 323 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 324 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 325 326 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ 327 ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ 328 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 329 330 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ 331 ((TYPE) == MPU_REGION_ALL_RW) || \ 332 ((TYPE) == MPU_REGION_PRIV_RO) || \ 333 ((TYPE) == MPU_REGION_ALL_RO)) 334 335 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 336 ((NUMBER) == MPU_REGION_NUMBER1) || \ 337 ((NUMBER) == MPU_REGION_NUMBER2) || \ 338 ((NUMBER) == MPU_REGION_NUMBER3) || \ 339 ((NUMBER) == MPU_REGION_NUMBER4) || \ 340 ((NUMBER) == MPU_REGION_NUMBER5) || \ 341 ((NUMBER) == MPU_REGION_NUMBER6) || \ 342 ((NUMBER) == MPU_REGION_NUMBER7)) 343 344 #define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ 345 ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ 346 ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ 347 ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ 348 ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ 349 ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ 350 ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ 351 ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) 352 353 #endif /* __MPU_PRESENT */ 354 355 /** 356 * @} 357 */ 358 359 /* Private functions ---------------------------------------------------------*/ 360 361 /** 362 * @} 363 */ 364 365 /** 366 * @} 367 */ 368 369 #ifdef __cplusplus 370 } 371 #endif 372 373 #endif /* STM32L5xx_HAL_CORTEX_H */ 374 375 376 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 377
