1 /**
2   ******************************************************************************
3   * @file    stm32l4xx_ll_system.h
4   * @author  MCD Application Team
5   * @brief   Header file of SYSTEM LL module.
6   *
7   ******************************************************************************
8   * @attention
9   *
10   * Copyright (c) 2017 STMicroelectronics.
11   * All rights reserved.
12   *
13   * This software is licensed under terms that can be found in the LICENSE file
14   * in the root directory of this software component.
15   * If no LICENSE file comes with this software, it is provided AS-IS.
16   *
17   ******************************************************************************
18   @verbatim
19   ==============================================================================
20                      ##### How to use this driver #####
21   ==============================================================================
22     [..]
23     The LL SYSTEM driver contains a set of generic APIs that can be
24     used by user:
25       (+) Some of the FLASH features need to be handled in the SYSTEM file.
26       (+) Access to DBGCMU registers
27       (+) Access to SYSCFG registers
28       (+) Access to VREFBUF registers
29 
30   @endverbatim
31   ******************************************************************************
32   */
33 
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32L4xx_LL_SYSTEM_H
36 #define STM32L4xx_LL_SYSTEM_H
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l4xx.h"
44 
45 /** @addtogroup STM32L4xx_LL_Driver
46   * @{
47   */
48 
49 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
50 
51 /** @defgroup SYSTEM_LL SYSTEM
52   * @{
53   */
54 
55 /* Private types -------------------------------------------------------------*/
56 /* Private variables ---------------------------------------------------------*/
57 
58 /* Private constants ---------------------------------------------------------*/
59 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
60   * @{
61   */
62 
63 #define LL_EXTI_REGISTER_PINPOS_SHFT        16U   /*!< Define used to shift pin position in EXTICR register */
64 
65 /**
66  * @brief Power-down in Run mode Flash key
67  */
68 #define FLASH_PDKEY1                  0x04152637U /*!< Flash power down key1 */
69 #define FLASH_PDKEY2                  0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
70                                                        to unlock the RUN_PD bit in FLASH_ACR */
71 
72 /**
73   * @}
74   */
75 
76 /* Private macros ------------------------------------------------------------*/
77 
78 /* Exported types ------------------------------------------------------------*/
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
81   * @{
82   */
83 
84 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
85 * @{
86 */
87 #define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */
88 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
89 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
90 #if defined(FMC_Bank1_R)
91 #define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
92 #endif /* FMC_Bank1_R */
93 #define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
94 /**
95   * @}
96   */
97 
98 #if defined(SYSCFG_MEMRMP_FB_MODE)
99 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
100   * @{
101   */
102 #define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
103                                                                       and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
104 #define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
105                                                                       and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
106 /**
107   * @}
108   */
109 
110 #endif /* SYSCFG_MEMRMP_FB_MODE */
111 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
112   * @{
113   */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
116 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
117 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
118 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
119 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
120 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
121 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
123 #if defined(I2C2)
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
125 #endif /* I2C2 */
126 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
127 #if defined(I2C4)
128 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4    SYSCFG_CFGR1_I2C4_FMP     /*!< Enable Fast Mode Plus on I2C4 pins */
129 #endif /* I2C4 */
130 /**
131   * @}
132   */
133 
134 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
135   * @{
136   */
137 #define LL_SYSCFG_EXTI_PORTA               0U                        /*!< EXTI PORT A                        */
138 #define LL_SYSCFG_EXTI_PORTB               1U                        /*!< EXTI PORT B                        */
139 #define LL_SYSCFG_EXTI_PORTC               2U                        /*!< EXTI PORT C                        */
140 #define LL_SYSCFG_EXTI_PORTD               3U                        /*!< EXTI PORT D                        */
141 #define LL_SYSCFG_EXTI_PORTE               4U                        /*!< EXTI PORT E                        */
142 #if defined(GPIOF)
143 #define LL_SYSCFG_EXTI_PORTF               5U                        /*!< EXTI PORT F                        */
144 #endif /* GPIOF */
145 #if defined(GPIOG)
146 #define LL_SYSCFG_EXTI_PORTG               6U                        /*!< EXTI PORT G                        */
147 #endif /* GPIOG */
148 #define LL_SYSCFG_EXTI_PORTH               7U                        /*!< EXTI PORT H                        */
149 #if defined(GPIOI)
150 #define LL_SYSCFG_EXTI_PORTI               8U                        /*!< EXTI PORT I                        */
151 #endif /* GPIOI */
152 /**
153   * @}
154   */
155 
156 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
157   * @{
158   */
159 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /* !< EXTI_POSITION_0  | EXTICR[0] */
160 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /* !< EXTI_POSITION_4  | EXTICR[0] */
161 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /* !< EXTI_POSITION_8  | EXTICR[0] */
162 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U)  /* !< EXTI_POSITION_12 | EXTICR[0] */
163 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /* !< EXTI_POSITION_0  | EXTICR[1] */
164 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /* !< EXTI_POSITION_4  | EXTICR[1] */
165 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /* !< EXTI_POSITION_8  | EXTICR[1] */
166 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U)  /* !< EXTI_POSITION_12 | EXTICR[1] */
167 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /* !< EXTI_POSITION_0  | EXTICR[2] */
168 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /* !< EXTI_POSITION_4  | EXTICR[2] */
169 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /* !< EXTI_POSITION_8  | EXTICR[2] */
170 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U)  /* !< EXTI_POSITION_12 | EXTICR[2] */
171 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)((0x000FU << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /* !< EXTI_POSITION_0  | EXTICR[3] */
172 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)((0x00F0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /* !< EXTI_POSITION_4  | EXTICR[3] */
173 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)((0x0F00U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /* !< EXTI_POSITION_8  | EXTICR[3] */
174 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)((0xF000U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U)  /* !< EXTI_POSITION_12 | EXTICR[3] */
175 /**
176   * @}
177   */
178 
179 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
180   * @{
181   */
182 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal
183                                                                    with Break Input of TIM1/8/15/16/17                           */
184 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection
185                                                                    with TIM1/8/15/16/17 Break Input
186                                                                    and also the PVDE and PLS bits of the Power Control Interface */
187 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY    SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal
188                                                                    with Break Input of TIM1/8/15/16/17                           */
189 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4
190                                                                    with Break Input of TIM1/15/16/17                             */
191 /**
192   * @}
193   */
194 
195 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
196   * @{
197   */
198 #define LL_SYSCFG_SRAM2WRP_PAGE0           SYSCFG_SWPR_PAGE0  /*!< SRAM2 Write protection page 0  */
199 #define LL_SYSCFG_SRAM2WRP_PAGE1           SYSCFG_SWPR_PAGE1  /*!< SRAM2 Write protection page 1  */
200 #define LL_SYSCFG_SRAM2WRP_PAGE2           SYSCFG_SWPR_PAGE2  /*!< SRAM2 Write protection page 2  */
201 #define LL_SYSCFG_SRAM2WRP_PAGE3           SYSCFG_SWPR_PAGE3  /*!< SRAM2 Write protection page 3  */
202 #define LL_SYSCFG_SRAM2WRP_PAGE4           SYSCFG_SWPR_PAGE4  /*!< SRAM2 Write protection page 4  */
203 #define LL_SYSCFG_SRAM2WRP_PAGE5           SYSCFG_SWPR_PAGE5  /*!< SRAM2 Write protection page 5  */
204 #define LL_SYSCFG_SRAM2WRP_PAGE6           SYSCFG_SWPR_PAGE6  /*!< SRAM2 Write protection page 6  */
205 #define LL_SYSCFG_SRAM2WRP_PAGE7           SYSCFG_SWPR_PAGE7  /*!< SRAM2 Write protection page 7  */
206 #define LL_SYSCFG_SRAM2WRP_PAGE8           SYSCFG_SWPR_PAGE8  /*!< SRAM2 Write protection page 8  */
207 #define LL_SYSCFG_SRAM2WRP_PAGE9           SYSCFG_SWPR_PAGE9  /*!< SRAM2 Write protection page 9  */
208 #define LL_SYSCFG_SRAM2WRP_PAGE10          SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
209 #define LL_SYSCFG_SRAM2WRP_PAGE11          SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
210 #define LL_SYSCFG_SRAM2WRP_PAGE12          SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
211 #define LL_SYSCFG_SRAM2WRP_PAGE13          SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
212 #define LL_SYSCFG_SRAM2WRP_PAGE14          SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
213 #define LL_SYSCFG_SRAM2WRP_PAGE15          SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
214 #if defined(SYSCFG_SWPR_PAGE31)
215 #define LL_SYSCFG_SRAM2WRP_PAGE16          SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
216 #define LL_SYSCFG_SRAM2WRP_PAGE17          SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
217 #define LL_SYSCFG_SRAM2WRP_PAGE18          SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
218 #define LL_SYSCFG_SRAM2WRP_PAGE19          SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
219 #define LL_SYSCFG_SRAM2WRP_PAGE20          SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
220 #define LL_SYSCFG_SRAM2WRP_PAGE21          SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
221 #define LL_SYSCFG_SRAM2WRP_PAGE22          SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
222 #define LL_SYSCFG_SRAM2WRP_PAGE23          SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
223 #define LL_SYSCFG_SRAM2WRP_PAGE24          SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
224 #define LL_SYSCFG_SRAM2WRP_PAGE25          SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
225 #define LL_SYSCFG_SRAM2WRP_PAGE26          SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
226 #define LL_SYSCFG_SRAM2WRP_PAGE27          SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
227 #define LL_SYSCFG_SRAM2WRP_PAGE28          SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
228 #define LL_SYSCFG_SRAM2WRP_PAGE29          SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
229 #define LL_SYSCFG_SRAM2WRP_PAGE30          SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
230 #define LL_SYSCFG_SRAM2WRP_PAGE31          SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
231 #endif /* SYSCFG_SWPR_PAGE31 */
232 #if defined(SYSCFG_SWPR2_PAGE63)
233 #define LL_SYSCFG_SRAM2WRP_PAGE32          SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */
234 #define LL_SYSCFG_SRAM2WRP_PAGE33          SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */
235 #define LL_SYSCFG_SRAM2WRP_PAGE34          SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */
236 #define LL_SYSCFG_SRAM2WRP_PAGE35          SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */
237 #define LL_SYSCFG_SRAM2WRP_PAGE36          SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */
238 #define LL_SYSCFG_SRAM2WRP_PAGE37          SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */
239 #define LL_SYSCFG_SRAM2WRP_PAGE38          SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */
240 #define LL_SYSCFG_SRAM2WRP_PAGE39          SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */
241 #define LL_SYSCFG_SRAM2WRP_PAGE40          SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */
242 #define LL_SYSCFG_SRAM2WRP_PAGE41          SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */
243 #define LL_SYSCFG_SRAM2WRP_PAGE42          SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */
244 #define LL_SYSCFG_SRAM2WRP_PAGE43          SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */
245 #define LL_SYSCFG_SRAM2WRP_PAGE44          SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */
246 #define LL_SYSCFG_SRAM2WRP_PAGE45          SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */
247 #define LL_SYSCFG_SRAM2WRP_PAGE46          SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */
248 #define LL_SYSCFG_SRAM2WRP_PAGE47          SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */
249 #define LL_SYSCFG_SRAM2WRP_PAGE48          SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */
250 #define LL_SYSCFG_SRAM2WRP_PAGE49          SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */
251 #define LL_SYSCFG_SRAM2WRP_PAGE50          SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */
252 #define LL_SYSCFG_SRAM2WRP_PAGE51          SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */
253 #define LL_SYSCFG_SRAM2WRP_PAGE52          SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */
254 #define LL_SYSCFG_SRAM2WRP_PAGE53          SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */
255 #define LL_SYSCFG_SRAM2WRP_PAGE54          SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */
256 #define LL_SYSCFG_SRAM2WRP_PAGE55          SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */
257 #define LL_SYSCFG_SRAM2WRP_PAGE56          SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */
258 #define LL_SYSCFG_SRAM2WRP_PAGE57          SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */
259 #define LL_SYSCFG_SRAM2WRP_PAGE58          SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */
260 #define LL_SYSCFG_SRAM2WRP_PAGE59          SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */
261 #define LL_SYSCFG_SRAM2WRP_PAGE60          SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */
262 #define LL_SYSCFG_SRAM2WRP_PAGE61          SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */
263 #define LL_SYSCFG_SRAM2WRP_PAGE62          SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */
264 #define LL_SYSCFG_SRAM2WRP_PAGE63          SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */
265 #endif /* SYSCFG_SWPR2_PAGE63 */
266 /**
267   * @}
268   */
269 
270 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
271   * @{
272   */
273 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
274 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
275 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
276 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
277 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
278 /**
279   * @}
280   */
281 
282 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
283   * @{
284   */
285 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
286 #if defined(TIM3)
287 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
288 #endif /* TIM3 */
289 #if defined(TIM4)
290 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
291 #endif /* TIM4 */
292 #if defined(TIM5)
293 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
294 #endif /* TIM5 */
295 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
296 #if defined(TIM7)
297 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
298 #endif /* TIM7 */
299 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
300 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
301 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
302 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
303 #if defined(I2C2)
304 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
305 #endif /* I2C2 */
306 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
307 #define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1FZR1_DBG_CAN_STOP    /*!< The bxCAN receive registers are frozen*/
308 #if defined(CAN2)
309 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1FZR1_DBG_CAN2_STOP   /*!< The bxCAN2 receive registers are frozen*/
310 #endif /* CAN2 */
311 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
312 /**
313   * @}
314   */
315 
316 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
317   * @{
318   */
319 #if defined(I2C4)
320 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/
321 #endif /* I2C4 */
322 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
323 /**
324   * @}
325   */
326 
327 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
328   * @{
329   */
330 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
331 #if defined(TIM8)
332 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
333 #endif /* TIM8 */
334 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
335 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
336 #if defined(TIM17)
337 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
338 #endif /* TIM17 */
339 /**
340   * @}
341   */
342 
343 #if defined(VREFBUF)
344 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
345   * @{
346   */
347 #define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
348 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
349 /**
350   * @}
351   */
352 #endif /* VREFBUF */
353 
354 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
355   * @{
356   */
357 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
358 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
359 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
360 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
361 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
362 #if defined(FLASH_ACR_LATENCY_5WS)
363 #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
364 #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
365 #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
366 #define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
367 #define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
368 #define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS  /*!< FLASH ten wait states */
369 #define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS  /*!< FLASH eleven wait states */
370 #define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS  /*!< FLASH twelve wait states */
371 #define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS  /*!< FLASH thirteen wait states */
372 #define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS  /*!< FLASH fourteen wait states */
373 #define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS  /*!< FLASH fifteen wait states */
374 #endif
375 /**
376   * @}
377   */
378 
379 /**
380   * @}
381   */
382 
383 /* Exported macro ------------------------------------------------------------*/
384 
385 /* Exported functions --------------------------------------------------------*/
386 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
387   * @{
388   */
389 
390 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
391   * @{
392   */
393 
394 /**
395   * @brief  Set memory mapping at address 0x00000000
396   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
397   * @param  Memory This parameter can be one of the following values:
398   *         @arg @ref LL_SYSCFG_REMAP_FLASH
399   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
400   *         @arg @ref LL_SYSCFG_REMAP_SRAM
401   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
402   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
403   *
404   *         (*) value not defined in all devices
405   * @retval None
406   */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)407 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
408 {
409   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
410 }
411 
412 /**
413   * @brief  Get memory mapping at address 0x00000000
414   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
415   * @retval Returned value can be one of the following values:
416   *         @arg @ref LL_SYSCFG_REMAP_FLASH
417   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
418   *         @arg @ref LL_SYSCFG_REMAP_SRAM
419   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
420   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
421   *
422   *         (*) value not defined in all devices
423   */
LL_SYSCFG_GetRemapMemory(void)424 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
425 {
426   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
427 }
428 
429 #if defined(SYSCFG_MEMRMP_FB_MODE)
430 /**
431   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
432   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
433   * @param  Bank This parameter can be one of the following values:
434   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
435   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
436   * @retval None
437   */
LL_SYSCFG_SetFlashBankMode(uint32_t Bank)438 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
439 {
440   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
441 }
442 
443 /**
444   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
445   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
446   * @retval Returned value can be one of the following values:
447   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
448   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
449   */
LL_SYSCFG_GetFlashBankMode(void)450 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
451 {
452   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
453 }
454 #endif /* SYSCFG_MEMRMP_FB_MODE */
455 
456 /**
457   * @brief  Firewall protection enabled
458   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_EnableFirewall
459   * @retval None
460   */
LL_SYSCFG_EnableFirewall(void)461 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
462 {
463   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
464 }
465 
466 /**
467   * @brief  Check if Firewall protection is enabled or not
468   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_IsEnabledFirewall
469   * @retval State of bit (1 or 0).
470   */
LL_SYSCFG_IsEnabledFirewall(void)471 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
472 {
473   return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
474 }
475 
476 /**
477   * @brief  Enable I/O analog switch voltage booster.
478   * @note   When voltage booster is enabled, I/O analog switches are supplied
479   *         by a dedicated voltage booster, from VDD power domain. This is
480   *         the recommended configuration with low VDDA voltage operation.
481   * @note   The I/O analog switch voltage booster is relevant for peripherals
482   *         using I/O in analog input: ADC, COMP, OPAMP.
483   *         However, COMP and OPAMP inputs have a high impedance and
484   *         voltage booster do not impact performance significantly.
485   *         Therefore, the voltage booster is mainly intended for
486   *         usage with ADC.
487   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
488   * @retval None
489   */
LL_SYSCFG_EnableAnalogBooster(void)490 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
491 {
492   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
493 }
494 
495 /**
496   * @brief  Disable I/O analog switch voltage booster.
497   * @note   When voltage booster is enabled, I/O analog switches are supplied
498   *         by a dedicated voltage booster, from VDD power domain. This is
499   *         the recommended configuration with low VDDA voltage operation.
500   * @note   The I/O analog switch voltage booster is relevant for peripherals
501   *         using I/O in analog input: ADC, COMP, OPAMP.
502   *         However, COMP and OPAMP inputs have a high impedance and
503   *         voltage booster do not impact performance significantly.
504   *         Therefore, the voltage booster is mainly intended for
505   *         usage with ADC.
506   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
507   * @retval None
508   */
LL_SYSCFG_DisableAnalogBooster(void)509 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
510 {
511   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
512 }
513 
514 /**
515   * @brief  Enable the I2C fast mode plus driving capability.
516   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
517   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
518   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
519   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
520   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
521   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
522   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
523   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
524   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
525   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
526   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
527   *
528   *         (*) value not defined in all devices
529   * @retval None
530   */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)531 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
532 {
533   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
534 }
535 
536 /**
537   * @brief  Disable the I2C fast mode plus driving capability.
538   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
539   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
540   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
541   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
542   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
543   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
544   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
545   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
546   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
547   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
548   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
549   *
550   *         (*) value not defined in all devices
551   * @retval None
552   */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)553 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
554 {
555   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
556 }
557 
558 /**
559   * @brief  Enable Floating Point Unit Invalid operation Interrupt
560   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
561   * @retval None
562   */
LL_SYSCFG_EnableIT_FPU_IOC(void)563 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
564 {
565   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
566 }
567 
568 /**
569   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
570   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
571   * @retval None
572   */
LL_SYSCFG_EnableIT_FPU_DZC(void)573 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
574 {
575   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
576 }
577 
578 /**
579   * @brief  Enable Floating Point Unit Underflow Interrupt
580   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
581   * @retval None
582   */
LL_SYSCFG_EnableIT_FPU_UFC(void)583 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
584 {
585   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
586 }
587 
588 /**
589   * @brief  Enable Floating Point Unit Overflow Interrupt
590   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
591   * @retval None
592   */
LL_SYSCFG_EnableIT_FPU_OFC(void)593 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
594 {
595   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
596 }
597 
598 /**
599   * @brief  Enable Floating Point Unit Input denormal Interrupt
600   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
601   * @retval None
602   */
LL_SYSCFG_EnableIT_FPU_IDC(void)603 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
604 {
605   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
606 }
607 
608 /**
609   * @brief  Enable Floating Point Unit Inexact Interrupt
610   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
611   * @retval None
612   */
LL_SYSCFG_EnableIT_FPU_IXC(void)613 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
614 {
615   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
616 }
617 
618 /**
619   * @brief  Disable Floating Point Unit Invalid operation Interrupt
620   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
621   * @retval None
622   */
LL_SYSCFG_DisableIT_FPU_IOC(void)623 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
624 {
625   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
626 }
627 
628 /**
629   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
630   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
631   * @retval None
632   */
LL_SYSCFG_DisableIT_FPU_DZC(void)633 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
634 {
635   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
636 }
637 
638 /**
639   * @brief  Disable Floating Point Unit Underflow Interrupt
640   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
641   * @retval None
642   */
LL_SYSCFG_DisableIT_FPU_UFC(void)643 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
644 {
645   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
646 }
647 
648 /**
649   * @brief  Disable Floating Point Unit Overflow Interrupt
650   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
651   * @retval None
652   */
LL_SYSCFG_DisableIT_FPU_OFC(void)653 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
654 {
655   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
656 }
657 
658 /**
659   * @brief  Disable Floating Point Unit Input denormal Interrupt
660   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
661   * @retval None
662   */
LL_SYSCFG_DisableIT_FPU_IDC(void)663 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
664 {
665   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
666 }
667 
668 /**
669   * @brief  Disable Floating Point Unit Inexact Interrupt
670   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
671   * @retval None
672   */
LL_SYSCFG_DisableIT_FPU_IXC(void)673 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
674 {
675   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
676 }
677 
678 /**
679   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
680   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
681   * @retval State of bit (1 or 0).
682   */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)683 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
684 {
685   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
686 }
687 
688 /**
689   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
690   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
691   * @retval State of bit (1 or 0).
692   */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)693 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
694 {
695   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
696 }
697 
698 /**
699   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
700   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
701   * @retval State of bit (1 or 0).
702   */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)703 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
704 {
705   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
706 }
707 
708 /**
709   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
710   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
711   * @retval State of bit (1 or 0).
712   */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)713 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
714 {
715   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
716 }
717 
718 /**
719   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
720   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
721   * @retval State of bit (1 or 0).
722   */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)723 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
724 {
725   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
726 }
727 
728 /**
729   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
730   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
731   * @retval State of bit (1 or 0).
732   */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)733 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
734 {
735   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
736 }
737 
738 /**
739   * @brief  Configure source input for the EXTI external interrupt.
740   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
741   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
742   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
743   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
744   * @param  Port This parameter can be one of the following values:
745   *         @arg @ref LL_SYSCFG_EXTI_PORTA
746   *         @arg @ref LL_SYSCFG_EXTI_PORTB
747   *         @arg @ref LL_SYSCFG_EXTI_PORTC
748   *         @arg @ref LL_SYSCFG_EXTI_PORTD
749   *         @arg @ref LL_SYSCFG_EXTI_PORTE
750   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
751   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
752   *         @arg @ref LL_SYSCFG_EXTI_PORTH
753   *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
754   *
755   *         (*) value not defined in all devices
756   * @param  Line This parameter can be one of the following values:
757   *         @arg @ref LL_SYSCFG_EXTI_LINE0
758   *         @arg @ref LL_SYSCFG_EXTI_LINE1
759   *         @arg @ref LL_SYSCFG_EXTI_LINE2
760   *         @arg @ref LL_SYSCFG_EXTI_LINE3
761   *         @arg @ref LL_SYSCFG_EXTI_LINE4
762   *         @arg @ref LL_SYSCFG_EXTI_LINE5
763   *         @arg @ref LL_SYSCFG_EXTI_LINE6
764   *         @arg @ref LL_SYSCFG_EXTI_LINE7
765   *         @arg @ref LL_SYSCFG_EXTI_LINE8
766   *         @arg @ref LL_SYSCFG_EXTI_LINE9
767   *         @arg @ref LL_SYSCFG_EXTI_LINE10
768   *         @arg @ref LL_SYSCFG_EXTI_LINE11
769   *         @arg @ref LL_SYSCFG_EXTI_LINE12
770   *         @arg @ref LL_SYSCFG_EXTI_LINE13
771   *         @arg @ref LL_SYSCFG_EXTI_LINE14
772   *         @arg @ref LL_SYSCFG_EXTI_LINE15
773   * @retval None
774   */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)775 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
776 {
777   MODIFY_REG(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << POSITION_VAL((Line >> LL_EXTI_REGISTER_PINPOS_SHFT)));
778 }
779 
780 /**
781   * @brief  Get the configured defined for specific EXTI Line
782   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
783   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
784   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
785   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
786   * @param  Line This parameter can be one of the following values:
787   *         @arg @ref LL_SYSCFG_EXTI_LINE0
788   *         @arg @ref LL_SYSCFG_EXTI_LINE1
789   *         @arg @ref LL_SYSCFG_EXTI_LINE2
790   *         @arg @ref LL_SYSCFG_EXTI_LINE3
791   *         @arg @ref LL_SYSCFG_EXTI_LINE4
792   *         @arg @ref LL_SYSCFG_EXTI_LINE5
793   *         @arg @ref LL_SYSCFG_EXTI_LINE6
794   *         @arg @ref LL_SYSCFG_EXTI_LINE7
795   *         @arg @ref LL_SYSCFG_EXTI_LINE8
796   *         @arg @ref LL_SYSCFG_EXTI_LINE9
797   *         @arg @ref LL_SYSCFG_EXTI_LINE10
798   *         @arg @ref LL_SYSCFG_EXTI_LINE11
799   *         @arg @ref LL_SYSCFG_EXTI_LINE12
800   *         @arg @ref LL_SYSCFG_EXTI_LINE13
801   *         @arg @ref LL_SYSCFG_EXTI_LINE14
802   *         @arg @ref LL_SYSCFG_EXTI_LINE15
803   * @retval Returned value can be one of the following values:
804   *         @arg @ref LL_SYSCFG_EXTI_PORTA
805   *         @arg @ref LL_SYSCFG_EXTI_PORTB
806   *         @arg @ref LL_SYSCFG_EXTI_PORTC
807   *         @arg @ref LL_SYSCFG_EXTI_PORTD
808   *         @arg @ref LL_SYSCFG_EXTI_PORTE
809   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
810   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
811   *         @arg @ref LL_SYSCFG_EXTI_PORTH
812   *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)
813   *
814   *         (*) value not defined in all devices
815   */
LL_SYSCFG_GetEXTISource(uint32_t Line)816 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
817 {
818   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
819 }
820 
821 /**
822   * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
823   * automatically cleared at the end of the SRAM2 erase operation.)
824   * @note This bit is write-protected: setting this bit is possible only after the
825   *       correct key sequence is written in the SYSCFG_SKR register as described in
826   *       the Reference Manual.
827   * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase
828   * @retval None
829   */
LL_SYSCFG_EnableSRAM2Erase(void)830 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
831 {
832   /* Starts a hardware SRAM2 erase operation*/
833   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
834 }
835 
836 /**
837   * @brief  Check if SRAM2 erase operation is on going
838   * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing
839   * @retval State of bit (1 or 0).
840   */
LL_SYSCFG_IsSRAM2EraseOngoing(void)841 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
842 {
843   return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
844 }
845 
846 /**
847   * @brief  Set connections to TIM1/8/15/16/17 Break inputs
848   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
849   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
850   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
851   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
852   * @param  Break This parameter can be a combination of the following values:
853   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
854   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
855   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
856   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
857   * @retval None
858   */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)859 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
860 {
861   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
862 }
863 
864 /**
865   * @brief  Get connections to TIM1/8/15/16/17 Break inputs
866   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
867   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
868   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
869   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
870   * @retval Returned value can be can be a combination of the following values:
871   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
872   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
873   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
874   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
875   */
LL_SYSCFG_GetTIMBreakInputs(void)876 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
877 {
878   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
879 }
880 
881 /**
882   * @brief  Check if SRAM2 parity error detected
883   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
884   * @retval State of bit (1 or 0).
885   */
LL_SYSCFG_IsActiveFlag_SP(void)886 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
887 {
888   return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
889 }
890 
891 /**
892   * @brief  Clear SRAM2 parity error flag
893   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
894   * @retval None
895   */
LL_SYSCFG_ClearFlag_SP(void)896 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
897 {
898   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
899 }
900 
901 /**
902   * @brief  Enable SRAM2 page write protection for Pages in range 0 to 31
903   * @note Write protection is cleared only by a system reset
904   * @rmtoll SYSCFG_SWPR  PxWP         LL_SYSCFG_EnableSRAM2PageWRP_0_31
905   * @param  SRAM2WRP This parameter can be a combination of the following values:
906   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
907   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
908   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
909   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
910   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
911   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
912   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
913   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
914   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
915   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
916   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
917   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
918   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
919   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
920   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
921   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
922   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
923   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
924   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
925   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
926   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
927   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
928   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
929   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
930   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
931   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
932   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
933   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
934   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
935   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
936   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
937   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
938   *
939   *         (*) value not defined in all devices
940   * @retval None
941   */
942 /* Legacy define */
943 #define LL_SYSCFG_EnableSRAM2PageWRP    LL_SYSCFG_EnableSRAM2PageWRP_0_31
LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)944 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)
945 {
946   SET_BIT(SYSCFG->SWPR, SRAM2WRP);
947 }
948 
949 #if defined(SYSCFG_SWPR2_PAGE63)
950 /**
951   * @brief  Enable SRAM2 page write protection for Pages in range 32 to 63
952   * @note Write protection is cleared only by a system reset
953   * @rmtoll SYSCFG_SWPR2 PxWP          LL_SYSCFG_EnableSRAM2PageWRP_32_63
954   * @param  SRAM2WRP This parameter can be a combination of the following values:
955   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)
956   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)
957   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)
958   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)
959   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)
960   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)
961   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)
962   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)
963   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)
964   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)
965   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)
966   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)
967   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)
968   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)
969   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)
970   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)
971   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)
972   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)
973   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)
974   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)
975   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)
976   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)
977   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)
978   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)
979   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)
980   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)
981   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)
982   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)
983   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)
984   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)
985   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)
986   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)
987   *
988   *         (*) value not defined in all devices
989   * @retval None
990   */
LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)991 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)
992 {
993   SET_BIT(SYSCFG->SWPR2, SRAM2WRP);
994 }
995 #endif /* SYSCFG_SWPR2_PAGE63 */
996 
997 /**
998   * @brief  SRAM2 page write protection lock prior to erase
999   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP
1000   * @retval None
1001   */
LL_SYSCFG_LockSRAM2WRP(void)1002 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
1003 {
1004   /* Writing a wrong key reactivates the write protection */
1005   WRITE_REG(SYSCFG->SKR, 0x00);
1006 }
1007 
1008 /**
1009   * @brief  SRAM2 page write protection unlock prior to erase
1010   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP
1011   * @retval None
1012   */
LL_SYSCFG_UnlockSRAM2WRP(void)1013 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
1014 {
1015   /* unlock the write protection of the SRAM2ER bit */
1016   WRITE_REG(SYSCFG->SKR, 0xCA);
1017   WRITE_REG(SYSCFG->SKR, 0x53);
1018 }
1019 
1020 /**
1021   * @}
1022   */
1023 
1024 
1025 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1026   * @{
1027   */
1028 
1029 /**
1030   * @brief  Return the device identifier
1031   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
1032   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1033   */
LL_DBGMCU_GetDeviceID(void)1034 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1035 {
1036   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1037 }
1038 
1039 /**
1040   * @brief  Return the device revision identifier
1041   * @note This field indicates the revision of the device.
1042   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
1043   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1044   */
LL_DBGMCU_GetRevisionID(void)1045 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1046 {
1047   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1048 }
1049 
1050 /**
1051   * @brief  Enable the Debug Module during SLEEP mode
1052   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
1053   * @retval None
1054   */
LL_DBGMCU_EnableDBGSleepMode(void)1055 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1056 {
1057   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1058 }
1059 
1060 /**
1061   * @brief  Disable the Debug Module during SLEEP mode
1062   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
1063   * @retval None
1064   */
LL_DBGMCU_DisableDBGSleepMode(void)1065 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1066 {
1067   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1068 }
1069 
1070 /**
1071   * @brief  Enable the Debug Module during STOP mode
1072   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
1073   * @retval None
1074   */
LL_DBGMCU_EnableDBGStopMode(void)1075 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1076 {
1077   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1078 }
1079 
1080 /**
1081   * @brief  Disable the Debug Module during STOP mode
1082   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
1083   * @retval None
1084   */
LL_DBGMCU_DisableDBGStopMode(void)1085 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1086 {
1087   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1088 }
1089 
1090 /**
1091   * @brief  Enable the Debug Module during STANDBY mode
1092   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
1093   * @retval None
1094   */
LL_DBGMCU_EnableDBGStandbyMode(void)1095 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1096 {
1097   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1098 }
1099 
1100 /**
1101   * @brief  Disable the Debug Module during STANDBY mode
1102   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
1103   * @retval None
1104   */
LL_DBGMCU_DisableDBGStandbyMode(void)1105 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1106 {
1107   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1108 }
1109 
1110 /**
1111   * @brief  Set Trace pin assignment control
1112   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
1113   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
1114   * @param  PinAssignment This parameter can be one of the following values:
1115   *         @arg @ref LL_DBGMCU_TRACE_NONE
1116   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1117   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1118   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1119   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1120   * @retval None
1121   */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1122 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1123 {
1124   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1125 }
1126 
1127 /**
1128   * @brief  Get Trace pin assignment control
1129   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
1130   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
1131   * @retval Returned value can be one of the following values:
1132   *         @arg @ref LL_DBGMCU_TRACE_NONE
1133   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1134   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1135   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1136   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1137   */
LL_DBGMCU_GetTracePinAssignment(void)1138 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1139 {
1140   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1141 }
1142 
1143 /**
1144   * @brief  Freeze APB1 peripherals (group1 peripherals)
1145   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
1146   * @param  Periphs This parameter can be a combination of the following values:
1147   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1148   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1149   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1150   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1151   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1152   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1153   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1154   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1155   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1156   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1157   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1158   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1159   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1160   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1161   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1162   *
1163   *         (*) value not defined in all devices.
1164   * @retval None
1165   */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1166 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1167 {
1168   SET_BIT(DBGMCU->APB1FZR1, Periphs);
1169 }
1170 
1171 /**
1172   * @brief  Freeze APB1 peripherals (group2 peripherals)
1173   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
1174   * @param  Periphs This parameter can be a combination of the following values:
1175   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1176   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1177   *
1178   *         (*) value not defined in all devices.
1179   * @retval None
1180   */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1181 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1182 {
1183   SET_BIT(DBGMCU->APB1FZR2, Periphs);
1184 }
1185 
1186 /**
1187   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
1188   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1189   * @param  Periphs This parameter can be a combination of the following values:
1190   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1191   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1192   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1193   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1194   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1195   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1196   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1197   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1198   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1199   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1200   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1201   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1202   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
1203   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
1204   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1205   *
1206   *         (*) value not defined in all devices.
1207   * @retval None
1208   */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1209 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1210 {
1211   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1212 }
1213 
1214 /**
1215   * @brief  Unfreeze APB1 peripherals (group2 peripherals)
1216   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1217   * @param  Periphs This parameter can be a combination of the following values:
1218   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
1219   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1220   *
1221   *         (*) value not defined in all devices.
1222   * @retval None
1223   */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1224 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1225 {
1226   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1227 }
1228 
1229 /**
1230   * @brief  Freeze APB2 peripherals
1231   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
1232   * @param  Periphs This parameter can be a combination of the following values:
1233   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1234   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1235   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1236   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1237   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1238   *
1239   *         (*) value not defined in all devices.
1240   * @retval None
1241   */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1242 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1243 {
1244   SET_BIT(DBGMCU->APB2FZ, Periphs);
1245 }
1246 
1247 /**
1248   * @brief  Unfreeze APB2 peripherals
1249   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1250   * @param  Periphs This parameter can be a combination of the following values:
1251   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1252   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1253   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1254   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1255   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
1256   *
1257   *         (*) value not defined in all devices.
1258   * @retval None
1259   */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1260 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1261 {
1262   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1263 }
1264 
1265 /**
1266   * @}
1267   */
1268 
1269 #if defined(VREFBUF)
1270 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1271   * @{
1272   */
1273 
1274 /**
1275   * @brief  Enable Internal voltage reference
1276   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
1277   * @retval None
1278   */
LL_VREFBUF_Enable(void)1279 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1280 {
1281   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1282 }
1283 
1284 /**
1285   * @brief  Disable Internal voltage reference
1286   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
1287   * @retval None
1288   */
LL_VREFBUF_Disable(void)1289 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1290 {
1291   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1292 }
1293 
1294 /**
1295   * @brief  Enable high impedance (VREF+pin is high impedance)
1296   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
1297   * @retval None
1298   */
LL_VREFBUF_EnableHIZ(void)1299 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1300 {
1301   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1302 }
1303 
1304 /**
1305   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1306   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
1307   * @retval None
1308   */
LL_VREFBUF_DisableHIZ(void)1309 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1310 {
1311   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1312 }
1313 
1314 /**
1315   * @brief  Set the Voltage reference scale
1316   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
1317   * @param  Scale This parameter can be one of the following values:
1318   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1319   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1320   * @retval None
1321   */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1322 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1323 {
1324   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1325 }
1326 
1327 /**
1328   * @brief  Get the Voltage reference scale
1329   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
1330   * @retval Returned value can be one of the following values:
1331   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1332   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1333   */
LL_VREFBUF_GetVoltageScaling(void)1334 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1335 {
1336   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1337 }
1338 
1339 /**
1340   * @brief  Check if Voltage reference buffer is ready
1341   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
1342   * @retval State of bit (1 or 0).
1343   */
LL_VREFBUF_IsVREFReady(void)1344 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1345 {
1346   return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
1347 }
1348 
1349 /**
1350   * @brief  Get the trimming code for VREFBUF calibration
1351   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
1352   * @retval Between 0 and 0x3F
1353   */
LL_VREFBUF_GetTrimming(void)1354 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1355 {
1356   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1357 }
1358 
1359 /**
1360   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1361   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
1362   * @param  Value Between 0 and 0x3F
1363   * @retval None
1364   */
LL_VREFBUF_SetTrimming(uint32_t Value)1365 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1366 {
1367   WRITE_REG(VREFBUF->CCR, Value);
1368 }
1369 
1370 /**
1371   * @}
1372   */
1373 #endif /* VREFBUF */
1374 
1375 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1376   * @{
1377   */
1378 
1379 /**
1380   * @brief  Set FLASH Latency
1381   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
1382   * @param  Latency This parameter can be one of the following values:
1383   *         @arg @ref LL_FLASH_LATENCY_0
1384   *         @arg @ref LL_FLASH_LATENCY_1
1385   *         @arg @ref LL_FLASH_LATENCY_2
1386   *         @arg @ref LL_FLASH_LATENCY_3
1387   *         @arg @ref LL_FLASH_LATENCY_4
1388   *         @arg @ref LL_FLASH_LATENCY_5 (*)
1389   *         @arg @ref LL_FLASH_LATENCY_6 (*)
1390   *         @arg @ref LL_FLASH_LATENCY_7 (*)
1391   *         @arg @ref LL_FLASH_LATENCY_8 (*)
1392   *         @arg @ref LL_FLASH_LATENCY_9 (*)
1393   *         @arg @ref LL_FLASH_LATENCY_10 (*)
1394   *         @arg @ref LL_FLASH_LATENCY_11 (*)
1395   *         @arg @ref LL_FLASH_LATENCY_12 (*)
1396   *         @arg @ref LL_FLASH_LATENCY_13 (*)
1397   *         @arg @ref LL_FLASH_LATENCY_14 (*)
1398   *         @arg @ref LL_FLASH_LATENCY_15 (*)
1399   *
1400   *         (*) value not defined in all devices.
1401   * @retval None
1402   */
LL_FLASH_SetLatency(uint32_t Latency)1403 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1404 {
1405   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1406 }
1407 
1408 /**
1409   * @brief  Get FLASH Latency
1410   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
1411   * @retval Returned value can be one of the following values:
1412   *         @arg @ref LL_FLASH_LATENCY_0
1413   *         @arg @ref LL_FLASH_LATENCY_1
1414   *         @arg @ref LL_FLASH_LATENCY_2
1415   *         @arg @ref LL_FLASH_LATENCY_3
1416   *         @arg @ref LL_FLASH_LATENCY_4
1417   *         @arg @ref LL_FLASH_LATENCY_5 (*)
1418   *         @arg @ref LL_FLASH_LATENCY_6 (*)
1419   *         @arg @ref LL_FLASH_LATENCY_7 (*)
1420   *         @arg @ref LL_FLASH_LATENCY_8 (*)
1421   *         @arg @ref LL_FLASH_LATENCY_9 (*)
1422   *         @arg @ref LL_FLASH_LATENCY_10 (*)
1423   *         @arg @ref LL_FLASH_LATENCY_11 (*)
1424   *         @arg @ref LL_FLASH_LATENCY_12 (*)
1425   *         @arg @ref LL_FLASH_LATENCY_13 (*)
1426   *         @arg @ref LL_FLASH_LATENCY_14 (*)
1427   *         @arg @ref LL_FLASH_LATENCY_15 (*)
1428   *
1429   *         (*) value not defined in all devices.
1430   */
LL_FLASH_GetLatency(void)1431 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1432 {
1433   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1434 }
1435 
1436 /**
1437   * @brief  Enable Prefetch
1438   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
1439   * @retval None
1440   */
LL_FLASH_EnablePrefetch(void)1441 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1442 {
1443   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1444 }
1445 
1446 /**
1447   * @brief  Disable Prefetch
1448   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
1449   * @retval None
1450   */
LL_FLASH_DisablePrefetch(void)1451 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1452 {
1453   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1454 }
1455 
1456 /**
1457   * @brief  Check if Prefetch buffer is enabled
1458   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
1459   * @retval State of bit (1 or 0).
1460   */
LL_FLASH_IsPrefetchEnabled(void)1461 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1462 {
1463   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1464 }
1465 
1466 /**
1467   * @brief  Enable Instruction cache
1468   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
1469   * @retval None
1470   */
LL_FLASH_EnableInstCache(void)1471 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1472 {
1473   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1474 }
1475 
1476 /**
1477   * @brief  Disable Instruction cache
1478   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
1479   * @retval None
1480   */
LL_FLASH_DisableInstCache(void)1481 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1482 {
1483   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1484 }
1485 
1486 /**
1487   * @brief  Enable Data cache
1488   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
1489   * @retval None
1490   */
LL_FLASH_EnableDataCache(void)1491 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1492 {
1493   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1494 }
1495 
1496 /**
1497   * @brief  Disable Data cache
1498   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
1499   * @retval None
1500   */
LL_FLASH_DisableDataCache(void)1501 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1502 {
1503   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1504 }
1505 
1506 /**
1507   * @brief  Enable Instruction cache reset
1508   * @note  bit can be written only when the instruction cache is disabled
1509   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
1510   * @retval None
1511   */
LL_FLASH_EnableInstCacheReset(void)1512 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1513 {
1514   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1515 }
1516 
1517 /**
1518   * @brief  Disable Instruction cache reset
1519   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
1520   * @retval None
1521   */
LL_FLASH_DisableInstCacheReset(void)1522 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1523 {
1524   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1525 }
1526 
1527 /**
1528   * @brief  Enable Data cache reset
1529   * @note bit can be written only when the data cache is disabled
1530   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
1531   * @retval None
1532   */
LL_FLASH_EnableDataCacheReset(void)1533 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1534 {
1535   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1536 }
1537 
1538 /**
1539   * @brief  Disable Data cache reset
1540   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
1541   * @retval None
1542   */
LL_FLASH_DisableDataCacheReset(void)1543 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1544 {
1545   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1546 }
1547 
1548 /**
1549   * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
1550   * @note Flash memory can be put in power-down mode only when the code is executed
1551   *       from RAM
1552   * @note Flash must not be accessed when power down is enabled
1553   * @note Flash must not be put in power-down while a program or an erase operation
1554   *       is on-going
1555   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
1556   *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
1557   *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
1558   * @retval None
1559   */
LL_FLASH_EnableRunPowerDown(void)1560 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
1561 {
1562   /* Following values must be written consecutively to unlock the RUN_PD bit in
1563      FLASH_ACR */
1564   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1565   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1566   SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1567 }
1568 
1569 /**
1570   * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
1571   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
1572   *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
1573   *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
1574   * @retval None
1575   */
LL_FLASH_DisableRunPowerDown(void)1576 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
1577 {
1578   /* Following values must be written consecutively to unlock the RUN_PD bit in
1579      FLASH_ACR */
1580   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
1581   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
1582   CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
1583 }
1584 
1585 /**
1586   * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
1587   * @note Flash must not be put in power-down while a program or an erase operation
1588   *       is on-going
1589   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
1590   * @retval None
1591   */
LL_FLASH_EnableSleepPowerDown(void)1592 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
1593 {
1594   SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1595 }
1596 
1597 /**
1598   * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
1599   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
1600   * @retval None
1601   */
LL_FLASH_DisableSleepPowerDown(void)1602 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
1603 {
1604   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
1605 }
1606 
1607 /**
1608   * @}
1609   */
1610 
1611 /**
1612   * @}
1613   */
1614 
1615 /**
1616   * @}
1617   */
1618 
1619 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
1620 
1621 /**
1622   * @}
1623   */
1624 
1625 #ifdef __cplusplus
1626 }
1627 #endif
1628 
1629 #endif /* STM32L4xx_LL_SYSTEM_H */
1630