1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_SPI_H
21 #define STM32L4xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief SPI Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary
59 function @ref LL_SPI_SetTransferDirection().*/
60
61 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
62 This parameter can be a value of @ref SPI_LL_EC_MODE.
63
64 This feature can be modified afterwards using unitary
65 function @ref LL_SPI_SetMode().*/
66
67 uint32_t DataWidth; /*!< Specifies the SPI data width.
68 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
69
70 This feature can be modified afterwards using unitary
71 function @ref LL_SPI_SetDataWidth().*/
72
73 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
74 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
75
76 This feature can be modified afterwards using unitary
77 function @ref LL_SPI_SetClockPolarity().*/
78
79 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
80 This parameter can be a value of @ref SPI_LL_EC_PHASE.
81
82 This feature can be modified afterwards using unitary
83 function @ref LL_SPI_SetClockPhase().*/
84
85 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
86 or by software using the SSI bit.
87 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
88
89 This feature can be modified afterwards using unitary
90 function @ref LL_SPI_SetNSSMode().*/
91
92 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used
93 to configure the transmit and receive SCK clock.
94 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
95 @note The communication clock is derived from the master clock.
96 The slave clock does not need to be set.
97
98 This feature can be modified afterwards using unitary
99 function @ref LL_SPI_SetBaudRatePrescaler().*/
100
101 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
102 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
103
104 This feature can be modified afterwards using unitary
105 function @ref LL_SPI_SetTransferBitOrder().*/
106
107 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
108 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
109
110 This feature can be modified afterwards using unitary
111 functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
112
113 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
115
116 This feature can be modified afterwards using unitary
117 function @ref LL_SPI_SetCRCPolynomial().*/
118
119 } LL_SPI_InitTypeDef;
120
121 /**
122 * @}
123 */
124 #endif /* USE_FULL_LL_DRIVER */
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
128 * @{
129 */
130
131 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
132 * @brief Flags defines which can be used with LL_SPI_ReadReg function
133 * @{
134 */
135 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
136 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
137 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
138 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
139 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
140 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
141 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
142 /**
143 * @}
144 */
145
146 /** @defgroup SPI_LL_EC_IT IT Defines
147 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
148 * @{
149 */
150 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
151 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
152 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
153 /**
154 * @}
155 */
156
157 /** @defgroup SPI_LL_EC_MODE Operation Mode
158 * @{
159 */
160 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
161 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
162 /**
163 * @}
164 */
165
166 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
167 * @{
168 */
169 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
170 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
171 /**
172 * @}
173 */
174
175 /** @defgroup SPI_LL_EC_PHASE Clock Phase
176 * @{
177 */
178 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
179 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
180 /**
181 * @}
182 */
183
184 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
185 * @{
186 */
187 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
188 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
189 /**
190 * @}
191 */
192
193 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
194 * @{
195 */
196 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
197 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
198 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
199 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
200 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
201 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
202 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
203 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
204 /**
205 * @}
206 */
207
208 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
209 * @{
210 */
211 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
212 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
213 /**
214 * @}
215 */
216
217 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
218 * @{
219 */
220 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
221 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
222 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
223 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
224 /**
225 * @}
226 */
227
228 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
229 * @{
230 */
231 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
232 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
233 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
234 /**
235 * @}
236 */
237
238 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
239 * @{
240 */
241 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
242 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
243 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
244 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
245 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
246 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
247 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
248 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
249 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
250 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
251 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
252 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
253 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
254 /**
255 * @}
256 */
257 #if defined(USE_FULL_LL_DRIVER)
258
259 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
260 * @{
261 */
262 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
263 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
264 /**
265 * @}
266 */
267 #endif /* USE_FULL_LL_DRIVER */
268
269 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
270 * @{
271 */
272 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
273 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
274 /**
275 * @}
276 */
277
278 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
279 * @{
280 */
281 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
282 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
283 /**
284 * @}
285 */
286
287 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
288 * @{
289 */
290 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
291 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
292 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
293 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
294 /**
295 * @}
296 */
297
298 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
299 * @{
300 */
301 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
302 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
303 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
304 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
305 /**
306 * @}
307 */
308
309 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
310 * @{
311 */
312 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
313 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
314
315 /**
316 * @}
317 */
318
319 /**
320 * @}
321 */
322
323 /* Exported macro ------------------------------------------------------------*/
324 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
325 * @{
326 */
327
328 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
329 * @{
330 */
331
332 /**
333 * @brief Write a value in SPI register
334 * @param __INSTANCE__ SPI Instance
335 * @param __REG__ Register to be written
336 * @param __VALUE__ Value to be written in the register
337 * @retval None
338 */
339 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
340
341 /**
342 * @brief Read a value in SPI register
343 * @param __INSTANCE__ SPI Instance
344 * @param __REG__ Register to be read
345 * @retval Register value
346 */
347 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
348 /**
349 * @}
350 */
351
352 /**
353 * @}
354 */
355
356 /* Exported functions --------------------------------------------------------*/
357 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
358 * @{
359 */
360
361 /** @defgroup SPI_LL_EF_Configuration Configuration
362 * @{
363 */
364
365 /**
366 * @brief Enable SPI peripheral
367 * @rmtoll CR1 SPE LL_SPI_Enable
368 * @param SPIx SPI Instance
369 * @retval None
370 */
LL_SPI_Enable(SPI_TypeDef * SPIx)371 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
372 {
373 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
374 }
375
376 /**
377 * @brief Disable SPI peripheral
378 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
379 * @rmtoll CR1 SPE LL_SPI_Disable
380 * @param SPIx SPI Instance
381 * @retval None
382 */
LL_SPI_Disable(SPI_TypeDef * SPIx)383 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
384 {
385 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
386 }
387
388 /**
389 * @brief Check if SPI peripheral is enabled
390 * @rmtoll CR1 SPE LL_SPI_IsEnabled
391 * @param SPIx SPI Instance
392 * @retval State of bit (1 or 0).
393 */
LL_SPI_IsEnabled(const SPI_TypeDef * SPIx)394 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
395 {
396 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
397 }
398
399 /**
400 * @brief Set SPI operation mode to Master or Slave
401 * @note This bit should not be changed when communication is ongoing.
402 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
403 * CR1 SSI LL_SPI_SetMode
404 * @param SPIx SPI Instance
405 * @param Mode This parameter can be one of the following values:
406 * @arg @ref LL_SPI_MODE_MASTER
407 * @arg @ref LL_SPI_MODE_SLAVE
408 * @retval None
409 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)410 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
411 {
412 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
413 }
414
415 /**
416 * @brief Get SPI operation mode (Master or Slave)
417 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
418 * CR1 SSI LL_SPI_GetMode
419 * @param SPIx SPI Instance
420 * @retval Returned value can be one of the following values:
421 * @arg @ref LL_SPI_MODE_MASTER
422 * @arg @ref LL_SPI_MODE_SLAVE
423 */
LL_SPI_GetMode(const SPI_TypeDef * SPIx)424 __STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
425 {
426 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
427 }
428
429 /**
430 * @brief Set serial protocol used
431 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
432 * @rmtoll CR2 FRF LL_SPI_SetStandard
433 * @param SPIx SPI Instance
434 * @param Standard This parameter can be one of the following values:
435 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
436 * @arg @ref LL_SPI_PROTOCOL_TI
437 * @retval None
438 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)439 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
440 {
441 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
442 }
443
444 /**
445 * @brief Get serial protocol used
446 * @rmtoll CR2 FRF LL_SPI_GetStandard
447 * @param SPIx SPI Instance
448 * @retval Returned value can be one of the following values:
449 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
450 * @arg @ref LL_SPI_PROTOCOL_TI
451 */
LL_SPI_GetStandard(const SPI_TypeDef * SPIx)452 __STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
453 {
454 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
455 }
456
457 /**
458 * @brief Set clock phase
459 * @note This bit should not be changed when communication is ongoing.
460 * This bit is not used in SPI TI mode.
461 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
462 * @param SPIx SPI Instance
463 * @param ClockPhase This parameter can be one of the following values:
464 * @arg @ref LL_SPI_PHASE_1EDGE
465 * @arg @ref LL_SPI_PHASE_2EDGE
466 * @retval None
467 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)468 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
469 {
470 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
471 }
472
473 /**
474 * @brief Get clock phase
475 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
476 * @param SPIx SPI Instance
477 * @retval Returned value can be one of the following values:
478 * @arg @ref LL_SPI_PHASE_1EDGE
479 * @arg @ref LL_SPI_PHASE_2EDGE
480 */
LL_SPI_GetClockPhase(const SPI_TypeDef * SPIx)481 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
482 {
483 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
484 }
485
486 /**
487 * @brief Set clock polarity
488 * @note This bit should not be changed when communication is ongoing.
489 * This bit is not used in SPI TI mode.
490 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
491 * @param SPIx SPI Instance
492 * @param ClockPolarity This parameter can be one of the following values:
493 * @arg @ref LL_SPI_POLARITY_LOW
494 * @arg @ref LL_SPI_POLARITY_HIGH
495 * @retval None
496 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)497 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
498 {
499 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
500 }
501
502 /**
503 * @brief Get clock polarity
504 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
505 * @param SPIx SPI Instance
506 * @retval Returned value can be one of the following values:
507 * @arg @ref LL_SPI_POLARITY_LOW
508 * @arg @ref LL_SPI_POLARITY_HIGH
509 */
LL_SPI_GetClockPolarity(const SPI_TypeDef * SPIx)510 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
511 {
512 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
513 }
514
515 /**
516 * @brief Set baud rate prescaler
517 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
518 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
519 * @param SPIx SPI Instance
520 * @param BaudRate This parameter can be one of the following values:
521 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
522 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
523 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
524 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
525 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
526 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
527 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
529 * @retval None
530 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)531 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
532 {
533 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
534 }
535
536 /**
537 * @brief Get baud rate prescaler
538 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
539 * @param SPIx SPI Instance
540 * @retval Returned value can be one of the following values:
541 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
542 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
543 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
544 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
545 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
546 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
547 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
549 */
LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef * SPIx)550 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
551 {
552 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
553 }
554
555 /**
556 * @brief Set transfer bit order
557 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
558 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
559 * @param SPIx SPI Instance
560 * @param BitOrder This parameter can be one of the following values:
561 * @arg @ref LL_SPI_LSB_FIRST
562 * @arg @ref LL_SPI_MSB_FIRST
563 * @retval None
564 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)565 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
566 {
567 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
568 }
569
570 /**
571 * @brief Get transfer bit order
572 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
573 * @param SPIx SPI Instance
574 * @retval Returned value can be one of the following values:
575 * @arg @ref LL_SPI_LSB_FIRST
576 * @arg @ref LL_SPI_MSB_FIRST
577 */
LL_SPI_GetTransferBitOrder(const SPI_TypeDef * SPIx)578 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
579 {
580 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
581 }
582
583 /**
584 * @brief Set transfer direction mode
585 * @note For Half-Duplex mode, Rx Direction is set by default.
586 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
587 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
588 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
589 * CR1 BIDIOE LL_SPI_SetTransferDirection
590 * @param SPIx SPI Instance
591 * @param TransferDirection This parameter can be one of the following values:
592 * @arg @ref LL_SPI_FULL_DUPLEX
593 * @arg @ref LL_SPI_SIMPLEX_RX
594 * @arg @ref LL_SPI_HALF_DUPLEX_RX
595 * @arg @ref LL_SPI_HALF_DUPLEX_TX
596 * @retval None
597 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)598 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
599 {
600 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
601 }
602
603 /**
604 * @brief Get transfer direction mode
605 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
606 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
607 * CR1 BIDIOE LL_SPI_GetTransferDirection
608 * @param SPIx SPI Instance
609 * @retval Returned value can be one of the following values:
610 * @arg @ref LL_SPI_FULL_DUPLEX
611 * @arg @ref LL_SPI_SIMPLEX_RX
612 * @arg @ref LL_SPI_HALF_DUPLEX_RX
613 * @arg @ref LL_SPI_HALF_DUPLEX_TX
614 */
LL_SPI_GetTransferDirection(const SPI_TypeDef * SPIx)615 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
616 {
617 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
618 }
619
620 /**
621 * @brief Set frame data width
622 * @rmtoll CR2 DS LL_SPI_SetDataWidth
623 * @param SPIx SPI Instance
624 * @param DataWidth This parameter can be one of the following values:
625 * @arg @ref LL_SPI_DATAWIDTH_4BIT
626 * @arg @ref LL_SPI_DATAWIDTH_5BIT
627 * @arg @ref LL_SPI_DATAWIDTH_6BIT
628 * @arg @ref LL_SPI_DATAWIDTH_7BIT
629 * @arg @ref LL_SPI_DATAWIDTH_8BIT
630 * @arg @ref LL_SPI_DATAWIDTH_9BIT
631 * @arg @ref LL_SPI_DATAWIDTH_10BIT
632 * @arg @ref LL_SPI_DATAWIDTH_11BIT
633 * @arg @ref LL_SPI_DATAWIDTH_12BIT
634 * @arg @ref LL_SPI_DATAWIDTH_13BIT
635 * @arg @ref LL_SPI_DATAWIDTH_14BIT
636 * @arg @ref LL_SPI_DATAWIDTH_15BIT
637 * @arg @ref LL_SPI_DATAWIDTH_16BIT
638 * @retval None
639 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)640 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
641 {
642 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
643 }
644
645 /**
646 * @brief Get frame data width
647 * @rmtoll CR2 DS LL_SPI_GetDataWidth
648 * @param SPIx SPI Instance
649 * @retval Returned value can be one of the following values:
650 * @arg @ref LL_SPI_DATAWIDTH_4BIT
651 * @arg @ref LL_SPI_DATAWIDTH_5BIT
652 * @arg @ref LL_SPI_DATAWIDTH_6BIT
653 * @arg @ref LL_SPI_DATAWIDTH_7BIT
654 * @arg @ref LL_SPI_DATAWIDTH_8BIT
655 * @arg @ref LL_SPI_DATAWIDTH_9BIT
656 * @arg @ref LL_SPI_DATAWIDTH_10BIT
657 * @arg @ref LL_SPI_DATAWIDTH_11BIT
658 * @arg @ref LL_SPI_DATAWIDTH_12BIT
659 * @arg @ref LL_SPI_DATAWIDTH_13BIT
660 * @arg @ref LL_SPI_DATAWIDTH_14BIT
661 * @arg @ref LL_SPI_DATAWIDTH_15BIT
662 * @arg @ref LL_SPI_DATAWIDTH_16BIT
663 */
LL_SPI_GetDataWidth(const SPI_TypeDef * SPIx)664 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
665 {
666 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
667 }
668
669 /**
670 * @brief Set threshold of RXFIFO that triggers an RXNE event
671 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
672 * @param SPIx SPI Instance
673 * @param Threshold This parameter can be one of the following values:
674 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
675 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
676 * @retval None
677 */
LL_SPI_SetRxFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)678 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
679 {
680 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
681 }
682
683 /**
684 * @brief Get threshold of RXFIFO that triggers an RXNE event
685 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
686 * @param SPIx SPI Instance
687 * @retval Returned value can be one of the following values:
688 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
689 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
690 */
LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef * SPIx)691 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx)
692 {
693 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
694 }
695
696 /**
697 * @}
698 */
699
700 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
701 * @{
702 */
703
704 /**
705 * @brief Enable CRC
706 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
707 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
708 * @param SPIx SPI Instance
709 * @retval None
710 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)711 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
712 {
713 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
714 }
715
716 /**
717 * @brief Disable CRC
718 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
719 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
720 * @param SPIx SPI Instance
721 * @retval None
722 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)723 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
724 {
725 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
726 }
727
728 /**
729 * @brief Check if CRC is enabled
730 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
731 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
732 * @param SPIx SPI Instance
733 * @retval State of bit (1 or 0).
734 */
LL_SPI_IsEnabledCRC(const SPI_TypeDef * SPIx)735 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
736 {
737 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
738 }
739
740 /**
741 * @brief Set CRC Length
742 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
743 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
744 * @param SPIx SPI Instance
745 * @param CRCLength This parameter can be one of the following values:
746 * @arg @ref LL_SPI_CRC_8BIT
747 * @arg @ref LL_SPI_CRC_16BIT
748 * @retval None
749 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)750 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
751 {
752 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
753 }
754
755 /**
756 * @brief Get CRC Length
757 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
758 * @param SPIx SPI Instance
759 * @retval Returned value can be one of the following values:
760 * @arg @ref LL_SPI_CRC_8BIT
761 * @arg @ref LL_SPI_CRC_16BIT
762 */
LL_SPI_GetCRCWidth(const SPI_TypeDef * SPIx)763 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
764 {
765 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
766 }
767
768 /**
769 * @brief Set CRCNext to transfer CRC on the line
770 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
771 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
772 * @param SPIx SPI Instance
773 * @retval None
774 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)775 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
776 {
777 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
778 }
779
780 /**
781 * @brief Set polynomial for CRC calculation
782 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
783 * @param SPIx SPI Instance
784 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
785 * @retval None
786 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)787 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
788 {
789 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
790 }
791
792 /**
793 * @brief Get polynomial for CRC calculation
794 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
795 * @param SPIx SPI Instance
796 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
797 */
LL_SPI_GetCRCPolynomial(const SPI_TypeDef * SPIx)798 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
799 {
800 return (uint32_t)(READ_REG(SPIx->CRCPR));
801 }
802
803 /**
804 * @brief Get Rx CRC
805 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
806 * @param SPIx SPI Instance
807 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
808 */
LL_SPI_GetRxCRC(const SPI_TypeDef * SPIx)809 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
810 {
811 return (uint32_t)(READ_REG(SPIx->RXCRCR));
812 }
813
814 /**
815 * @brief Get Tx CRC
816 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
817 * @param SPIx SPI Instance
818 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
819 */
LL_SPI_GetTxCRC(const SPI_TypeDef * SPIx)820 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
821 {
822 return (uint32_t)(READ_REG(SPIx->TXCRCR));
823 }
824
825 /**
826 * @}
827 */
828
829 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
830 * @{
831 */
832
833 /**
834 * @brief Set NSS mode
835 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
836 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
837 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
838 * @param SPIx SPI Instance
839 * @param NSS This parameter can be one of the following values:
840 * @arg @ref LL_SPI_NSS_SOFT
841 * @arg @ref LL_SPI_NSS_HARD_INPUT
842 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
843 * @retval None
844 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)845 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
846 {
847 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
848 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
849 }
850
851 /**
852 * @brief Get NSS mode
853 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
854 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
855 * @param SPIx SPI Instance
856 * @retval Returned value can be one of the following values:
857 * @arg @ref LL_SPI_NSS_SOFT
858 * @arg @ref LL_SPI_NSS_HARD_INPUT
859 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
860 */
LL_SPI_GetNSSMode(const SPI_TypeDef * SPIx)861 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
862 {
863 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
864 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
865 return (Ssm | Ssoe);
866 }
867
868 /**
869 * @brief Enable NSS pulse management
870 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
871 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
872 * @param SPIx SPI Instance
873 * @retval None
874 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)875 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
876 {
877 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
878 }
879
880 /**
881 * @brief Disable NSS pulse management
882 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
883 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
884 * @param SPIx SPI Instance
885 * @retval None
886 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)887 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
888 {
889 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
890 }
891
892 /**
893 * @brief Check if NSS pulse is enabled
894 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
895 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
896 * @param SPIx SPI Instance
897 * @retval State of bit (1 or 0).
898 */
LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef * SPIx)899 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
900 {
901 return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
902 }
903
904 /**
905 * @}
906 */
907
908 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
909 * @{
910 */
911
912 /**
913 * @brief Check if Rx buffer is not empty
914 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
915 * @param SPIx SPI Instance
916 * @retval State of bit (1 or 0).
917 */
LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef * SPIx)918 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
919 {
920 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
921 }
922
923 /**
924 * @brief Check if Tx buffer is empty
925 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
926 * @param SPIx SPI Instance
927 * @retval State of bit (1 or 0).
928 */
LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef * SPIx)929 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
930 {
931 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
932 }
933
934 /**
935 * @brief Get CRC error flag
936 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
937 * @param SPIx SPI Instance
938 * @retval State of bit (1 or 0).
939 */
LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef * SPIx)940 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
941 {
942 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
943 }
944
945 /**
946 * @brief Get mode fault error flag
947 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
948 * @param SPIx SPI Instance
949 * @retval State of bit (1 or 0).
950 */
LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef * SPIx)951 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
952 {
953 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
954 }
955
956 /**
957 * @brief Get overrun error flag
958 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
959 * @param SPIx SPI Instance
960 * @retval State of bit (1 or 0).
961 */
LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef * SPIx)962 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
963 {
964 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
965 }
966
967 /**
968 * @brief Get busy flag
969 * @note The BSY flag is cleared under any one of the following conditions:
970 * -When the SPI is correctly disabled
971 * -When a fault is detected in Master mode (MODF bit set to 1)
972 * -In Master mode, when it finishes a data transmission and no new data is ready to be
973 * sent
974 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
975 * each data transfer.
976 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
977 * @param SPIx SPI Instance
978 * @retval State of bit (1 or 0).
979 */
LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef * SPIx)980 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
981 {
982 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
983 }
984
985 /**
986 * @brief Get frame format error flag
987 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
988 * @param SPIx SPI Instance
989 * @retval State of bit (1 or 0).
990 */
LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef * SPIx)991 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
992 {
993 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
994 }
995
996 /**
997 * @brief Get FIFO reception Level
998 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
999 * @param SPIx SPI Instance
1000 * @retval Returned value can be one of the following values:
1001 * @arg @ref LL_SPI_RX_FIFO_EMPTY
1002 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
1003 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
1004 * @arg @ref LL_SPI_RX_FIFO_FULL
1005 */
LL_SPI_GetRxFIFOLevel(const SPI_TypeDef * SPIx)1006 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx)
1007 {
1008 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
1009 }
1010
1011 /**
1012 * @brief Get FIFO Transmission Level
1013 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
1014 * @param SPIx SPI Instance
1015 * @retval Returned value can be one of the following values:
1016 * @arg @ref LL_SPI_TX_FIFO_EMPTY
1017 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
1018 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
1019 * @arg @ref LL_SPI_TX_FIFO_FULL
1020 */
LL_SPI_GetTxFIFOLevel(const SPI_TypeDef * SPIx)1021 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx)
1022 {
1023 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
1024 }
1025
1026 /**
1027 * @brief Clear CRC error flag
1028 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
1029 * @param SPIx SPI Instance
1030 * @retval None
1031 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1032 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1033 {
1034 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
1035 }
1036
1037 /**
1038 * @brief Clear mode fault error flag
1039 * @note Clearing this flag is done by a read access to the SPIx_SR
1040 * register followed by a write access to the SPIx_CR1 register
1041 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
1042 * @param SPIx SPI Instance
1043 * @retval None
1044 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1045 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1046 {
1047 __IO uint32_t tmpreg_sr;
1048 tmpreg_sr = SPIx->SR;
1049 (void) tmpreg_sr;
1050 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
1051 }
1052
1053 /**
1054 * @brief Clear overrun error flag
1055 * @note Clearing this flag is done by a read access to the SPIx_DR
1056 * register followed by a read access to the SPIx_SR register
1057 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
1058 * @param SPIx SPI Instance
1059 * @retval None
1060 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1061 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1062 {
1063 __IO uint32_t tmpreg;
1064 tmpreg = SPIx->DR;
1065 (void) tmpreg;
1066 tmpreg = SPIx->SR;
1067 (void) tmpreg;
1068 }
1069
1070 /**
1071 * @brief Clear frame format error flag
1072 * @note Clearing this flag is done by reading SPIx_SR register
1073 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
1074 * @param SPIx SPI Instance
1075 * @retval None
1076 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1077 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1078 {
1079 __IO uint32_t tmpreg;
1080 tmpreg = SPIx->SR;
1081 (void) tmpreg;
1082 }
1083
1084 /**
1085 * @}
1086 */
1087
1088 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
1089 * @{
1090 */
1091
1092 /**
1093 * @brief Enable error interrupt
1094 * @note This bit controls the generation of an interrupt when an error condition
1095 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1096 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
1097 * @param SPIx SPI Instance
1098 * @retval None
1099 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)1100 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
1101 {
1102 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1103 }
1104
1105 /**
1106 * @brief Enable Rx buffer not empty interrupt
1107 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
1108 * @param SPIx SPI Instance
1109 * @retval None
1110 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)1111 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
1112 {
1113 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1114 }
1115
1116 /**
1117 * @brief Enable Tx buffer empty interrupt
1118 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
1119 * @param SPIx SPI Instance
1120 * @retval None
1121 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)1122 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
1123 {
1124 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1125 }
1126
1127 /**
1128 * @brief Disable error interrupt
1129 * @note This bit controls the generation of an interrupt when an error condition
1130 * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1131 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
1132 * @param SPIx SPI Instance
1133 * @retval None
1134 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)1135 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
1136 {
1137 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1138 }
1139
1140 /**
1141 * @brief Disable Rx buffer not empty interrupt
1142 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
1143 * @param SPIx SPI Instance
1144 * @retval None
1145 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)1146 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
1147 {
1148 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1149 }
1150
1151 /**
1152 * @brief Disable Tx buffer empty interrupt
1153 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
1154 * @param SPIx SPI Instance
1155 * @retval None
1156 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)1157 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
1158 {
1159 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1160 }
1161
1162 /**
1163 * @brief Check if error interrupt is enabled
1164 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
1165 * @param SPIx SPI Instance
1166 * @retval State of bit (1 or 0).
1167 */
LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef * SPIx)1168 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
1169 {
1170 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
1171 }
1172
1173 /**
1174 * @brief Check if Rx buffer not empty interrupt is enabled
1175 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
1176 * @param SPIx SPI Instance
1177 * @retval State of bit (1 or 0).
1178 */
LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef * SPIx)1179 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
1180 {
1181 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
1182 }
1183
1184 /**
1185 * @brief Check if Tx buffer empty interrupt
1186 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
1187 * @param SPIx SPI Instance
1188 * @retval State of bit (1 or 0).
1189 */
LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef * SPIx)1190 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
1191 {
1192 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
1193 }
1194
1195 /**
1196 * @}
1197 */
1198
1199 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
1200 * @{
1201 */
1202
1203 /**
1204 * @brief Enable DMA Rx
1205 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1206 * @param SPIx SPI Instance
1207 * @retval None
1208 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)1209 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1210 {
1211 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1212 }
1213
1214 /**
1215 * @brief Disable DMA Rx
1216 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1217 * @param SPIx SPI Instance
1218 * @retval None
1219 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1220 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1221 {
1222 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1223 }
1224
1225 /**
1226 * @brief Check if DMA Rx is enabled
1227 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1228 * @param SPIx SPI Instance
1229 * @retval State of bit (1 or 0).
1230 */
LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef * SPIx)1231 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1232 {
1233 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1234 }
1235
1236 /**
1237 * @brief Enable DMA Tx
1238 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1239 * @param SPIx SPI Instance
1240 * @retval None
1241 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1242 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1243 {
1244 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1245 }
1246
1247 /**
1248 * @brief Disable DMA Tx
1249 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1250 * @param SPIx SPI Instance
1251 * @retval None
1252 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1253 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1254 {
1255 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1256 }
1257
1258 /**
1259 * @brief Check if DMA Tx is enabled
1260 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1261 * @param SPIx SPI Instance
1262 * @retval State of bit (1 or 0).
1263 */
LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef * SPIx)1264 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1265 {
1266 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1267 }
1268
1269 /**
1270 * @brief Set parity of Last DMA reception
1271 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
1272 * @param SPIx SPI Instance
1273 * @param Parity This parameter can be one of the following values:
1274 * @arg @ref LL_SPI_DMA_PARITY_ODD
1275 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1276 * @retval None
1277 */
LL_SPI_SetDMAParity_RX(SPI_TypeDef * SPIx,uint32_t Parity)1278 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
1279 {
1280 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
1281 }
1282
1283 /**
1284 * @brief Get parity configuration for Last DMA reception
1285 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
1286 * @param SPIx SPI Instance
1287 * @retval Returned value can be one of the following values:
1288 * @arg @ref LL_SPI_DMA_PARITY_ODD
1289 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1290 */
LL_SPI_GetDMAParity_RX(const SPI_TypeDef * SPIx)1291 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx)
1292 {
1293 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
1294 }
1295
1296 /**
1297 * @brief Set parity of Last DMA transmission
1298 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
1299 * @param SPIx SPI Instance
1300 * @param Parity This parameter can be one of the following values:
1301 * @arg @ref LL_SPI_DMA_PARITY_ODD
1302 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1303 * @retval None
1304 */
LL_SPI_SetDMAParity_TX(SPI_TypeDef * SPIx,uint32_t Parity)1305 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
1306 {
1307 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
1308 }
1309
1310 /**
1311 * @brief Get parity configuration for Last DMA transmission
1312 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
1313 * @param SPIx SPI Instance
1314 * @retval Returned value can be one of the following values:
1315 * @arg @ref LL_SPI_DMA_PARITY_ODD
1316 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1317 */
LL_SPI_GetDMAParity_TX(const SPI_TypeDef * SPIx)1318 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx)
1319 {
1320 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
1321 }
1322
1323 /**
1324 * @brief Get the data register address used for DMA transfer
1325 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1326 * @param SPIx SPI Instance
1327 * @retval Address of data register
1328 */
LL_SPI_DMA_GetRegAddr(const SPI_TypeDef * SPIx)1329 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
1330 {
1331 return (uint32_t) &(SPIx->DR);
1332 }
1333
1334 /**
1335 * @}
1336 */
1337
1338 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1339 * @{
1340 */
1341
1342 /**
1343 * @brief Read 8-Bits in the data register
1344 * @rmtoll DR DR LL_SPI_ReceiveData8
1345 * @param SPIx SPI Instance
1346 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1347 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1348 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1349 {
1350 return (*((__IO uint8_t *)&SPIx->DR));
1351 }
1352
1353 /**
1354 * @brief Read 16-Bits in the data register
1355 * @rmtoll DR DR LL_SPI_ReceiveData16
1356 * @param SPIx SPI Instance
1357 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1358 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1359 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1360 {
1361 return (uint16_t)(READ_REG(SPIx->DR));
1362 }
1363
1364 /**
1365 * @brief Write 8-Bits in the data register
1366 * @rmtoll DR DR LL_SPI_TransmitData8
1367 * @param SPIx SPI Instance
1368 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1369 * @retval None
1370 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1371 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1372 {
1373 #if defined (__GNUC__)
1374 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1375 *spidr = TxData;
1376 #else
1377 *((__IO uint8_t *)&SPIx->DR) = TxData;
1378 #endif /* __GNUC__ */
1379 }
1380
1381 /**
1382 * @brief Write 16-Bits in the data register
1383 * @rmtoll DR DR LL_SPI_TransmitData16
1384 * @param SPIx SPI Instance
1385 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1386 * @retval None
1387 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1388 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1389 {
1390 #if defined (__GNUC__)
1391 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1392 *spidr = TxData;
1393 #else
1394 SPIx->DR = TxData;
1395 #endif /* __GNUC__ */
1396 }
1397
1398 /**
1399 * @}
1400 */
1401 #if defined(USE_FULL_LL_DRIVER)
1402 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1403 * @{
1404 */
1405
1406 ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
1407 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1408 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1409
1410 /**
1411 * @}
1412 */
1413 #endif /* USE_FULL_LL_DRIVER */
1414 /**
1415 * @}
1416 */
1417
1418 /**
1419 * @}
1420 */
1421
1422 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
1423
1424 /**
1425 * @}
1426 */
1427
1428 #ifdef __cplusplus
1429 }
1430 #endif
1431
1432 #endif /* STM32L4xx_LL_SPI_H */
1433
1434
