1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_LL_SDMMC_H 22 #define STM32L4xx_LL_SDMMC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(SDMMC1) 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32l4xx_hal_def.h" 32 33 /** @addtogroup STM32L4xx_Driver 34 * @{ 35 */ 36 37 /** @addtogroup SDMMC_LL 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief SDMMC Configuration Structure definition 48 */ 49 typedef struct 50 { 51 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 52 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 53 54 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 55 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 56 enabled or disabled. 57 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 58 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 59 60 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 61 disabled when the bus is idle. 62 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 63 64 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 65 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 66 67 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 68 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 69 70 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 71 This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ 72 73 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 74 uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. 75 This parameter can be a value of @ref SDMMC_LL_Transceiver */ 76 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 77 78 }SDMMC_InitTypeDef; 79 80 81 /** 82 * @brief SDMMC Command Control structure 83 */ 84 typedef struct 85 { 86 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 87 to a card as part of a command message. If a command 88 contains an argument, it must be loaded into this register 89 before writing the command to the command register. */ 90 91 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 92 Max_Data = 64 */ 93 94 uint32_t Response; /*!< Specifies the SDMMC response type. 95 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 96 97 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 98 enabled or disabled. 99 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 100 101 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 102 is enabled or disabled. 103 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 104 }SDMMC_CmdInitTypeDef; 105 106 107 /** 108 * @brief SDMMC Data Control structure 109 */ 110 typedef struct 111 { 112 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 113 114 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 115 116 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 117 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 118 119 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 120 is a read or write. 121 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 122 123 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 124 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 125 126 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 127 is enabled or disabled. 128 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 129 }SDMMC_DataInitTypeDef; 130 131 /** 132 * @} 133 */ 134 135 /* Exported constants --------------------------------------------------------*/ 136 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 137 * @{ 138 */ 139 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 140 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 141 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 142 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 143 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 144 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 145 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 146 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 147 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the 148 number of transferred bytes does not match the block length */ 149 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 150 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 151 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 152 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock 153 command or if there was an attempt to access a locked card */ 154 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 155 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 156 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 157 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 158 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 159 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 160 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 161 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 162 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 163 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 164 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out 165 of erase sequence command was received */ 166 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 167 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 168 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 169 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 170 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 171 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 172 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 173 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 174 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 175 176 /** 177 * @brief SDMMC Commands Index 178 */ 179 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 180 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 181 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 182 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 183 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 184 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 185 operating condition register (OCR) content in the response on the CMD line. */ 186 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 187 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 188 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 189 and asks the card whether card supports voltage. */ 190 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 191 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 192 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 193 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 194 #else 195 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ 196 #endif 197 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 198 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 199 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 200 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 201 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands 202 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 203 for SDHS and SDXC. */ 204 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 205 fixed 512 bytes in case of SDHC and SDXC. */ 206 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by 207 STOP_TRANSMISSION command. */ 208 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 209 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 210 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 211 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 212 fixed 512 bytes in case of SDHC and SDXC. */ 213 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 214 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 215 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 216 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 217 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 218 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 219 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 220 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 221 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command 222 system set by switch function command (CMD6). */ 223 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. 224 Reserved for each command system set by switch function command (CMD6). */ 225 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 226 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 227 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 228 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 229 the SET_BLOCK_LEN command. */ 230 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather 231 than a standard command. */ 232 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card 233 for general purpose/application specific commands. */ 234 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 235 236 /** 237 * @brief Following commands are SD Card Specific commands. 238 * SDMMC_APP_CMD should be sent before sending these commands. 239 */ 240 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 241 widths are given in SCR register. */ 242 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 243 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 244 32bit+CRC data block. */ 245 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 246 send its operating condition register (OCR) content in the response on the CMD line. */ 247 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 248 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 249 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 250 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 251 252 /** 253 * @brief Following commands are SD Card Specific security commands. 254 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 255 */ 256 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 257 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 258 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 259 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 260 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 261 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 262 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 263 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 264 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 265 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 266 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 267 268 /** 269 * @brief Masks for errors Card Status R1 (OCR Register) 270 */ 271 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 272 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 273 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 274 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 275 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 276 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 277 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 278 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 279 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 280 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 281 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 282 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 283 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 284 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 285 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 286 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 287 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 288 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 289 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 290 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 291 292 /** 293 * @brief Masks for R6 Response 294 */ 295 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 296 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 297 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 298 299 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 300 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 301 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 302 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 303 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 304 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 305 #define SDMMC_DDR50_SWITCH_PATTERN ((uint32_t)0x80FFFF04U) 306 #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) 307 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 308 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 309 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 310 311 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 312 313 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 314 315 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 316 317 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 318 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 319 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 320 321 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 322 323 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 324 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 325 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 326 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 327 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 328 329 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 330 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 331 332 /** 333 * @brief Command Class supported 334 */ 335 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 336 337 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 338 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 339 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 340 341 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 342 * @{ 343 */ 344 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 345 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 346 347 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 348 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 349 /** 350 * @} 351 */ 352 353 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 354 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 355 * @{ 356 */ 357 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) 358 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 359 360 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 361 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 362 /** 363 * @} 364 */ 365 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 366 367 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 368 * @{ 369 */ 370 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 371 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 372 373 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 374 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 375 /** 376 * @} 377 */ 378 379 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 380 * @{ 381 */ 382 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 383 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 384 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 385 386 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 387 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 388 ((WIDE) == SDMMC_BUS_WIDE_8B)) 389 /** 390 * @} 391 */ 392 393 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 394 /** @defgroup SDMMC_LL_Speed_Mode 395 * @{ 396 */ 397 #define SDMMC_SPEED_MODE_AUTO ((uint32_t)0x00000000U) 398 #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) 399 #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) 400 #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) 401 #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) 402 403 #define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ 404 ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ 405 ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ 406 ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ 407 ((MODE) == SDMMC_SPEED_MODE_DDR)) 408 409 /** 410 * @} 411 */ 412 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 413 414 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 415 * @{ 416 */ 417 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 418 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 419 420 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 421 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 422 /** 423 * @} 424 */ 425 426 /** @defgroup SDMMC_LL_Clock_Division Clock Division 427 * @{ 428 */ 429 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 430 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 431 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 432 #else 433 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) 434 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 435 /** 436 * @} 437 */ 438 439 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 440 /** @defgroup SDMMC_LL_Transceiver Transceiver 441 * @{ 442 */ 443 #define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U) 444 #define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U) 445 446 #define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \ 447 ((MODE) == SDMMC_TRANSCEIVER_ENABLE)) 448 /** 449 * @} 450 */ 451 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 452 453 /** @defgroup SDMMC_LL_Command_Index Command Index 454 * @{ 455 */ 456 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 457 /** 458 * @} 459 */ 460 461 /** @defgroup SDMMC_LL_Response_Type Response Type 462 * @{ 463 */ 464 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 465 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 466 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 467 468 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 469 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 470 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 471 /** 472 * @} 473 */ 474 475 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 476 * @{ 477 */ 478 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 479 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 480 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 481 482 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 483 ((WAIT) == SDMMC_WAIT_IT) || \ 484 ((WAIT) == SDMMC_WAIT_PEND)) 485 /** 486 * @} 487 */ 488 489 /** @defgroup SDMMC_LL_CPSM_State CPSM State 490 * @{ 491 */ 492 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 493 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 494 495 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 496 ((CPSM) == SDMMC_CPSM_ENABLE)) 497 /** 498 * @} 499 */ 500 501 /** @defgroup SDMMC_LL_Response_Registers Response Register 502 * @{ 503 */ 504 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 505 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 506 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 507 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 508 509 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 510 ((RESP) == SDMMC_RESP2) || \ 511 ((RESP) == SDMMC_RESP3) || \ 512 ((RESP) == SDMMC_RESP4)) 513 514 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 515 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 516 * @{ 517 */ 518 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 519 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 520 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 521 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 522 523 /** 524 * @} 525 */ 526 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 527 528 /** @defgroup SDMMC_LL_Data_Length Data Lenght 529 * @{ 530 */ 531 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 532 /** 533 * @} 534 */ 535 536 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 537 * @{ 538 */ 539 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 540 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 541 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 542 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 543 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 544 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 545 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 546 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 547 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 548 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 549 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 550 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 551 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 552 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 553 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 554 555 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 556 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 557 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 558 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 559 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 560 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 561 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 562 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 563 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 564 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 565 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 566 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 567 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 568 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 569 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 570 /** 571 * @} 572 */ 573 574 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 575 * @{ 576 */ 577 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 578 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 579 580 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 581 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 582 /** 583 * @} 584 */ 585 586 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 587 * @{ 588 */ 589 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 590 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 591 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 592 #else 593 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 594 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 595 596 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 597 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 598 /** 599 * @} 600 */ 601 602 /** @defgroup SDMMC_LL_DPSM_State DPSM State 603 * @{ 604 */ 605 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 606 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 607 608 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 609 ((DPSM) == SDMMC_DPSM_ENABLE)) 610 /** 611 * @} 612 */ 613 614 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 615 * @{ 616 */ 617 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 618 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 619 620 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 621 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 622 /** 623 * @} 624 */ 625 626 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 627 * @{ 628 */ 629 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 630 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 631 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 632 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 633 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 634 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 635 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 636 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 637 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 638 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 639 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 640 #endif 641 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 642 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 643 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE 644 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE 645 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE 646 #else 647 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 648 #endif 649 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 650 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 651 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 652 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE 653 #endif 654 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 655 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 656 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 657 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 658 #else 659 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE 660 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE 661 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE 662 #endif 663 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 664 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 665 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 666 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 667 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 668 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 669 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 670 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 671 /** 672 * @} 673 */ 674 675 /** @defgroup SDMMC_LL_Flags Flags 676 * @{ 677 */ 678 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 679 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 680 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 681 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 682 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 683 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 684 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 685 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 686 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 687 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 688 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 689 #endif 690 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 691 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 692 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 693 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 694 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 695 #else 696 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 697 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 698 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 699 #endif 700 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 701 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 702 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 703 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 704 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 705 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 706 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 707 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 708 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 709 #else 710 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 711 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 712 #endif 713 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 714 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 715 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 716 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 717 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 718 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 719 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 720 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 721 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 722 723 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 724 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 725 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 726 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 727 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 728 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 729 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 730 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 731 732 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 733 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 734 735 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 736 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 737 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 738 SDMMC_FLAG_IDMABTC)) 739 740 #else 741 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 742 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 743 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 744 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) 745 746 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 747 SDMMC_FLAG_CMDSENT)) 748 749 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 750 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) 751 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 752 753 /** 754 * @} 755 */ 756 757 /** 758 * @} 759 */ 760 761 /* Exported macro ------------------------------------------------------------*/ 762 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 763 * @{ 764 */ 765 766 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 767 * @brief SDMMC_LL registers bit address in the alias region 768 * @{ 769 */ 770 /* ---------------------- SDMMC registers bit mask --------------------------- */ 771 /* --- CLKCR Register ---*/ 772 /* CLKCR register clear mask */ 773 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 774 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 775 SDMMC_CLKCR_WIDBUS |\ 776 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\ 777 SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\ 778 SDMMC_CLKCR_SELCLKRX)) 779 #else 780 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 781 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 782 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 783 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 784 785 /* --- DCTRL Register ---*/ 786 /* SDMMC DCTRL Clear Mask */ 787 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 788 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 789 790 /* --- CMD Register ---*/ 791 /* CMD Register clear mask */ 792 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 793 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 794 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 795 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 796 #else 797 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 798 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 799 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 800 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 801 802 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 803 /* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 110MHz*/ 804 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x8A) 805 806 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 110MHz*/ 807 #define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x3) 808 809 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 110MHz*/ 810 #define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2) 811 812 /* SDMMC Data Transfer Frequency (25MHz max) */ 813 #define SDMMC_TRANSFER_CLK_DIV SDMMC_NSpeed_CLK_DIV 814 #else 815 /* SDMMC Initialization Frequency (400KHz max) */ 816 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 817 818 /* SDMMC Data Transfer Frequency (25MHz max) */ 819 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ 820 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 821 822 /** 823 * @} 824 */ 825 826 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 827 * @brief macros to handle interrupts and specific clock configurations 828 * @{ 829 */ 830 831 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 832 /** 833 * @brief Enable the SDMMC device. 834 * @param __INSTANCE__ SDMMC Instance 835 * @retval None 836 */ 837 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 838 839 /** 840 * @brief Disable the SDMMC device. 841 * @param __INSTANCE__ SDMMC Instance 842 * @retval None 843 */ 844 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 845 846 /** 847 * @brief Enable the SDMMC DMA transfer. 848 * @param __INSTANCE__ SDMMC Instance 849 * @retval None 850 */ 851 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 852 853 /** 854 * @brief Disable the SDMMC DMA transfer. 855 * @param __INSTANCE__ SDMMC Instance 856 * @retval None 857 */ 858 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 859 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 860 861 /** 862 * @brief Enable the SDMMC device interrupt. 863 * @param __INSTANCE__ Pointer to SDMMC register base 864 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 865 * This parameter can be one or a combination of the following values: 866 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 867 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 868 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 869 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 870 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 871 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 872 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 873 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 874 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 875 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 876 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 877 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 878 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 879 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 880 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 881 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 882 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 883 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 884 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 885 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 886 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 887 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 888 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 889 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 890 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 891 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 892 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 893 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 894 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 895 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 896 * @retval None 897 */ 898 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 899 900 /** 901 * @brief Disable the SDMMC device interrupt. 902 * @param __INSTANCE__ Pointer to SDMMC register base 903 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 904 * This parameter can be one or a combination of the following values: 905 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 906 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 907 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 908 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 909 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 910 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 911 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 912 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 913 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 914 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 915 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 916 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 917 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 918 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 919 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 920 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 921 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 922 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 923 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 924 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 925 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 926 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 927 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 928 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 929 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 930 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 931 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 932 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 933 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 934 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 935 * @retval None 936 */ 937 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 938 939 /** 940 * @brief Checks whether the specified SDMMC flag is set or not. 941 * @param __INSTANCE__ Pointer to SDMMC register base 942 * @param __FLAG__ specifies the flag to check. 943 * This parameter can be one of the following values: 944 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 945 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 946 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 947 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 948 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 949 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 950 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 951 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 952 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 953 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 954 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 955 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 956 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 957 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 958 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 959 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 960 * @arg SDMMC_FLAG_RXACT: Data receive in progress 961 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 962 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 963 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 964 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 965 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 966 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 967 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 968 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 969 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 970 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 971 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 972 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 973 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 974 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 975 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 976 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 977 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 978 * @retval The new state of SDMMC_FLAG (SET or RESET). 979 */ 980 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 981 982 983 /** 984 * @brief Clears the SDMMC pending flags. 985 * @param __INSTANCE__ Pointer to SDMMC register base 986 * @param __FLAG__ specifies the flag to clear. 987 * This parameter can be one or a combination of the following values: 988 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 989 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 990 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 991 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 992 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 993 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 994 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 995 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 996 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 997 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 998 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 999 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 1000 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 1001 * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received 1002 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 1003 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 1004 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 1005 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 1006 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 1007 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 1008 * @retval None 1009 */ 1010 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 1011 1012 /** 1013 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 1014 * @param __INSTANCE__ Pointer to SDMMC register base 1015 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 1016 * This parameter can be one of the following values: 1017 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1018 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1019 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1020 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1021 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1022 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1023 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1024 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1025 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1026 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1027 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1028 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1029 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 1030 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 1031 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 1032 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 1033 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 1034 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 1035 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1036 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1037 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 1038 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 1039 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 1040 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1041 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1042 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1043 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1044 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1045 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1046 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1047 * @retval The new state of SDMMC_IT (SET or RESET). 1048 */ 1049 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 1050 1051 /** 1052 * @brief Clears the SDMMC's interrupt pending bits. 1053 * @param __INSTANCE__ Pointer to SDMMC register base 1054 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1055 * This parameter can be one or a combination of the following values: 1056 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1057 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1058 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1059 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1060 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1061 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1062 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1063 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1064 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 1065 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1066 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 1067 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1068 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1069 * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt 1070 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1071 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1072 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1073 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1074 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1075 * @retval None 1076 */ 1077 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 1078 1079 /** 1080 * @brief Enable Start the SD I/O Read Wait operation. 1081 * @param __INSTANCE__ Pointer to SDMMC register base 1082 * @retval None 1083 */ 1084 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 1085 1086 /** 1087 * @brief Disable Start the SD I/O Read Wait operations. 1088 * @param __INSTANCE__ Pointer to SDMMC register base 1089 * @retval None 1090 */ 1091 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 1092 1093 /** 1094 * @brief Enable Start the SD I/O Read Wait operation. 1095 * @param __INSTANCE__ Pointer to SDMMC register base 1096 * @retval None 1097 */ 1098 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 1099 1100 /** 1101 * @brief Disable Stop the SD I/O Read Wait operations. 1102 * @param __INSTANCE__ Pointer to SDMMC register base 1103 * @retval None 1104 */ 1105 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 1106 1107 /** 1108 * @brief Enable the SD I/O Mode Operation. 1109 * @param __INSTANCE__ Pointer to SDMMC register base 1110 * @retval None 1111 */ 1112 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 1113 1114 /** 1115 * @brief Disable the SD I/O Mode Operation. 1116 * @param __INSTANCE__ Pointer to SDMMC register base 1117 * @retval None 1118 */ 1119 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 1120 1121 /** 1122 * @brief Enable the SD I/O Suspend command sending. 1123 * @param __INSTANCE__ Pointer to SDMMC register base 1124 * @retval None 1125 */ 1126 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1127 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 1128 #else 1129 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 1130 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1131 1132 /** 1133 * @brief Disable the SD I/O Suspend command sending. 1134 * @param __INSTANCE__ Pointer to SDMMC register base 1135 * @retval None 1136 */ 1137 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1138 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 1139 #else 1140 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 1141 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1142 1143 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1144 /** 1145 * @brief Enable the CMDTRANS mode. 1146 * @param __INSTANCE__ Pointer to SDMMC register base 1147 * @retval None 1148 */ 1149 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 1150 1151 /** 1152 * @brief Disable the CMDTRANS mode. 1153 * @param __INSTANCE__ Pointer to SDMMC register base 1154 * @retval None 1155 */ 1156 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1157 1158 /** 1159 * @brief Enable the CMDSTOP mode. 1160 * @param __INSTANCE__ Pointer to SDMMC register base 1161 * @retval None 1162 */ 1163 #define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP) 1164 1165 /** 1166 * @brief Disable the CMDSTOP mode. 1167 * @param __INSTANCE__ Pointer to SDMMC register base 1168 * @retval None 1169 */ 1170 #define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP) 1171 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1172 1173 /** 1174 * @} 1175 */ 1176 1177 /** 1178 * @} 1179 */ 1180 1181 /* Exported functions --------------------------------------------------------*/ 1182 /** @addtogroup SDMMC_LL_Exported_Functions 1183 * @{ 1184 */ 1185 1186 /* Initialization/de-initialization functions **********************************/ 1187 /** @addtogroup HAL_SDMMC_LL_Group1 1188 * @{ 1189 */ 1190 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1191 /** 1192 * @} 1193 */ 1194 1195 /* I/O operation functions *****************************************************/ 1196 /** @addtogroup HAL_SDMMC_LL_Group2 1197 * @{ 1198 */ 1199 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 1200 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1201 /** 1202 * @} 1203 */ 1204 1205 /* Peripheral Control functions ************************************************/ 1206 /** @addtogroup HAL_SDMMC_LL_Group3 1207 * @{ 1208 */ 1209 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1210 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1211 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1212 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1213 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1214 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1215 1216 /* Command path state machine (CPSM) management functions */ 1217 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1218 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1219 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1220 1221 /* Data path state machine (DPSM) management functions */ 1222 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 1223 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1224 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1225 1226 /* SDMMC Cards mode management functions */ 1227 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1228 1229 /* SDMMC Commands management functions */ 1230 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1231 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1232 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1233 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1234 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1235 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1236 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1237 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1238 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1239 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); 1240 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1241 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 1242 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1243 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1244 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1245 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1246 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1247 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1248 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1249 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1250 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1251 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); 1252 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1253 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1254 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1255 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1256 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1257 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1258 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1259 uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1260 1261 /* SDMMC Responses management functions */ 1262 uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); 1263 uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); 1264 uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); 1265 uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); 1266 uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); 1267 1268 /** 1269 * @} 1270 */ 1271 1272 /** 1273 * @} 1274 */ 1275 1276 /** 1277 * @} 1278 */ 1279 1280 /** 1281 * @} 1282 */ 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /** 1289 * @} 1290 */ 1291 #endif /* SDMMC1 */ 1292 1293 #ifdef __cplusplus 1294 } 1295 #endif 1296 1297 #endif /* STM32L4xx_LL_SDMMC_H */ 1298 1299 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1300
