1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32l4xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26 /** @addtogroup STM32L4xx_LL_Driver
27 * @{
28 */
29
30 #if defined(RCC)
31
32 /** @addtogroup RCC_LL
33 * @{
34 */
35
36 /* Private types -------------------------------------------------------------*/
37 /* Private variables ---------------------------------------------------------*/
38 /* Private constants ---------------------------------------------------------*/
39 /* Private macros ------------------------------------------------------------*/
40 /** @addtogroup RCC_LL_Private_Macros
41 * @{
42 */
43 #if defined(RCC_CCIPR_USART3SEL)
44 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
45 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
46 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
47 #else
48 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
49 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
50
51 #endif /* RCC_CCIPR_USART3SEL */
52 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
53 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
55 #elif defined(RCC_CCIPR_UART4SEL)
56 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
57 #elif defined(RCC_CCIPR_UART5SEL)
58 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
59 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
60
61 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
62
63 #if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL)
64 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
65 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
66 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
68 #elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
69 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
70 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
71 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
72
73 #elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
74 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
76
77 #else
78 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
79
80 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */
81 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
82 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
83
84 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
85 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
86 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
87 #elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
88 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
89 #endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/
90
91 #if defined(SDMMC1)
92 #if defined(RCC_CCIPR2_SDMMCSEL)
93 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
94 #endif /* RCC_CCIPR2_SDMMCSEL */
95
96 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
97 #endif /* SDMMC1 */
98
99 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
100
101 #if defined(USB_OTG_FS) || defined(USB)
102 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
103 #endif /* USB_OTG_FS || USB */
104
105 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
106
107 #if defined(SWPMI1)
108 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
109 #endif /* SWPMI1 */
110
111 #if defined(DFSDM1_Channel0)
112 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
113 #if defined(RCC_CCIPR2_DFSDM1SEL)
114 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
115 #endif /* RCC_CCIPR2_DFSDM1SEL */
116 #endif /* DFSDM1_Channel0 */
117
118 #if defined(DSI)
119 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
120 #endif /* DSI */
121
122 #if defined(LTDC)
123 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
124 #endif /* LTDC */
125
126 #if defined(OCTOSPI1)
127 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
128 #endif /* OCTOSPI */
129
130 /**
131 * @}
132 */
133
134 /* Private function prototypes -----------------------------------------------*/
135 /** @defgroup RCC_LL_Private_Functions RCC Private functions
136 * @{
137 */
138 static uint32_t RCC_GetSystemClockFreq(void);
139 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
140 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
141 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
142 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
143 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
144 static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
145 #endif
146 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
147 #if defined(RCC_PLLSAI1_SUPPORT)
148 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
149 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
150 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
151 #endif /* RCC_PLLSAI1_SUPPORT */
152 #if defined(RCC_PLLSAI2_SUPPORT)
153 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
154 #if defined(LTDC)
155 static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void);
156 #else
157 static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
158 #endif /* LTDC */
159 #if defined(DSI)
160 static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void);
161 #endif /* DSI */
162 #endif /*RCC_PLLSAI2_SUPPORT*/
163 /**
164 * @}
165 */
166
167
168 /* Exported functions --------------------------------------------------------*/
169 /** @addtogroup RCC_LL_Exported_Functions
170 * @{
171 */
172
173 /** @addtogroup RCC_LL_EF_Init
174 * @{
175 */
176
177 /**
178 * @brief Reset the RCC clock configuration to the default reset state.
179 * @note The default reset state of the clock configuration is given below:
180 * - MSI ON and used as system clock source
181 * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
182 * - AHB, APB1 and APB2 prescaler set to 1.
183 * - CSS, MCO OFF
184 * - All interrupts disabled
185 * @note This function doesn't modify the configuration of the
186 * - Peripheral clocks
187 * - LSI, LSE and RTC clocks
188 * @retval An ErrorStatus enumeration value:
189 * - SUCCESS: RCC registers are de-initialized
190 * - ERROR: not applicable
191 */
LL_RCC_DeInit(void)192 ErrorStatus LL_RCC_DeInit(void)
193 {
194 __IO uint32_t vl_mask;
195
196 /* Set MSION bit */
197 LL_RCC_MSI_Enable();
198
199 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
200 while (LL_RCC_MSI_IsReady() == 0U)
201 {
202 }
203
204 /* Set MSIRANGE default value */
205 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
206
207 /* Set MSITRIM bits to the reset value*/
208 LL_RCC_MSI_SetCalibTrimming(0);
209
210 /* Set HSITRIM bits to the reset value*/
211 #if defined(RCC_ICSCR_HSITRIM_6)
212 LL_RCC_HSI_SetCalibTrimming(0x40U);
213 #else
214 LL_RCC_HSI_SetCalibTrimming(0x10U);
215 #endif /* RCC_ICSCR_HSITRIM_6 */
216
217 /* Reset CFGR register */
218 LL_RCC_WriteReg(CFGR, 0x00000000U);
219
220 /* Read CR register */
221 vl_mask = LL_RCC_ReadReg(CR);
222
223 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */
224 CLEAR_BIT(vl_mask,
225 (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON));
226
227 #if defined(RCC_PLLSAI1_SUPPORT)
228 /* Reset PLLSAI1ON bit */
229 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
230 #endif /*RCC_PLLSAI1_SUPPORT*/
231
232 #if defined(RCC_PLLSAI2_SUPPORT)
233 /* Reset PLLSAI2ON bit */
234 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
235 #endif /*RCC_PLLSAI2_SUPPORT*/
236
237 /* Write new value in CR register */
238 LL_RCC_WriteReg(CR, vl_mask);
239
240 #if defined(RCC_PLLSAI2_SUPPORT)
241 /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */
242 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
243 {
244 }
245 #elif defined(RCC_PLLSAI1_SUPPORT)
246 /* Wait for PLLRDY and PLLSAI1RDY to be reset */
247 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
248 {
249 }
250 #else
251 /* Wait for PLLRDY bit to be reset */
252 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
253 {
254 }
255 #endif
256
257 /* Reset PLLCFGR register */
258 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
259
260 #if defined(RCC_PLLSAI1_SUPPORT)
261 /* Reset PLLSAI1CFGR register */
262 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
263 #endif /*RCC_PLLSAI1_SUPPORT*/
264
265 #if defined(RCC_PLLSAI2_SUPPORT)
266 /* Reset PLLSAI2CFGR register */
267 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
268 #endif /*RCC_PLLSAI2_SUPPORT*/
269
270 /* Reset HSEBYP bit */
271 LL_RCC_HSE_DisableBypass();
272
273 /* Disable all interrupts */
274 LL_RCC_WriteReg(CIER, 0x00000000U);
275
276 /* Clear all interrupt flags */
277 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
278 RCC_CICR_CSSC | RCC_CICR_LSECSSC;
279 #if defined(RCC_HSI48_SUPPORT)
280 vl_mask |= RCC_CICR_HSI48RDYC;
281 #endif
282 #if defined(RCC_PLLSAI1_SUPPORT)
283 vl_mask |= RCC_CICR_PLLSAI1RDYC;
284 #endif
285 #if defined(RCC_PLLSAI2_SUPPORT)
286 vl_mask |= RCC_CICR_PLLSAI2RDYC;
287 #endif
288 LL_RCC_WriteReg(CICR, vl_mask);
289
290 /* Clear reset flags */
291 LL_RCC_ClearResetFlags();
292
293 return SUCCESS;
294 }
295
296 /**
297 * @}
298 */
299
300 /** @addtogroup RCC_LL_EF_Get_Freq
301 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
302 * and different peripheral clocks available on the device.
303 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
304 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
305 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
306 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
307 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
308 * @note (*) MSI_VALUE is a constant defined in this file (default value
309 * 4 MHz) but the real value may vary depending on the variations
310 * in voltage and temperature.
311 * @note (**) HSI_VALUE is a constant defined in this file (default value
312 * 16 MHz) but the real value may vary depending on the variations
313 * in voltage and temperature.
314 * @note (***) HSE_VALUE is a constant defined in this file (default value
315 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
316 * frequency of the crystal used. Otherwise, this function may
317 * have wrong result.
318 * @note The result of this function could be incorrect when using fractional
319 * value for HSE crystal.
320 * @note This function can be used by the user application to compute the
321 * baud-rate for the communication peripherals or configure other parameters.
322 * @{
323 */
324
325 /**
326 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
327 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
328 * must be called to update structure fields. Otherwise, any
329 * configuration based on this function will be incorrect.
330 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
331 * @retval None
332 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)333 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
334 {
335 /* Get SYSCLK frequency */
336 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
337
338 /* HCLK clock frequency */
339 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
340
341 /* PCLK1 clock frequency */
342 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
343
344 /* PCLK2 clock frequency */
345 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
346 }
347
348 /**
349 * @brief Return USARTx clock frequency
350 * @param USARTxSource This parameter can be one of the following values:
351 * @arg @ref LL_RCC_USART1_CLKSOURCE
352 * @arg @ref LL_RCC_USART2_CLKSOURCE
353 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
354 *
355 * (*) value not defined in all devices.
356 * @retval USART clock frequency (in Hz)
357 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
358 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)359 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
360 {
361 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
362
363 /* Check parameter */
364 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
365
366 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
367 {
368 /* USART1CLK clock frequency */
369 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
370 {
371 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
372 usart_frequency = RCC_GetSystemClockFreq();
373 break;
374
375 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
376 if (LL_RCC_HSI_IsReady() != 0U)
377 {
378 usart_frequency = HSI_VALUE;
379 }
380 break;
381
382 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
383 if (LL_RCC_LSE_IsReady() != 0U)
384 {
385 usart_frequency = LSE_VALUE;
386 }
387 break;
388
389 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
390 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
391 break;
392
393 default:
394 break;
395 }
396 }
397 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
398 {
399 /* USART2CLK clock frequency */
400 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
401 {
402 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
403 usart_frequency = RCC_GetSystemClockFreq();
404 break;
405
406 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
407 if (LL_RCC_HSI_IsReady() != 0U)
408 {
409 usart_frequency = HSI_VALUE;
410 }
411 break;
412
413 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
414 if (LL_RCC_LSE_IsReady() != 0U)
415 {
416 usart_frequency = LSE_VALUE;
417 }
418 break;
419
420 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
421 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
422 break;
423
424 default:
425 break;
426 }
427 }
428 else
429 {
430 #if defined(RCC_CCIPR_USART3SEL)
431 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
432 {
433 /* USART3CLK clock frequency */
434 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
435 {
436 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
437 usart_frequency = RCC_GetSystemClockFreq();
438 break;
439
440 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
441 if (LL_RCC_HSI_IsReady() != 0U)
442 {
443 usart_frequency = HSI_VALUE;
444 }
445 break;
446
447 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
448 if (LL_RCC_LSE_IsReady() != 0U)
449 {
450 usart_frequency = LSE_VALUE;
451 }
452 break;
453
454 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
455 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
456 break;
457
458 default:
459 break;
460 }
461 }
462 #endif /* RCC_CCIPR_USART3SEL */
463 }
464 return usart_frequency;
465 }
466
467 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
468 /**
469 * @brief Return UARTx clock frequency
470 * @param UARTxSource This parameter can be one of the following values:
471 * @arg @ref LL_RCC_UART4_CLKSOURCE
472 * @arg @ref LL_RCC_UART5_CLKSOURCE
473 * @retval UART clock frequency (in Hz)
474 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
475 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)476 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
477 {
478 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
479
480 /* Check parameter */
481 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
482
483 #if defined(RCC_CCIPR_UART4SEL)
484 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
485 {
486 /* UART4CLK clock frequency */
487 switch (LL_RCC_GetUARTClockSource(UARTxSource))
488 {
489 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
490 uart_frequency = RCC_GetSystemClockFreq();
491 break;
492
493 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
494 if (LL_RCC_HSI_IsReady() != 0U)
495 {
496 uart_frequency = HSI_VALUE;
497 }
498 break;
499
500 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
501 if (LL_RCC_LSE_IsReady() != 0U)
502 {
503 uart_frequency = LSE_VALUE;
504 }
505 break;
506
507 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
508 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
509 break;
510
511 default:
512 break;
513 }
514 }
515 #endif /* RCC_CCIPR_UART4SEL */
516
517 #if defined(RCC_CCIPR_UART5SEL)
518 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
519 {
520 /* UART5CLK clock frequency */
521 switch (LL_RCC_GetUARTClockSource(UARTxSource))
522 {
523 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
524 uart_frequency = RCC_GetSystemClockFreq();
525 break;
526
527 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
528 if (LL_RCC_HSI_IsReady() != 0U)
529 {
530 uart_frequency = HSI_VALUE;
531 }
532 break;
533
534 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
535 if (LL_RCC_LSE_IsReady() != 0U)
536 {
537 uart_frequency = LSE_VALUE;
538 }
539 break;
540
541 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
542 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
543 break;
544
545 default:
546 break;
547 }
548 }
549 #endif /* RCC_CCIPR_UART5SEL */
550
551 return uart_frequency;
552 }
553 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
554
555 /**
556 * @brief Return I2Cx clock frequency
557 * @param I2CxSource This parameter can be one of the following values:
558 * @arg @ref LL_RCC_I2C1_CLKSOURCE
559 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
560 * @arg @ref LL_RCC_I2C3_CLKSOURCE
561 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
562 *
563 * (*) value not defined in all devices.
564 * @retval I2C clock frequency (in Hz)
565 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
566 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)567 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
568 {
569 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
570
571 /* Check parameter */
572 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
573
574 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
575 {
576 /* I2C1 CLK clock frequency */
577 switch (LL_RCC_GetI2CClockSource(I2CxSource))
578 {
579 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
580 i2c_frequency = RCC_GetSystemClockFreq();
581 break;
582
583 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
584 if (LL_RCC_HSI_IsReady() != 0U)
585 {
586 i2c_frequency = HSI_VALUE;
587 }
588 break;
589
590 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
591 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
592 break;
593
594 default:
595 break;
596 }
597 }
598 #if defined(RCC_CCIPR_I2C2SEL)
599 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
600 {
601 /* I2C2 CLK clock frequency */
602 switch (LL_RCC_GetI2CClockSource(I2CxSource))
603 {
604 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
605 i2c_frequency = RCC_GetSystemClockFreq();
606 break;
607
608 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
609 if (LL_RCC_HSI_IsReady() != 0U)
610 {
611 i2c_frequency = HSI_VALUE;
612 }
613 break;
614
615 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
616 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
617 break;
618
619 default:
620 break;
621 }
622 }
623 #endif /*RCC_CCIPR_I2C2SEL*/
624 else
625 {
626 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
627 {
628 /* I2C3 CLK clock frequency */
629 switch (LL_RCC_GetI2CClockSource(I2CxSource))
630 {
631 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
632 i2c_frequency = RCC_GetSystemClockFreq();
633 break;
634
635 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
636 if (LL_RCC_HSI_IsReady() != 0U)
637 {
638 i2c_frequency = HSI_VALUE;
639 }
640 break;
641
642 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
643 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
644 break;
645
646 default:
647 break;
648 }
649 }
650 #if defined(RCC_CCIPR2_I2C4SEL)
651 else
652 {
653 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
654 {
655 /* I2C4 CLK clock frequency */
656 switch (LL_RCC_GetI2CClockSource(I2CxSource))
657 {
658 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
659 i2c_frequency = RCC_GetSystemClockFreq();
660 break;
661
662 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
663 if (LL_RCC_HSI_IsReady() != 0U)
664 {
665 i2c_frequency = HSI_VALUE;
666 }
667 break;
668
669 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
670 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
671 break;
672
673 default:
674 break;
675 }
676 }
677 }
678 #endif /*RCC_CCIPR2_I2C4SEL*/
679 }
680
681 return i2c_frequency;
682 }
683
684
685 /**
686 * @brief Return LPUARTx clock frequency
687 * @param LPUARTxSource This parameter can be one of the following values:
688 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
689 * @retval LPUART clock frequency (in Hz)
690 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
691 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)692 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
693 {
694 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
695
696 /* Check parameter */
697 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
698
699 /* LPUART1CLK clock frequency */
700 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
701 {
702 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
703 lpuart_frequency = RCC_GetSystemClockFreq();
704 break;
705
706 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
707 if (LL_RCC_HSI_IsReady() != 0U)
708 {
709 lpuart_frequency = HSI_VALUE;
710 }
711 break;
712
713 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
714 if (LL_RCC_LSE_IsReady() != 0U)
715 {
716 lpuart_frequency = LSE_VALUE;
717 }
718 break;
719
720 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
721 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
722 break;
723
724 default:
725 break;
726 }
727
728 return lpuart_frequency;
729 }
730
731 /**
732 * @brief Return LPTIMx clock frequency
733 * @param LPTIMxSource This parameter can be one of the following values:
734 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
735 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
736 * @retval LPTIM clock frequency (in Hz)
737 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
738 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)739 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
740 {
741 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
742
743 /* Check parameter */
744 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
745
746 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
747 {
748 /* LPTIM1CLK clock frequency */
749 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
750 {
751 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
752 if (LL_RCC_LSI_IsReady() != 0U)
753 {
754 #if defined(RCC_CSR_LSIPREDIV)
755 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
756 {
757 lptim_frequency = LSI_VALUE / 128U;
758 }
759 else
760 #endif /* RCC_CSR_LSIPREDIV */
761 {
762 lptim_frequency = LSI_VALUE;
763 }
764 }
765 break;
766
767 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
768 if (LL_RCC_HSI_IsReady() != 0U)
769 {
770 lptim_frequency = HSI_VALUE;
771 }
772 break;
773
774 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
775 if (LL_RCC_LSE_IsReady() != 0U)
776 {
777 lptim_frequency = LSE_VALUE;
778 }
779 break;
780
781 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
782 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
783 break;
784
785 default:
786 break;
787 }
788 }
789 else
790 {
791 if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
792 {
793 /* LPTIM2CLK clock frequency */
794 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
795 {
796 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
797 if (LL_RCC_LSI_IsReady() != 0U)
798 {
799 #if defined(RCC_CSR_LSIPREDIV)
800 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
801 {
802 lptim_frequency = LSI_VALUE / 128U;
803 }
804 else
805 #endif /* RCC_CSR_LSIPREDIV */
806 {
807 lptim_frequency = LSI_VALUE;
808 }
809 }
810 break;
811
812 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
813 if (LL_RCC_HSI_IsReady() != 0U)
814 {
815 lptim_frequency = HSI_VALUE;
816 }
817 break;
818
819 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
820 if (LL_RCC_LSE_IsReady() != 0U)
821 {
822 lptim_frequency = LSE_VALUE;
823 }
824 break;
825
826 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
827 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
828 break;
829
830 default:
831 break;
832 }
833 }
834 }
835
836 return lptim_frequency;
837 }
838
839 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
840 /**
841 * @brief Return SAIx clock frequency
842 * @param SAIxSource This parameter can be one of the following values:
843 * @arg @ref LL_RCC_SAI1_CLKSOURCE
844 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
845 *
846 * (*) value not defined in all devices.
847 * @retval SAI clock frequency (in Hz)
848 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
849
850 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)851 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
852 {
853 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
854
855 /* Check parameter */
856 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
857
858 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
859 {
860 /* SAI1CLK clock frequency */
861 switch (LL_RCC_GetSAIClockSource(SAIxSource))
862 {
863 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
864 if (LL_RCC_PLLSAI1_IsReady() != 0U)
865 {
866 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
867 {
868 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
869 }
870 }
871 break;
872
873 #if defined(RCC_PLLSAI2_SUPPORT)
874 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
875 if (LL_RCC_PLLSAI2_IsReady() != 0U)
876 {
877 if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
878 {
879 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
880 }
881 }
882 break;
883
884 #endif /* RCC_PLLSAI2_SUPPORT */
885 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
886 if (LL_RCC_PLL_IsReady() != 0U)
887 {
888 if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
889 {
890 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
891 }
892 }
893 break;
894
895 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
896 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
897 break;
898
899 default:
900 break;
901 }
902 }
903 else
904 {
905 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
906 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
907 {
908 /* SAI2CLK clock frequency */
909 switch (LL_RCC_GetSAIClockSource(SAIxSource))
910 {
911 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
912 if (LL_RCC_PLLSAI1_IsReady() != 0U)
913 {
914 if (LL_RCC_PLLSAI1_IsEnabledDomain_SAI() != 0U)
915 {
916 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
917 }
918 }
919 break;
920
921 #if defined(RCC_PLLSAI2_SUPPORT)
922 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
923 if (LL_RCC_PLLSAI2_IsReady() != 0U)
924 {
925 if (LL_RCC_PLLSAI2_IsEnabledDomain_SAI() != 0U)
926 {
927 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
928 }
929 }
930 break;
931
932 #endif /* RCC_PLLSAI2_SUPPORT */
933 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
934 if (LL_RCC_PLL_IsReady() != 0U)
935 {
936 if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
937 {
938 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
939 }
940 }
941 break;
942
943 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
944 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
945 break;
946
947 default:
948 break;
949 }
950 }
951 #endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */
952 }
953
954 return sai_frequency;
955 }
956 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/
957
958 #if defined(SDMMC1)
959 #if defined(RCC_CCIPR2_SDMMCSEL)
960 /**
961 * @brief Return SDMMCx kernel clock frequency
962 * @param SDMMCxSource This parameter can be one of the following values:
963 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
964 * @retval SDMMC clock frequency (in Hz)
965 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
966 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
967 */
LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)968 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
969 {
970 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
971
972 /* Check parameter */
973 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
974
975 /* SDMMC1CLK kernel clock frequency */
976 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
977 {
978 case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
979 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
980 break;
981
982 case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
983 if (LL_RCC_PLL_IsReady() != 0U)
984 {
985 if (LL_RCC_PLL_IsEnabledDomain_SAI() != 0U)
986 {
987 sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
988 }
989 }
990 break;
991
992 default:
993 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
994 break;
995 }
996
997 return sdmmc_frequency;
998 }
999 #endif
1000
1001 /**
1002 * @brief Return SDMMCx clock frequency
1003 * @param SDMMCxSource This parameter can be one of the following values:
1004 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
1005 * @retval SDMMC clock frequency (in Hz)
1006 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1007 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1008 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)1009 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
1010 {
1011 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1012
1013 /* Check parameter */
1014 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
1015
1016 /* SDMMC1CLK clock frequency */
1017 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
1018 {
1019 #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1)
1020 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
1021 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1022 {
1023 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
1024 {
1025 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1026 }
1027 }
1028 break;
1029 #endif
1030
1031 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
1032 if (LL_RCC_PLL_IsReady() != 0U)
1033 {
1034 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
1035 {
1036 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
1037 }
1038 }
1039 break;
1040
1041 #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI)
1042 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
1043 if (LL_RCC_MSI_IsReady() != 0U)
1044 {
1045 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1046 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1047 LL_RCC_MSI_GetRange() :
1048 LL_RCC_MSI_GetRangeAfterStandby()));
1049 }
1050 break;
1051 #endif
1052
1053 #if defined(RCC_HSI48_SUPPORT)
1054 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
1055 if (LL_RCC_HSI48_IsReady() != 0U)
1056 {
1057 sdmmc_frequency = HSI48_VALUE;
1058 }
1059 break;
1060 #else
1061 case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
1062 #endif
1063 default:
1064 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1065 break;
1066 }
1067
1068 return sdmmc_frequency;
1069 }
1070 #endif /* SDMMC1 */
1071
1072 /**
1073 * @brief Return RNGx clock frequency
1074 * @param RNGxSource This parameter can be one of the following values:
1075 * @arg @ref LL_RCC_RNG_CLKSOURCE
1076 * @retval RNG clock frequency (in Hz)
1077 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1078 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1079 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1080 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1081 {
1082 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1083
1084 /* Check parameter */
1085 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
1086
1087 /* RNGCLK clock frequency */
1088 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1089 {
1090 #if defined(RCC_PLLSAI1_SUPPORT)
1091 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
1092 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1093 {
1094 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() !=0U)
1095 {
1096 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1097 }
1098 }
1099 break;
1100 #endif /* RCC_PLLSAI1_SUPPORT */
1101
1102 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
1103 if (LL_RCC_PLL_IsReady() != 0U)
1104 {
1105 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
1106 {
1107 rng_frequency = RCC_PLL_GetFreqDomain_48M();
1108 }
1109 }
1110 break;
1111
1112 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
1113 if (LL_RCC_MSI_IsReady() != 0U)
1114 {
1115 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1116 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1117 LL_RCC_MSI_GetRange() :
1118 LL_RCC_MSI_GetRangeAfterStandby()));
1119 }
1120 break;
1121
1122
1123 #if defined(RCC_HSI48_SUPPORT)
1124 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
1125 if (LL_RCC_HSI48_IsReady() != 0U)
1126 {
1127 rng_frequency = HSI48_VALUE;
1128 }
1129 break;
1130 #else
1131 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */
1132 #endif
1133 default:
1134 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1135 break;
1136
1137 }
1138
1139 return rng_frequency;
1140 }
1141
1142
1143 #if defined(USB_OTG_FS)||defined(USB)
1144 /**
1145 * @brief Return USBx clock frequency
1146 * @param USBxSource This parameter can be one of the following values:
1147 * @arg @ref LL_RCC_USB_CLKSOURCE
1148 * @retval USB clock frequency (in Hz)
1149 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1150 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1151 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1152 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1153 {
1154 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1155
1156 /* Check parameter */
1157 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1158
1159 /* USBCLK clock frequency */
1160 switch (LL_RCC_GetUSBClockSource(USBxSource))
1161 {
1162 #if defined(RCC_PLLSAI1_SUPPORT)
1163 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
1164 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1165 {
1166 if (LL_RCC_PLLSAI1_IsEnabledDomain_48M() != 0U)
1167 {
1168 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1169 }
1170 }
1171 break;
1172 #endif /* RCC_PLLSAI1_SUPPORT */
1173
1174 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1175 if (LL_RCC_PLL_IsReady() != 0U)
1176 {
1177 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
1178 {
1179 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1180 }
1181 }
1182 break;
1183
1184 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
1185 if (LL_RCC_MSI_IsReady() != 0U)
1186 {
1187 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1188 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1189 LL_RCC_MSI_GetRange() :
1190 LL_RCC_MSI_GetRangeAfterStandby()));
1191 }
1192 break;
1193
1194 #if defined(RCC_HSI48_SUPPORT)
1195 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
1196 if (LL_RCC_HSI48_IsReady() != 0U)
1197 {
1198 usb_frequency = HSI48_VALUE;
1199 }
1200 break;
1201 #else
1202 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
1203 #endif
1204 default:
1205 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1206 break;
1207 }
1208
1209 return usb_frequency;
1210 }
1211 #endif /* USB_OTG_FS || USB */
1212
1213 /**
1214 * @brief Return ADCx clock frequency
1215 * @param ADCxSource This parameter can be one of the following values:
1216 * @arg @ref LL_RCC_ADC_CLKSOURCE
1217 * @retval ADC clock frequency (in Hz)
1218 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1219 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1220 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1221 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1222 {
1223 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1224
1225 /* Check parameter */
1226 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1227
1228 /* ADCCLK clock frequency */
1229 switch (LL_RCC_GetADCClockSource(ADCxSource))
1230 {
1231 #if defined(RCC_PLLSAI1_SUPPORT)
1232 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
1233 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1234 {
1235 if (LL_RCC_PLLSAI1_IsEnabledDomain_ADC() != 0U)
1236 {
1237 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
1238 }
1239 }
1240 break;
1241 #endif /* RCC_PLLSAI1_SUPPORT */
1242
1243 #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2)
1244 case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
1245 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1246 {
1247 if (LL_RCC_PLLSAI2_IsEnabledDomain_ADC() != 0U)
1248 {
1249 adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
1250 }
1251 }
1252 break;
1253 #endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */
1254
1255 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
1256 adc_frequency = RCC_GetSystemClockFreq();
1257 break;
1258
1259 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
1260 default:
1261 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1262 break;
1263 }
1264
1265 return adc_frequency;
1266 }
1267
1268 #if defined(SWPMI1)
1269 /**
1270 * @brief Return SWPMIx clock frequency
1271 * @param SWPMIxSource This parameter can be one of the following values:
1272 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
1273 * @retval SWPMI clock frequency (in Hz)
1274 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
1275 */
LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)1276 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
1277 {
1278 uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1279
1280 /* Check parameter */
1281 assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
1282
1283 /* SWPMI1CLK clock frequency */
1284 switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
1285 {
1286 case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
1287 if (LL_RCC_HSI_IsReady())
1288 {
1289 swpmi_frequency = HSI_VALUE;
1290 }
1291 break;
1292
1293 case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */
1294 swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1295 break;
1296
1297 default:
1298 break;
1299 }
1300
1301 return swpmi_frequency;
1302 }
1303 #endif /* SWPMI1 */
1304
1305 #if defined(DFSDM1_Channel0)
1306 /**
1307 * @brief Return DFSDMx clock frequency
1308 * @param DFSDMxSource This parameter can be one of the following values:
1309 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1310 * @retval DFSDM clock frequency (in Hz)
1311 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1312 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1313 {
1314 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1315
1316 /* Check parameter */
1317 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1318
1319 /* DFSDM1CLK clock frequency */
1320 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1321 {
1322 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1323 dfsdm_frequency = RCC_GetSystemClockFreq();
1324 break;
1325
1326 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1327 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1328 break;
1329
1330 default:
1331 break;
1332 }
1333
1334 return dfsdm_frequency;
1335 }
1336
1337 #if defined(RCC_CCIPR2_DFSDM1SEL)
1338 /**
1339 * @brief Return DFSDMx Audio clock frequency
1340 * @param DFSDMxSource This parameter can be one of the following values:
1341 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1342 * @retval DFSDM clock frequency (in Hz)
1343 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1344 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1345 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1346 {
1347 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1348
1349 /* Check parameter */
1350 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1351
1352 /* DFSDM1CLK clock frequency */
1353 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1354 {
1355 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1356 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1357 break;
1358
1359 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */
1360 if (LL_RCC_MSI_IsReady() != 0U)
1361 {
1362 dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1363 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1364 LL_RCC_MSI_GetRange() :
1365 LL_RCC_MSI_GetRangeAfterStandby()));
1366 }
1367 break;
1368
1369 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */
1370 default:
1371 if (LL_RCC_HSI_IsReady() != 0U)
1372 {
1373 dfsdm_frequency = HSI_VALUE;
1374 }
1375 break;
1376 }
1377
1378 return dfsdm_frequency;
1379 }
1380 #endif /* RCC_CCIPR2_DFSDM1SEL */
1381 #endif /* DFSDM1_Channel0 */
1382
1383 #if defined(DSI)
1384 /**
1385 * @brief Return DSI clock frequency
1386 * @param DSIxSource This parameter can be one of the following values:
1387 * @arg @ref LL_RCC_DSI_CLKSOURCE
1388 * @retval DSI clock frequency (in Hz)
1389 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1390 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1391 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1392 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1393 {
1394 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1395
1396 /* Check parameter */
1397 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1398
1399 /* DSICLK clock frequency */
1400 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1401 {
1402 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */
1403 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1404 {
1405 if (LL_RCC_PLLSAI2_IsEnabledDomain_DSI() != 0U)
1406 {
1407 dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
1408 }
1409 }
1410 break;
1411
1412 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1413 default:
1414 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1415 break;
1416 }
1417
1418 return dsi_frequency;
1419 }
1420 #endif /* DSI */
1421
1422 #if defined(LTDC)
1423 /**
1424 * @brief Return LTDC clock frequency
1425 * @param LTDCxSource This parameter can be one of the following values:
1426 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1427 * @retval LTDC clock frequency (in Hz)
1428 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1429 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1430 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1431 {
1432 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1433
1434 /* Check parameter */
1435 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1436
1437 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1438 {
1439 if (LL_RCC_PLLSAI2_IsEnabledDomain_LTDC() != 0U)
1440 {
1441 ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
1442 }
1443 }
1444
1445 return ltdc_frequency;
1446 }
1447 #endif /* LTDC */
1448
1449 #if defined(OCTOSPI1)
1450 /**
1451 * @brief Return OCTOSPI clock frequency
1452 * @param OCTOSPIxSource This parameter can be one of the following values:
1453 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
1454 * @retval OCTOSPI clock frequency (in Hz)
1455 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1456 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)1457 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
1458 {
1459 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1460
1461 /* Check parameter */
1462 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
1463
1464 /* OCTOSPI clock frequency */
1465 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
1466 {
1467 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
1468 octospi_frequency = RCC_GetSystemClockFreq();
1469 break;
1470
1471 case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */
1472 if (LL_RCC_MSI_IsReady() != 0U)
1473 {
1474 octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1475 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1476 LL_RCC_MSI_GetRange() :
1477 LL_RCC_MSI_GetRangeAfterStandby()));
1478 }
1479 break;
1480
1481 case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
1482 if (LL_RCC_PLL_IsReady() != 0U)
1483 {
1484 if (LL_RCC_PLL_IsEnabledDomain_48M() != 0U)
1485 {
1486 octospi_frequency = RCC_PLL_GetFreqDomain_48M();
1487 }
1488 }
1489 break;
1490
1491 default:
1492 octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1493 break;
1494 }
1495
1496 return octospi_frequency;
1497 }
1498 #endif /* OCTOSPI1 */
1499
1500 /**
1501 * @}
1502 */
1503
1504 /**
1505 * @}
1506 */
1507
1508 /** @addtogroup RCC_LL_Private_Functions
1509 * @{
1510 */
1511
1512 /**
1513 * @brief Return SYSTEM clock frequency
1514 * @retval SYSTEM clock frequency (in Hz)
1515 */
RCC_GetSystemClockFreq(void)1516 static uint32_t RCC_GetSystemClockFreq(void)
1517 {
1518 uint32_t frequency;
1519
1520 /* Get SYSCLK source -------------------------------------------------------*/
1521 switch (LL_RCC_GetSysClkSource())
1522 {
1523 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
1524 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1525 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1526 LL_RCC_MSI_GetRange() :
1527 LL_RCC_MSI_GetRangeAfterStandby()));
1528 break;
1529
1530 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1531 frequency = HSI_VALUE;
1532 break;
1533
1534 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1535 frequency = HSE_VALUE;
1536 break;
1537
1538 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1539 frequency = RCC_PLL_GetFreqDomain_SYS();
1540 break;
1541
1542 default:
1543 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1544 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1545 LL_RCC_MSI_GetRange() :
1546 LL_RCC_MSI_GetRangeAfterStandby()));
1547 break;
1548 }
1549
1550 return frequency;
1551 }
1552
1553 /**
1554 * @brief Return HCLK clock frequency
1555 * @param SYSCLK_Frequency SYSCLK clock frequency
1556 * @retval HCLK clock frequency (in Hz)
1557 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1558 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1559 {
1560 /* HCLK clock frequency */
1561 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1562 }
1563
1564 /**
1565 * @brief Return PCLK1 clock frequency
1566 * @param HCLK_Frequency HCLK clock frequency
1567 * @retval PCLK1 clock frequency (in Hz)
1568 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1569 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1570 {
1571 /* PCLK1 clock frequency */
1572 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1573 }
1574
1575 /**
1576 * @brief Return PCLK2 clock frequency
1577 * @param HCLK_Frequency HCLK clock frequency
1578 * @retval PCLK2 clock frequency (in Hz)
1579 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1580 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1581 {
1582 /* PCLK2 clock frequency */
1583 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1584 }
1585
1586 /**
1587 * @brief Return PLL clock frequency used for system domain
1588 * @retval PLL clock frequency (in Hz)
1589 */
RCC_PLL_GetFreqDomain_SYS(void)1590 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1591 {
1592 uint32_t pllinputfreq, pllsource;
1593
1594 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1595 SYSCLK = PLL_VCO / PLLR
1596 */
1597 pllsource = LL_RCC_PLL_GetMainSource();
1598
1599 switch (pllsource)
1600 {
1601 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1602 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1603 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1604 LL_RCC_MSI_GetRange() :
1605 LL_RCC_MSI_GetRangeAfterStandby()));
1606 break;
1607
1608 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1609 pllinputfreq = HSI_VALUE;
1610 break;
1611
1612 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1613 pllinputfreq = HSE_VALUE;
1614 break;
1615
1616 default:
1617 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1618 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1619 LL_RCC_MSI_GetRange() :
1620 LL_RCC_MSI_GetRangeAfterStandby()));
1621 break;
1622 }
1623 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1624 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1625 }
1626
1627 #if defined(SAI1)
1628 /**
1629 * @brief Return PLL clock frequency used for SAI domain
1630 * @retval PLL clock frequency (in Hz)
1631 */
RCC_PLL_GetFreqDomain_SAI(void)1632 static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1633 {
1634 uint32_t pllinputfreq, pllsource;
1635
1636 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
1637 SAI Domain clock = PLL_VCO / PLLP
1638 */
1639 pllsource = LL_RCC_PLL_GetMainSource();
1640
1641 switch (pllsource)
1642 {
1643 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1644 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1645 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1646 LL_RCC_MSI_GetRange() :
1647 LL_RCC_MSI_GetRangeAfterStandby()));
1648 break;
1649
1650 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1651 pllinputfreq = HSI_VALUE;
1652 break;
1653
1654 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1655 pllinputfreq = HSE_VALUE;
1656 break;
1657
1658 default:
1659 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1660 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1661 LL_RCC_MSI_GetRange() :
1662 LL_RCC_MSI_GetRangeAfterStandby()));
1663 break;
1664 }
1665 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1666 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1667 }
1668 #endif /* SAI1 */
1669
1670 /**
1671 * @brief Return PLL clock frequency used for 48 MHz domain
1672 * @retval PLL clock frequency (in Hz)
1673 */
RCC_PLL_GetFreqDomain_48M(void)1674 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1675 {
1676 uint32_t pllinputfreq, pllsource;
1677
1678 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1679 48M Domain clock = PLL_VCO / PLLQ
1680 */
1681 pllsource = LL_RCC_PLL_GetMainSource();
1682
1683 switch (pllsource)
1684 {
1685 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1686 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1687 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1688 LL_RCC_MSI_GetRange() :
1689 LL_RCC_MSI_GetRangeAfterStandby()));
1690 break;
1691
1692 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1693 pllinputfreq = HSI_VALUE;
1694 break;
1695
1696 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1697 pllinputfreq = HSE_VALUE;
1698 break;
1699
1700 default:
1701 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1702 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1703 LL_RCC_MSI_GetRange() :
1704 LL_RCC_MSI_GetRangeAfterStandby()));
1705 break;
1706 }
1707 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1708 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1709 }
1710 #if defined(DSI)
1711 /**
1712 * @brief Return PLL clock frequency used for DSI clock
1713 * @retval PLL clock frequency (in Hz)
1714 */
RCC_PLLSAI2_GetFreqDomain_DSI(void)1715 static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)
1716 {
1717 uint32_t pllinputfreq, pllsource;
1718
1719 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1720 /* DSICLK = PLLSAI2_VCO / PLLSAI2R */
1721 pllsource = LL_RCC_PLL_GetMainSource();
1722
1723 switch (pllsource)
1724 {
1725 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1726 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1727 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1728 LL_RCC_MSI_GetRange() :
1729 LL_RCC_MSI_GetRangeAfterStandby()));
1730 break;
1731
1732 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1733 pllinputfreq = HSI_VALUE;
1734 break;
1735
1736 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1737 pllinputfreq = HSE_VALUE;
1738 break;
1739
1740 default:
1741 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1742 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1743 LL_RCC_MSI_GetRange() :
1744 LL_RCC_MSI_GetRangeAfterStandby()));
1745 break;
1746 }
1747
1748 return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1749 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
1750 }
1751 #endif /* DSI */
1752
1753 #if defined(RCC_PLLSAI1_SUPPORT)
1754 /**
1755 * @brief Return PLLSAI1 clock frequency used for SAI domain
1756 * @retval PLLSAI1 clock frequency (in Hz)
1757 */
RCC_PLLSAI1_GetFreqDomain_SAI(void)1758 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
1759 {
1760 uint32_t pllinputfreq, pllsource;
1761
1762 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1763 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1764 #else
1765 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1766 #endif
1767 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
1768 pllsource = LL_RCC_PLL_GetMainSource();
1769
1770 switch (pllsource)
1771 {
1772 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1773 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1774 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1775 LL_RCC_MSI_GetRange() :
1776 LL_RCC_MSI_GetRangeAfterStandby()));
1777 break;
1778
1779 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1780 pllinputfreq = HSI_VALUE;
1781 break;
1782
1783 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1784 pllinputfreq = HSE_VALUE;
1785 break;
1786
1787 default:
1788 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1789 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1790 LL_RCC_MSI_GetRange() :
1791 LL_RCC_MSI_GetRangeAfterStandby()));
1792 break;
1793 }
1794 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1795 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
1796 }
1797
1798 /**
1799 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
1800 * @retval PLLSAI1 clock frequency (in Hz)
1801 */
RCC_PLLSAI1_GetFreqDomain_48M(void)1802 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
1803 {
1804 uint32_t pllinputfreq, pllsource;
1805
1806 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1807 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1808 #else
1809 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1810 #endif
1811 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
1812 pllsource = LL_RCC_PLL_GetMainSource();
1813
1814 switch (pllsource)
1815 {
1816 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1817 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1818 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1819 LL_RCC_MSI_GetRange() :
1820 LL_RCC_MSI_GetRangeAfterStandby()));
1821 break;
1822
1823 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1824 pllinputfreq = HSI_VALUE;
1825 break;
1826
1827 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1828 pllinputfreq = HSE_VALUE;
1829 break;
1830
1831 default:
1832 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1833 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1834 LL_RCC_MSI_GetRange() :
1835 LL_RCC_MSI_GetRangeAfterStandby()));
1836 break;
1837 }
1838 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1839 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
1840 }
1841
1842 /**
1843 * @brief Return PLLSAI1 clock frequency used for ADC domain
1844 * @retval PLLSAI1 clock frequency (in Hz)
1845 */
RCC_PLLSAI1_GetFreqDomain_ADC(void)1846 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
1847 {
1848 uint32_t pllinputfreq, pllsource;
1849
1850 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1851 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1852 #else
1853 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1854 #endif
1855 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
1856 pllsource = LL_RCC_PLL_GetMainSource();
1857
1858 switch (pllsource)
1859 {
1860 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1861 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1862 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1863 LL_RCC_MSI_GetRange() :
1864 LL_RCC_MSI_GetRangeAfterStandby()));
1865 break;
1866
1867 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1868 pllinputfreq = HSI_VALUE;
1869 break;
1870
1871 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1872 pllinputfreq = HSE_VALUE;
1873 break;
1874
1875 default:
1876 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1877 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1878 LL_RCC_MSI_GetRange() :
1879 LL_RCC_MSI_GetRangeAfterStandby()));
1880 break;
1881 }
1882 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1883 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
1884 }
1885 #endif /* RCC_PLLSAI1_SUPPORT */
1886
1887 #if defined(RCC_PLLSAI2_SUPPORT)
1888 /**
1889 * @brief Return PLLSAI2 clock frequency used for SAI domain
1890 * @retval PLLSAI2 clock frequency (in Hz)
1891 */
RCC_PLLSAI2_GetFreqDomain_SAI(void)1892 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
1893 {
1894 uint32_t pllinputfreq, pllsource;
1895
1896 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1897 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1898 #else
1899 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1900 #endif
1901 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
1902 pllsource = LL_RCC_PLL_GetMainSource();
1903
1904 switch (pllsource)
1905 {
1906 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1907 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1908 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1909 LL_RCC_MSI_GetRange() :
1910 LL_RCC_MSI_GetRangeAfterStandby()));
1911 break;
1912
1913 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1914 pllinputfreq = HSI_VALUE;
1915 break;
1916
1917 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1918 pllinputfreq = HSE_VALUE;
1919 break;
1920
1921 default:
1922 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1923 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1924 LL_RCC_MSI_GetRange() :
1925 LL_RCC_MSI_GetRangeAfterStandby()));
1926 break;
1927 }
1928 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1929 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1930 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1931 #else
1932 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1933 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1934 #endif
1935 }
1936
1937 #if defined(LTDC)
1938 /**
1939 * @brief Return PLLSAI2 clock frequency used for LTDC domain
1940 * @retval PLLSAI2 clock frequency (in Hz)
1941 */
RCC_PLLSAI2_GetFreqDomain_LTDC(void)1942 static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)
1943 {
1944 uint32_t pllinputfreq, pllsource;
1945
1946 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1947 /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */
1948 pllsource = LL_RCC_PLL_GetMainSource();
1949
1950 switch (pllsource)
1951 {
1952 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1953 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1954 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1955 LL_RCC_MSI_GetRange() :
1956 LL_RCC_MSI_GetRangeAfterStandby()));
1957 break;
1958
1959 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1960 pllinputfreq = HSI_VALUE;
1961 break;
1962
1963 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1964 pllinputfreq = HSE_VALUE;
1965 break;
1966
1967 default:
1968 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1969 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1970 LL_RCC_MSI_GetRange() :
1971 LL_RCC_MSI_GetRangeAfterStandby()));
1972 break;
1973 }
1974
1975 return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1976 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
1977 }
1978
1979 #else
1980
1981 /**
1982 * @brief Return PLLSAI2 clock frequency used for ADC domain
1983 * @retval PLLSAI2 clock frequency (in Hz)
1984 */
RCC_PLLSAI2_GetFreqDomain_ADC(void)1985 static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
1986 {
1987 uint32_t pllinputfreq = 0U, pllsource = 0U;
1988
1989 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1990 /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */
1991 pllsource = LL_RCC_PLL_GetMainSource();
1992
1993 switch (pllsource)
1994 {
1995 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1996 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1997 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1998 LL_RCC_MSI_GetRange() :
1999 LL_RCC_MSI_GetRangeAfterStandby()));
2000 break;
2001
2002 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
2003 pllinputfreq = HSI_VALUE;
2004 break;
2005
2006 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
2007 pllinputfreq = HSE_VALUE;
2008 break;
2009
2010 default:
2011 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
2012 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
2013 LL_RCC_MSI_GetRange() :
2014 LL_RCC_MSI_GetRangeAfterStandby()));
2015 break;
2016 }
2017 return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
2018 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
2019 }
2020 #endif /* LTDC */
2021
2022 #endif /*RCC_PLLSAI2_SUPPORT*/
2023
2024 /**
2025 * @}
2026 */
2027
2028 /**
2029 * @}
2030 */
2031
2032 #endif /* defined(RCC) */
2033
2034 /**
2035 * @}
2036 */
2037
2038 #endif /* USE_FULL_LL_DRIVER */
2039
2040
