1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32l4xx_ll_rcc.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif
28 /** @addtogroup STM32L4xx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @addtogroup RCC_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /* Private macros ------------------------------------------------------------*/
42 /** @addtogroup RCC_LL_Private_Macros
43 * @{
44 */
45 #if defined(RCC_CCIPR_USART3SEL)
46 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
47 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
48 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
49 #else
50 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
51 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
52
53 #endif /* RCC_CCIPR_USART3SEL */
54 #if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)
55 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
56 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
57 #elif defined(RCC_CCIPR_UART4SEL)
58 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
59 #elif defined(RCC_CCIPR_UART5SEL)
60 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)
61 #endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/
62
63 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
64
65 #if defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL) && defined(RCC_CCIPR2_I2C4SEL)
66 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
67 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
68 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
69 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
70 #elif defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
71 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
73 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
74
75 #elif !defined(RCC_CCIPR_I2C2SEL) && defined(RCC_CCIPR_I2C3SEL)
76 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
78
79 #else
80 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
81
82 #endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL && RCC_CCIPR2_I2C4SEL */
83 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
84 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))
85
86 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
87 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
88 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
89 #elif defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR2_SAI1SEL)
90 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
91 #endif /* RCC_CCIPR_SAI2SEL RCC_CCIPR2_SAI2SEL ||*/
92
93 #if defined(SDMMC1)
94 #if defined(RCC_CCIPR2_SDMMCSEL)
95 #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))
96 #endif /* RCC_CCIPR2_SDMMCSEL */
97
98 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))
99 #endif /* SDMMC1 */
100
101 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
102
103 #if defined(USB_OTG_FS) || defined(USB)
104 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
105 #endif /* USB_OTG_FS || USB */
106
107 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
108
109 #if defined(SWPMI1)
110 #define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))
111 #endif /* SWPMI1 */
112
113 #if defined(DFSDM1_Channel0)
114 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
115 #if defined(RCC_CCIPR2_DFSDM1SEL)
116 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
117 #endif /* RCC_CCIPR2_DFSDM1SEL */
118 #endif /* DFSDM1_Channel0 */
119
120 #if defined(DSI)
121 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
122 #endif /* DSI */
123
124 #if defined(LTDC)
125 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
126 #endif /* LTDC */
127
128 #if defined(OCTOSPI1)
129 #define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))
130 #endif /* OCTOSPI */
131
132 /**
133 * @}
134 */
135
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup RCC_LL_Private_Functions RCC Private functions
138 * @{
139 */
140 static uint32_t RCC_GetSystemClockFreq(void);
141 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
142 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
143 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
144 static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
145 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
146 static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
147 #endif
148 static uint32_t RCC_PLL_GetFreqDomain_48M(void);
149 #if defined(RCC_PLLSAI1_SUPPORT)
150 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
151 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
152 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
153 #endif /* RCC_PLLSAI1_SUPPORT */
154 #if defined(RCC_PLLSAI2_SUPPORT)
155 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);
156 #if defined(LTDC)
157 static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void);
158 #else
159 static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);
160 #endif /* LTDC */
161 #if defined(DSI)
162 static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void);
163 #endif /* DSI */
164 #endif /*RCC_PLLSAI2_SUPPORT*/
165 /**
166 * @}
167 */
168
169
170 /* Exported functions --------------------------------------------------------*/
171 /** @addtogroup RCC_LL_Exported_Functions
172 * @{
173 */
174
175 /** @addtogroup RCC_LL_EF_Init
176 * @{
177 */
178
179 /**
180 * @brief Reset the RCC clock configuration to the default reset state.
181 * @note The default reset state of the clock configuration is given below:
182 * - MSI ON and used as system clock source
183 * - HSE, HSI, PLL, PLLSAI1 and PLLSAI2 OFF
184 * - AHB, APB1 and APB2 prescaler set to 1.
185 * - CSS, MCO OFF
186 * - All interrupts disabled
187 * @note This function doesn't modify the configuration of the
188 * - Peripheral clocks
189 * - LSI, LSE and RTC clocks
190 * @retval An ErrorStatus enumeration value:
191 * - SUCCESS: RCC registers are de-initialized
192 * - ERROR: not applicable
193 */
LL_RCC_DeInit(void)194 ErrorStatus LL_RCC_DeInit(void)
195 {
196 __IO uint32_t vl_mask;
197
198 /* Set MSION bit */
199 LL_RCC_MSI_Enable();
200
201 /* Insure MSIRDY bit is set before writing default MSIRANGE value */
202 while (LL_RCC_MSI_IsReady() == 0U)
203 {
204 }
205
206 /* Set MSIRANGE default value */
207 LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);
208
209 /* Set MSITRIM bits to the reset value*/
210 LL_RCC_MSI_SetCalibTrimming(0);
211
212 /* Set HSITRIM bits to the reset value*/
213 #if defined(RCC_ICSCR_HSITRIM_6)
214 LL_RCC_HSI_SetCalibTrimming(0x40U);
215 #else
216 LL_RCC_HSI_SetCalibTrimming(0x10U);
217 #endif /* RCC_ICSCR_HSITRIM_6 */
218
219 /* Reset CFGR register */
220 LL_RCC_WriteReg(CFGR, 0x00000000U);
221
222 /* Read CR register */
223 vl_mask = LL_RCC_ReadReg(CR);
224
225 /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON bits */
226 CLEAR_BIT(vl_mask,
227 (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLLON));
228
229 #if defined(RCC_PLLSAI1_SUPPORT)
230 /* Reset PLLSAI1ON bit */
231 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);
232 #endif /*RCC_PLLSAI1_SUPPORT*/
233
234 #if defined(RCC_PLLSAI2_SUPPORT)
235 /* Reset PLLSAI2ON bit */
236 CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);
237 #endif /*RCC_PLLSAI2_SUPPORT*/
238
239 /* Write new value in CR register */
240 LL_RCC_WriteReg(CR, vl_mask);
241
242 #if defined(RCC_PLLSAI2_SUPPORT)
243 /* Wait for PLLRDY, PLLSAI1RDY and PLLSAI2RDY bits to be reset */
244 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U)
245 {
246 }
247 #elif defined(RCC_PLLSAI1_SUPPORT)
248 /* Wait for PLLRDY and PLLSAI1RDY to be reset */
249 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U)
250 {
251 }
252 #else
253 /* Wait for PLLRDY bit to be reset */
254 while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
255 {
256 }
257 #endif
258
259 /* Reset PLLCFGR register */
260 LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
261
262 #if defined(RCC_PLLSAI1_SUPPORT)
263 /* Reset PLLSAI1CFGR register */
264 LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
265 #endif /*RCC_PLLSAI1_SUPPORT*/
266
267 #if defined(RCC_PLLSAI2_SUPPORT)
268 /* Reset PLLSAI2CFGR register */
269 LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
270 #endif /*RCC_PLLSAI2_SUPPORT*/
271
272 /* Reset HSEBYP bit */
273 LL_RCC_HSE_DisableBypass();
274
275 /* Disable all interrupts */
276 LL_RCC_WriteReg(CIER, 0x00000000U);
277
278 /* Clear all interrupt flags */
279 vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
280 RCC_CICR_CSSC | RCC_CICR_LSECSSC;
281 #if defined(RCC_HSI48_SUPPORT)
282 vl_mask |= RCC_CICR_HSI48RDYC;
283 #endif
284 #if defined(RCC_PLLSAI1_SUPPORT)
285 vl_mask |= RCC_CICR_PLLSAI1RDYC;
286 #endif
287 #if defined(RCC_PLLSAI2_SUPPORT)
288 vl_mask |= RCC_CICR_PLLSAI2RDYC;
289 #endif
290 LL_RCC_WriteReg(CICR, vl_mask);
291
292 /* Clear reset flags */
293 LL_RCC_ClearResetFlags();
294
295 return SUCCESS;
296 }
297
298 /**
299 * @}
300 */
301
302 /** @addtogroup RCC_LL_EF_Get_Freq
303 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
304 * and different peripheral clocks available on the device.
305 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)
306 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
307 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
308 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
309 * or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.
310 * @note (*) MSI_VALUE is a constant defined in this file (default value
311 * 4 MHz) but the real value may vary depending on the variations
312 * in voltage and temperature.
313 * @note (**) HSI_VALUE is a constant defined in this file (default value
314 * 16 MHz) but the real value may vary depending on the variations
315 * in voltage and temperature.
316 * @note (***) HSE_VALUE is a constant defined in this file (default value
317 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
318 * frequency of the crystal used. Otherwise, this function may
319 * have wrong result.
320 * @note The result of this function could be incorrect when using fractional
321 * value for HSE crystal.
322 * @note This function can be used by the user application to compute the
323 * baud-rate for the communication peripherals or configure other parameters.
324 * @{
325 */
326
327 /**
328 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
329 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
330 * must be called to update structure fields. Otherwise, any
331 * configuration based on this function will be incorrect.
332 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
333 * @retval None
334 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)335 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
336 {
337 /* Get SYSCLK frequency */
338 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
339
340 /* HCLK clock frequency */
341 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
342
343 /* PCLK1 clock frequency */
344 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
345
346 /* PCLK2 clock frequency */
347 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
348 }
349
350 /**
351 * @brief Return USARTx clock frequency
352 * @param USARTxSource This parameter can be one of the following values:
353 * @arg @ref LL_RCC_USART1_CLKSOURCE
354 * @arg @ref LL_RCC_USART2_CLKSOURCE
355 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
356 *
357 * (*) value not defined in all devices.
358 * @retval USART clock frequency (in Hz)
359 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
360 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)361 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
362 {
363 uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
364
365 /* Check parameter */
366 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
367
368 if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
369 {
370 /* USART1CLK clock frequency */
371 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
372 {
373 case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
374 usart_frequency = RCC_GetSystemClockFreq();
375 break;
376
377 case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
378 if (LL_RCC_HSI_IsReady() != 0U)
379 {
380 usart_frequency = HSI_VALUE;
381 }
382 break;
383
384 case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
385 if (LL_RCC_LSE_IsReady() != 0U)
386 {
387 usart_frequency = LSE_VALUE;
388 }
389 break;
390
391 case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */
392 usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
393 break;
394
395 default:
396 break;
397 }
398 }
399 else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
400 {
401 /* USART2CLK clock frequency */
402 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
403 {
404 case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
405 usart_frequency = RCC_GetSystemClockFreq();
406 break;
407
408 case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
409 if (LL_RCC_HSI_IsReady() != 0U)
410 {
411 usart_frequency = HSI_VALUE;
412 }
413 break;
414
415 case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
416 if (LL_RCC_LSE_IsReady() != 0U)
417 {
418 usart_frequency = LSE_VALUE;
419 }
420 break;
421
422 case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
423 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
424 break;
425
426 default:
427 break;
428 }
429 }
430 else
431 {
432 #if defined(RCC_CCIPR_USART3SEL)
433 if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
434 {
435 /* USART3CLK clock frequency */
436 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
437 {
438 case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
439 usart_frequency = RCC_GetSystemClockFreq();
440 break;
441
442 case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
443 if (LL_RCC_HSI_IsReady() != 0U)
444 {
445 usart_frequency = HSI_VALUE;
446 }
447 break;
448
449 case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
450 if (LL_RCC_LSE_IsReady() != 0U)
451 {
452 usart_frequency = LSE_VALUE;
453 }
454 break;
455
456 case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
457 usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
458 break;
459
460 default:
461 break;
462 }
463 }
464 #endif /* RCC_CCIPR_USART3SEL */
465 }
466 return usart_frequency;
467 }
468
469 #if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)
470 /**
471 * @brief Return UARTx clock frequency
472 * @param UARTxSource This parameter can be one of the following values:
473 * @arg @ref LL_RCC_UART4_CLKSOURCE
474 * @arg @ref LL_RCC_UART5_CLKSOURCE
475 * @retval UART clock frequency (in Hz)
476 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
477 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)478 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
479 {
480 uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
481
482 /* Check parameter */
483 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
484
485 #if defined(RCC_CCIPR_UART4SEL)
486 if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
487 {
488 /* UART4CLK clock frequency */
489 switch (LL_RCC_GetUARTClockSource(UARTxSource))
490 {
491 case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
492 uart_frequency = RCC_GetSystemClockFreq();
493 break;
494
495 case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */
496 if (LL_RCC_HSI_IsReady() != 0U)
497 {
498 uart_frequency = HSI_VALUE;
499 }
500 break;
501
502 case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */
503 if (LL_RCC_LSE_IsReady() != 0U)
504 {
505 uart_frequency = LSE_VALUE;
506 }
507 break;
508
509 case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */
510 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
511 break;
512
513 default:
514 break;
515 }
516 }
517 #endif /* RCC_CCIPR_UART4SEL */
518
519 #if defined(RCC_CCIPR_UART5SEL)
520 if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
521 {
522 /* UART5CLK clock frequency */
523 switch (LL_RCC_GetUARTClockSource(UARTxSource))
524 {
525 case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
526 uart_frequency = RCC_GetSystemClockFreq();
527 break;
528
529 case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */
530 if (LL_RCC_HSI_IsReady() != 0U)
531 {
532 uart_frequency = HSI_VALUE;
533 }
534 break;
535
536 case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */
537 if (LL_RCC_LSE_IsReady() != 0U)
538 {
539 uart_frequency = LSE_VALUE;
540 }
541 break;
542
543 case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */
544 uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
545 break;
546
547 default:
548 break;
549 }
550 }
551 #endif /* RCC_CCIPR_UART5SEL */
552
553 return uart_frequency;
554 }
555 #endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */
556
557 /**
558 * @brief Return I2Cx clock frequency
559 * @param I2CxSource This parameter can be one of the following values:
560 * @arg @ref LL_RCC_I2C1_CLKSOURCE
561 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
562 * @arg @ref LL_RCC_I2C3_CLKSOURCE
563 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
564 *
565 * (*) value not defined in all devices.
566 * @retval I2C clock frequency (in Hz)
567 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
568 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)569 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
570 {
571 uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
572
573 /* Check parameter */
574 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
575
576 if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
577 {
578 /* I2C1 CLK clock frequency */
579 switch (LL_RCC_GetI2CClockSource(I2CxSource))
580 {
581 case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
582 i2c_frequency = RCC_GetSystemClockFreq();
583 break;
584
585 case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
586 if (LL_RCC_HSI_IsReady() != 0U)
587 {
588 i2c_frequency = HSI_VALUE;
589 }
590 break;
591
592 case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */
593 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
594 break;
595
596 default:
597 break;
598 }
599 }
600 #if defined(RCC_CCIPR_I2C2SEL)
601 else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
602 {
603 /* I2C2 CLK clock frequency */
604 switch (LL_RCC_GetI2CClockSource(I2CxSource))
605 {
606 case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
607 i2c_frequency = RCC_GetSystemClockFreq();
608 break;
609
610 case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */
611 if (LL_RCC_HSI_IsReady() != 0U)
612 {
613 i2c_frequency = HSI_VALUE;
614 }
615 break;
616
617 case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */
618 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
619 break;
620
621 default:
622 break;
623 }
624 }
625 #endif /*RCC_CCIPR_I2C2SEL*/
626 else
627 {
628 if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
629 {
630 /* I2C3 CLK clock frequency */
631 switch (LL_RCC_GetI2CClockSource(I2CxSource))
632 {
633 case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
634 i2c_frequency = RCC_GetSystemClockFreq();
635 break;
636
637 case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */
638 if (LL_RCC_HSI_IsReady() != 0U)
639 {
640 i2c_frequency = HSI_VALUE;
641 }
642 break;
643
644 case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */
645 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
646 break;
647
648 default:
649 break;
650 }
651 }
652 #if defined(RCC_CCIPR2_I2C4SEL)
653 else
654 {
655 if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
656 {
657 /* I2C4 CLK clock frequency */
658 switch (LL_RCC_GetI2CClockSource(I2CxSource))
659 {
660 case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
661 i2c_frequency = RCC_GetSystemClockFreq();
662 break;
663
664 case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */
665 if (LL_RCC_HSI_IsReady() != 0U)
666 {
667 i2c_frequency = HSI_VALUE;
668 }
669 break;
670
671 case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */
672 i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
673 break;
674
675 default:
676 break;
677 }
678 }
679 }
680 #endif /*RCC_CCIPR2_I2C4SEL*/
681 }
682
683 return i2c_frequency;
684 }
685
686
687 /**
688 * @brief Return LPUARTx clock frequency
689 * @param LPUARTxSource This parameter can be one of the following values:
690 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
691 * @retval LPUART clock frequency (in Hz)
692 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
693 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)694 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
695 {
696 uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
697
698 /* Check parameter */
699 assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
700
701 /* LPUART1CLK clock frequency */
702 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
703 {
704 case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
705 lpuart_frequency = RCC_GetSystemClockFreq();
706 break;
707
708 case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */
709 if (LL_RCC_HSI_IsReady() != 0U)
710 {
711 lpuart_frequency = HSI_VALUE;
712 }
713 break;
714
715 case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */
716 if (LL_RCC_LSE_IsReady() != 0U)
717 {
718 lpuart_frequency = LSE_VALUE;
719 }
720 break;
721
722 case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */
723 lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
724 break;
725
726 default:
727 break;
728 }
729
730 return lpuart_frequency;
731 }
732
733 /**
734 * @brief Return LPTIMx clock frequency
735 * @param LPTIMxSource This parameter can be one of the following values:
736 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
737 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
738 * @retval LPTIM clock frequency (in Hz)
739 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
740 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)741 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
742 {
743 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
744
745 /* Check parameter */
746 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
747
748 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
749 {
750 /* LPTIM1CLK clock frequency */
751 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
752 {
753 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
754 if (LL_RCC_LSI_IsReady() != 0U)
755 {
756 #if defined(RCC_CSR_LSIPREDIV)
757 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
758 {
759 lptim_frequency = LSI_VALUE / 128U;
760 }
761 else
762 #endif /* RCC_CSR_LSIPREDIV */
763 {
764 lptim_frequency = LSI_VALUE;
765 }
766 }
767 break;
768
769 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
770 if (LL_RCC_HSI_IsReady() != 0U)
771 {
772 lptim_frequency = HSI_VALUE;
773 }
774 break;
775
776 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
777 if (LL_RCC_LSE_IsReady() != 0U)
778 {
779 lptim_frequency = LSE_VALUE;
780 }
781 break;
782
783 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
784 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
785 break;
786
787 default:
788 break;
789 }
790 }
791 else
792 {
793 if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)
794 {
795 /* LPTIM2CLK clock frequency */
796 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
797 {
798 case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */
799 if (LL_RCC_LSI_IsReady() != 0U)
800 {
801 #if defined(RCC_CSR_LSIPREDIV)
802 if (LL_RCC_LSI_GetPrediv() == LL_RCC_LSI_PREDIV_128)
803 {
804 lptim_frequency = LSI_VALUE / 128U;
805 }
806 else
807 #endif /* RCC_CSR_LSIPREDIV */
808 {
809 lptim_frequency = LSI_VALUE;
810 }
811 }
812 break;
813
814 case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */
815 if (LL_RCC_HSI_IsReady() != 0U)
816 {
817 lptim_frequency = HSI_VALUE;
818 }
819 break;
820
821 case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */
822 if (LL_RCC_LSE_IsReady() != 0U)
823 {
824 lptim_frequency = LSE_VALUE;
825 }
826 break;
827
828 case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */
829 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
830 break;
831
832 default:
833 break;
834 }
835 }
836 }
837
838 return lptim_frequency;
839 }
840
841 #if defined(RCC_CCIPR_SAI1SEL) || defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI1SEL) || defined(RCC_CCIPR2_SAI2SEL)
842 /**
843 * @brief Return SAIx clock frequency
844 * @param SAIxSource This parameter can be one of the following values:
845 * @arg @ref LL_RCC_SAI1_CLKSOURCE
846 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
847 *
848 * (*) value not defined in all devices.
849 * @retval SAI clock frequency (in Hz)
850 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
851
852 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)853 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
854 {
855 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
856
857 /* Check parameter */
858 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
859
860 if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
861 {
862 /* SAI1CLK clock frequency */
863 switch (LL_RCC_GetSAIClockSource(SAIxSource))
864 {
865 case LL_RCC_SAI1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI1 clock source */
866 if (LL_RCC_PLLSAI1_IsReady() != 0U)
867 {
868 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
869 }
870 break;
871
872 #if defined(RCC_PLLSAI2_SUPPORT)
873 case LL_RCC_SAI1_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI1 clock source */
874 if (LL_RCC_PLLSAI2_IsReady() != 0U)
875 {
876 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
877 }
878 break;
879
880 #endif /* RCC_PLLSAI2_SUPPORT */
881 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
882 if (LL_RCC_PLL_IsReady() != 0U)
883 {
884 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
885 }
886 break;
887
888 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
889 sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE;
890 break;
891
892 default:
893 break;
894 }
895 }
896 else
897 {
898 #if defined(RCC_CCIPR_SAI2SEL) || defined(RCC_CCIPR2_SAI2SEL)
899 if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)
900 {
901 /* SAI2CLK clock frequency */
902 switch (LL_RCC_GetSAIClockSource(SAIxSource))
903 {
904 case LL_RCC_SAI2_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SAI2 clock source */
905 if (LL_RCC_PLLSAI1_IsReady() != 0U)
906 {
907 sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();
908 }
909 break;
910
911 #if defined(RCC_PLLSAI2_SUPPORT)
912 case LL_RCC_SAI2_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as SAI2 clock source */
913 if (LL_RCC_PLLSAI2_IsReady() != 0U)
914 {
915 sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();
916 }
917 break;
918
919 #endif /* RCC_PLLSAI2_SUPPORT */
920 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
921 if (LL_RCC_PLL_IsReady() != 0U)
922 {
923 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
924 }
925 break;
926
927 case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */
928 sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE;
929 break;
930
931 default:
932 break;
933 }
934 }
935 #endif /* RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI2SEL */
936 }
937
938 return sai_frequency;
939 }
940 #endif /* RCC_CCIPR_SAI1SEL || RCC_CCIPR_SAI2SEL || RCC_CCIPR2_SAI1SEL || RCC_CCIPR2_SAI2SEL*/
941
942 #if defined(SDMMC1)
943 #if defined(RCC_CCIPR2_SDMMCSEL)
944 /**
945 * @brief Return SDMMCx kernel clock frequency
946 * @param SDMMCxSource This parameter can be one of the following values:
947 * @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
948 * @retval SDMMC clock frequency (in Hz)
949 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
950 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
951 */
LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)952 uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)
953 {
954 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
955
956 /* Check parameter */
957 assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));
958
959 /* SDMMC1CLK kernel clock frequency */
960 switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))
961 {
962 case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK: /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */
963 sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);
964 break;
965
966 case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP: /* PLL "P" output (PLLSAI3CLK) clock used as SDMMC1 clock source */
967 if (LL_RCC_PLL_IsReady() != 0U)
968 {
969 sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();
970 }
971 break;
972
973 default:
974 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
975 break;
976 }
977
978 return sdmmc_frequency;
979 }
980 #endif
981
982 /**
983 * @brief Return SDMMCx clock frequency
984 * @param SDMMCxSource This parameter can be one of the following values:
985 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
986 * @retval SDMMC clock frequency (in Hz)
987 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
988 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
989 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)990 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
991 {
992 uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
993
994 /* Check parameter */
995 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
996
997 /* SDMMC1CLK clock frequency */
998 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
999 {
1000 #if defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1)
1001 case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as SDMMC1 clock source */
1002 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1003 {
1004 sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1005 }
1006 break;
1007 #endif
1008
1009 case LL_RCC_SDMMC1_CLKSOURCE_PLL: /* PLL clock used as SDMMC1 clock source */
1010 if (LL_RCC_PLL_IsReady() != 0U)
1011 {
1012 sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();
1013 }
1014 break;
1015
1016 #if defined(LL_RCC_SDMMC1_CLKSOURCE_MSI)
1017 case LL_RCC_SDMMC1_CLKSOURCE_MSI: /* MSI clock used as SDMMC1 clock source */
1018 if (LL_RCC_MSI_IsReady() != 0U)
1019 {
1020 sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1021 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1022 LL_RCC_MSI_GetRange() :
1023 LL_RCC_MSI_GetRangeAfterStandby()));
1024 }
1025 break;
1026 #endif
1027
1028 #if defined(RCC_HSI48_SUPPORT)
1029 case LL_RCC_SDMMC1_CLKSOURCE_HSI48: /* HSI48 used as SDMMC1 clock source */
1030 if (LL_RCC_HSI48_IsReady() != 0U)
1031 {
1032 sdmmc_frequency = HSI48_VALUE;
1033 }
1034 break;
1035 #else
1036 case LL_RCC_SDMMC1_CLKSOURCE_NONE: /* No clock used as SDMMC1 clock source */
1037 #endif
1038 default:
1039 sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1040 break;
1041 }
1042
1043 return sdmmc_frequency;
1044 }
1045 #endif /* SDMMC1 */
1046
1047 /**
1048 * @brief Return RNGx clock frequency
1049 * @param RNGxSource This parameter can be one of the following values:
1050 * @arg @ref LL_RCC_RNG_CLKSOURCE
1051 * @retval RNG clock frequency (in Hz)
1052 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1053 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1054 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)1055 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
1056 {
1057 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1058
1059 /* Check parameter */
1060 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
1061
1062 /* RNGCLK clock frequency */
1063 switch (LL_RCC_GetRNGClockSource(RNGxSource))
1064 {
1065 #if defined(RCC_PLLSAI1_SUPPORT)
1066 case LL_RCC_RNG_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as RNG clock source */
1067 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1068 {
1069 rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1070 }
1071 break;
1072 #endif /* RCC_PLLSAI1_SUPPORT */
1073
1074 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
1075 if (LL_RCC_PLL_IsReady() != 0U)
1076 {
1077 rng_frequency = RCC_PLL_GetFreqDomain_48M();
1078 }
1079 break;
1080
1081 case LL_RCC_RNG_CLKSOURCE_MSI: /* MSI clock used as RNG clock source */
1082 if (LL_RCC_MSI_IsReady() != 0U)
1083 {
1084 rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1085 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1086 LL_RCC_MSI_GetRange() :
1087 LL_RCC_MSI_GetRangeAfterStandby()));
1088 }
1089 break;
1090
1091
1092 #if defined(RCC_HSI48_SUPPORT)
1093 case LL_RCC_RNG_CLKSOURCE_HSI48: /* HSI48 used as RNG clock source */
1094 if (LL_RCC_HSI48_IsReady() != 0U)
1095 {
1096 rng_frequency = HSI48_VALUE;
1097 }
1098 break;
1099 #else
1100 case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */
1101 #endif
1102 default:
1103 rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1104 break;
1105
1106 }
1107
1108 return rng_frequency;
1109 }
1110
1111
1112 #if defined(USB_OTG_FS)||defined(USB)
1113 /**
1114 * @brief Return USBx clock frequency
1115 * @param USBxSource This parameter can be one of the following values:
1116 * @arg @ref LL_RCC_USB_CLKSOURCE
1117 * @retval USB clock frequency (in Hz)
1118 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1119 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1120 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)1121 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
1122 {
1123 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1124
1125 /* Check parameter */
1126 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
1127
1128 /* USBCLK clock frequency */
1129 switch (LL_RCC_GetUSBClockSource(USBxSource))
1130 {
1131 #if defined(RCC_PLLSAI1_SUPPORT)
1132 case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
1133 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1134 {
1135 usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();
1136 }
1137 break;
1138 #endif /* RCC_PLLSAI1_SUPPORT */
1139
1140 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
1141 if (LL_RCC_PLL_IsReady() != 0U)
1142 {
1143 usb_frequency = RCC_PLL_GetFreqDomain_48M();
1144 }
1145 break;
1146
1147 case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */
1148 if (LL_RCC_MSI_IsReady() != 0U)
1149 {
1150 usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1151 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1152 LL_RCC_MSI_GetRange() :
1153 LL_RCC_MSI_GetRangeAfterStandby()));
1154 }
1155 break;
1156
1157 #if defined(RCC_HSI48_SUPPORT)
1158 case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */
1159 if (LL_RCC_HSI48_IsReady() != 0U)
1160 {
1161 usb_frequency = HSI48_VALUE;
1162 }
1163 break;
1164 #else
1165 case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
1166 #endif
1167 default:
1168 usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1169 break;
1170 }
1171
1172 return usb_frequency;
1173 }
1174 #endif /* USB_OTG_FS || USB */
1175
1176 /**
1177 * @brief Return ADCx clock frequency
1178 * @param ADCxSource This parameter can be one of the following values:
1179 * @arg @ref LL_RCC_ADC_CLKSOURCE
1180 * @retval ADC clock frequency (in Hz)
1181 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready
1182 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
1183 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)1184 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
1185 {
1186 uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1187
1188 /* Check parameter */
1189 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
1190
1191 /* ADCCLK clock frequency */
1192 switch (LL_RCC_GetADCClockSource(ADCxSource))
1193 {
1194 #if defined(RCC_PLLSAI1_SUPPORT)
1195 case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
1196 if (LL_RCC_PLLSAI1_IsReady() != 0U)
1197 {
1198 adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();
1199 }
1200 break;
1201 #endif /* RCC_PLLSAI1_SUPPORT */
1202
1203 #if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2)
1204 case LL_RCC_ADC_CLKSOURCE_PLLSAI2: /* PLLSAI2 clock used as ADC clock source */
1205 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1206 {
1207 adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();
1208 }
1209 break;
1210 #endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */
1211
1212 case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
1213 adc_frequency = RCC_GetSystemClockFreq();
1214 break;
1215
1216 case LL_RCC_ADC_CLKSOURCE_NONE: /* No clock used as ADC clock source */
1217 default:
1218 adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1219 break;
1220 }
1221
1222 return adc_frequency;
1223 }
1224
1225 #if defined(SWPMI1)
1226 /**
1227 * @brief Return SWPMIx clock frequency
1228 * @param SWPMIxSource This parameter can be one of the following values:
1229 * @arg @ref LL_RCC_SWPMI1_CLKSOURCE
1230 * @retval SWPMI clock frequency (in Hz)
1231 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready
1232 */
LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)1233 uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)
1234 {
1235 uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1236
1237 /* Check parameter */
1238 assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));
1239
1240 /* SWPMI1CLK clock frequency */
1241 switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))
1242 {
1243 case LL_RCC_SWPMI1_CLKSOURCE_HSI: /* SWPMI1 Clock is HSI Osc. */
1244 if (LL_RCC_HSI_IsReady())
1245 {
1246 swpmi_frequency = HSI_VALUE;
1247 }
1248 break;
1249
1250 case LL_RCC_SWPMI1_CLKSOURCE_PCLK1: /* SWPMI1 Clock is PCLK1 */
1251 swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1252 break;
1253
1254 default:
1255 break;
1256 }
1257
1258 return swpmi_frequency;
1259 }
1260 #endif /* SWPMI1 */
1261
1262 #if defined(DFSDM1_Channel0)
1263 /**
1264 * @brief Return DFSDMx clock frequency
1265 * @param DFSDMxSource This parameter can be one of the following values:
1266 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
1267 * @retval DFSDM clock frequency (in Hz)
1268 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)1269 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
1270 {
1271 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1272
1273 /* Check parameter */
1274 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
1275
1276 /* DFSDM1CLK clock frequency */
1277 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
1278 {
1279 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
1280 dfsdm_frequency = RCC_GetSystemClockFreq();
1281 break;
1282
1283 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
1284 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
1285 break;
1286
1287 default:
1288 break;
1289 }
1290
1291 return dfsdm_frequency;
1292 }
1293
1294 #if defined(RCC_CCIPR2_DFSDM1SEL)
1295 /**
1296 * @brief Return DFSDMx Audio clock frequency
1297 * @param DFSDMxSource This parameter can be one of the following values:
1298 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
1299 * @retval DFSDM clock frequency (in Hz)
1300 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1301 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)1302 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
1303 {
1304 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1305
1306 /* Check parameter */
1307 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
1308
1309 /* DFSDM1CLK clock frequency */
1310 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1311 {
1312 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */
1313 dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);
1314 break;
1315
1316 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI: /* MSI clock used as DFSDM1 audio clock */
1317 if (LL_RCC_MSI_IsReady() != 0U)
1318 {
1319 dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1320 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1321 LL_RCC_MSI_GetRange() :
1322 LL_RCC_MSI_GetRangeAfterStandby()));
1323 }
1324 break;
1325
1326 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI: /* HSI clock used as DFSDM1 audio clock */
1327 default:
1328 if (LL_RCC_HSI_IsReady() != 0U)
1329 {
1330 dfsdm_frequency = HSI_VALUE;
1331 }
1332 break;
1333 }
1334
1335 return dfsdm_frequency;
1336 }
1337 #endif /* RCC_CCIPR2_DFSDM1SEL */
1338 #endif /* DFSDM1_Channel0 */
1339
1340 #if defined(DSI)
1341 /**
1342 * @brief Return DSI clock frequency
1343 * @param DSIxSource This parameter can be one of the following values:
1344 * @arg @ref LL_RCC_DSI_CLKSOURCE
1345 * @retval DSI clock frequency (in Hz)
1346 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1347 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1348 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1349 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1350 {
1351 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1352
1353 /* Check parameter */
1354 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1355
1356 /* DSICLK clock frequency */
1357 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1358 {
1359 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLLSAI2 Osc. */
1360 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1361 {
1362 dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();
1363 }
1364 break;
1365
1366 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1367 default:
1368 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1369 break;
1370 }
1371
1372 return dsi_frequency;
1373 }
1374 #endif /* DSI */
1375
1376 #if defined(LTDC)
1377 /**
1378 * @brief Return LTDC clock frequency
1379 * @param LTDCxSource This parameter can be one of the following values:
1380 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1381 * @retval LTDC clock frequency (in Hz)
1382 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1383 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1384 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1385 {
1386 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1387
1388 /* Check parameter */
1389 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1390
1391 if (LL_RCC_PLLSAI2_IsReady() != 0U)
1392 {
1393 ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();
1394 }
1395
1396 return ltdc_frequency;
1397 }
1398 #endif /* LTDC */
1399
1400 #if defined(OCTOSPI1)
1401 /**
1402 * @brief Return OCTOSPI clock frequency
1403 * @param OCTOSPIxSource This parameter can be one of the following values:
1404 * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
1405 * @retval OCTOSPI clock frequency (in Hz)
1406 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1407 */
LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)1408 uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)
1409 {
1410 uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1411
1412 /* Check parameter */
1413 assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));
1414
1415 /* OCTOSPI clock frequency */
1416 switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))
1417 {
1418 case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK: /* OCTOSPI clock is SYSCLK */
1419 octospi_frequency = RCC_GetSystemClockFreq();
1420 break;
1421
1422 case LL_RCC_OCTOSPI_CLKSOURCE_MSI: /* MSI clock used as OCTOSPI clock */
1423 if (LL_RCC_MSI_IsReady() != 0U)
1424 {
1425 octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1426 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1427 LL_RCC_MSI_GetRange() :
1428 LL_RCC_MSI_GetRangeAfterStandby()));
1429 }
1430 break;
1431
1432 case LL_RCC_OCTOSPI_CLKSOURCE_PLL: /* PLL clock used as OCTOSPI source */
1433 if (LL_RCC_PLL_IsReady() != 0U)
1434 {
1435 octospi_frequency = RCC_PLL_GetFreqDomain_48M();
1436 }
1437 break;
1438
1439 default:
1440 octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1441 break;
1442 }
1443
1444 return octospi_frequency;
1445 }
1446 #endif /* OCTOSPI1 */
1447
1448 /**
1449 * @}
1450 */
1451
1452 /**
1453 * @}
1454 */
1455
1456 /** @addtogroup RCC_LL_Private_Functions
1457 * @{
1458 */
1459
1460 /**
1461 * @brief Return SYSTEM clock frequency
1462 * @retval SYSTEM clock frequency (in Hz)
1463 */
RCC_GetSystemClockFreq(void)1464 static uint32_t RCC_GetSystemClockFreq(void)
1465 {
1466 uint32_t frequency;
1467
1468 /* Get SYSCLK source -------------------------------------------------------*/
1469 switch (LL_RCC_GetSysClkSource())
1470 {
1471 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
1472 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1473 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1474 LL_RCC_MSI_GetRange() :
1475 LL_RCC_MSI_GetRangeAfterStandby()));
1476 break;
1477
1478 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1479 frequency = HSI_VALUE;
1480 break;
1481
1482 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1483 frequency = HSE_VALUE;
1484 break;
1485
1486 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1487 frequency = RCC_PLL_GetFreqDomain_SYS();
1488 break;
1489
1490 default:
1491 frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1492 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1493 LL_RCC_MSI_GetRange() :
1494 LL_RCC_MSI_GetRangeAfterStandby()));
1495 break;
1496 }
1497
1498 return frequency;
1499 }
1500
1501 /**
1502 * @brief Return HCLK clock frequency
1503 * @param SYSCLK_Frequency SYSCLK clock frequency
1504 * @retval HCLK clock frequency (in Hz)
1505 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1506 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1507 {
1508 /* HCLK clock frequency */
1509 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1510 }
1511
1512 /**
1513 * @brief Return PCLK1 clock frequency
1514 * @param HCLK_Frequency HCLK clock frequency
1515 * @retval PCLK1 clock frequency (in Hz)
1516 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1517 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1518 {
1519 /* PCLK1 clock frequency */
1520 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1521 }
1522
1523 /**
1524 * @brief Return PCLK2 clock frequency
1525 * @param HCLK_Frequency HCLK clock frequency
1526 * @retval PCLK2 clock frequency (in Hz)
1527 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1528 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1529 {
1530 /* PCLK2 clock frequency */
1531 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1532 }
1533
1534 /**
1535 * @brief Return PLL clock frequency used for system domain
1536 * @retval PLL clock frequency (in Hz)
1537 */
RCC_PLL_GetFreqDomain_SYS(void)1538 static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1539 {
1540 uint32_t pllinputfreq, pllsource;
1541
1542 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1543 SYSCLK = PLL_VCO / PLLR
1544 */
1545 pllsource = LL_RCC_PLL_GetMainSource();
1546
1547 switch (pllsource)
1548 {
1549 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1550 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1551 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1552 LL_RCC_MSI_GetRange() :
1553 LL_RCC_MSI_GetRangeAfterStandby()));
1554 break;
1555
1556 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1557 pllinputfreq = HSI_VALUE;
1558 break;
1559
1560 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1561 pllinputfreq = HSE_VALUE;
1562 break;
1563
1564 default:
1565 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1566 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1567 LL_RCC_MSI_GetRange() :
1568 LL_RCC_MSI_GetRangeAfterStandby()));
1569 break;
1570 }
1571 return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1572 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1573 }
1574
1575 #if defined(SAI1)
1576 /**
1577 * @brief Return PLL clock frequency used for SAI domain
1578 * @retval PLL clock frequency (in Hz)
1579 */
RCC_PLL_GetFreqDomain_SAI(void)1580 static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1581 {
1582 uint32_t pllinputfreq, pllsource;
1583
1584 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN
1585 SAI Domain clock = PLL_VCO / PLLP
1586 */
1587 pllsource = LL_RCC_PLL_GetMainSource();
1588
1589 switch (pllsource)
1590 {
1591 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1592 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1593 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1594 LL_RCC_MSI_GetRange() :
1595 LL_RCC_MSI_GetRangeAfterStandby()));
1596 break;
1597
1598 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1599 pllinputfreq = HSI_VALUE;
1600 break;
1601
1602 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1603 pllinputfreq = HSE_VALUE;
1604 break;
1605
1606 default:
1607 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1608 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1609 LL_RCC_MSI_GetRange() :
1610 LL_RCC_MSI_GetRangeAfterStandby()));
1611 break;
1612 }
1613 return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1614 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1615 }
1616 #endif /* SAI1 */
1617
1618 /**
1619 * @brief Return PLL clock frequency used for 48 MHz domain
1620 * @retval PLL clock frequency (in Hz)
1621 */
RCC_PLL_GetFreqDomain_48M(void)1622 static uint32_t RCC_PLL_GetFreqDomain_48M(void)
1623 {
1624 uint32_t pllinputfreq, pllsource;
1625
1626 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
1627 48M Domain clock = PLL_VCO / PLLQ
1628 */
1629 pllsource = LL_RCC_PLL_GetMainSource();
1630
1631 switch (pllsource)
1632 {
1633 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1634 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1635 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1636 LL_RCC_MSI_GetRange() :
1637 LL_RCC_MSI_GetRangeAfterStandby()));
1638 break;
1639
1640 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1641 pllinputfreq = HSI_VALUE;
1642 break;
1643
1644 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1645 pllinputfreq = HSE_VALUE;
1646 break;
1647
1648 default:
1649 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1650 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1651 LL_RCC_MSI_GetRange() :
1652 LL_RCC_MSI_GetRangeAfterStandby()));
1653 break;
1654 }
1655 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1656 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1657 }
1658 #if defined(DSI)
1659 /**
1660 * @brief Return PLL clock frequency used for DSI clock
1661 * @retval PLL clock frequency (in Hz)
1662 */
RCC_PLLSAI2_GetFreqDomain_DSI(void)1663 static uint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)
1664 {
1665 uint32_t pllinputfreq, pllsource;
1666
1667 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1668 /* DSICLK = PLLSAI2_VCO / PLLSAI2R */
1669 pllsource = LL_RCC_PLL_GetMainSource();
1670
1671 switch (pllsource)
1672 {
1673 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1674 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1675 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1676 LL_RCC_MSI_GetRange() :
1677 LL_RCC_MSI_GetRangeAfterStandby()));
1678 break;
1679
1680 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1681 pllinputfreq = HSI_VALUE;
1682 break;
1683
1684 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1685 pllinputfreq = HSE_VALUE;
1686 break;
1687
1688 default:
1689 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1690 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1691 LL_RCC_MSI_GetRange() :
1692 LL_RCC_MSI_GetRangeAfterStandby()));
1693 break;
1694 }
1695
1696 return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1697 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
1698 }
1699 #endif /* DSI */
1700
1701 #if defined(RCC_PLLSAI1_SUPPORT)
1702 /**
1703 * @brief Return PLLSAI1 clock frequency used for SAI domain
1704 * @retval PLLSAI1 clock frequency (in Hz)
1705 */
RCC_PLLSAI1_GetFreqDomain_SAI(void)1706 static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
1707 {
1708 uint32_t pllinputfreq, pllsource;
1709
1710 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1711 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1712 #else
1713 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1714 #endif
1715 /* SAI Domain clock = PLLSAI1_VCO / PLLSAI1P */
1716 pllsource = LL_RCC_PLL_GetMainSource();
1717
1718 switch (pllsource)
1719 {
1720 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1721 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1722 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1723 LL_RCC_MSI_GetRange() :
1724 LL_RCC_MSI_GetRangeAfterStandby()));
1725 break;
1726
1727 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1728 pllinputfreq = HSI_VALUE;
1729 break;
1730
1731 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1732 pllinputfreq = HSE_VALUE;
1733 break;
1734
1735 default:
1736 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1737 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1738 LL_RCC_MSI_GetRange() :
1739 LL_RCC_MSI_GetRangeAfterStandby()));
1740 break;
1741 }
1742 return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1743 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());
1744 }
1745
1746 /**
1747 * @brief Return PLLSAI1 clock frequency used for 48Mhz domain
1748 * @retval PLLSAI1 clock frequency (in Hz)
1749 */
RCC_PLLSAI1_GetFreqDomain_48M(void)1750 static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
1751 {
1752 uint32_t pllinputfreq, pllsource;
1753
1754 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1755 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1756 #else
1757 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1758 #endif
1759 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1Q */
1760 pllsource = LL_RCC_PLL_GetMainSource();
1761
1762 switch (pllsource)
1763 {
1764 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1765 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1766 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1767 LL_RCC_MSI_GetRange() :
1768 LL_RCC_MSI_GetRangeAfterStandby()));
1769 break;
1770
1771 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1772 pllinputfreq = HSI_VALUE;
1773 break;
1774
1775 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1776 pllinputfreq = HSE_VALUE;
1777 break;
1778
1779 default:
1780 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1781 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1782 LL_RCC_MSI_GetRange() :
1783 LL_RCC_MSI_GetRangeAfterStandby()));
1784 break;
1785 }
1786 return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1787 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
1788 }
1789
1790 /**
1791 * @brief Return PLLSAI1 clock frequency used for ADC domain
1792 * @retval PLLSAI1 clock frequency (in Hz)
1793 */
RCC_PLLSAI1_GetFreqDomain_ADC(void)1794 static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
1795 {
1796 uint32_t pllinputfreq, pllsource;
1797
1798 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1799 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */
1800 #else
1801 /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */
1802 #endif
1803 /* 48M Domain clock = PLLSAI1_VCO / PLLSAI1R */
1804 pllsource = LL_RCC_PLL_GetMainSource();
1805
1806 switch (pllsource)
1807 {
1808 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI1 clock source */
1809 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1810 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1811 LL_RCC_MSI_GetRange() :
1812 LL_RCC_MSI_GetRangeAfterStandby()));
1813 break;
1814
1815 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI1 clock source */
1816 pllinputfreq = HSI_VALUE;
1817 break;
1818
1819 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
1820 pllinputfreq = HSE_VALUE;
1821 break;
1822
1823 default:
1824 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1825 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1826 LL_RCC_MSI_GetRange() :
1827 LL_RCC_MSI_GetRangeAfterStandby()));
1828 break;
1829 }
1830 return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1831 LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());
1832 }
1833 #endif /* RCC_PLLSAI1_SUPPORT */
1834
1835 #if defined(RCC_PLLSAI2_SUPPORT)
1836 /**
1837 * @brief Return PLLSAI2 clock frequency used for SAI domain
1838 * @retval PLLSAI2 clock frequency (in Hz)
1839 */
RCC_PLLSAI2_GetFreqDomain_SAI(void)1840 static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)
1841 {
1842 uint32_t pllinputfreq, pllsource;
1843
1844 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1845 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1846 #else
1847 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1848 #endif
1849 /* SAI Domain clock = PLLSAI2_VCO / PLLSAI2P */
1850 pllsource = LL_RCC_PLL_GetMainSource();
1851
1852 switch (pllsource)
1853 {
1854 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1855 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1856 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1857 LL_RCC_MSI_GetRange() :
1858 LL_RCC_MSI_GetRangeAfterStandby()));
1859 break;
1860
1861 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1862 pllinputfreq = HSI_VALUE;
1863 break;
1864
1865 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1866 pllinputfreq = HSE_VALUE;
1867 break;
1868
1869 default:
1870 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1871 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1872 LL_RCC_MSI_GetRange() :
1873 LL_RCC_MSI_GetRangeAfterStandby()));
1874 break;
1875 }
1876 #if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
1877 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1878 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1879 #else
1880 return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1881 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());
1882 #endif
1883 }
1884
1885 #if defined(LTDC)
1886 /**
1887 * @brief Return PLLSAI2 clock frequency used for LTDC domain
1888 * @retval PLLSAI2 clock frequency (in Hz)
1889 */
RCC_PLLSAI2_GetFreqDomain_LTDC(void)1890 static uint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)
1891 {
1892 uint32_t pllinputfreq, pllsource;
1893
1894 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */
1895 /* LTDC Domain clock = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */
1896 pllsource = LL_RCC_PLL_GetMainSource();
1897
1898 switch (pllsource)
1899 {
1900 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1901 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1902 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1903 LL_RCC_MSI_GetRange() :
1904 LL_RCC_MSI_GetRangeAfterStandby()));
1905 break;
1906
1907 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1908 pllinputfreq = HSI_VALUE;
1909 break;
1910
1911 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1912 pllinputfreq = HSE_VALUE;
1913 break;
1914
1915 default:
1916 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1917 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1918 LL_RCC_MSI_GetRange() :
1919 LL_RCC_MSI_GetRangeAfterStandby()));
1920 break;
1921 }
1922
1923 return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),
1924 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());
1925 }
1926
1927 #else
1928
1929 /**
1930 * @brief Return PLLSAI2 clock frequency used for ADC domain
1931 * @retval PLLSAI2 clock frequency (in Hz)
1932 */
RCC_PLLSAI2_GetFreqDomain_ADC(void)1933 static uint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)
1934 {
1935 uint32_t pllinputfreq = 0U, pllsource = 0U;
1936
1937 /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */
1938 /* 48M Domain clock = PLLSAI2_VCO / PLLSAI2R */
1939 pllsource = LL_RCC_PLL_GetMainSource();
1940
1941 switch (pllsource)
1942 {
1943 case LL_RCC_PLLSOURCE_MSI: /* MSI used as PLLSAI2 clock source */
1944 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1945 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1946 LL_RCC_MSI_GetRange() :
1947 LL_RCC_MSI_GetRangeAfterStandby()));
1948 break;
1949
1950 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI2 clock source */
1951 pllinputfreq = HSI_VALUE;
1952 break;
1953
1954 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI2 clock source */
1955 pllinputfreq = HSE_VALUE;
1956 break;
1957
1958 default:
1959 pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
1960 ((LL_RCC_MSI_IsEnabledRangeSelect() != 0U) ?
1961 LL_RCC_MSI_GetRange() :
1962 LL_RCC_MSI_GetRangeAfterStandby()));
1963 break;
1964 }
1965 return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1966 LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());
1967 }
1968 #endif /* LTDC */
1969
1970 #endif /*RCC_PLLSAI2_SUPPORT*/
1971
1972 /**
1973 * @}
1974 */
1975
1976 /**
1977 * @}
1978 */
1979
1980 #endif /* defined(RCC) */
1981
1982 /**
1983 * @}
1984 */
1985
1986 #endif /* USE_FULL_LL_DRIVER */
1987
1988 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1989
