1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_fmc.h 4 * @author MCD Application Team 5 * @brief Header file of FMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_LL_FMC_H 21 #define STM32L4xx_LL_FMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup FMC_LL 35 * @{ 36 */ 37 38 /** @addtogroup FMC_LL_Private_Macros 39 * @{ 40 */ 41 #if defined(FMC_BANK1) 42 43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ 44 ((__BANK__) == FMC_NORSRAM_BANK2) || \ 45 ((__BANK__) == FMC_NORSRAM_BANK3) || \ 46 ((__BANK__) == FMC_NORSRAM_BANK4)) 47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \ 59 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 60 #if defined(FMC_BCR1_WFDIS) 61 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 62 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 63 #endif /* FMC_BCR1_WFDIS */ 64 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 65 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 66 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 67 ((__MODE__) == FMC_ACCESS_MODE_D)) 68 #if defined(FMC_BCRx_NBLSET) 69 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ 70 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ 71 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ 72 ((__NBL__) == FMC_NBL_SETUPTIME_3)) 73 #endif /* FMC_BCRx_NBLSET */ 74 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 75 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 76 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 77 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 78 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 79 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 80 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 81 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 82 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 83 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 84 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 85 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 86 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 87 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 88 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) 89 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 90 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 91 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 92 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 93 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) 94 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) 95 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) 96 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) 97 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) 98 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) 99 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 100 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 101 #if defined(FMC_PCSCNTR_CSCOUNT) 102 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U)) 103 #endif /* FMC_PCSCNTR_CSCOUNT */ 104 105 #endif /* FMC_BANK1 */ 106 #if defined(FMC_BANK3) 107 108 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) 109 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 110 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) 111 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 112 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) 113 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ 114 ((__STATE__) == FMC_NAND_ECC_ENABLE)) 115 116 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 117 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 118 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 119 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 120 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 121 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 122 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) 123 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) 124 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) 125 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) 126 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) 127 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) 128 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 129 130 #endif /* FMC_BANK3 */ 131 132 /** 133 * @} 134 */ 135 136 /* Exported typedef ----------------------------------------------------------*/ 137 138 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types 139 * @{ 140 */ 141 142 #if defined(FMC_BANK1) 143 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 144 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 145 #endif /* FMC_BANK1 */ 146 #if defined(FMC_BANK3) 147 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 148 #endif /* FMC_BANK3 */ 149 150 #if defined(FMC_BANK1) 151 #define FMC_NORSRAM_DEVICE FMC_Bank1_R 152 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R 153 #endif /* FMC_BANK1 */ 154 #if defined(FMC_BANK3) 155 #define FMC_NAND_DEVICE FMC_Bank3_R 156 #endif /* FMC_BANK3 */ 157 158 #if defined(FMC_BANK1) 159 /** 160 * @brief FMC NORSRAM Configuration Structure definition 161 */ 162 typedef struct 163 { 164 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 165 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 166 167 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 168 multiplexed on the data bus or not. 169 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ 170 171 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 172 the corresponding memory device. 173 This parameter can be a value of @ref FMC_Memory_Type */ 174 175 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 176 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 177 178 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 179 valid only with synchronous burst Flash memories. 180 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 181 182 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 183 the Flash memory in burst mode. 184 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 185 186 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 187 clock cycle before the wait state or during the wait state, 188 valid only when accessing memories in burst mode. 189 This parameter can be a value of @ref FMC_Wait_Timing */ 190 191 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device 192 by the FMC. 193 This parameter can be a value of @ref FMC_Write_Operation */ 194 195 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 196 signal, valid for Flash memory access in burst mode. 197 This parameter can be a value of @ref FMC_Wait_Signal */ 198 199 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 200 This parameter can be a value of @ref FMC_Extended_Mode */ 201 202 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 203 valid only with asynchronous Flash memories. 204 This parameter can be a value of @ref FMC_AsynchronousWait */ 205 206 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 207 This parameter can be a value of @ref FMC_Write_Burst */ 208 209 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 210 This parameter is only enabled through the FMC_BCR1 register, 211 and don't care through FMC_BCR2..4 registers. 212 This parameter can be a value of @ref FMC_Continous_Clock */ 213 214 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 215 This parameter is only enabled through the FMC_BCR1 register, 216 and don't care through FMC_BCR2..4 registers. 217 This parameter can be a value of @ref FMC_Write_FIFO */ 218 219 uint32_t PageSize; /*!< Specifies the memory page size. 220 This parameter can be a value of @ref FMC_Page_Size */ 221 222 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number 223 This parameter can be a value of @ref FMC_Byte_Lane */ 224 #if defined(FMC_PCSCNTR_CSCOUNT) 225 226 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this 227 NSBank for PSRAM refresh. 228 This parameter can be set to ENABLE or DISABLE */ 229 230 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for 231 synchronous accesses and in HCLK cycles for asynchronous accesses, 232 valid only if MaxChipSelectPulse is ENABLE. 233 This parameter can be a value between Min_Data = 1 and Max_Data = 65535. 234 @note: This parameter is common to all NSBank. */ 235 #endif /* FMC_PCSCNTR_CSCOUNT */ 236 } FMC_NORSRAM_InitTypeDef; 237 238 /** 239 * @brief FMC NORSRAM Timing parameters structure definition 240 */ 241 typedef struct 242 { 243 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 244 the duration of the address setup time. 245 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 246 @note This parameter is not used with synchronous NOR Flash memories. */ 247 248 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 249 the duration of the address hold time. 250 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 251 @note This parameter is not used with synchronous NOR Flash memories. */ 252 253 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 254 the duration of the data setup time. 255 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 256 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 257 NOR Flash memories. */ 258 259 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure 260 the duration of the data hold time. 261 This parameter can be a value between Min_Data = 0 and Max_Data = 3. 262 @note This parameter is used for used in asynchronous accesses. */ 263 264 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 265 the duration of the bus turnaround. 266 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 267 @note This parameter is only used for multiplexed NOR Flash memories. */ 268 269 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 270 HCLK cycles. This parameter can be a value between Min_Data = 2 and 271 Max_Data = 16. 272 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 273 accesses. */ 274 275 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 276 to the memory before getting the first data. 277 The parameter value depends on the memory type as shown below: 278 - It must be set to 0 in case of a CRAM 279 - It is don't care in asynchronous NOR, SRAM or ROM accesses 280 - It may assume a value between Min_Data = 2 and Max_Data = 17 281 in NOR Flash memories with synchronous burst mode enable */ 282 283 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 284 This parameter can be a value of @ref FMC_Access_Mode */ 285 } FMC_NORSRAM_TimingTypeDef; 286 #endif /* FMC_BANK1 */ 287 288 #if defined(FMC_BANK3) 289 /** 290 * @brief FMC NAND Configuration Structure definition 291 */ 292 typedef struct 293 { 294 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 295 This parameter can be a value of @ref FMC_NAND_Bank */ 296 297 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 298 This parameter can be any value of @ref FMC_Wait_feature */ 299 300 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 301 This parameter can be any value of @ref FMC_NAND_Data_Width */ 302 303 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 304 This parameter can be any value of @ref FMC_ECC */ 305 306 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 307 This parameter can be any value of @ref FMC_ECC_Page_Size */ 308 309 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 310 delay between CLE low and RE low. 311 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 312 313 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 314 delay between ALE low and RE low. 315 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 316 } FMC_NAND_InitTypeDef; 317 #endif /* FMC_BANK3 */ 318 319 #if defined(FMC_BANK3) 320 /** 321 * @brief FMC NAND Timing parameters structure definition 322 */ 323 typedef struct 324 { 325 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 326 the command assertion for NAND-Flash read or write access 327 to common/Attribute or I/O memory space (depending on 328 the memory space timing to be configured). 329 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 330 331 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 332 command for NAND-Flash read or write access to 333 common/Attribute or I/O memory space (depending on the 334 memory space timing to be configured). 335 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 336 337 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 338 (and data for write access) after the command de-assertion 339 for NAND-Flash read or write access to common/Attribute 340 or I/O memory space (depending on the memory space timing 341 to be configured). 342 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 343 344 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 345 data bus is kept in HiZ after the start of a NAND-Flash 346 write access to common/Attribute or I/O memory space (depending 347 on the memory space timing to be configured). 348 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 349 } FMC_NAND_PCC_TimingTypeDef; 350 #endif /* FMC_BANK3 */ 351 352 353 /** 354 * @} 355 */ 356 357 /* Exported constants --------------------------------------------------------*/ 358 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 359 * @{ 360 */ 361 #if defined(FMC_BANK1) 362 363 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 364 * @{ 365 */ 366 367 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 368 * @{ 369 */ 370 #define FMC_NORSRAM_BANK1 (0x00000000U) 371 #define FMC_NORSRAM_BANK2 (0x00000002U) 372 #define FMC_NORSRAM_BANK3 (0x00000004U) 373 #define FMC_NORSRAM_BANK4 (0x00000006U) 374 /** 375 * @} 376 */ 377 378 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 379 * @{ 380 */ 381 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) 382 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) 383 /** 384 * @} 385 */ 386 387 /** @defgroup FMC_Memory_Type FMC Memory Type 388 * @{ 389 */ 390 #define FMC_MEMORY_TYPE_SRAM (0x00000000U) 391 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U) 392 #define FMC_MEMORY_TYPE_NOR (0x00000008U) 393 /** 394 * @} 395 */ 396 397 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 398 * @{ 399 */ 400 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) 401 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) 402 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) 403 /** 404 * @} 405 */ 406 407 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 408 * @{ 409 */ 410 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) 411 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) 412 /** 413 * @} 414 */ 415 416 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 417 * @{ 418 */ 419 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) 420 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) 421 /** 422 * @} 423 */ 424 425 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 426 * @{ 427 */ 428 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) 429 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) 430 /** 431 * @} 432 */ 433 434 /** @defgroup FMC_Wait_Timing FMC Wait Timing 435 * @{ 436 */ 437 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) 438 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U) 439 /** 440 * @} 441 */ 442 443 /** @defgroup FMC_Write_Operation FMC Write Operation 444 * @{ 445 */ 446 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U) 447 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U) 448 /** 449 * @} 450 */ 451 452 /** @defgroup FMC_Wait_Signal FMC Wait Signal 453 * @{ 454 */ 455 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) 456 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) 457 /** 458 * @} 459 */ 460 461 /** @defgroup FMC_Extended_Mode FMC Extended Mode 462 * @{ 463 */ 464 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U) 465 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U) 466 /** 467 * @} 468 */ 469 470 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 471 * @{ 472 */ 473 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) 474 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) 475 /** 476 * @} 477 */ 478 479 /** @defgroup FMC_Page_Size FMC Page Size 480 * @{ 481 */ 482 #define FMC_PAGE_SIZE_NONE (0x00000000U) 483 #define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 484 #define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 485 #define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ 486 | FMC_BCRx_CPSIZE_1) 487 #define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 488 /** 489 * @} 490 */ 491 492 /** @defgroup FMC_Write_Burst FMC Write Burst 493 * @{ 494 */ 495 #define FMC_WRITE_BURST_DISABLE (0x00000000U) 496 #define FMC_WRITE_BURST_ENABLE (0x00080000U) 497 /** 498 * @} 499 */ 500 501 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 502 * @{ 503 */ 504 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) 505 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) 506 /** 507 * @} 508 */ 509 510 #if defined(FMC_BCR1_WFDIS) 511 /** @defgroup FMC_Write_FIFO FMC Write FIFO 512 * @{ 513 */ 514 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS 515 #define FMC_WRITE_FIFO_ENABLE (0x00000000U) 516 #endif /* FMC_BCR1_WFDIS */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup FMC_Access_Mode FMC Access Mode 522 * @{ 523 */ 524 #define FMC_ACCESS_MODE_A (0x00000000U) 525 #define FMC_ACCESS_MODE_B (0x10000000U) 526 #define FMC_ACCESS_MODE_C (0x20000000U) 527 #define FMC_ACCESS_MODE_D (0x30000000U) 528 /** 529 * @} 530 */ 531 532 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup 533 * @{ 534 */ 535 #define FMC_NBL_SETUPTIME_0 (0x00000000U) 536 #define FMC_NBL_SETUPTIME_1 (0x00400000U) 537 #define FMC_NBL_SETUPTIME_2 (0x00800000U) 538 #define FMC_NBL_SETUPTIME_3 (0x00C00000U) 539 /** 540 * @} 541 */ 542 543 /** 544 * @} 545 */ 546 #endif /* FMC_BANK1 */ 547 548 #if defined(FMC_BANK3) 549 550 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 551 * @{ 552 */ 553 /** @defgroup FMC_NAND_Bank FMC NAND Bank 554 * @{ 555 */ 556 #define FMC_NAND_BANK3 (0x00000100U) 557 /** 558 * @} 559 */ 560 561 /** @defgroup FMC_Wait_feature FMC Wait feature 562 * @{ 563 */ 564 #define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) 565 #define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) 566 /** 567 * @} 568 */ 569 570 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 571 * @{ 572 */ 573 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) 574 /** 575 * @} 576 */ 577 578 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 579 * @{ 580 */ 581 #define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) 582 #define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) 583 /** 584 * @} 585 */ 586 587 /** @defgroup FMC_ECC FMC ECC 588 * @{ 589 */ 590 #define FMC_NAND_ECC_DISABLE (0x00000000U) 591 #define FMC_NAND_ECC_ENABLE (0x00000040U) 592 /** 593 * @} 594 */ 595 596 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 597 * @{ 598 */ 599 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) 600 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) 601 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) 602 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) 603 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) 604 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 #endif /* FMC_BANK3 */ 613 614 615 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 616 * @{ 617 */ 618 #if defined(FMC_BANK3) 619 #define FMC_IT_RISING_EDGE (0x00000008U) 620 #define FMC_IT_LEVEL (0x00000010U) 621 #define FMC_IT_FALLING_EDGE (0x00000020U) 622 #endif /* FMC_BANK3 */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 628 * @{ 629 */ 630 #if defined(FMC_BANK3) 631 #define FMC_FLAG_RISING_EDGE (0x00000001U) 632 #define FMC_FLAG_LEVEL (0x00000002U) 633 #define FMC_FLAG_FALLING_EDGE (0x00000004U) 634 #define FMC_FLAG_FEMPT (0x00000040U) 635 #endif /* FMC_BANK3 */ 636 /** 637 * @} 638 */ 639 640 /** 641 * @} 642 */ 643 644 /** 645 * @} 646 */ 647 648 /* Private macro -------------------------------------------------------------*/ 649 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 650 * @{ 651 */ 652 #if defined(FMC_BANK1) 653 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 654 * @brief macros to handle NOR device enable/disable and read/write operations 655 * @{ 656 */ 657 658 /** 659 * @brief Enable the NORSRAM device access. 660 * @param __INSTANCE__ FMC_NORSRAM Instance 661 * @param __BANK__ FMC_NORSRAM Bank 662 * @retval None 663 */ 664 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 665 |= FMC_BCRx_MBKEN) 666 667 /** 668 * @brief Disable the NORSRAM device access. 669 * @param __INSTANCE__ FMC_NORSRAM Instance 670 * @param __BANK__ FMC_NORSRAM Bank 671 * @retval None 672 */ 673 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ 674 &= ~FMC_BCRx_MBKEN) 675 676 /** 677 * @} 678 */ 679 #endif /* FMC_BANK1 */ 680 681 #if defined(FMC_BANK3) 682 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 683 * @brief macros to handle NAND device enable/disable 684 * @{ 685 */ 686 687 /** 688 * @brief Enable the NAND device access. 689 * @param __INSTANCE__ FMC_NAND Instance 690 * @retval None 691 */ 692 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 693 694 /** 695 * @brief Disable the NAND device access. 696 * @param __INSTANCE__ FMC_NAND Instance 697 * @param __BANK__ FMC_NAND Bank 698 * @retval None 699 */ 700 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) 701 702 /** 703 * @} 704 */ 705 #endif /* FMC_BANK3 */ 706 707 #if defined(FMC_BANK3) 708 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt 709 * @brief macros to handle NAND interrupts 710 * @{ 711 */ 712 713 /** 714 * @brief Enable the NAND device interrupt. 715 * @param __INSTANCE__ FMC_NAND instance 716 * @param __INTERRUPT__ FMC_NAND interrupt 717 * This parameter can be any combination of the following values: 718 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 719 * @arg FMC_IT_LEVEL: Interrupt level. 720 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 721 * @retval None 722 */ 723 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 724 725 /** 726 * @brief Disable the NAND device interrupt. 727 * @param __INSTANCE__ FMC_NAND Instance 728 * @param __INTERRUPT__ FMC_NAND interrupt 729 * This parameter can be any combination of the following values: 730 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 731 * @arg FMC_IT_LEVEL: Interrupt level. 732 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 733 * @retval None 734 */ 735 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 736 737 /** 738 * @brief Get flag status of the NAND device. 739 * @param __INSTANCE__ FMC_NAND Instance 740 * @param __BANK__ FMC_NAND Bank 741 * @param __FLAG__ FMC_NAND flag 742 * This parameter can be any combination of the following values: 743 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 744 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 745 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 746 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 747 * @retval The state of FLAG (SET or RESET). 748 */ 749 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 750 751 /** 752 * @brief Clear flag status of the NAND device. 753 * @param __INSTANCE__ FMC_NAND Instance 754 * @param __FLAG__ FMC_NAND flag 755 * This parameter can be any combination of the following values: 756 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 757 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 758 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 759 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 760 * @retval None 761 */ 762 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 763 764 /** 765 * @} 766 */ 767 #endif /* FMC_BANK3 */ 768 769 770 /** 771 * @} 772 */ 773 774 /** 775 * @} 776 */ 777 778 /* Private functions ---------------------------------------------------------*/ 779 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 780 * @{ 781 */ 782 783 #if defined(FMC_BANK1) 784 /** @defgroup FMC_LL_NORSRAM NOR SRAM 785 * @{ 786 */ 787 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 788 * @{ 789 */ 790 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, 791 const FMC_NORSRAM_InitTypeDef *Init); 792 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, 793 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 794 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, 795 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, 796 uint32_t ExtendedMode); 797 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, 798 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 799 /** 800 * @} 801 */ 802 803 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 804 * @{ 805 */ 806 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 807 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 808 /** 809 * @} 810 */ 811 /** 812 * @} 813 */ 814 #endif /* FMC_BANK1 */ 815 816 #if defined(FMC_BANK3) 817 /** @defgroup FMC_LL_NAND NAND 818 * @{ 819 */ 820 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 821 * @{ 822 */ 823 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); 824 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, 825 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 826 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, 827 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 828 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 829 /** 830 * @} 831 */ 832 833 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 834 * @{ 835 */ 836 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 837 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 838 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, 839 uint32_t Timeout); 840 /** 841 * @} 842 */ 843 /** 844 * @} 845 */ 846 #endif /* FMC_BANK3 */ 847 848 849 /** 850 * @} 851 */ 852 853 /** 854 * @} 855 */ 856 857 /** 858 * @} 859 */ 860 861 #ifdef __cplusplus 862 } 863 #endif 864 865 #endif /* STM32L4xx_LL_FMC_H */ 866
