1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible memory controller (FMC) includes following memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND memory controller
20
21 [..] The FMC functional block makes the interface with synchronous and asynchronous static
22 memories. Its main purposes are:
23 (+) to translate AHB transactions into the appropriate external device protocol
24 (+) to meet the access time requirements of the external memory devices
25
26 [..] All external memories share the addresses, data and control signals with the controller.
27 Each external device is accessed by means of a unique Chip Select. The FMC performs
28 only one access at a time to an external device.
29 The main features of the FMC controller are the following:
30 (+) Interface with static-memory mapped devices including:
31 (++) Static random access memory (SRAM)
32 (++) Read-only memory (ROM)
33 (++) NOR Flash memory/OneNAND Flash memory
34 (++) PSRAM (4 memory banks)
35 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
36 data
37 (+) Independent Chip Select control for each memory bank
38 (+) Independent configuration for each memory bank
39
40 @endverbatim
41 ******************************************************************************
42 * @attention
43 *
44 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
45 *
46 * Redistribution and use in source and binary forms, with or without modification,
47 * are permitted provided that the following conditions are met:
48 * 1. Redistributions of source code must retain the above copyright notice,
49 * this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright notice,
51 * this list of conditions and the following disclaimer in the documentation
52 * and/or other materials provided with the distribution.
53 * 3. Neither the name of STMicroelectronics nor the names of its contributors
54 * may be used to endorse or promote products derived from this software
55 * without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
58 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
60 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
63 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
64 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 *
68 ******************************************************************************
69 */
70
71 /* Includes ------------------------------------------------------------------*/
72 #include "stm32l4xx_hal.h"
73
74 /** @addtogroup STM32L4xx_HAL_Driver
75 * @{
76 */
77
78 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
79
80 /** @defgroup FMC_LL FMC Low Layer
81 * @brief FMC driver modules
82 * @{
83 */
84
85 /* Private typedef -----------------------------------------------------------*/
86 /* Private define ------------------------------------------------------------*/
87
88 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
89 * @{
90 */
91
92 /* ----------------------- FMC registers bit mask --------------------------- */
93
94 #if defined(FMC_BANK1)
95 /* --- BCR Register ---*/
96 /* BCR register clear mask */
97 #if defined(FMC_BCRx_NBLSET)
98 #if defined(FMC_BCR1_WFDIS)
99 #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
100 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
101 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
102 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
103 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
104 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
105 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
106 FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS |\
107 FMC_BCRx_NBLSET))
108 #else
109 #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
110 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
111 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
112 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
113 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
114 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
115 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
116 FMC_BCR1_CCLKEN | FMC_BCRx_NBLSET))
117 #endif /* FMC_BCR1_WFDIS */
118 #else
119 #if defined(FMC_BCR1_WFDIS)
120 #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
121 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
122 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
123 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
124 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
125 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
126 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
127 FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS))
128 #else
129 #define BCR_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\
130 FMC_BCRx_MTYP | FMC_BCRx_MWID |\
131 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\
132 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\
133 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\
134 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\
135 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\
136 FMC_BCR1_CCLKEN))
137 #endif /* FMC_BCR1_WFDIS */
138 #endif /* FMC_BCRx_NBLSET */
139
140 /* --- BTR Register ---*/
141 /* BTR register clear mask */
142 #if defined(FMC_BTRx_DATAHLD)
143 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
144 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
145 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
146 FMC_BTRx_ACCMOD | FMC_BTRx_DATAHLD))
147 #else
148 #define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\
149 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
150 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\
151 FMC_BTRx_ACCMOD))
152 #endif /* FMC_BTRx_DATAHLD */
153
154 /* --- BWTR Register ---*/
155 /* BWTR register clear mask */
156 #if defined(FMC_BWTRx_DATAHLD)
157 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
158 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
159 FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD))
160 #else
161 #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
162 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\
163 FMC_BWTRx_ACCMOD))
164 #endif /* FMC_BWTRx_DATAHLD */
165 #endif /* FMC_BANK1 */
166 #if defined(FMC_BANK3)
167
168 /* --- PCR Register ---*/
169 /* PCR register clear mask */
170 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
171 FMC_PCR_PTYP | FMC_PCR_PWID | \
172 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
173 FMC_PCR_TAR | FMC_PCR_ECCPS))
174
175 /* --- PMEM Register ---*/
176 /* PMEM register clear mask */
177 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\
178 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ))
179
180 /* --- PATT Register ---*/
181 /* PATT register clear mask */
182 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\
183 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ))
184
185 #endif /* FMC_BANK3 */
186
187 /**
188 * @}
189 */
190
191 /* Private macro -------------------------------------------------------------*/
192 /* Private variables ---------------------------------------------------------*/
193 /* Private function prototypes -----------------------------------------------*/
194 /* Exported functions --------------------------------------------------------*/
195
196 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
197 * @{
198 */
199
200 #if defined(FMC_BANK1)
201
202 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
203 * @brief NORSRAM Controller functions
204 *
205 @verbatim
206 ==============================================================================
207 ##### How to use NORSRAM device driver #####
208 ==============================================================================
209
210 [..]
211 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
212 to run the NORSRAM external devices.
213
214 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
215 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
216 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
217 (+) FMC NORSRAM bank extended timing configuration using the function
218 FMC_NORSRAM_Extended_Timing_Init()
219 (+) FMC NORSRAM bank enable/disable write operation using the functions
220 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
221
222 @endverbatim
223 * @{
224 */
225
226 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
227 * @brief Initialization and Configuration functions
228 *
229 @verbatim
230 ==============================================================================
231 ##### Initialization and de_initialization functions #####
232 ==============================================================================
233 [..]
234 This section provides functions allowing to:
235 (+) Initialize and configure the FMC NORSRAM interface
236 (+) De-initialize the FMC NORSRAM interface
237 (+) Configure the FMC clock and associated GPIOs
238
239 @endverbatim
240 * @{
241 */
242
243 /**
244 * @brief Initialize the FMC_NORSRAM device according to the specified
245 * control parameters in the FMC_NORSRAM_InitTypeDef
246 * @param Device Pointer to NORSRAM device instance
247 * @param Init Pointer to NORSRAM Initialization structure
248 * @retval HAL status
249 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)250 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
251 {
252 uint32_t flashaccess;
253
254 /* Check the parameters */
255 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
256 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
257 assert_param(IS_FMC_MUX(Init->DataAddressMux));
258 assert_param(IS_FMC_MEMORY(Init->MemoryType));
259 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
260 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
261 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
262 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
263 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
264 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
265 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
266 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
267 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
268 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
269 #if defined(FMC_BCR1_WFDIS)
270 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
271 #endif /* FMC_BCR1_WFDIS */
272 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
273 #if defined(FMC_BCRx_NBLSET)
274 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime));
275 #endif /* FMC_BCRx_NBLSET */
276
277 /* Disable NORSRAM Device */
278 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
279
280 /* Set NORSRAM device control parameters */
281 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
282 {
283 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
284 }
285 else
286 {
287 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
288 }
289
290 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (flashaccess |
291 Init->DataAddressMux |
292 Init->MemoryType |
293 Init->MemoryDataWidth |
294 Init->BurstAccessMode |
295 Init->WaitSignalPolarity |
296 Init->WaitSignalActive |
297 Init->WriteOperation |
298 Init->WaitSignal |
299 Init->ExtendedMode |
300 Init->AsynchronousWait |
301 Init->WriteBurst |
302 Init->ContinuousClock |
303 #if defined(FMC_BCR1_WFDIS)
304 Init->WriteFifo |
305 #endif /* FMC_BCR1_WFDIS */
306 #if defined(FMC_BCRx_NBLSET)
307 Init->NBLSetupTime |
308 #endif /* FMC_BCRx_NBLSET */
309 Init->PageSize));
310
311 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
312 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
313 {
314 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
315 }
316
317 #if defined(FMC_BCR1_WFDIS)
318 if (Init->NSBank != FMC_NORSRAM_BANK1)
319 {
320 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
321 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
322 }
323 #endif /* FMC_BCR1_WFDIS */
324
325 return HAL_OK;
326 }
327
328
329 /**
330 * @brief DeInitialize the FMC_NORSRAM peripheral
331 * @param Device Pointer to NORSRAM device instance
332 * @param ExDevice Pointer to NORSRAM extended mode device instance
333 * @param Bank NORSRAM bank number
334 * @retval HAL status
335 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)336 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
337 {
338 /* Check the parameters */
339 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
340 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
341 assert_param(IS_FMC_NORSRAM_BANK(Bank));
342
343 /* Disable the FMC_NORSRAM device */
344 __FMC_NORSRAM_DISABLE(Device, Bank);
345
346 /* De-initialize the FMC_NORSRAM device */
347 /* FMC_NORSRAM_BANK1 */
348 if (Bank == FMC_NORSRAM_BANK1)
349 {
350 Device->BTCR[Bank] = 0x000030DBU;
351 }
352 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
353 else
354 {
355 Device->BTCR[Bank] = 0x000030D2U;
356 }
357
358 Device->BTCR[Bank + 1] = 0x0FFFFFFFU;
359 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
360
361 return HAL_OK;
362 }
363
364
365 /**
366 * @brief Initialize the FMC_NORSRAM Timing according to the specified
367 * parameters in the FMC_NORSRAM_TimingTypeDef
368 * @param Device Pointer to NORSRAM device instance
369 * @param Timing Pointer to NORSRAM Timing structure
370 * @param Bank NORSRAM bank number
371 * @retval HAL status
372 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)373 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
374 {
375 uint32_t tmpr = 0;
376
377 /* Check the parameters */
378 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
379 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
380 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
381 #if defined(FMC_BTRx_DATAHLD)
382 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
383 #endif /* FMC_BTRx_DATAHLD */
384 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
385 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
386 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
387 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
388 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
389 assert_param(IS_FMC_NORSRAM_BANK(Bank));
390
391 /* Set FMC_NORSRAM device timing parameters */
392 MODIFY_REG(Device->BTCR[Bank + 1], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
393 ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
394 ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
395 #if defined(FMC_BTRx_DATAHLD)
396 ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
397 #endif /* FMC_BTRx_DATAHLD */
398 ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
399 (((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos) |
400 (((Timing->DataLatency) - 2) << FMC_BTRx_DATLAT_Pos) |
401 (Timing->AccessMode)));
402
403 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
404 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
405 {
406 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos));
407 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << FMC_BTRx_CLKDIV_Pos);
408 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
409 }
410
411 return HAL_OK;
412 }
413
414 /**
415 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
416 * parameters in the FMC_NORSRAM_TimingTypeDef
417 * @param Device Pointer to NORSRAM device instance
418 * @param Timing Pointer to NORSRAM Timing structure
419 * @param Bank NORSRAM bank number
420 * @param ExtendedMode FMC Extended Mode
421 * This parameter can be one of the following values:
422 * @arg FMC_EXTENDED_MODE_DISABLE
423 * @arg FMC_EXTENDED_MODE_ENABLE
424 * @retval HAL status
425 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)426 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
427 {
428 /* Check the parameters */
429 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
430
431 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
432 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
433 {
434 /* Check the parameters */
435 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
436 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
437 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
438 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
439 #if defined(FMC_BTRx_DATAHLD)
440 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime));
441 #endif /* FMC_BTRx_DATAHLD */
442 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
443 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
444 assert_param(IS_FMC_NORSRAM_BANK(Bank));
445
446 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
447 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
448 ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) |
449 ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) |
450 #if defined(FMC_BTRx_DATAHLD)
451 ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) |
452 #endif /* FMC_BTRx_DATAHLD */
453 Timing->AccessMode |
454 ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos)));
455 }
456 else
457 {
458 Device->BWTR[Bank] = 0x0FFFFFFFU;
459 }
460
461 return HAL_OK;
462 }
463 /**
464 * @}
465 */
466
467 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
468 * @brief management functions
469 *
470 @verbatim
471 ==============================================================================
472 ##### FMC_NORSRAM Control functions #####
473 ==============================================================================
474 [..]
475 This subsection provides a set of functions allowing to control dynamically
476 the FMC NORSRAM interface.
477
478 @endverbatim
479 * @{
480 */
481
482 /**
483 * @brief Enables dynamically FMC_NORSRAM write operation.
484 * @param Device Pointer to NORSRAM device instance
485 * @param Bank NORSRAM bank number
486 * @retval HAL status
487 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)488 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
489 {
490 /* Check the parameters */
491 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
492 assert_param(IS_FMC_NORSRAM_BANK(Bank));
493
494 /* Enable write operation */
495 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
496
497 return HAL_OK;
498 }
499
500 /**
501 * @brief Disables dynamically FMC_NORSRAM write operation.
502 * @param Device Pointer to NORSRAM device instance
503 * @param Bank NORSRAM bank number
504 * @retval HAL status
505 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)506 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
507 {
508 /* Check the parameters */
509 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
510 assert_param(IS_FMC_NORSRAM_BANK(Bank));
511
512 /* Disable write operation */
513 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
514
515 return HAL_OK;
516 }
517
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525 #endif /* FMC_BANK1 */
526
527 #if defined(FMC_BANK3)
528
529 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
530 * @brief NAND Controller functions
531 *
532 @verbatim
533 ==============================================================================
534 ##### How to use NAND device driver #####
535 ==============================================================================
536 [..]
537 This driver contains a set of APIs to interface with the FMC NAND banks in order
538 to run the NAND external devices.
539
540 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
541 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
542 (+) FMC NAND bank common space timing configuration using the function
543 FMC_NAND_CommonSpace_Timing_Init()
544 (+) FMC NAND bank attribute space timing configuration using the function
545 FMC_NAND_AttributeSpace_Timing_Init()
546 (+) FMC NAND bank enable/disable ECC correction feature using the functions
547 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
548 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
549
550 @endverbatim
551 * @{
552 */
553
554 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
555 * @brief Initialization and Configuration functions
556 *
557 @verbatim
558 ==============================================================================
559 ##### Initialization and de_initialization functions #####
560 ==============================================================================
561 [..]
562 This section provides functions allowing to:
563 (+) Initialize and configure the FMC NAND interface
564 (+) De-initialize the FMC NAND interface
565 (+) Configure the FMC clock and associated GPIOs
566
567 @endverbatim
568 * @{
569 */
570
571 /**
572 * @brief Initializes the FMC_NAND device according to the specified
573 * control parameters in the FMC_NAND_HandleTypeDef
574 * @param Device Pointer to NAND device instance
575 * @param Init Pointer to NAND Initialization structure
576 * @retval HAL status
577 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)578 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
579 {
580 /* Check the parameters */
581 assert_param(IS_FMC_NAND_DEVICE(Device));
582 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
583 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
584 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
585 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
586 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
587 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
588 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
589
590 /* NAND bank 3 registers configuration */
591 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
592 FMC_PCR_MEMORY_TYPE_NAND |
593 Init->MemoryDataWidth |
594 Init->EccComputation |
595 Init->ECCPageSize |
596 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
597 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
598
599 return HAL_OK;
600 }
601
602 /**
603 * @brief Initializes the FMC_NAND Common space Timing according to the specified
604 * parameters in the FMC_NAND_PCC_TimingTypeDef
605 * @param Device Pointer to NAND device instance
606 * @param Timing Pointer to NAND timing structure
607 * @param Bank NAND bank number
608 * @retval HAL status
609 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)610 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
611 {
612 /* Check the parameters */
613 assert_param(IS_FMC_NAND_DEVICE(Device));
614 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
615 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
616 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
617 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
618
619 /* Prevent unused argument(s) compilation warning if no assert_param check */
620 UNUSED(Bank);
621
622 /* NAND bank 3 registers configuration */
623 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |
624 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) |
625 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) |
626 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)));
627
628 return HAL_OK;
629 }
630
631 /**
632 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
633 * parameters in the FMC_NAND_PCC_TimingTypeDef
634 * @param Device Pointer to NAND device instance
635 * @param Timing Pointer to NAND timing structure
636 * @param Bank NAND bank number
637 * @retval HAL status
638 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)639 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
640 {
641 /* Check the parameters */
642 assert_param(IS_FMC_NAND_DEVICE(Device));
643 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
644 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
645 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
646 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
647
648 /* Prevent unused argument(s) compilation warning if no assert_param check */
649 UNUSED(Bank);
650
651 /* NAND bank 3 registers configuration */
652 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |
653 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) |
654 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) |
655 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)));
656
657 return HAL_OK;
658 }
659
660 /**
661 * @brief DeInitializes the FMC_NAND device
662 * @param Device Pointer to NAND device instance
663 * @param Bank NAND bank number
664 * @retval HAL status
665 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)666 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
667 {
668 /* Check the parameters */
669 assert_param(IS_FMC_NAND_DEVICE(Device));
670
671 /* Prevent unused argument(s) compilation warning if no assert_param check */
672 UNUSED(Bank);
673
674 /* Disable the NAND Bank */
675 __FMC_NAND_DISABLE(Device);
676
677 /* De-initialize the NAND Bank */
678 /* Set the FMC_NAND_BANK3 registers to their reset values */
679 WRITE_REG(Device->PCR, 0x00000018);
680 WRITE_REG(Device->SR, 0x00000040);
681 WRITE_REG(Device->PMEM, 0xFCFCFCFC);
682 WRITE_REG(Device->PATT, 0xFCFCFCFC);
683
684 return HAL_OK;
685 }
686
687 /**
688 * @}
689 */
690
691 /** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions
692 * @brief management functions
693 *
694 @verbatim
695 ==============================================================================
696 ##### FMC_NAND Control functions #####
697 ==============================================================================
698 [..]
699 This subsection provides a set of functions allowing to control dynamically
700 the FMC NAND interface.
701
702 @endverbatim
703 * @{
704 */
705
706
707 /**
708 * @brief Enables dynamically FMC_NAND ECC feature.
709 * @param Device Pointer to NAND device instance
710 * @param Bank NAND bank number
711 * @retval HAL status
712 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)713 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
714 {
715 /* Check the parameters */
716 assert_param(IS_FMC_NAND_DEVICE(Device));
717
718 /* Prevent unused argument(s) compilation warning if no assert_param check */
719 UNUSED(Bank);
720
721 /* Enable ECC feature */
722 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
723
724 return HAL_OK;
725 }
726
727
728 /**
729 * @brief Disables dynamically FMC_NAND ECC feature.
730 * @param Device Pointer to NAND device instance
731 * @param Bank NAND bank number
732 * @retval HAL status
733 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)734 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
735 {
736 /* Check the parameters */
737 assert_param(IS_FMC_NAND_DEVICE(Device));
738
739 /* Prevent unused argument(s) compilation warning if no assert_param check */
740 UNUSED(Bank);
741
742 /* Disable ECC feature */
743 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
744
745 return HAL_OK;
746 }
747
748 /**
749 * @brief Disables dynamically FMC_NAND ECC feature.
750 * @param Device Pointer to NAND device instance
751 * @param ECCval Pointer to ECC value
752 * @param Bank NAND bank number
753 * @param Timeout Timeout wait value
754 * @retval HAL status
755 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)756 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
757 {
758 uint32_t tickstart = 0;
759
760 /* Check the parameters */
761 assert_param(IS_FMC_NAND_DEVICE(Device));
762
763 /* Prevent unused argument(s) compilation warning if no assert_param check */
764 UNUSED(Bank);
765
766 /* Get tick */
767 tickstart = HAL_GetTick();
768
769 /* Wait until FIFO is empty */
770 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
771 {
772 /* Check for the Timeout */
773 if (Timeout != HAL_MAX_DELAY)
774 {
775 if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
776 {
777 return HAL_TIMEOUT;
778 }
779 }
780 }
781
782 /* Get the ECCR register value */
783 *ECCval = (uint32_t)Device->ECCR;
784
785 return HAL_OK;
786 }
787
788 /**
789 * @}
790 */
791 #endif /* FMC_BANK3 */
792
793
794
795 /**
796 * @}
797 */
798
799 /**
800 * @}
801 */
802
803 #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
804 /**
805 * @}
806 */
807
808 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
809
