1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) MPU API to configure and enable regions
17 (+) API to access to MCU info (CPUID register)
18 (+) API to enable fault handler (SHCSR accesses)
19
20 @endverbatim
21 ******************************************************************************
22 * @attention
23 *
24 * Copyright (c) 2017 STMicroelectronics.
25 * All rights reserved.
26 *
27 * This software is licensed under terms that can be found in the LICENSE file in
28 * the root directory of this software component.
29 * If no LICENSE file comes with this software, it is provided AS-IS.
30 *
31 ******************************************************************************
32 */
33
34 /* Define to prevent recursive inclusion -------------------------------------*/
35 #ifndef STM32L4xx_LL_CORTEX_H
36 #define STM32L4xx_LL_CORTEX_H
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32l4xx.h"
44
45 /** @addtogroup STM32L4xx_LL_Driver
46 * @{
47 */
48
49 /** @defgroup CORTEX_LL CORTEX
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55
56 /* Private constants ---------------------------------------------------------*/
57
58 /* Private macros ------------------------------------------------------------*/
59
60 /* Exported types ------------------------------------------------------------*/
61 /* Exported constants --------------------------------------------------------*/
62 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
63 * @{
64 */
65
66 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
67 * @{
68 */
69 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
70 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
71 /**
72 * @}
73 */
74
75 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
76 * @{
77 */
78 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
79 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
80 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
81 /**
82 * @}
83 */
84
85 #if __MPU_PRESENT
86
87 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
88 * @{
89 */
90 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
91 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
92 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
93 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
94 /**
95 * @}
96 */
97
98 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
99 * @{
100 */
101 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
102 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
103 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
104 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
105 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
106 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
107 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
108 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
109 /**
110 * @}
111 */
112
113 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
114 * @{
115 */
116 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
117 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
118 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
119 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
120 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
144 /**
145 * @}
146 */
147
148 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
149 * @{
150 */
151 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
152 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
153 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
154 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
155 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
156 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
157 /**
158 * @}
159 */
160
161 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
162 * @{
163 */
164 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
165 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
166 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
167 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
168 /**
169 * @}
170 */
171
172 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
173 * @{
174 */
175 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
176 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
177 /**
178 * @}
179 */
180
181 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
182 * @{
183 */
184 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
185 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
186 /**
187 * @}
188 */
189
190 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
191 * @{
192 */
193 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
194 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
195 /**
196 * @}
197 */
198
199 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
200 * @{
201 */
202 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
203 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
204 /**
205 * @}
206 */
207 #endif /* __MPU_PRESENT */
208 /**
209 * @}
210 */
211
212 /* Exported macro ------------------------------------------------------------*/
213
214 /* Exported functions --------------------------------------------------------*/
215 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
216 * @{
217 */
218
219 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
220 * @{
221 */
222
223 /**
224 * @brief This function checks if the Systick counter flag is active or not.
225 * @note It can be used in timeout function on application side.
226 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
227 * @retval State of bit (1 or 0).
228 */
LL_SYSTICK_IsActiveCounterFlag(void)229 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
230 {
231 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
232 }
233
234 /**
235 * @brief Configures the SysTick clock source
236 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
237 * @param Source This parameter can be one of the following values:
238 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
239 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
240 * @retval None
241 */
LL_SYSTICK_SetClkSource(uint32_t Source)242 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
243 {
244 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
245 {
246 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
247 }
248 else
249 {
250 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
251 }
252 }
253
254 /**
255 * @brief Get the SysTick clock source
256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
257 * @retval Returned value can be one of the following values:
258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
260 */
LL_SYSTICK_GetClkSource(void)261 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
262 {
263 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
264 }
265
266 /**
267 * @brief Enable SysTick exception request
268 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
269 * @retval None
270 */
LL_SYSTICK_EnableIT(void)271 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
272 {
273 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
274 }
275
276 /**
277 * @brief Disable SysTick exception request
278 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
279 * @retval None
280 */
LL_SYSTICK_DisableIT(void)281 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
282 {
283 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
284 }
285
286 /**
287 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
289 * @retval State of bit (1 or 0).
290 */
LL_SYSTICK_IsEnabledIT(void)291 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
292 {
293 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
294 }
295
296 /**
297 * @}
298 */
299
300 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
301 * @{
302 */
303
304 /**
305 * @brief Processor uses sleep as its low power mode
306 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
307 * @retval None
308 */
LL_LPM_EnableSleep(void)309 __STATIC_INLINE void LL_LPM_EnableSleep(void)
310 {
311 /* Clear SLEEPDEEP bit of Cortex System Control Register */
312 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
313 }
314
315 /**
316 * @brief Processor uses deep sleep as its low power mode
317 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
318 * @retval None
319 */
LL_LPM_EnableDeepSleep(void)320 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
321 {
322 /* Set SLEEPDEEP bit of Cortex System Control Register */
323 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
324 }
325
326 /**
327 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
328 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
329 * empty main application.
330 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
331 * @retval None
332 */
LL_LPM_EnableSleepOnExit(void)333 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
334 {
335 /* Set SLEEPONEXIT bit of Cortex System Control Register */
336 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
337 }
338
339 /**
340 * @brief Do not sleep when returning to Thread mode.
341 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
342 * @retval None
343 */
LL_LPM_DisableSleepOnExit(void)344 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
345 {
346 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
347 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
348 }
349
350 /**
351 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
352 * processor.
353 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
354 * @retval None
355 */
LL_LPM_EnableEventOnPend(void)356 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
357 {
358 /* Set SEVEONPEND bit of Cortex System Control Register */
359 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
360 }
361
362 /**
363 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
364 * excluded
365 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
366 * @retval None
367 */
LL_LPM_DisableEventOnPend(void)368 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
369 {
370 /* Clear SEVEONPEND bit of Cortex System Control Register */
371 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
372 }
373
374 /**
375 * @}
376 */
377
378 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
379 * @{
380 */
381
382 /**
383 * @brief Enable a fault in System handler control register (SHCSR)
384 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
385 * @param Fault This parameter can be a combination of the following values:
386 * @arg @ref LL_HANDLER_FAULT_USG
387 * @arg @ref LL_HANDLER_FAULT_BUS
388 * @arg @ref LL_HANDLER_FAULT_MEM
389 * @retval None
390 */
LL_HANDLER_EnableFault(uint32_t Fault)391 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
392 {
393 /* Enable the system handler fault */
394 SET_BIT(SCB->SHCSR, Fault);
395 }
396
397 /**
398 * @brief Disable a fault in System handler control register (SHCSR)
399 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
400 * @param Fault This parameter can be a combination of the following values:
401 * @arg @ref LL_HANDLER_FAULT_USG
402 * @arg @ref LL_HANDLER_FAULT_BUS
403 * @arg @ref LL_HANDLER_FAULT_MEM
404 * @retval None
405 */
LL_HANDLER_DisableFault(uint32_t Fault)406 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
407 {
408 /* Disable the system handler fault */
409 CLEAR_BIT(SCB->SHCSR, Fault);
410 }
411
412 /**
413 * @}
414 */
415
416 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
417 * @{
418 */
419
420 /**
421 * @brief Get Implementer code
422 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
423 * @retval Value should be equal to 0x41 for ARM
424 */
LL_CPUID_GetImplementer(void)425 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
426 {
427 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
428 }
429
430 /**
431 * @brief Get Variant number (The r value in the rnpn product revision identifier)
432 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
433 * @retval Value between 0 and 255 (0x0: revision 0)
434 */
LL_CPUID_GetVariant(void)435 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
436 {
437 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
438 }
439
440 /**
441 * @brief Get Constant number
442 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
443 * @retval Value should be equal to 0xF for Cortex-M4 devices
444 */
LL_CPUID_GetConstant(void)445 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
446 {
447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
448 }
449
450 /**
451 * @brief Get Part number
452 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
453 * @retval Value should be equal to 0xC24 for Cortex-M4
454 */
LL_CPUID_GetParNo(void)455 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
456 {
457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
458 }
459
460 /**
461 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
462 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
463 * @retval Value between 0 and 255 (0x1: patch 1)
464 */
LL_CPUID_GetRevision(void)465 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
466 {
467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
468 }
469
470 /**
471 * @}
472 */
473
474 #if __MPU_PRESENT
475 /** @defgroup CORTEX_LL_EF_MPU MPU
476 * @{
477 */
478
479 /**
480 * @brief Enable MPU with input options
481 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
482 * @param Options This parameter can be one of the following values:
483 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
484 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
485 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
486 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
487 * @retval None
488 */
LL_MPU_Enable(uint32_t Options)489 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
490 {
491 /* Enable the MPU*/
492 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
493 /* Ensure MPU settings take effects */
494 __DSB();
495 /* Sequence instruction fetches using update settings */
496 __ISB();
497 }
498
499 /**
500 * @brief Disable MPU
501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
502 * @retval None
503 */
LL_MPU_Disable(void)504 __STATIC_INLINE void LL_MPU_Disable(void)
505 {
506 /* Make sure outstanding transfers are done */
507 __DMB();
508 /* Disable MPU*/
509 WRITE_REG(MPU->CTRL, 0U);
510 }
511
512 /**
513 * @brief Check if MPU is enabled or not
514 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
515 * @retval State of bit (1 or 0).
516 */
LL_MPU_IsEnabled(void)517 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
518 {
519 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
520 }
521
522 /**
523 * @brief Enable a MPU region
524 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
525 * @param Region This parameter can be one of the following values:
526 * @arg @ref LL_MPU_REGION_NUMBER0
527 * @arg @ref LL_MPU_REGION_NUMBER1
528 * @arg @ref LL_MPU_REGION_NUMBER2
529 * @arg @ref LL_MPU_REGION_NUMBER3
530 * @arg @ref LL_MPU_REGION_NUMBER4
531 * @arg @ref LL_MPU_REGION_NUMBER5
532 * @arg @ref LL_MPU_REGION_NUMBER6
533 * @arg @ref LL_MPU_REGION_NUMBER7
534 * @retval None
535 */
LL_MPU_EnableRegion(uint32_t Region)536 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
537 {
538 /* Set Region number */
539 WRITE_REG(MPU->RNR, Region);
540 /* Enable the MPU region */
541 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
542 }
543
544 /**
545 * @brief Configure and enable a region
546 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
547 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
548 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
549 * MPU_RASR XN LL_MPU_ConfigRegion\n
550 * MPU_RASR AP LL_MPU_ConfigRegion\n
551 * MPU_RASR S LL_MPU_ConfigRegion\n
552 * MPU_RASR C LL_MPU_ConfigRegion\n
553 * MPU_RASR B LL_MPU_ConfigRegion\n
554 * MPU_RASR SIZE LL_MPU_ConfigRegion
555 * @param Region This parameter can be one of the following values:
556 * @arg @ref LL_MPU_REGION_NUMBER0
557 * @arg @ref LL_MPU_REGION_NUMBER1
558 * @arg @ref LL_MPU_REGION_NUMBER2
559 * @arg @ref LL_MPU_REGION_NUMBER3
560 * @arg @ref LL_MPU_REGION_NUMBER4
561 * @arg @ref LL_MPU_REGION_NUMBER5
562 * @arg @ref LL_MPU_REGION_NUMBER6
563 * @arg @ref LL_MPU_REGION_NUMBER7
564 * @param Address Value of region base address
565 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
566 * @param Attributes This parameter can be a combination of the following values:
567 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
568 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
569 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
570 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
571 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
572 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
573 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
574 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
575 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
576 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
577 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
578 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
579 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
580 * @retval None
581 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)582 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
583 {
584 /* Set Region number */
585 WRITE_REG(MPU->RNR, Region);
586 /* Set base address */
587 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
588 /* Configure MPU */
589 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
590 }
591
592 /**
593 * @brief Disable a region
594 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
595 * MPU_RASR ENABLE LL_MPU_DisableRegion
596 * @param Region This parameter can be one of the following values:
597 * @arg @ref LL_MPU_REGION_NUMBER0
598 * @arg @ref LL_MPU_REGION_NUMBER1
599 * @arg @ref LL_MPU_REGION_NUMBER2
600 * @arg @ref LL_MPU_REGION_NUMBER3
601 * @arg @ref LL_MPU_REGION_NUMBER4
602 * @arg @ref LL_MPU_REGION_NUMBER5
603 * @arg @ref LL_MPU_REGION_NUMBER6
604 * @arg @ref LL_MPU_REGION_NUMBER7
605 * @retval None
606 */
LL_MPU_DisableRegion(uint32_t Region)607 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
608 {
609 /* Set Region number */
610 WRITE_REG(MPU->RNR, Region);
611 /* Disable the MPU region */
612 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
613 }
614
615 /**
616 * @}
617 */
618
619 #endif /* __MPU_PRESENT */
620 /**
621 * @}
622 */
623
624 /**
625 * @}
626 */
627
628 /**
629 * @}
630 */
631
632 #ifdef __cplusplus
633 }
634 #endif
635
636 #endif /* STM32L4xx_LL_CORTEX_H */
637
638
