1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
27 *
28 * Redistribution and use in source and binary forms, with or without modification,
29 * are permitted provided that the following conditions are met:
30 * 1. Redistributions of source code must retain the above copyright notice,
31 * this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright notice,
33 * this list of conditions and the following disclaimer in the documentation
34 * and/or other materials provided with the distribution.
35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 ******************************************************************************
51 */
52
53 /* Define to prevent recursive inclusion -------------------------------------*/
54 #ifndef STM32L4xx_LL_BUS_H
55 #define STM32L4xx_LL_BUS_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 /* Includes ------------------------------------------------------------------*/
62 #include "stm32l4xx.h"
63
64 /** @addtogroup STM32L4xx_LL_Driver
65 * @{
66 */
67
68 #if defined(RCC)
69
70 /** @defgroup BUS_LL BUS
71 * @{
72 */
73
74 /* Private types -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76
77 /* Private constants ---------------------------------------------------------*/
78
79 /* Private macros ------------------------------------------------------------*/
80
81 /* Exported types ------------------------------------------------------------*/
82 /* Exported constants --------------------------------------------------------*/
83 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
84 * @{
85 */
86
87 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
88 * @{
89 */
90 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
91 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
92 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
93 #if defined(DMAMUX1)
94 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
95 #endif /* DMAMUX1 */
96 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
97 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
98 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
99 #if defined(DMA2D)
100 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
101 #endif /* DMA2D */
102 #if defined(GFXMMU)
103 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
104 #endif /* GFXMMU */
105 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
106 /**
107 * @}
108 */
109
110 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
111 * @{
112 */
113 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
114 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
115 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
116 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
117 #if defined(GPIOD)
118 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
119 #endif /*GPIOD*/
120 #if defined(GPIOE)
121 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
122 #endif /*GPIOE*/
123 #if defined(GPIOF)
124 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
125 #endif /* GPIOF */
126 #if defined(GPIOG)
127 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
128 #endif /* GPIOG */
129 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
130 #if defined(GPIOI)
131 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
132 #endif /* GPIOI */
133 #if defined(USB_OTG_FS)
134 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
135 #endif /* USB_OTG_FS */
136 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
137 #if defined(DCMI)
138 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
139 #endif /* DCMI */
140 #if defined(AES)
141 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
142 #endif /* AES */
143 #if defined(HASH)
144 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
145 #endif /* HASH */
146 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
147 #if defined(OCTOSPIM)
148 #define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
149 #endif /* OCTOSPIM */
150 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
151 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
152 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
153 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
154 #if defined(SRAM3_BASE)
155 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
156 #endif /* SRAM3_BASE */
157 /**
158 * @}
159 */
160
161 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
162 * @{
163 */
164 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
165 #if defined(FMC_Bank1_R)
166 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
167 #endif /* FMC_Bank1_R */
168 #if defined(QUADSPI)
169 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
170 #endif /* QUADSPI */
171 #if defined(OCTOSPI1)
172 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
173 #endif /* OCTOSPI1 */
174 #if defined(OCTOSPI2)
175 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
176 #endif /* OCTOSPI2 */
177 /**
178 * @}
179 */
180
181 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
182 * @{
183 */
184 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
185 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
186 #if defined(TIM3)
187 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
188 #endif /* TIM3 */
189 #if defined(TIM4)
190 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
191 #endif /* TIM4 */
192 #if defined(TIM5)
193 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
194 #endif /* TIM5 */
195 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
196 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
197 #if defined(LCD)
198 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
199 #endif /* LCD */
200 #if defined(RCC_APB1ENR1_RTCAPBEN)
201 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
202 #endif /* RCC_APB1ENR1_RTCAPBEN */
203 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
204 #if defined(SPI2)
205 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
206 #endif /* SPI2 */
207 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
208 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
209 #if defined(USART3)
210 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
211 #endif /* USART3 */
212 #if defined(UART4)
213 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
214 #endif /* UART4 */
215 #if defined(UART5)
216 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
217 #endif /* UART5 */
218 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
219 #if defined(I2C2)
220 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
221 #endif /* I2C2 */
222 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
223 #if defined(CRS)
224 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
225 #endif /* CRS */
226 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
227 #if defined(CAN2)
228 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
229 #endif /* CAN2 */
230 #if defined(USB)
231 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
232 #endif /* USB */
233 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
234 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
235 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
236 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
237 /**
238 * @}
239 */
240
241
242 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
243 * @{
244 */
245 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
246 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
247 #if defined(I2C4)
248 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
249 #endif /* I2C4 */
250 #if defined(SWPMI1)
251 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
252 #endif /* SWPMI1 */
253 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
254 /**
255 * @}
256 */
257
258 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
259 * @{
260 */
261 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
262 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
263 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
264 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
265 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
266 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
267 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
268 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
269 #if defined(TIM8)
270 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
271 #endif /* TIM8 */
272 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
273 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
274 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
275 #if defined(TIM17)
276 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
277 #endif /* TIM17 */
278 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
279 #if defined(SAI2)
280 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
281 #endif /* SAI2 */
282 #if defined(DFSDM1_Channel0)
283 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
284 #endif /* DFSDM1_Channel0 */
285 #if defined(LTDC)
286 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
287 #endif /* LTDC */
288 #if defined(DSI)
289 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
290 #endif /* DSI */
291 /**
292 * @}
293 */
294
295 /** Legacy definitions for compatibility purpose
296 @cond 0
297 */
298 #if defined(DFSDM1_Channel0)
299 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
300 #endif /* DFSDM1_Channel0 */
301 /**
302 @endcond
303 */
304
305 /**
306 * @}
307 */
308
309 /* Exported macro ------------------------------------------------------------*/
310 /* Exported functions --------------------------------------------------------*/
311 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
312 * @{
313 */
314
315 /** @defgroup BUS_LL_EF_AHB1 AHB1
316 * @{
317 */
318
319 /**
320 * @brief Enable AHB1 peripherals clock.
321 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
322 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
323 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
324 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
325 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
326 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
327 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
328 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
329 * @param Periphs This parameter can be a combination of the following values:
330 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
331 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
333 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
334 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
335 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
336 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
337 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
338 *
339 * (*) value not defined in all devices.
340 * @retval None
341 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)342 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
343 {
344 __IO uint32_t tmpreg;
345 SET_BIT(RCC->AHB1ENR, Periphs);
346 /* Delay after an RCC peripheral clock enabling */
347 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
348 (void)tmpreg;
349 }
350
351 /**
352 * @brief Check if AHB1 peripheral clock is enabled or not
353 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
354 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
355 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
356 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
357 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
358 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
359 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
360 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
361 * @param Periphs This parameter can be a combination of the following values:
362 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
363 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
364 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
365 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
366 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
367 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
368 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
370 *
371 * (*) value not defined in all devices.
372 * @retval State of Periphs (1 or 0).
373 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)374 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
375 {
376 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
377 }
378
379 /**
380 * @brief Disable AHB1 peripherals clock.
381 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
382 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
383 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
384 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
385 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
386 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
387 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
388 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
389 * @param Periphs This parameter can be a combination of the following values:
390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
393 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
395 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
396 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
397 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
398 *
399 * (*) value not defined in all devices.
400 * @retval None
401 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)402 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
403 {
404 CLEAR_BIT(RCC->AHB1ENR, Periphs);
405 }
406
407 /**
408 * @brief Force AHB1 peripherals reset.
409 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
410 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
411 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
412 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
413 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
414 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
415 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
416 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
417 * @param Periphs This parameter can be a combination of the following values:
418 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
421 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
422 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
423 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
424 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
425 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
426 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
427 *
428 * (*) value not defined in all devices.
429 * @retval None
430 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)431 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
432 {
433 SET_BIT(RCC->AHB1RSTR, Periphs);
434 }
435
436 /**
437 * @brief Release AHB1 peripherals reset.
438 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
439 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
440 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
441 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
442 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
443 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
444 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
445 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
446 * @param Periphs This parameter can be a combination of the following values:
447 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
448 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
449 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
450 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
451 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
452 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
453 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
454 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
456 *
457 * (*) value not defined in all devices.
458 * @retval None
459 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)460 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
461 {
462 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
463 }
464
465 /**
466 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
467 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
468 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
469 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
470 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
471 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
472 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
473 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
474 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
475 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
476 * @param Periphs This parameter can be a combination of the following values:
477 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
479 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
480 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
481 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
482 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
483 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
484 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
485 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
486 *
487 * (*) value not defined in all devices.
488 * @retval None
489 */
LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)490 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
491 {
492 __IO uint32_t tmpreg;
493 SET_BIT(RCC->AHB1SMENR, Periphs);
494 /* Delay after an RCC peripheral clock enabling */
495 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
496 (void)tmpreg;
497 }
498
499 /**
500 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
501 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
502 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
503 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
504 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
505 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
506 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
507 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
508 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
509 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
510 * @param Periphs This parameter can be a combination of the following values:
511 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
512 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
513 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
514 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
515 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
516 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
517 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC
518 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
519 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
520 *
521 * (*) value not defined in all devices.
522 * @retval None
523 */
LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)524 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
525 {
526 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
527 }
528
529 /**
530 * @}
531 */
532
533 /** @defgroup BUS_LL_EF_AHB2 AHB2
534 * @{
535 */
536
537 /**
538 * @brief Enable AHB2 peripherals clock.
539 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
540 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
541 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
542 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
543 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
544 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
545 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
546 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
547 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
548 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
549 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
550 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
551 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
552 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
553 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
554 * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
555 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
556 * @param Periphs This parameter can be a combination of the following values:
557 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
558 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
559 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
560 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
561 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
562 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
563 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
565 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
566 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
567 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
568 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
569 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
570 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
571 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
572 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
573 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
574 *
575 * (*) value not defined in all devices.
576 * @retval None
577 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)578 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
579 {
580 __IO uint32_t tmpreg;
581 SET_BIT(RCC->AHB2ENR, Periphs);
582 /* Delay after an RCC peripheral clock enabling */
583 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
584 (void)tmpreg;
585 }
586
587 /**
588 * @brief Check if AHB2 peripheral clock is enabled or not
589 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
590 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
591 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
592 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
593 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
594 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
595 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
596 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
597 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
598 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
599 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
600 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
601 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
602 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
603 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
604 * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
605 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
606 * @param Periphs This parameter can be a combination of the following values:
607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
613 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
614 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
615 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
616 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
617 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
618 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
619 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
620 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
621 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
622 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
623 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
624 *
625 * (*) value not defined in all devices.
626 * @retval State of Periphs (1 or 0).
627 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)628 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
629 {
630 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
631 }
632
633 /**
634 * @brief Disable AHB2 peripherals clock.
635 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
636 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
637 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
638 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
639 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
640 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
641 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
642 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
643 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
644 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
645 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
646 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
647 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
648 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
649 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
650 * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
651 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
652 * @param Periphs This parameter can be a combination of the following values:
653 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
654 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
655 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
656 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
657 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
658 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
659 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
660 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
661 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
662 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
663 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
664 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
665 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
666 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
667 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
668 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
669 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
670 *
671 * (*) value not defined in all devices.
672 * @retval None
673 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)674 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
675 {
676 CLEAR_BIT(RCC->AHB2ENR, Periphs);
677 }
678
679 /**
680 * @brief Force AHB2 peripherals reset.
681 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
682 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
683 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
684 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
685 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
686 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
687 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
688 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
689 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
690 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
691 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
692 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
693 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
694 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
695 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
696 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
697 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
698 * @param Periphs This parameter can be a combination of the following values:
699 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
700 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
701 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
702 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
703 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
704 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
705 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
706 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
707 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
708 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
709 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
710 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
711 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
712 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
713 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
714 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
715 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
716 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
717 *
718 * (*) value not defined in all devices.
719 * @retval None
720 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)721 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
722 {
723 SET_BIT(RCC->AHB2RSTR, Periphs);
724 }
725
726 /**
727 * @brief Release AHB2 peripherals reset.
728 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
729 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
730 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
731 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
732 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
733 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
734 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
735 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
736 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
737 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
738 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
739 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
740 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
741 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
742 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
743 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
744 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
745 * @param Periphs This parameter can be a combination of the following values:
746 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
747 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
748 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
749 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
750 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
751 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
752 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
753 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
754 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
755 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
756 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
757 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
758 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
759 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
760 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
761 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
762 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
763 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
764 *
765 * (*) value not defined in all devices.
766 * @retval None
767 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)768 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
769 {
770 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
771 }
772
773 /**
774 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
775 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
776 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
777 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
778 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
779 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
780 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
781 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
782 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
783 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
784 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
785 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
786 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
787 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
788 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
789 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
790 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
791 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
792 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
793 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
794 * @param Periphs This parameter can be a combination of the following values:
795 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
796 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
797 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
798 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
799 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
800 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
801 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
802 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
803 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
804 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
805 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
806 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
807 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
808 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
809 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
810 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
811 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
812 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
813 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
814 *
815 * (*) value not defined in all devices.
816 * @retval None
817 */
LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)818 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
819 {
820 __IO uint32_t tmpreg;
821 SET_BIT(RCC->AHB2SMENR, Periphs);
822 /* Delay after an RCC peripheral clock enabling */
823 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
824 (void)tmpreg;
825 }
826
827 /**
828 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
829 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
830 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
831 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
832 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
833 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
834 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
835 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
836 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
837 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
838 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
839 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
840 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
841 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
842 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
843 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
844 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
845 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
846 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
847 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
848 * @param Periphs This parameter can be a combination of the following values:
849 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
850 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
851 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
852 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
853 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
854 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
855 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
856 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
857 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
858 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
859 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
860 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
861 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC
862 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
863 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
864 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
865 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
866 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
867 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
868 *
869 * (*) value not defined in all devices.
870 * @retval None
871 */
LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)872 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
873 {
874 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
875 }
876
877 /**
878 * @}
879 */
880
881 /** @defgroup BUS_LL_EF_AHB3 AHB3
882 * @{
883 */
884
885 /**
886 * @brief Enable AHB3 peripherals clock.
887 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
888 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
889 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
890 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
891 * @param Periphs This parameter can be a combination of the following values:
892 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
893 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
894 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
895 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
896 *
897 * (*) value not defined in all devices.
898 * @retval None
899 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)900 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
901 {
902 __IO uint32_t tmpreg;
903 SET_BIT(RCC->AHB3ENR, Periphs);
904 /* Delay after an RCC peripheral clock enabling */
905 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
906 (void)tmpreg;
907 }
908
909 /**
910 * @brief Check if AHB3 peripheral clock is enabled or not
911 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
912 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
913 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
914 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
915 * @param Periphs This parameter can be a combination of the following values:
916 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
917 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
918 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
919 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
920 *
921 * (*) value not defined in all devices.
922 * @retval State of Periphs (1 or 0).
923 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)924 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
925 {
926 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
927 }
928
929 /**
930 * @brief Disable AHB3 peripherals clock.
931 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
932 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
933 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
934 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
935 * @param Periphs This parameter can be a combination of the following values:
936 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
937 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
938 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
939 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
940 *
941 * (*) value not defined in all devices.
942 * @retval None
943 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)944 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
945 {
946 CLEAR_BIT(RCC->AHB3ENR, Periphs);
947 }
948
949 /**
950 * @brief Force AHB3 peripherals reset.
951 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
952 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
953 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
954 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
955 * @param Periphs This parameter can be a combination of the following values:
956 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
957 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
958 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
959 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
960 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
961 *
962 * (*) value not defined in all devices.
963 * @retval None
964 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)965 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
966 {
967 SET_BIT(RCC->AHB3RSTR, Periphs);
968 }
969
970 /**
971 * @brief Release AHB3 peripherals reset.
972 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
973 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
974 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
975 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
976 * @param Periphs This parameter can be a combination of the following values:
977 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
978 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
979 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
980 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
981 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
982 *
983 * (*) value not defined in all devices.
984 * @retval None
985 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)986 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
987 {
988 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
989 }
990
991 /**
992 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
993 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
994 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
995 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
996 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
997 * @param Periphs This parameter can be a combination of the following values:
998 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
999 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1000 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
1001 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
1002 *
1003 * (*) value not defined in all devices.
1004 * @retval None
1005 */
LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)1006 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
1007 {
1008 __IO uint32_t tmpreg;
1009 SET_BIT(RCC->AHB3SMENR, Periphs);
1010 /* Delay after an RCC peripheral clock enabling */
1011 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
1012 (void)tmpreg;
1013 }
1014
1015 /**
1016 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
1017 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1018 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1019 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1020 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
1021 * @param Periphs This parameter can be a combination of the following values:
1022 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1023 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1024 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
1025 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
1026 *
1027 * (*) value not defined in all devices.
1028 * @retval None
1029 */
LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)1030 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
1031 {
1032 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
1033 }
1034
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup BUS_LL_EF_APB1 APB1
1040 * @{
1041 */
1042
1043 /**
1044 * @brief Enable APB1 peripherals clock.
1045 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
1046 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
1047 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
1048 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
1049 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
1050 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
1051 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
1052 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
1053 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
1054 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
1055 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
1056 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
1057 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
1058 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
1059 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
1060 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
1061 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
1062 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
1063 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
1064 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
1065 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
1066 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
1067 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
1068 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
1069 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
1070 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
1071 * @param Periphs This parameter can be a combination of the following values:
1072 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1073 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1074 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1075 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1076 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1077 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1078 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1079 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1080 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1081 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1082 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1083 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1084 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1085 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1086 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1087 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1088 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1089 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1090 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1091 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1092 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1093 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1094 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1095 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1096 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1097 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1098 *
1099 * (*) value not defined in all devices.
1100 * @retval None
1101 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1102 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1103 {
1104 __IO uint32_t tmpreg;
1105 SET_BIT(RCC->APB1ENR1, Periphs);
1106 /* Delay after an RCC peripheral clock enabling */
1107 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
1108 (void)tmpreg;
1109 }
1110
1111 /**
1112 * @brief Enable APB1 peripherals clock.
1113 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
1114 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
1115 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
1116 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
1117 * @param Periphs This parameter can be a combination of the following values:
1118 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1119 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1120 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1121 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1122 *
1123 * (*) value not defined in all devices.
1124 * @retval None
1125 */
LL_APB1_GRP2_EnableClock(uint32_t Periphs)1126 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
1127 {
1128 __IO uint32_t tmpreg;
1129 SET_BIT(RCC->APB1ENR2, Periphs);
1130 /* Delay after an RCC peripheral clock enabling */
1131 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
1132 (void)tmpreg;
1133 }
1134
1135 /**
1136 * @brief Check if APB1 peripheral clock is enabled or not
1137 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1138 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1139 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1140 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1141 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1142 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1143 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
1144 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
1145 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1146 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1147 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1148 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
1149 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
1150 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
1151 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
1152 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1153 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1154 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1155 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
1156 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1157 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
1158 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1159 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
1160 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
1161 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
1162 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
1163 * @param Periphs This parameter can be a combination of the following values:
1164 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1165 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1167 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1169 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1170 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1171 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1172 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1173 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1174 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1175 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1176 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1177 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1178 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1179 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1180 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1181 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1182 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1183 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1184 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1185 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1186 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1187 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1188 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1189 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1190 *
1191 * (*) value not defined in all devices.
1192 * @retval State of Periphs (1 or 0).
1193 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1194 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1195 {
1196 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1197 }
1198
1199 /**
1200 * @brief Check if APB1 peripheral clock is enabled or not
1201 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1202 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1203 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
1204 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
1205 * @param Periphs This parameter can be a combination of the following values:
1206 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1207 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1208 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1209 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1210 *
1211 * (*) value not defined in all devices.
1212 * @retval State of Periphs (1 or 0).
1213 */
LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)1214 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1215 {
1216 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1217 }
1218
1219 /**
1220 * @brief Disable APB1 peripherals clock.
1221 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1222 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1223 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1224 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1225 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1226 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1227 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
1228 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1229 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1230 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1231 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1232 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1233 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1234 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1235 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1236 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1237 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1238 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1239 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1240 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
1241 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
1242 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
1243 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1244 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
1245 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
1246 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1247 * @param Periphs This parameter can be a combination of the following values:
1248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1249 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1250 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1251 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1254 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1255 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1257 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1258 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1259 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1260 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1261 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1262 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1263 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1264 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1265 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1266 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1267 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1268 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1269 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1270 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1271 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1272 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1273 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1274 *
1275 * (*) value not defined in all devices.
1276 * @retval None
1277 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1278 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1279 {
1280 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1281 }
1282
1283 /**
1284 * @brief Disable APB1 peripherals clock.
1285 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1286 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1287 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
1288 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
1289 * @param Periphs This parameter can be a combination of the following values:
1290 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1291 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1292 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1293 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1294 *
1295 * (*) value not defined in all devices.
1296 * @retval None
1297 */
LL_APB1_GRP2_DisableClock(uint32_t Periphs)1298 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1299 {
1300 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1301 }
1302
1303 /**
1304 * @brief Force APB1 peripherals reset.
1305 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1306 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1307 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1308 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1309 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1310 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1311 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
1312 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1313 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1314 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1315 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1316 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1317 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1318 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1319 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1320 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1321 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1322 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
1323 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
1324 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
1325 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1326 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
1327 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
1328 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1329 * @param Periphs This parameter can be a combination of the following values:
1330 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1331 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1332 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1333 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1334 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1337 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1338 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1339 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1340 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1341 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1342 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1343 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1344 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1345 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1346 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1347 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1348 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1349 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1350 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1351 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1352 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1353 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1354 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1355 *
1356 * (*) value not defined in all devices.
1357 * @retval None
1358 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1359 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1360 {
1361 SET_BIT(RCC->APB1RSTR1, Periphs);
1362 }
1363
1364 /**
1365 * @brief Force APB1 peripherals reset.
1366 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1367 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1368 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
1369 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
1370 * @param Periphs This parameter can be a combination of the following values:
1371 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1372 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1373 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1374 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1375 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1376 *
1377 * (*) value not defined in all devices.
1378 * @retval None
1379 */
LL_APB1_GRP2_ForceReset(uint32_t Periphs)1380 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1381 {
1382 SET_BIT(RCC->APB1RSTR2, Periphs);
1383 }
1384
1385 /**
1386 * @brief Release APB1 peripherals reset.
1387 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1388 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1389 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1390 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1391 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1392 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1393 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
1394 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1395 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1396 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1397 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1398 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1399 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1400 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1401 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1402 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1403 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1404 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
1405 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
1406 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
1407 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1408 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
1409 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
1410 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1411 * @param Periphs This parameter can be a combination of the following values:
1412 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
1413 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1414 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1415 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1416 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1417 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1418 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1419 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1420 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1421 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1422 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1423 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1424 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1425 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1426 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1427 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1428 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1429 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1430 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1431 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1432 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1433 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1434 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1435 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1436 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1437 *
1438 * (*) value not defined in all devices.
1439 * @retval None
1440 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1441 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1442 {
1443 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1444 }
1445
1446 /**
1447 * @brief Release APB1 peripherals reset.
1448 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1449 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1450 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
1451 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
1452 * @param Periphs This parameter can be a combination of the following values:
1453 * @arg @ref LL_APB1_GRP2_PERIPH_ALL
1454 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1455 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1456 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1457 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1458 *
1459 * (*) value not defined in all devices.
1460 * @retval None
1461 */
LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)1462 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1463 {
1464 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1465 }
1466
1467 /**
1468 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1469 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1470 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1471 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1472 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1473 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1474 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1475 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1476 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1477 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1478 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1479 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1480 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1481 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1482 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1483 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1484 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1485 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1486 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1487 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1488 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1489 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1490 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1491 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1492 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1493 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1494 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1495 * @param Periphs This parameter can be a combination of the following values:
1496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1499 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1500 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1501 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1502 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1503 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1504 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1505 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1506 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1507 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1508 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1509 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1510 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1511 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1512 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1513 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1514 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1515 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1516 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1517 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1518 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1519 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1520 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1521 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1522 *
1523 * (*) value not defined in all devices.
1524 * @retval None
1525 */
LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)1526 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1527 {
1528 __IO uint32_t tmpreg;
1529 SET_BIT(RCC->APB1SMENR1, Periphs);
1530 /* Delay after an RCC peripheral clock enabling */
1531 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1532 (void)tmpreg;
1533 }
1534
1535 /**
1536 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1537 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1538 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1539 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1540 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
1541 * @param Periphs This parameter can be a combination of the following values:
1542 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1543 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1544 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1545 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1546 *
1547 * (*) value not defined in all devices.
1548 * @retval None
1549 */
LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)1550 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1551 {
1552 __IO uint32_t tmpreg;
1553 SET_BIT(RCC->APB1SMENR2, Periphs);
1554 /* Delay after an RCC peripheral clock enabling */
1555 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1556 (void)tmpreg;
1557 }
1558
1559 /**
1560 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1561 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1562 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1563 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1564 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1565 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1566 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1567 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1568 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1569 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1570 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1571 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1572 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1573 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1574 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1575 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1576 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1577 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1578 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1579 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1580 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1581 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1582 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1583 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1584 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1585 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1586 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1587 * @param Periphs This parameter can be a combination of the following values:
1588 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1589 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1590 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1591 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1592 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1593 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1594 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
1595 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1596 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1597 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1598 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1599 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1600 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1601 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1602 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1603 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1604 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
1605 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1606 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
1607 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1608 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1609 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
1610 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1611 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1612 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
1613 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1614 *
1615 * (*) value not defined in all devices.
1616 * @retval None
1617 */
LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)1618 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1619 {
1620 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1621 }
1622
1623 /**
1624 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1625 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1626 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1627 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1628 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
1629 * @param Periphs This parameter can be a combination of the following values:
1630 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1631 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1632 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
1633 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
1634 *
1635 * (*) value not defined in all devices.
1636 * @retval None
1637 */
LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)1638 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1639 {
1640 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1641 }
1642
1643 /**
1644 * @}
1645 */
1646
1647 /** @defgroup BUS_LL_EF_APB2 APB2
1648 * @{
1649 */
1650
1651 /**
1652 * @brief Enable APB2 peripherals clock.
1653 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1654 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
1655 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1656 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1657 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1658 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1659 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1660 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1661 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1662 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1663 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1664 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1665 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1666 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1667 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock
1668 * @param Periphs This parameter can be a combination of the following values:
1669 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1670 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1671 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1672 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1673 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1674 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1675 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1677 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1678 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1679 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1680 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1681 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1682 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1683 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1684 *
1685 * (*) value not defined in all devices.
1686 * @retval None
1687 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1688 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1689 {
1690 __IO uint32_t tmpreg;
1691 SET_BIT(RCC->APB2ENR, Periphs);
1692 /* Delay after an RCC peripheral clock enabling */
1693 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1694 (void)tmpreg;
1695 }
1696
1697 /**
1698 * @brief Check if APB2 peripheral clock is enabled or not
1699 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1700 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
1701 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1702 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1703 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1704 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1705 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1706 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1707 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1708 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1709 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1710 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1711 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1712 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1713 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
1714 * @param Periphs This parameter can be a combination of the following values:
1715 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1716 * @arg @ref LL_APB2_GRP1_PERIPH_FW
1717 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1718 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1719 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1720 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1721 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1722 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1723 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1724 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1725 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1726 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1727 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1728 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1729 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1730 *
1731 * (*) value not defined in all devices.
1732 * @retval State of Periphs (1 or 0).
1733 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1734 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1735 {
1736 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1737 }
1738
1739 /**
1740 * @brief Disable APB2 peripherals clock.
1741 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1742 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1743 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1744 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1745 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1746 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1747 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1748 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1749 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1750 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1751 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1752 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1753 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1754 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock
1755 * @param Periphs This parameter can be a combination of the following values:
1756 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1757 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1759 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1761 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1762 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1763 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1764 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1766 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1767 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1768 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1769 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1770 *
1771 * (*) value not defined in all devices.
1772 * @retval None
1773 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1774 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1775 {
1776 CLEAR_BIT(RCC->APB2ENR, Periphs);
1777 }
1778
1779 /**
1780 * @brief Force APB2 peripherals reset.
1781 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1782 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1783 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1784 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1785 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1786 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1787 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1788 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1789 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1790 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1791 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1792 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1793 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1794 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
1795 * @param Periphs This parameter can be a combination of the following values:
1796 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1797 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1798 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1799 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1800 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1801 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1802 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1803 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1804 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1806 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1807 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1808 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1809 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1810 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1811 *
1812 * (*) value not defined in all devices.
1813 * @retval None
1814 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1815 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1816 {
1817 SET_BIT(RCC->APB2RSTR, Periphs);
1818 }
1819
1820 /**
1821 * @brief Release APB2 peripherals reset.
1822 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1823 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1824 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1825 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1826 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1827 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1828 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
1829 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
1830 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
1831 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1832 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1833 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1834 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1835 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
1836 * @param Periphs This parameter can be a combination of the following values:
1837 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1838 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1839 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1840 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1841 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1842 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1843 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1844 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1845 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1846 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1847 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1848 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1849 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1850 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1851 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1852 *
1853 * (*) value not defined in all devices.
1854 * @retval None
1855 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1856 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1857 {
1858 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1859 }
1860
1861 /**
1862 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1863 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1864 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1865 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1866 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1867 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1868 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1869 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1870 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1871 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1872 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1873 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1874 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1875 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1876 * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
1877 * @param Periphs This parameter can be a combination of the following values:
1878 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1879 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1880 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1881 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1883 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1887 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1888 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1889 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1890 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1891 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1892 *
1893 * (*) value not defined in all devices.
1894 * @retval None
1895 */
LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)1896 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1897 {
1898 __IO uint32_t tmpreg;
1899 SET_BIT(RCC->APB2SMENR, Periphs);
1900 /* Delay after an RCC peripheral clock enabling */
1901 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1902 (void)tmpreg;
1903 }
1904
1905 /**
1906 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1907 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1908 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1909 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1910 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1911 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1912 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1913 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1914 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1915 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1916 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1917 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1918 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1919 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1920 * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
1921 * @param Periphs This parameter can be a combination of the following values:
1922 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1923 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1924 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1925 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1926 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1927 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1928 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1929 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1930 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
1931 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1932 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1933 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1934 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1935 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1936 *
1937 * (*) value not defined in all devices.
1938 * @retval None
1939 */
LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)1940 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1941 {
1942 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1943 }
1944
1945 /**
1946 * @}
1947 */
1948
1949
1950 /**
1951 * @}
1952 */
1953
1954 /**
1955 * @}
1956 */
1957
1958 #endif /* defined(RCC) */
1959
1960 /**
1961 * @}
1962 */
1963
1964 #ifdef __cplusplus
1965 }
1966 #endif
1967
1968 #endif /* STM32L4xx_LL_BUS_H */
1969
1970 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1971
