1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32L4xx_LL_ADC_H
38 #define __STM32L4xx_LL_ADC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32l4xx.h"
46
47 /** @addtogroup STM32L4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
52
53 /** @defgroup ADC_LL ADC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
62 * @{
63 */
64
65 /* Internal mask for ADC group regular sequencer: */
66 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
67 /* - sequencer register offset */
68 /* - sequencer rank bits position into the selected register */
69
70 /* Internal register offset for ADC group regular sequencer configuration */
71 /* (offset placed into a spare area of literal definition) */
72 #define ADC_SQR1_REGOFFSET (0x00000000UL)
73 #define ADC_SQR2_REGOFFSET (0x00000100UL)
74 #define ADC_SQR3_REGOFFSET (0x00000200UL)
75 #define ADC_SQR4_REGOFFSET (0x00000300UL)
76
77 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
78 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
79 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
80
81 /* Definition of ADC group regular sequencer bits information to be inserted */
82 /* into ADC group regular sequencer ranks literals definition. */
83 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */
84 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */
85 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */
86 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */
87 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */
88 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */
89 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */
90 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */
91 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */
92 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */
93 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */
94 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */
95 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */
96 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */
97 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */
98 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */
99
100
101
102 /* Internal mask for ADC group injected sequencer: */
103 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
104 /* - data register offset */
105 /* - sequencer rank bits position into the selected register */
106
107 /* Internal register offset for ADC group injected data register */
108 /* (offset placed into a spare area of literal definition) */
109 #define ADC_JDR1_REGOFFSET (0x00000000UL)
110 #define ADC_JDR2_REGOFFSET (0x00000100UL)
111 #define ADC_JDR3_REGOFFSET (0x00000200UL)
112 #define ADC_JDR4_REGOFFSET (0x00000300UL)
113
114 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
115 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
116 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
117
118 /* Definition of ADC group injected sequencer bits information to be inserted */
119 /* into ADC group injected sequencer ranks literals definition. */
120 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ1" position in register */
121 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ2" position in register */
122 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ3" position in register */
123 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Value equivalent to bitfield "ADC_JSQR_JSQ4" position in register */
124
125
126
127 /* Internal mask for ADC group regular trigger: */
128 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
129 /* - regular trigger source */
130 /* - regular trigger edge */
131 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
132
133 /* Mask containing trigger source masks for each of possible */
134 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
135 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
136 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
137 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
138 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
139 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
140
141 /* Mask containing trigger edge masks for each of possible */
142 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
143 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
144 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
145 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
146 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
147 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
148
149 /* Definition of ADC group regular trigger bits information. */
150 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */
151 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */
152
153
154
155 /* Internal mask for ADC group injected trigger: */
156 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
157 /* - injected trigger source */
158 /* - injected trigger edge */
159 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
160
161 /* Mask containing trigger source masks for each of possible */
162 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
163 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
164 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
165 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
166 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
167 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
168
169 /* Mask containing trigger edge masks for each of possible */
170 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
171 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
172 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
173 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
174 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
175 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
176
177 /* Definition of ADC group injected trigger bits information. */
178 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */
179 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */
180
181
182
183
184
185
186 /* Internal mask for ADC channel: */
187 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
188 /* - channel identifier defined by number */
189 /* - channel identifier defined by bitfield */
190 /* - channel differentiation between external channels (connected to */
191 /* GPIO pins) and internal channels (connected to internal paths) */
192 /* - channel sampling time defined by SMPRx register offset */
193 /* and SMPx bits positions into SMPRx register */
194 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
195 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
196 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
197 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
198 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
199 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
200
201 /* Channel differentiation between external and internal channels */
202 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
203 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
204 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
205
206 /* Internal register offset for ADC channel sampling time configuration */
207 /* (offset placed into a spare area of literal definition) */
208 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
209 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
210 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
211 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
212
213 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
214 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
215
216 /* Definition of channels ID number information to be inserted into */
217 /* channels literals definition. */
218 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
219 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
221 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
222 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
223 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
224 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
225 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
226 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
227 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
228 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
229 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
230 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
231 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
232 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
233 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
234 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
235 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
236 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
237
238 /* Definition of channels ID bitfield information to be inserted into */
239 /* channels literals definition. */
240 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
241 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
242 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
243 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
244 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
245 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
246 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
247 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
248 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
249 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
250 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
251 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
252 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
253 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
254 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
255 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
256 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
257 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
258 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
259
260 /* Definition of channels sampling time information to be inserted into */
261 /* channels literals definition. */
262 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
263 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
264 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
265 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
266 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
267 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
268 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
269 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
270 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
271 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
272 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
273 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
274 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
275 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
276 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
277 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
278 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
279 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
280 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
281
282
283 /* Internal mask for ADC mode single or differential ended: */
284 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
285 /* the relevant bits for: */
286 /* (concatenation of multiple bits used in different registers) */
287 /* - ADC calibration: calibration start, calibration factor get or set */
288 /* - ADC channels: set each ADC channel ending mode */
289 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
290 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
291 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
292 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
293 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
294 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
295 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
296
297 /* Internal mask for ADC analog watchdog: */
298 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
299 /* (concatenation of multiple bits used in different analog watchdogs, */
300 /* (feature of several watchdogs not available on all STM32 families)). */
301 /* - analog watchdog 1: monitored channel defined by number, */
302 /* selection of ADC group (ADC groups regular and-or injected). */
303 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
304 /* selection on groups. */
305
306 /* Internal register offset for ADC analog watchdog channel configuration */
307 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
308 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
309 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
310
311 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
312 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
313 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
314 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
315
316 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
317
318 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
319 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
320 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
321
322 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
323
324 /* Internal register offset for ADC analog watchdog threshold configuration */
325 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
326 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
327 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
328 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
329 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
330 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
331 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
332 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
333
334 /* Internal mask for ADC offset: */
335 /* Internal register offset for ADC offset number configuration */
336 #define ADC_OFR1_REGOFFSET (0x00000000UL)
337 #define ADC_OFR2_REGOFFSET (0x00000001UL)
338 #define ADC_OFR3_REGOFFSET (0x00000002UL)
339 #define ADC_OFR4_REGOFFSET (0x00000003UL)
340 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
341
342
343 /* ADC registers bits positions */
344 #define ADC_CFGR_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR_RES" position in register */
345 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1SGL" position in register */
346 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
347 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
348 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
349
350
351 /* ADC registers bits groups */
352 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
353
354
355 /* ADC internal channels related definitions */
356 /* Internal voltage reference VrefInt */
357 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
358 #define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
359 /* Temperature sensor */
360 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
361 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature defined by TEMPSENSOR_CAL2_TEMP (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
362 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
363 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
364 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
365 #else
366 #define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
367 #endif
368 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
369
370
371 /**
372 * @}
373 */
374
375
376 /* Private macros ------------------------------------------------------------*/
377 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
378 * @{
379 */
380
381 /**
382 * @brief Driver macro reserved for internal use: set a pointer to
383 * a register from a register basis from which an offset
384 * is applied.
385 * @param __REG__ Register basis from which the offset is applied.
386 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
387 * @retval Pointer to register address
388 */
389 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
390 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
391
392 /**
393 * @}
394 */
395
396
397 /* Exported types ------------------------------------------------------------*/
398 #if defined(USE_FULL_LL_DRIVER)
399 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
400 * @{
401 */
402
403 /**
404 * @brief Structure definition of some features of ADC common parameters
405 * and multimode
406 * (all ADC instances belonging to the same ADC common instance).
407 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
408 * is conditioned to ADC instances state (all ADC instances
409 * sharing the same ADC common instance):
410 * All ADC instances sharing the same ADC common instance must be
411 * disabled.
412 */
413 typedef struct
414 {
415 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
416 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
417 @note On this STM32 serie, if ADC group injected is used, some
418 clock ratio constraints between ADC clock and AHB clock
419 must be respected. Refer to reference manual.
420
421 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
422
423 #if defined(ADC_MULTIMODE_SUPPORT)
424 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
425 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
426
427 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
428
429 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
430 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
431
432 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
433
434 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
435 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
436
437 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
438 #endif /* ADC_MULTIMODE_SUPPORT */
439
440 } LL_ADC_CommonInitTypeDef;
441
442 /**
443 * @brief Structure definition of some features of ADC instance.
444 * @note These parameters have an impact on ADC scope: ADC instance.
445 * Affects both group regular and group injected (availability
446 * of ADC group injected depends on STM32 families).
447 * Refer to corresponding unitary functions into
448 * @ref ADC_LL_EF_Configuration_ADC_Instance .
449 * @note The setting of these parameters by function @ref LL_ADC_Init()
450 * is conditioned to ADC state:
451 * ADC instance must be disabled.
452 * This condition is applied to all ADC features, for efficiency
453 * and compatibility over all STM32 families. However, the different
454 * features can be set under different ADC state conditions
455 * (setting possible with ADC enabled without conversion on going,
456 * ADC enabled with conversion on going, ...)
457 * Each feature can be updated afterwards with a unitary function
458 * and potentially with ADC in a different state than disabled,
459 * refer to description of each function for setting
460 * conditioned to ADC state.
461 */
462 typedef struct
463 {
464 uint32_t Resolution; /*!< Set ADC resolution.
465 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
466
467 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
468
469 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
470 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
471
472 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
473
474 uint32_t LowPowerMode; /*!< Set ADC low power mode.
475 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
476
477 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
478
479 } LL_ADC_InitTypeDef;
480
481 /**
482 * @brief Structure definition of some features of ADC group regular.
483 * @note These parameters have an impact on ADC scope: ADC group regular.
484 * Refer to corresponding unitary functions into
485 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
486 * (functions with prefix "REG").
487 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
488 * is conditioned to ADC state:
489 * ADC instance must be disabled.
490 * This condition is applied to all ADC features, for efficiency
491 * and compatibility over all STM32 families. However, the different
492 * features can be set under different ADC state conditions
493 * (setting possible with ADC enabled without conversion on going,
494 * ADC enabled with conversion on going, ...)
495 * Each feature can be updated afterwards with a unitary function
496 * and potentially with ADC in a different state than disabled,
497 * refer to description of each function for setting
498 * conditioned to ADC state.
499 */
500 typedef struct
501 {
502 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
503 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
504 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
505 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
506 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
507
508 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
509
510 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
511 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
512
513 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
514
515 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
516 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
517 @note This parameter has an effect only if group regular sequencer is enabled
518 (scan length of 2 ranks or more).
519
520 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
521
522 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
523 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
524 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
525
526 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
527
528 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
529 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
530
531 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
532
533 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
534 data preserved or overwritten.
535 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
536
537 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
538
539 } LL_ADC_REG_InitTypeDef;
540
541 /**
542 * @brief Structure definition of some features of ADC group injected.
543 * @note These parameters have an impact on ADC scope: ADC group injected.
544 * Refer to corresponding unitary functions into
545 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
546 * (functions with prefix "INJ").
547 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
548 * is conditioned to ADC state:
549 * ADC instance must be disabled.
550 * This condition is applied to all ADC features, for efficiency
551 * and compatibility over all STM32 families. However, the different
552 * features can be set under different ADC state conditions
553 * (setting possible with ADC enabled without conversion on going,
554 * ADC enabled with conversion on going, ...)
555 * Each feature can be updated afterwards with a unitary function
556 * and potentially with ADC in a different state than disabled,
557 * refer to description of each function for setting
558 * conditioned to ADC state.
559 */
560 typedef struct
561 {
562 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
563 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
564 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
565 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
566 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
567
568 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
569
570 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
571 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
572
573 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
574
575 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
576 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
577 @note This parameter has an effect only if group injected sequencer is enabled
578 (scan length of 2 ranks or more).
579
580 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
581
582 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
583 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
584 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
585
586 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
587
588 } LL_ADC_INJ_InitTypeDef;
589
590 /**
591 * @}
592 */
593 #endif /* USE_FULL_LL_DRIVER */
594
595 /* Exported constants --------------------------------------------------------*/
596 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
597 * @{
598 */
599
600 /** @defgroup ADC_LL_EC_FLAG ADC flags
601 * @brief Flags defines which can be used with LL_ADC_ReadReg function
602 * @{
603 */
604 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
605 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
606 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
607 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
608 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
609 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
610 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
611 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
612 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
613 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
614 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
615 #if defined(ADC_MULTIMODE_SUPPORT)
616 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
617 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
618 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
619 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
620 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
621 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
622 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
623 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
624 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
625 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
626 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
627 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
628 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
629 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
630 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
631 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
632 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
633 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
634 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
635 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
636 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
637 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
638 #endif
639 /**
640 * @}
641 */
642
643 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
644 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
645 * @{
646 */
647 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
648 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
649 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
650 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
651 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
652 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
653 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
654 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
655 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
656 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
657 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
658 /**
659 * @}
660 */
661
662 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
663 * @{
664 */
665 /* List of ADC registers intended to be used (most commonly) with */
666 /* DMA transfer. */
667 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
668 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
669 #if defined(ADC_MULTIMODE_SUPPORT)
670 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
671 #endif
672 /**
673 * @}
674 */
675
676 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
677 * @{
678 */
679 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
680 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
681 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
682 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
683 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
684 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
685 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
686 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
687 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
688 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
689 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
690 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
691 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
692 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
693 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
694 /**
695 * @}
696 */
697
698 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
699 * @{
700 */
701 /* Note: Other measurement paths to internal channels may be available */
702 /* (connections to other peripherals). */
703 /* If they are not listed below, they do not require any specific */
704 /* path enable. In this case, Access to measurement path is done */
705 /* only by selecting the corresponding ADC internal channel. */
706 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
707 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
708 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
709 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
710 /**
711 * @}
712 */
713
714 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
715 * @{
716 */
717 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
718 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
719 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
720 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
721 /**
722 * @}
723 */
724
725 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
726 * @{
727 */
728 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
729 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
730 /**
731 * @}
732 */
733
734 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
735 * @{
736 */
737 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
738 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
739 /**
740 * @}
741 */
742
743 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
744 * @{
745 */
746 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
747 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
748 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
749 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
750 /**
751 * @}
752 */
753
754 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
755 * @{
756 */
757 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
758 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
759 /**
760 * @}
761 */
762
763 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
764 * @{
765 */
766 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
767 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
768 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
769 /**
770 * @}
771 */
772
773 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
774 * @{
775 */
776 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
777 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
778 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
779 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
780 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
781 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
782 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
783 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
784 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
785 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
786 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
787 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
788 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
789 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
790 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
791 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
792 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
793 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
794 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
795 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */
796 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
797 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */
798 #if defined(ADC1) && !defined(ADC2)
799 #define LL_ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
800 #define LL_ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */
801 #elif defined(ADC2)
802 #define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
803 #define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
804 #if defined(ADC3)
805 #define LL_ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */
806 #define LL_ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */
807 #endif
808 #endif
809 /**
810 * @}
811 */
812
813 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
814 * @{
815 */
816 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
817 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
818 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
819 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
820 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
821 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
822 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
823 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
824 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
825 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
826 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
827 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
828 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
829 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
830 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
831 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
832 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
833 /**
834 * @}
835 */
836
837 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
838 * @{
839 */
840 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
841 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
842 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
843 /**
844 * @}
845 */
846
847 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
848 * @{
849 */
850 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
851 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
852 /**
853 * @}
854 */
855
856 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
857 * @{
858 */
859 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
860 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
861 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
862 /**
863 * @}
864 */
865
866 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
867 /** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
868 * @{
869 */
870 #define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
871 #define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
872 /**
873 * @}
874 */
875 #endif
876
877 #if defined(ADC_SMPR1_SMPPLUS)
878 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
879 * @{
880 */
881 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
882 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
883 /**
884 * @}
885 */
886 #endif
887
888 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
889 * @{
890 */
891 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
892 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
893 /**
894 * @}
895 */
896
897 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
898 * @{
899 */
900 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
901 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
902 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
903 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
904 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
905 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
906 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
907 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
908 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
909 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
910 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
911 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
912 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
913 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
914 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
915 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
916 /**
917 * @}
918 */
919
920 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
921 * @{
922 */
923 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
924 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
925 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
926 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
927 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
928 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
929 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
930 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
931 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
932 /**
933 * @}
934 */
935
936 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
937 * @{
938 */
939 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
940 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
941 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
942 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
943 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
944 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
945 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
946 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
947 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
948 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
949 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
950 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
951 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
952 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
953 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
954 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
955 /**
956 * @}
957 */
958
959 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
960 * @{
961 */
962 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
963 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
964 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
965 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
966 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
967 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
968 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
969 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
970 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
971 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
972 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
973 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
974 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
975 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
976 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
977 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
978 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
979 /**
980 * @}
981 */
982
983 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
984 * @{
985 */
986 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
987 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
988 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
989 /**
990 * @}
991 */
992
993 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
994 * @{
995 */
996 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
997 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
998 /**
999 * @}
1000 */
1001
1002 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1003 * @{
1004 */
1005 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1006 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1007 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1013 * @{
1014 */
1015 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1016 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1017 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1018 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1024 * @{
1025 */
1026 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1027 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1033 * @{
1034 */
1035 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1036 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1037 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1038 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1044 * @{
1045 */
1046 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1047 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1048 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1049 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1050 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1051 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1052 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1053 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1054 /**
1055 * @}
1056 */
1057
1058 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1059 * @{
1060 */
1061 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1062 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1063 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1064 /**
1065 * @}
1066 */
1067
1068 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1069 * @{
1070 */
1071 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1072 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1073 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1074 /**
1075 * @}
1076 */
1077
1078 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1079 * @{
1080 */
1081 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1082 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1083 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1084 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1085 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1086 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1087 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1088 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1089 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1090 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1091 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1092 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1093 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1094 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1095 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1096 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1097 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1098 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1099 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1100 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1101 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1102 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1103 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1104 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1105 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1106 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1107 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1108 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1109 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1110 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1111 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1112 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1113 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1114 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1115 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1116 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1117 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1118 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1119 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1120 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1121 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1122 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1123 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1124 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1125 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1126 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1127 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1128 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1129 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1130 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1131 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1132 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1133 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1134 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1135 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1136 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1137 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1138 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1139 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1140 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1141 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1142 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1143 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1144 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1145 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
1146 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
1147 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
1148 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1149 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1150 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1151 #if defined(ADC1) && !defined(ADC2)
1152 #define LL_ADC_AWD_CH_DAC1CH1_REG ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
1153 #define LL_ADC_AWD_CH_DAC1CH1_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
1154 #define LL_ADC_AWD_CH_DAC1CH1_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
1155 #define LL_ADC_AWD_CH_DAC1CH2_REG ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */
1156 #define LL_ADC_AWD_CH_DAC1CH2_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */
1157 #define LL_ADC_AWD_CH_DAC1CH2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */
1158 #elif defined(ADC2)
1159 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1160 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1161 #define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1162 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
1163 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
1164 #define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
1165 #if defined(ADC3)
1166 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1167 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1168 #define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1169 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */
1170 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */
1171 #define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */
1172 #endif
1173 #endif
1174 /**
1175 * @}
1176 */
1177
1178 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1179 * @{
1180 */
1181 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1182 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1183 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1189 * @{
1190 */
1191 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1192 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1193 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1194 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1195 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1201 * @{
1202 */
1203 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1204 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1205 /**
1206 * @}
1207 */
1208
1209 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1210 * @{
1211 */
1212 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1213 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1214 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1215 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1216 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1217 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1218 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1219 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1225 * @{
1226 */
1227 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1228 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1229 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1230 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1231 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1232 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1233 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1234 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1235 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1236 /**
1237 * @}
1238 */
1239
1240 #if defined(ADC_MULTIMODE_SUPPORT)
1241 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1242 * @{
1243 */
1244 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1245 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1246 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1247 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1248 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1249 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1250 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1251 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1257 * @{
1258 */
1259 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1260 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1261 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1262 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1263 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1264 /**
1265 * @}
1266 */
1267
1268 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1269 * @{
1270 */
1271 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1272 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1273 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1274 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1275 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1276 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1277 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1278 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1279 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1280 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1281 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1282 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1283 /**
1284 * @}
1285 */
1286
1287 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1288 * @{
1289 */
1290 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1291 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1292 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1293 /**
1294 * @}
1295 */
1296
1297 #endif /* ADC_MULTIMODE_SUPPORT */
1298
1299 /** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming
1300 * @{
1301 */
1302 #define LL_ADC_REG_TRIG_SW_START (LL_ADC_REG_TRIG_SOFTWARE)
1303 #define LL_ADC_REG_TRIG_EXT_TIM1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
1304 #define LL_ADC_REG_TRIG_EXT_TIM1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
1305 #define LL_ADC_REG_TRIG_EXT_TIM1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
1306 #define LL_ADC_REG_TRIG_EXT_TIM2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
1307 #define LL_ADC_REG_TRIG_EXT_TIM3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
1308 #define LL_ADC_REG_TRIG_EXT_TIM4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
1309
1310 #define LL_ADC_INJ_TRIG_SW_START (LL_ADC_INJ_TRIG_SOFTWARE)
1311 #define LL_ADC_INJ_TRIG_EXT_TIM1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)
1312 #define LL_ADC_INJ_TRIG_EXT_TIM2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)
1313 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)
1314 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)
1315 #define LL_ADC_INJ_TRIG_EXT_TIM3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)
1316 #define LL_ADC_INJ_TRIG_EXT_TIM8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)
1317
1318 #define LL_ADC_OVS_DATA_SHIFT_NONE (LL_ADC_OVS_SHIFT_NONE)
1319 #define LL_ADC_OVS_DATA_SHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1)
1320 #define LL_ADC_OVS_DATA_SHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2)
1321 #define LL_ADC_OVS_DATA_SHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3)
1322 #define LL_ADC_OVS_DATA_SHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4)
1323 #define LL_ADC_OVS_DATA_SHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5)
1324 #define LL_ADC_OVS_DATA_SHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6)
1325 #define LL_ADC_OVS_DATA_SHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7)
1326 #define LL_ADC_OVS_DATA_SHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8)
1327
1328 /**
1329 * @}
1330 */
1331
1332
1333 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1334 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1335 * not timeout values.
1336 * For details on delays values, refer to descriptions in source code
1337 * above each literal definition.
1338 * @{
1339 */
1340
1341 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1342 /* not timeout values. */
1343 /* Timeout values for ADC operations are dependent to device clock */
1344 /* configuration (system clock versus ADC clock), */
1345 /* and therefore must be defined in user application. */
1346 /* Indications for estimation of ADC timeout delays, for this */
1347 /* STM32 serie: */
1348 /* - ADC calibration time: maximum delay is 112/fADC. */
1349 /* (refer to device datasheet, parameter "tCAL") */
1350 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1351 /* (refer to device datasheet, parameter "tSTAB") */
1352 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1353 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1354 /* cycles */
1355 /* - ADC conversion time: duration depending on ADC clock and ADC */
1356 /* configuration. */
1357 /* (refer to device reference manual, section "Timing") */
1358
1359 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1360 /* Delay set to maximum value (refer to device datasheet, */
1361 /* parameter "tADCVREG_STUP"). */
1362 /* Unit: us */
1363 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1364
1365 /* Delay for internal voltage reference stabilization time. */
1366 /* Delay set to maximum value (refer to device datasheet, */
1367 /* parameter "tstart_vrefint"). */
1368 /* Unit: us */
1369 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1370
1371 /* Delay for temperature sensor stabilization time. */
1372 /* Literal set to maximum value (refer to device datasheet, */
1373 /* parameter "tSTART"). */
1374 /* Unit: us */
1375 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1376
1377 /* Delay required between ADC end of calibration and ADC enable. */
1378 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1379 /* are required between ADC end of calibration and ADC enable. */
1380 /* Wait time can be computed in user application by waiting for the */
1381 /* equivalent number of CPU cycles, by taking into account */
1382 /* ratio of CPU clock versus ADC clock prescalers. */
1383 /* Unit: ADC clock cycles. */
1384 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1385
1386 /**
1387 * @}
1388 */
1389
1390 /**
1391 * @}
1392 */
1393
1394
1395 /* Exported macro ------------------------------------------------------------*/
1396 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1397 * @{
1398 */
1399
1400 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1401 * @{
1402 */
1403
1404 /**
1405 * @brief Write a value in ADC register
1406 * @param __INSTANCE__ ADC Instance
1407 * @param __REG__ Register to be written
1408 * @param __VALUE__ Value to be written in the register
1409 * @retval None
1410 */
1411 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1412
1413 /**
1414 * @brief Read a value in ADC register
1415 * @param __INSTANCE__ ADC Instance
1416 * @param __REG__ Register to be read
1417 * @retval Register value
1418 */
1419 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1420 /**
1421 * @}
1422 */
1423
1424 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1425 * @{
1426 */
1427
1428 /**
1429 * @brief Helper macro to get ADC channel number in decimal format
1430 * from literals LL_ADC_CHANNEL_x.
1431 * @note Example:
1432 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1433 * will return decimal number "4".
1434 * @note The input can be a value from functions where a channel
1435 * number is returned, either defined with number
1436 * or with bitfield (only one bit must be set).
1437 * @param __CHANNEL__ This parameter can be one of the following values:
1438 * @arg @ref LL_ADC_CHANNEL_0
1439 * @arg @ref LL_ADC_CHANNEL_1 (7)
1440 * @arg @ref LL_ADC_CHANNEL_2 (7)
1441 * @arg @ref LL_ADC_CHANNEL_3 (7)
1442 * @arg @ref LL_ADC_CHANNEL_4 (7)
1443 * @arg @ref LL_ADC_CHANNEL_5 (7)
1444 * @arg @ref LL_ADC_CHANNEL_6
1445 * @arg @ref LL_ADC_CHANNEL_7
1446 * @arg @ref LL_ADC_CHANNEL_8
1447 * @arg @ref LL_ADC_CHANNEL_9
1448 * @arg @ref LL_ADC_CHANNEL_10
1449 * @arg @ref LL_ADC_CHANNEL_11
1450 * @arg @ref LL_ADC_CHANNEL_12
1451 * @arg @ref LL_ADC_CHANNEL_13
1452 * @arg @ref LL_ADC_CHANNEL_14
1453 * @arg @ref LL_ADC_CHANNEL_15
1454 * @arg @ref LL_ADC_CHANNEL_16
1455 * @arg @ref LL_ADC_CHANNEL_17
1456 * @arg @ref LL_ADC_CHANNEL_18
1457 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1458 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1459 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1460 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1461 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1462 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1463 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1464 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1465 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1466 *
1467 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1468 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1469 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1470 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1471 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1472 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1473 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1474 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1475 * @retval Value between Min_Data=0 and Max_Data=18
1476 */
1477 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1478 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1479 ? ( \
1480 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1481 ) \
1482 : \
1483 ( \
1484 POSITION_VAL((__CHANNEL__)) \
1485 ) \
1486 )
1487
1488 /**
1489 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1490 * from number in decimal format.
1491 * @note Example:
1492 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1493 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1494 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1495 * @retval Returned value can be one of the following values:
1496 * @arg @ref LL_ADC_CHANNEL_0
1497 * @arg @ref LL_ADC_CHANNEL_1 (7)
1498 * @arg @ref LL_ADC_CHANNEL_2 (7)
1499 * @arg @ref LL_ADC_CHANNEL_3 (7)
1500 * @arg @ref LL_ADC_CHANNEL_4 (7)
1501 * @arg @ref LL_ADC_CHANNEL_5 (7)
1502 * @arg @ref LL_ADC_CHANNEL_6
1503 * @arg @ref LL_ADC_CHANNEL_7
1504 * @arg @ref LL_ADC_CHANNEL_8
1505 * @arg @ref LL_ADC_CHANNEL_9
1506 * @arg @ref LL_ADC_CHANNEL_10
1507 * @arg @ref LL_ADC_CHANNEL_11
1508 * @arg @ref LL_ADC_CHANNEL_12
1509 * @arg @ref LL_ADC_CHANNEL_13
1510 * @arg @ref LL_ADC_CHANNEL_14
1511 * @arg @ref LL_ADC_CHANNEL_15
1512 * @arg @ref LL_ADC_CHANNEL_16
1513 * @arg @ref LL_ADC_CHANNEL_17
1514 * @arg @ref LL_ADC_CHANNEL_18
1515 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1516 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1517 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1518 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1519 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1520 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1521 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1522 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1523 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1524 *
1525 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1526 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1527 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1528 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1529 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1530 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1531 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1532 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1533 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1534 * comparison with internal channel parameter to be done
1535 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1536 */
1537 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1538 (((__DECIMAL_NB__) <= 9UL) \
1539 ? ( \
1540 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1541 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1542 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1543 ) \
1544 : \
1545 ( \
1546 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1547 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1548 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1549 ) \
1550 )
1551
1552 /**
1553 * @brief Helper macro to determine whether the selected channel
1554 * corresponds to literal definitions of driver.
1555 * @note The different literal definitions of ADC channels are:
1556 * - ADC internal channel:
1557 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1558 * - ADC external channel (channel connected to a GPIO pin):
1559 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1560 * @note The channel parameter must be a value defined from literal
1561 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1562 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1563 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1564 * must not be a value from functions where a channel number is
1565 * returned from ADC registers,
1566 * because internal and external channels share the same channel
1567 * number in ADC registers. The differentiation is made only with
1568 * parameters definitions of driver.
1569 * @param __CHANNEL__ This parameter can be one of the following values:
1570 * @arg @ref LL_ADC_CHANNEL_0
1571 * @arg @ref LL_ADC_CHANNEL_1 (7)
1572 * @arg @ref LL_ADC_CHANNEL_2 (7)
1573 * @arg @ref LL_ADC_CHANNEL_3 (7)
1574 * @arg @ref LL_ADC_CHANNEL_4 (7)
1575 * @arg @ref LL_ADC_CHANNEL_5 (7)
1576 * @arg @ref LL_ADC_CHANNEL_6
1577 * @arg @ref LL_ADC_CHANNEL_7
1578 * @arg @ref LL_ADC_CHANNEL_8
1579 * @arg @ref LL_ADC_CHANNEL_9
1580 * @arg @ref LL_ADC_CHANNEL_10
1581 * @arg @ref LL_ADC_CHANNEL_11
1582 * @arg @ref LL_ADC_CHANNEL_12
1583 * @arg @ref LL_ADC_CHANNEL_13
1584 * @arg @ref LL_ADC_CHANNEL_14
1585 * @arg @ref LL_ADC_CHANNEL_15
1586 * @arg @ref LL_ADC_CHANNEL_16
1587 * @arg @ref LL_ADC_CHANNEL_17
1588 * @arg @ref LL_ADC_CHANNEL_18
1589 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1590 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1591 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1592 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1593 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1594 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1595 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1596 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1597 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1598 *
1599 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1600 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1601 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1602 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1603 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1604 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1605 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1606 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1607 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1608 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1609 */
1610 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1611 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1612
1613 /**
1614 * @brief Helper macro to convert a channel defined from parameter
1615 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1616 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1617 * to its equivalent parameter definition of a ADC external channel
1618 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1619 * @note The channel parameter can be, additionally to a value
1620 * defined from parameter definition of a ADC internal channel
1621 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1622 * a value defined from parameter definition of
1623 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1624 * or a value from functions where a channel number is returned
1625 * from ADC registers.
1626 * @param __CHANNEL__ This parameter can be one of the following values:
1627 * @arg @ref LL_ADC_CHANNEL_0
1628 * @arg @ref LL_ADC_CHANNEL_1 (7)
1629 * @arg @ref LL_ADC_CHANNEL_2 (7)
1630 * @arg @ref LL_ADC_CHANNEL_3 (7)
1631 * @arg @ref LL_ADC_CHANNEL_4 (7)
1632 * @arg @ref LL_ADC_CHANNEL_5 (7)
1633 * @arg @ref LL_ADC_CHANNEL_6
1634 * @arg @ref LL_ADC_CHANNEL_7
1635 * @arg @ref LL_ADC_CHANNEL_8
1636 * @arg @ref LL_ADC_CHANNEL_9
1637 * @arg @ref LL_ADC_CHANNEL_10
1638 * @arg @ref LL_ADC_CHANNEL_11
1639 * @arg @ref LL_ADC_CHANNEL_12
1640 * @arg @ref LL_ADC_CHANNEL_13
1641 * @arg @ref LL_ADC_CHANNEL_14
1642 * @arg @ref LL_ADC_CHANNEL_15
1643 * @arg @ref LL_ADC_CHANNEL_16
1644 * @arg @ref LL_ADC_CHANNEL_17
1645 * @arg @ref LL_ADC_CHANNEL_18
1646 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1647 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1648 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1649 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1650 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1651 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1652 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1653 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1654 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1655 *
1656 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1657 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1658 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1659 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1660 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1661 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1662 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1663 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
1664 * @retval Returned value can be one of the following values:
1665 * @arg @ref LL_ADC_CHANNEL_0
1666 * @arg @ref LL_ADC_CHANNEL_1
1667 * @arg @ref LL_ADC_CHANNEL_2
1668 * @arg @ref LL_ADC_CHANNEL_3
1669 * @arg @ref LL_ADC_CHANNEL_4
1670 * @arg @ref LL_ADC_CHANNEL_5
1671 * @arg @ref LL_ADC_CHANNEL_6
1672 * @arg @ref LL_ADC_CHANNEL_7
1673 * @arg @ref LL_ADC_CHANNEL_8
1674 * @arg @ref LL_ADC_CHANNEL_9
1675 * @arg @ref LL_ADC_CHANNEL_10
1676 * @arg @ref LL_ADC_CHANNEL_11
1677 * @arg @ref LL_ADC_CHANNEL_12
1678 * @arg @ref LL_ADC_CHANNEL_13
1679 * @arg @ref LL_ADC_CHANNEL_14
1680 * @arg @ref LL_ADC_CHANNEL_15
1681 * @arg @ref LL_ADC_CHANNEL_16
1682 * @arg @ref LL_ADC_CHANNEL_17
1683 * @arg @ref LL_ADC_CHANNEL_18
1684 */
1685 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1686 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1687
1688 /**
1689 * @brief Helper macro to determine whether the internal channel
1690 * selected is available on the ADC instance selected.
1691 * @note The channel parameter must be a value defined from parameter
1692 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1693 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1694 * must not be a value defined from parameter definition of
1695 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1696 * or a value from functions where a channel number is
1697 * returned from ADC registers,
1698 * because internal and external channels share the same channel
1699 * number in ADC registers. The differentiation is made only with
1700 * parameters definitions of driver.
1701 * @param __ADC_INSTANCE__ ADC instance
1702 * @param __CHANNEL__ This parameter can be one of the following values:
1703 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1704 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1705 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1706 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1707 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1708 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1709 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1710 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1711 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1712 *
1713 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1714 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1715 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1716 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1717 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1718 * (6) On STM32L4, parameter available on devices with several ADC instances.
1719 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1720 * Value "1" if the internal channel selected is available on the ADC instance selected.
1721 */
1722 #if defined (ADC1) && defined (ADC2) && defined (ADC3)
1723 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1724 (((__ADC_INSTANCE__) == ADC1) \
1725 ? ( \
1726 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1727 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1728 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1729 ) \
1730 : \
1731 ((__ADC_INSTANCE__) == ADC2) \
1732 ? ( \
1733 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1734 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1735 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1736 ) \
1737 : \
1738 ((__ADC_INSTANCE__) == ADC3) \
1739 ? ( \
1740 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1741 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1742 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1743 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) || \
1744 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3) \
1745 ) \
1746 : \
1747 (0UL) \
1748 )
1749 #elif defined (ADC1) && defined (ADC2)
1750 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1751 (((__ADC_INSTANCE__) == ADC1) \
1752 ? ( \
1753 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1754 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1755 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1756 ) \
1757 : \
1758 ((__ADC_INSTANCE__) == ADC2) \
1759 ? ( \
1760 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1761 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
1762 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
1763 ) \
1764 : \
1765 (0UL) \
1766 )
1767 #elif defined (ADC1)
1768 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1769 ( \
1770 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1771 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1772 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1773 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1) || \
1774 ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2) \
1775 )
1776 #endif
1777
1778 /**
1779 * @brief Helper macro to define ADC analog watchdog parameter:
1780 * define a single channel to monitor with analog watchdog
1781 * from sequencer channel and groups definition.
1782 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1783 * Example:
1784 * LL_ADC_SetAnalogWDMonitChannels(
1785 * ADC1, LL_ADC_AWD1,
1786 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1787 * @param __CHANNEL__ This parameter can be one of the following values:
1788 * @arg @ref LL_ADC_CHANNEL_0
1789 * @arg @ref LL_ADC_CHANNEL_1 (7)
1790 * @arg @ref LL_ADC_CHANNEL_2 (7)
1791 * @arg @ref LL_ADC_CHANNEL_3 (7)
1792 * @arg @ref LL_ADC_CHANNEL_4 (7)
1793 * @arg @ref LL_ADC_CHANNEL_5 (7)
1794 * @arg @ref LL_ADC_CHANNEL_6
1795 * @arg @ref LL_ADC_CHANNEL_7
1796 * @arg @ref LL_ADC_CHANNEL_8
1797 * @arg @ref LL_ADC_CHANNEL_9
1798 * @arg @ref LL_ADC_CHANNEL_10
1799 * @arg @ref LL_ADC_CHANNEL_11
1800 * @arg @ref LL_ADC_CHANNEL_12
1801 * @arg @ref LL_ADC_CHANNEL_13
1802 * @arg @ref LL_ADC_CHANNEL_14
1803 * @arg @ref LL_ADC_CHANNEL_15
1804 * @arg @ref LL_ADC_CHANNEL_16
1805 * @arg @ref LL_ADC_CHANNEL_17
1806 * @arg @ref LL_ADC_CHANNEL_18
1807 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1808 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
1809 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
1810 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
1811 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
1812 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
1813 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
1814 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
1815 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
1816 *
1817 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1818 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1819 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1820 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
1821 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1822 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
1823 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
1824 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
1825 * (1, 2, 3, 4) For ADC channel read back from ADC register,
1826 * comparison with internal channel parameter to be done
1827 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1828 * @param __GROUP__ This parameter can be one of the following values:
1829 * @arg @ref LL_ADC_GROUP_REGULAR
1830 * @arg @ref LL_ADC_GROUP_INJECTED
1831 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1832 * @retval Returned value can be one of the following values:
1833 * @arg @ref LL_ADC_AWD_DISABLE
1834 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
1835 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
1836 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1837 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
1838 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
1839 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1840 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
1841 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
1842 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1843 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
1844 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
1845 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1846 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
1847 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
1848 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1849 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
1850 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
1851 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1852 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
1853 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
1854 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1855 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
1856 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
1857 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1858 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
1859 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
1860 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1861 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
1862 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
1863 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1864 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
1865 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
1866 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1867 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
1868 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
1869 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1870 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
1871 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
1872 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1873 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
1874 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
1875 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1876 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
1877 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
1878 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1879 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
1880 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
1881 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1882 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
1883 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
1884 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1885 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
1886 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
1887 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1888 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
1889 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
1890 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1891 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
1892 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
1893 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
1894 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
1895 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
1896 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1897 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
1898 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
1899 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
1900 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
1901 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
1902 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
1903 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
1904 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
1905 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
1906 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
1907 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
1908 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
1909 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
1910 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
1911 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
1912 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
1913 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
1914 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
1915 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
1916 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
1917 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
1918 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
1919 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
1920 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
1921 *
1922 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
1923 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
1924 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
1925 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
1926 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
1927 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
1928 * (6) On STM32L4, parameter available on devices with several ADC instances.
1929 */
1930 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1931 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1932 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1933 : \
1934 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1935 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
1936 : \
1937 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
1938 )
1939
1940 /**
1941 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1942 * or low in function of ADC resolution, when ADC resolution is
1943 * different of 12 bits.
1944 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1945 * or @ref LL_ADC_SetAnalogWDThresholds().
1946 * Example, with a ADC resolution of 8 bits, to set the value of
1947 * analog watchdog threshold high (on 8 bits):
1948 * LL_ADC_SetAnalogWDThresholds
1949 * (< ADCx param >,
1950 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1951 * );
1952 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1953 * @arg @ref LL_ADC_RESOLUTION_12B
1954 * @arg @ref LL_ADC_RESOLUTION_10B
1955 * @arg @ref LL_ADC_RESOLUTION_8B
1956 * @arg @ref LL_ADC_RESOLUTION_6B
1957 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1958 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1959 */
1960 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1961 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1962
1963 /**
1964 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1965 * or low in function of ADC resolution, when ADC resolution is
1966 * different of 12 bits.
1967 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1968 * Example, with a ADC resolution of 8 bits, to get the value of
1969 * analog watchdog threshold high (on 8 bits):
1970 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1971 * (LL_ADC_RESOLUTION_8B,
1972 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1973 * );
1974 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1975 * @arg @ref LL_ADC_RESOLUTION_12B
1976 * @arg @ref LL_ADC_RESOLUTION_10B
1977 * @arg @ref LL_ADC_RESOLUTION_8B
1978 * @arg @ref LL_ADC_RESOLUTION_6B
1979 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1980 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1981 */
1982 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1983 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
1984
1985 /**
1986 * @brief Helper macro to get the ADC analog watchdog threshold high
1987 * or low from raw value containing both thresholds concatenated.
1988 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1989 * Example, to get analog watchdog threshold high from the register raw value:
1990 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1991 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1992 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1993 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1994 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1995 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1996 */
1997 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1998 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
1999
2000 /**
2001 * @brief Helper macro to set the ADC calibration value with both single ended
2002 * and differential modes calibration factors concatenated.
2003 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2004 * Example, to set calibration factors single ended to 0x55
2005 * and differential ended to 0x2A:
2006 * LL_ADC_SetCalibrationFactor(
2007 * ADC1,
2008 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2009 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2010 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2011 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2012 */
2013 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2014 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2015
2016 #if defined(ADC_MULTIMODE_SUPPORT)
2017 /**
2018 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2019 * or ADC slave from raw value with both ADC conversion data concatenated.
2020 * @note This macro is intended to be used when multimode transfer by DMA
2021 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2022 * In this case the transferred data need to processed with this macro
2023 * to separate the conversion data of ADC master and ADC slave.
2024 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2025 * @arg @ref LL_ADC_MULTI_MASTER
2026 * @arg @ref LL_ADC_MULTI_SLAVE
2027 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2028 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2029 */
2030 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2031 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2032 #endif
2033
2034 #if defined(ADC_MULTIMODE_SUPPORT)
2035 /**
2036 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2037 * it has a dependence in multimode (ADC master of the corresponding
2038 * ADC common instance).
2039 * @note In case of device with multimode available and a mix of
2040 * ADC instances compliant and not compliant with multimode feature,
2041 * ADC instances not compliant with multimode feature are
2042 * considered as master instances (do not depend to
2043 * any other ADC instance).
2044 * @param __ADCx__ ADC instance
2045 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2046 */
2047 #if defined(ADC2)
2048 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2049 ( ( ((__ADCx__) == ADC2) \
2050 )? \
2051 (ADC1) \
2052 : \
2053 (__ADCx__) \
2054 )
2055 #else
2056 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2057 (__ADCx__)
2058 #endif
2059 #endif
2060
2061 /**
2062 * @brief Helper macro to select the ADC common instance
2063 * to which is belonging the selected ADC instance.
2064 * @note ADC common register instance can be used for:
2065 * - Set parameters common to several ADC instances
2066 * - Multimode (for devices with several ADC instances)
2067 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2068 * @param __ADCx__ ADC instance
2069 * @retval ADC common register instance
2070 */
2071 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2072 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2073 (ADC123_COMMON)
2074 #elif defined(ADC1) && defined(ADC2)
2075 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2076 (ADC12_COMMON)
2077 #else
2078 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2079 (ADC1_COMMON)
2080 #endif
2081
2082 /**
2083 * @brief Helper macro to check if all ADC instances sharing the same
2084 * ADC common instance are disabled.
2085 * @note This check is required by functions with setting conditioned to
2086 * ADC state:
2087 * All ADC instances of the ADC common group must be disabled.
2088 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2089 * @note On devices with only 1 ADC common instance, parameter of this macro
2090 * is useless and can be ignored (parameter kept for compatibility
2091 * with devices featuring several ADC common instances).
2092 * @param __ADCXY_COMMON__ ADC common instance
2093 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2094 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2095 * are disabled.
2096 * Value "1" if at least one ADC instance sharing the same ADC common instance
2097 * is enabled.
2098 */
2099 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
2100 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2101 (LL_ADC_IsEnabled(ADC1) | \
2102 LL_ADC_IsEnabled(ADC2) | \
2103 LL_ADC_IsEnabled(ADC3) )
2104 #elif defined(ADC1) && defined(ADC2)
2105 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2106 (LL_ADC_IsEnabled(ADC1) | \
2107 LL_ADC_IsEnabled(ADC2) )
2108 #else
2109 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2110 (LL_ADC_IsEnabled(ADC1))
2111 #endif
2112
2113 /**
2114 * @brief Helper macro to define the ADC conversion data full-scale digital
2115 * value corresponding to the selected ADC resolution.
2116 * @note ADC conversion data full-scale corresponds to voltage range
2117 * determined by analog voltage references Vref+ and Vref-
2118 * (refer to reference manual).
2119 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2120 * @arg @ref LL_ADC_RESOLUTION_12B
2121 * @arg @ref LL_ADC_RESOLUTION_10B
2122 * @arg @ref LL_ADC_RESOLUTION_8B
2123 * @arg @ref LL_ADC_RESOLUTION_6B
2124 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2125 */
2126 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2127 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2128
2129 /**
2130 * @brief Helper macro to convert the ADC conversion data from
2131 * a resolution to another resolution.
2132 * @param __DATA__ ADC conversion data to be converted
2133 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2134 * This parameter can be one of the following values:
2135 * @arg @ref LL_ADC_RESOLUTION_12B
2136 * @arg @ref LL_ADC_RESOLUTION_10B
2137 * @arg @ref LL_ADC_RESOLUTION_8B
2138 * @arg @ref LL_ADC_RESOLUTION_6B
2139 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2140 * This parameter can be one of the following values:
2141 * @arg @ref LL_ADC_RESOLUTION_12B
2142 * @arg @ref LL_ADC_RESOLUTION_10B
2143 * @arg @ref LL_ADC_RESOLUTION_8B
2144 * @arg @ref LL_ADC_RESOLUTION_6B
2145 * @retval ADC conversion data to the requested resolution
2146 */
2147 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2148 __ADC_RESOLUTION_CURRENT__,\
2149 __ADC_RESOLUTION_TARGET__) \
2150 (((__DATA__) \
2151 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2152 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2153 )
2154
2155 /**
2156 * @brief Helper macro to calculate the voltage (unit: mVolt)
2157 * corresponding to a ADC conversion data (unit: digital value).
2158 * @note Analog reference voltage (Vref+) must be either known from
2159 * user board environment or can be calculated using ADC measurement
2160 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2161 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2162 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2163 * (unit: digital value).
2164 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2165 * @arg @ref LL_ADC_RESOLUTION_12B
2166 * @arg @ref LL_ADC_RESOLUTION_10B
2167 * @arg @ref LL_ADC_RESOLUTION_8B
2168 * @arg @ref LL_ADC_RESOLUTION_6B
2169 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2170 */
2171 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2172 __ADC_DATA__,\
2173 __ADC_RESOLUTION__) \
2174 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2175 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2176 )
2177
2178 /* Legacy define */
2179 #define __LL_ADC_CALC_DATA_VOLTAGE() __LL_ADC_CALC_DATA_TO_VOLTAGE()
2180
2181 /**
2182 * @brief Helper macro to calculate analog reference voltage (Vref+)
2183 * (unit: mVolt) from ADC conversion data of internal voltage
2184 * reference VrefInt.
2185 * @note Computation is using VrefInt calibration value
2186 * stored in system memory for each device during production.
2187 * @note This voltage depends on user board environment: voltage level
2188 * connected to pin Vref+.
2189 * On devices with small package, the pin Vref+ is not present
2190 * and internally bonded to pin Vdda.
2191 * @note On this STM32 serie, calibration data of internal voltage reference
2192 * VrefInt corresponds to a resolution of 12 bits,
2193 * this is the recommended ADC resolution to convert voltage of
2194 * internal voltage reference VrefInt.
2195 * Otherwise, this macro performs the processing to scale
2196 * ADC conversion data to 12 bits.
2197 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2198 * of internal voltage reference VrefInt (unit: digital value).
2199 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2200 * @arg @ref LL_ADC_RESOLUTION_12B
2201 * @arg @ref LL_ADC_RESOLUTION_10B
2202 * @arg @ref LL_ADC_RESOLUTION_8B
2203 * @arg @ref LL_ADC_RESOLUTION_6B
2204 * @retval Analog reference voltage (unit: mV)
2205 */
2206 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2207 __ADC_RESOLUTION__) \
2208 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2209 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2210 (__ADC_RESOLUTION__), \
2211 LL_ADC_RESOLUTION_12B) \
2212 )
2213
2214 /**
2215 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2216 * from ADC conversion data of internal temperature sensor.
2217 * @note Computation is using temperature sensor calibration values
2218 * stored in system memory for each device during production.
2219 * @note Calculation formula:
2220 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2221 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2222 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2223 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2224 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2225 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2226 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2227 * TEMP_DEGC_CAL1 (calibrated in factory)
2228 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2229 * TEMP_DEGC_CAL2 (calibrated in factory)
2230 * Caution: Calculation relevancy under reserve that calibration
2231 * parameters are correct (address and data).
2232 * To calculate temperature using temperature sensor
2233 * datasheet typical values (generic values less, therefore
2234 * less accurate than calibrated values),
2235 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2236 * @note As calculation input, the analog reference voltage (Vref+) must be
2237 * defined as it impacts the ADC LSB equivalent voltage.
2238 * @note Analog reference voltage (Vref+) must be either known from
2239 * user board environment or can be calculated using ADC measurement
2240 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2241 * @note On this STM32 serie, calibration data of temperature sensor
2242 * corresponds to a resolution of 12 bits,
2243 * this is the recommended ADC resolution to convert voltage of
2244 * temperature sensor.
2245 * Otherwise, this macro performs the processing to scale
2246 * ADC conversion data to 12 bits.
2247 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2248 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2249 * temperature sensor (unit: digital value).
2250 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2251 * sensor voltage has been measured.
2252 * This parameter can be one of the following values:
2253 * @arg @ref LL_ADC_RESOLUTION_12B
2254 * @arg @ref LL_ADC_RESOLUTION_10B
2255 * @arg @ref LL_ADC_RESOLUTION_8B
2256 * @arg @ref LL_ADC_RESOLUTION_6B
2257 * @retval Temperature (unit: degree Celsius)
2258 */
2259 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2260 __TEMPSENSOR_ADC_DATA__,\
2261 __ADC_RESOLUTION__) \
2262 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2263 (__ADC_RESOLUTION__), \
2264 LL_ADC_RESOLUTION_12B) \
2265 * (__VREFANALOG_VOLTAGE__)) \
2266 / TEMPSENSOR_CAL_VREFANALOG) \
2267 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2268 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2269 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2270 ) + TEMPSENSOR_CAL1_TEMP \
2271 )
2272
2273 /**
2274 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2275 * from ADC conversion data of internal temperature sensor.
2276 * @note Computation is using temperature sensor typical values
2277 * (refer to device datasheet).
2278 * @note Calculation formula:
2279 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2280 * / Avg_Slope + CALx_TEMP
2281 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2282 * (unit: digital value)
2283 * Avg_Slope = temperature sensor slope
2284 * (unit: uV/Degree Celsius)
2285 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2286 * temperature CALx_TEMP (unit: mV)
2287 * Caution: Calculation relevancy under reserve the temperature sensor
2288 * of the current device has characteristics in line with
2289 * datasheet typical values.
2290 * If temperature sensor calibration values are available on
2291 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2292 * temperature calculation will be more accurate using
2293 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2294 * @note As calculation input, the analog reference voltage (Vref+) must be
2295 * defined as it impacts the ADC LSB equivalent voltage.
2296 * @note Analog reference voltage (Vref+) must be either known from
2297 * user board environment or can be calculated using ADC measurement
2298 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2299 * @note ADC measurement data must correspond to a resolution of 12 bits
2300 * (full scale digital value 4095). If not the case, the data must be
2301 * preliminarily rescaled to an equivalent resolution of 12 bits.
2302 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2303 * On STM32L4, refer to device datasheet parameter "Avg_Slope".
2304 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2305 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2306 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2307 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2308 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2309 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2310 * This parameter can be one of the following values:
2311 * @arg @ref LL_ADC_RESOLUTION_12B
2312 * @arg @ref LL_ADC_RESOLUTION_10B
2313 * @arg @ref LL_ADC_RESOLUTION_8B
2314 * @arg @ref LL_ADC_RESOLUTION_6B
2315 * @retval Temperature (unit: degree Celsius)
2316 */
2317 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2318 __TEMPSENSOR_TYP_CALX_V__,\
2319 __TEMPSENSOR_CALX_TEMP__,\
2320 __VREFANALOG_VOLTAGE__,\
2321 __TEMPSENSOR_ADC_DATA__,\
2322 __ADC_RESOLUTION__) \
2323 ((( ( \
2324 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2325 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2326 * 1000UL) \
2327 - \
2328 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2329 * 1000UL) \
2330 ) \
2331 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2332 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2333 )
2334
2335 /**
2336 * @}
2337 */
2338
2339 /**
2340 * @}
2341 */
2342
2343
2344 /* Exported functions --------------------------------------------------------*/
2345 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2346 * @{
2347 */
2348
2349 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2350 * @{
2351 */
2352 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2353 /* configuration of ADC instance, groups and multimode (if available): */
2354 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2355
2356 /**
2357 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2358 * ADC register address from ADC instance and a list of ADC registers
2359 * intended to be used (most commonly) with DMA transfer.
2360 * @note These ADC registers are data registers:
2361 * when ADC conversion data is available in ADC data registers,
2362 * ADC generates a DMA transfer request.
2363 * @note This macro is intended to be used with LL DMA driver, refer to
2364 * function "LL_DMA_ConfigAddresses()".
2365 * Example:
2366 * LL_DMA_ConfigAddresses(DMA1,
2367 * LL_DMA_CHANNEL_1,
2368 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2369 * (uint32_t)&< array or variable >,
2370 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2371 * @note For devices with several ADC: in multimode, some devices
2372 * use a different data register outside of ADC instance scope
2373 * (common data register). This macro manages this register difference,
2374 * only ADC instance has to be set as parameter.
2375 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2376 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2377 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2378 * @param ADCx ADC instance
2379 * @param Register This parameter can be one of the following values:
2380 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2381 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2382 *
2383 * (1) Available on devices with several ADC instances.
2384 * @retval ADC register address
2385 */
2386 #if defined(ADC_MULTIMODE_SUPPORT)
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2387 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2388 {
2389 register uint32_t data_reg_addr;
2390
2391 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2392 {
2393 /* Retrieve address of register DR */
2394 data_reg_addr = (uint32_t)&(ADCx->DR);
2395 }
2396 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2397 {
2398 /* Retrieve address of register CDR */
2399 data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2400 }
2401
2402 return data_reg_addr;
2403 }
2404 #else
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)2405 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2406 {
2407 /* Prevent unused argument(s) compilation warning */
2408 (void)(Register);
2409
2410 /* Retrieve address of register DR */
2411 return (uint32_t)&(ADCx->DR);
2412 }
2413 #endif
2414
2415 /**
2416 * @}
2417 */
2418
2419 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2420 * @{
2421 */
2422
2423 /**
2424 * @brief Set parameter common to several ADC: Clock source and prescaler.
2425 * @note On this STM32 serie, if ADC group injected is used, some
2426 * clock ratio constraints between ADC clock and AHB clock
2427 * must be respected.
2428 * Refer to reference manual.
2429 * @note On this STM32 serie, setting of this feature is conditioned to
2430 * ADC state:
2431 * All ADC instances of the ADC common group must be disabled.
2432 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2433 * ADC instance or by using helper macro helper macro
2434 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2435 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2436 * CCR PRESC LL_ADC_SetCommonClock
2437 * @param ADCxy_COMMON ADC common instance
2438 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2439 * @param CommonClock This parameter can be one of the following values:
2440 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2441 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2442 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2443 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2444 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2445 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2446 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2447 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2448 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2449 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2450 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2451 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2452 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2453 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2454 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2455 * @retval None
2456 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)2457 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2458 {
2459 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2460 }
2461
2462 /**
2463 * @brief Get parameter common to several ADC: Clock source and prescaler.
2464 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2465 * CCR PRESC LL_ADC_GetCommonClock
2466 * @param ADCxy_COMMON ADC common instance
2467 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2468 * @retval Returned value can be one of the following values:
2469 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2470 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2471 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2472 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2473 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2474 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2475 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2476 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2477 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2478 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2479 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2480 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2481 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2482 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2483 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2484 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)2485 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2486 {
2487 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2488 }
2489
2490 /**
2491 * @brief Set parameter common to several ADC: measurement path to internal
2492 * channels (VrefInt, temperature sensor, ...).
2493 * @note One or several values can be selected.
2494 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2495 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2496 * @note Stabilization time of measurement path to internal channel:
2497 * After enabling internal paths, before starting ADC conversion,
2498 * a delay is required for internal voltage reference and
2499 * temperature sensor stabilization time.
2500 * Refer to device datasheet.
2501 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2502 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2503 * @note ADC internal channel sampling time constraint:
2504 * For ADC conversion of internal channels,
2505 * a sampling time minimum value is required.
2506 * Refer to device datasheet.
2507 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2508 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
2509 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
2510 * @param ADCxy_COMMON ADC common instance
2511 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2512 * @param PathInternal This parameter can be a combination of the following values:
2513 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2514 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2515 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2516 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2517 * @retval None
2518 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)2519 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2520 {
2521 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
2522 }
2523
2524 /**
2525 * @brief Get parameter common to several ADC: measurement path to internal
2526 * channels (VrefInt, temperature sensor, ...).
2527 * @note One or several values can be selected.
2528 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2529 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2530 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2531 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
2532 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
2533 * @param ADCxy_COMMON ADC common instance
2534 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2535 * @retval Returned value can be a combination of the following values:
2536 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2537 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2538 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2539 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2540 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)2541 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2542 {
2543 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
2544 }
2545
2546 /**
2547 * @}
2548 */
2549
2550 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2551 * @{
2552 */
2553
2554 /**
2555 * @brief Set ADC calibration factor in the mode single-ended
2556 * or differential (for devices with differential mode available).
2557 * @note This function is intended to set calibration parameters
2558 * without having to perform a new calibration using
2559 * @ref LL_ADC_StartCalibration().
2560 * @note For devices with differential mode available:
2561 * Calibration of offset is specific to each of
2562 * single-ended and differential modes
2563 * (calibration factor must be specified for each of these
2564 * differential modes, if used afterwards and if the application
2565 * requires their calibration).
2566 * @note In case of setting calibration factors of both modes single ended
2567 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2568 * both calibration factors must be concatenated.
2569 * To perform this processing, use helper macro
2570 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2571 * @note On this STM32 serie, setting of this feature is conditioned to
2572 * ADC state:
2573 * ADC must be enabled, without calibration on going, without conversion
2574 * on going on group regular.
2575 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2576 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2577 * @param ADCx ADC instance
2578 * @param SingleDiff This parameter can be one of the following values:
2579 * @arg @ref LL_ADC_SINGLE_ENDED
2580 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2581 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2582 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2583 * @retval None
2584 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff,uint32_t CalibrationFactor)2585 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2586 {
2587 MODIFY_REG(ADCx->CALFACT,
2588 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2589 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2590 }
2591
2592 /**
2593 * @brief Get ADC calibration factor in the mode single-ended
2594 * or differential (for devices with differential mode available).
2595 * @note Calibration factors are set by hardware after performing
2596 * a calibration run using function @ref LL_ADC_StartCalibration().
2597 * @note For devices with differential mode available:
2598 * Calibration of offset is specific to each of
2599 * single-ended and differential modes
2600 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2601 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2602 * @param ADCx ADC instance
2603 * @param SingleDiff This parameter can be one of the following values:
2604 * @arg @ref LL_ADC_SINGLE_ENDED
2605 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2606 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2607 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t SingleDiff)2608 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2609 {
2610 /* Retrieve bits with position in register depending on parameter */
2611 /* "SingleDiff". */
2612 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2613 /* containing other bits reserved for other purpose. */
2614 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2615 }
2616
2617 /**
2618 * @brief Set ADC resolution.
2619 * Refer to reference manual for alignments formats
2620 * dependencies to ADC resolutions.
2621 * @note On this STM32 serie, setting of this feature is conditioned to
2622 * ADC state:
2623 * ADC must be disabled or enabled without conversion on going
2624 * on either groups regular or injected.
2625 * @rmtoll CFGR RES LL_ADC_SetResolution
2626 * @param ADCx ADC instance
2627 * @param Resolution This parameter can be one of the following values:
2628 * @arg @ref LL_ADC_RESOLUTION_12B
2629 * @arg @ref LL_ADC_RESOLUTION_10B
2630 * @arg @ref LL_ADC_RESOLUTION_8B
2631 * @arg @ref LL_ADC_RESOLUTION_6B
2632 * @retval None
2633 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2634 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2635 {
2636 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2637 }
2638
2639 /**
2640 * @brief Get ADC resolution.
2641 * Refer to reference manual for alignments formats
2642 * dependencies to ADC resolutions.
2643 * @rmtoll CFGR RES LL_ADC_GetResolution
2644 * @param ADCx ADC instance
2645 * @retval Returned value can be one of the following values:
2646 * @arg @ref LL_ADC_RESOLUTION_12B
2647 * @arg @ref LL_ADC_RESOLUTION_10B
2648 * @arg @ref LL_ADC_RESOLUTION_8B
2649 * @arg @ref LL_ADC_RESOLUTION_6B
2650 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2651 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2652 {
2653 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2654 }
2655
2656 /**
2657 * @brief Set ADC conversion data alignment.
2658 * @note Refer to reference manual for alignments formats
2659 * dependencies to ADC resolutions.
2660 * @note On this STM32 serie, setting of this feature is conditioned to
2661 * ADC state:
2662 * ADC must be disabled or enabled without conversion on going
2663 * on either groups regular or injected.
2664 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2665 * @param ADCx ADC instance
2666 * @param DataAlignment This parameter can be one of the following values:
2667 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2668 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2669 * @retval None
2670 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2671 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2672 {
2673 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2674 }
2675
2676 /**
2677 * @brief Get ADC conversion data alignment.
2678 * @note Refer to reference manual for alignments formats
2679 * dependencies to ADC resolutions.
2680 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2681 * @param ADCx ADC instance
2682 * @retval Returned value can be one of the following values:
2683 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2684 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2685 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2686 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2687 {
2688 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2689 }
2690
2691 /**
2692 * @brief Set ADC low power mode.
2693 * @note Description of ADC low power modes:
2694 * - ADC low power mode "auto wait": Dynamic low power mode,
2695 * ADC conversions occurrences are limited to the minimum necessary
2696 * in order to reduce power consumption.
2697 * New ADC conversion starts only when the previous
2698 * unitary conversion data (for ADC group regular)
2699 * or previous sequence conversions data (for ADC group injected)
2700 * has been retrieved by user software.
2701 * In the meantime, ADC remains idle: does not performs any
2702 * other conversion.
2703 * This mode allows to automatically adapt the ADC conversions
2704 * triggers to the speed of the software that reads the data.
2705 * Moreover, this avoids risk of overrun for low frequency
2706 * applications.
2707 * How to use this low power mode:
2708 * - Do not use with interruption or DMA since these modes
2709 * have to clear immediately the EOC flag to free the
2710 * IRQ vector sequencer.
2711 * - Do use with polling: 1. Start conversion,
2712 * 2. Later on, when conversion data is needed: poll for end of
2713 * conversion to ensure that conversion is completed and
2714 * retrieve ADC conversion data. This will trig another
2715 * ADC conversion start.
2716 * - ADC low power mode "auto power-off" (feature available on
2717 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2718 * the ADC automatically powers-off after a conversion and
2719 * automatically wakes up when a new conversion is triggered
2720 * (with startup time between trigger and start of sampling).
2721 * This feature can be combined with low power mode "auto wait".
2722 * @note With ADC low power mode "auto wait", the ADC conversion data read
2723 * is corresponding to previous ADC conversion start, independently
2724 * of delay during which ADC was idle.
2725 * Therefore, the ADC conversion data may be outdated: does not
2726 * correspond to the current voltage level on the selected
2727 * ADC channel.
2728 * @note On this STM32 serie, setting of this feature is conditioned to
2729 * ADC state:
2730 * ADC must be disabled or enabled without conversion on going
2731 * on either groups regular or injected.
2732 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2733 * @param ADCx ADC instance
2734 * @param LowPowerMode This parameter can be one of the following values:
2735 * @arg @ref LL_ADC_LP_MODE_NONE
2736 * @arg @ref LL_ADC_LP_AUTOWAIT
2737 * @retval None
2738 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2739 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2740 {
2741 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2742 }
2743
2744 /**
2745 * @brief Get ADC low power mode:
2746 * @note Description of ADC low power modes:
2747 * - ADC low power mode "auto wait": Dynamic low power mode,
2748 * ADC conversions occurrences are limited to the minimum necessary
2749 * in order to reduce power consumption.
2750 * New ADC conversion starts only when the previous
2751 * unitary conversion data (for ADC group regular)
2752 * or previous sequence conversions data (for ADC group injected)
2753 * has been retrieved by user software.
2754 * In the meantime, ADC remains idle: does not performs any
2755 * other conversion.
2756 * This mode allows to automatically adapt the ADC conversions
2757 * triggers to the speed of the software that reads the data.
2758 * Moreover, this avoids risk of overrun for low frequency
2759 * applications.
2760 * How to use this low power mode:
2761 * - Do not use with interruption or DMA since these modes
2762 * have to clear immediately the EOC flag to free the
2763 * IRQ vector sequencer.
2764 * - Do use with polling: 1. Start conversion,
2765 * 2. Later on, when conversion data is needed: poll for end of
2766 * conversion to ensure that conversion is completed and
2767 * retrieve ADC conversion data. This will trig another
2768 * ADC conversion start.
2769 * - ADC low power mode "auto power-off" (feature available on
2770 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2771 * the ADC automatically powers-off after a conversion and
2772 * automatically wakes up when a new conversion is triggered
2773 * (with startup time between trigger and start of sampling).
2774 * This feature can be combined with low power mode "auto wait".
2775 * @note With ADC low power mode "auto wait", the ADC conversion data read
2776 * is corresponding to previous ADC conversion start, independently
2777 * of delay during which ADC was idle.
2778 * Therefore, the ADC conversion data may be outdated: does not
2779 * correspond to the current voltage level on the selected
2780 * ADC channel.
2781 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2782 * @param ADCx ADC instance
2783 * @retval Returned value can be one of the following values:
2784 * @arg @ref LL_ADC_LP_MODE_NONE
2785 * @arg @ref LL_ADC_LP_AUTOWAIT
2786 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2787 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2788 {
2789 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2790 }
2791
2792 /**
2793 * @brief Set ADC selected offset number 1, 2, 3 or 4.
2794 * @note This function set the 2 items of offset configuration:
2795 * - ADC channel to which the offset programmed will be applied
2796 * (independently of channel mapped on ADC group regular
2797 * or group injected)
2798 * - Offset level (offset to be subtracted from the raw
2799 * converted data).
2800 * @note Caution: Offset format is dependent to ADC resolution:
2801 * offset has to be left-aligned on bit 11, the LSB (right bits)
2802 * are set to 0.
2803 * @note This function enables the offset, by default. It can be forced
2804 * to disable state using function LL_ADC_SetOffsetState().
2805 * @note If a channel is mapped on several offsets numbers, only the offset
2806 * with the lowest value is considered for the subtraction.
2807 * @note On this STM32 serie, setting of this feature is conditioned to
2808 * ADC state:
2809 * ADC must be disabled or enabled without conversion on going
2810 * on either groups regular or injected.
2811 * @note On STM32L4, some fast channels are available: fast analog inputs
2812 * coming from GPIO pads (ADC_IN1..5).
2813 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
2814 * OFR1 OFFSET1 LL_ADC_SetOffset\n
2815 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
2816 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
2817 * OFR2 OFFSET2 LL_ADC_SetOffset\n
2818 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
2819 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
2820 * OFR3 OFFSET3 LL_ADC_SetOffset\n
2821 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
2822 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
2823 * OFR4 OFFSET4 LL_ADC_SetOffset\n
2824 * OFR4 OFFSET4_EN LL_ADC_SetOffset
2825 * @param ADCx ADC instance
2826 * @param Offsety This parameter can be one of the following values:
2827 * @arg @ref LL_ADC_OFFSET_1
2828 * @arg @ref LL_ADC_OFFSET_2
2829 * @arg @ref LL_ADC_OFFSET_3
2830 * @arg @ref LL_ADC_OFFSET_4
2831 * @param Channel This parameter can be one of the following values:
2832 * @arg @ref LL_ADC_CHANNEL_0
2833 * @arg @ref LL_ADC_CHANNEL_1 (7)
2834 * @arg @ref LL_ADC_CHANNEL_2 (7)
2835 * @arg @ref LL_ADC_CHANNEL_3 (7)
2836 * @arg @ref LL_ADC_CHANNEL_4 (7)
2837 * @arg @ref LL_ADC_CHANNEL_5 (7)
2838 * @arg @ref LL_ADC_CHANNEL_6
2839 * @arg @ref LL_ADC_CHANNEL_7
2840 * @arg @ref LL_ADC_CHANNEL_8
2841 * @arg @ref LL_ADC_CHANNEL_9
2842 * @arg @ref LL_ADC_CHANNEL_10
2843 * @arg @ref LL_ADC_CHANNEL_11
2844 * @arg @ref LL_ADC_CHANNEL_12
2845 * @arg @ref LL_ADC_CHANNEL_13
2846 * @arg @ref LL_ADC_CHANNEL_14
2847 * @arg @ref LL_ADC_CHANNEL_15
2848 * @arg @ref LL_ADC_CHANNEL_16
2849 * @arg @ref LL_ADC_CHANNEL_17
2850 * @arg @ref LL_ADC_CHANNEL_18
2851 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2852 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2853 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2854 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2855 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2856 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2857 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2858 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2859 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2860 *
2861 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2862 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2863 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2864 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2865 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2866 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2867 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2868 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
2869 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2870 * @retval None
2871 */
LL_ADC_SetOffset(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t Channel,uint32_t OffsetLevel)2872 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
2873 {
2874 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2875
2876 MODIFY_REG(*preg,
2877 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
2878 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
2879 }
2880
2881 /**
2882 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2883 * Channel to which the offset programmed will be applied
2884 * (independently of channel mapped on ADC group regular
2885 * or group injected)
2886 * @note Usage of the returned channel number:
2887 * - To reinject this channel into another function LL_ADC_xxx:
2888 * the returned channel number is only partly formatted on definition
2889 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2890 * with parts of literals LL_ADC_CHANNEL_x or using
2891 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2892 * Then the selected literal LL_ADC_CHANNEL_x can be used
2893 * as parameter for another function.
2894 * - To get the channel number in decimal format:
2895 * process the returned value with the helper macro
2896 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2897 * @note On STM32L4, some fast channels are available: fast analog inputs
2898 * coming from GPIO pads (ADC_IN1..5).
2899 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
2900 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
2901 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
2902 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
2903 * @param ADCx ADC instance
2904 * @param Offsety This parameter can be one of the following values:
2905 * @arg @ref LL_ADC_OFFSET_1
2906 * @arg @ref LL_ADC_OFFSET_2
2907 * @arg @ref LL_ADC_OFFSET_3
2908 * @arg @ref LL_ADC_OFFSET_4
2909 * @retval Returned value can be one of the following values:
2910 * @arg @ref LL_ADC_CHANNEL_0
2911 * @arg @ref LL_ADC_CHANNEL_1 (7)
2912 * @arg @ref LL_ADC_CHANNEL_2 (7)
2913 * @arg @ref LL_ADC_CHANNEL_3 (7)
2914 * @arg @ref LL_ADC_CHANNEL_4 (7)
2915 * @arg @ref LL_ADC_CHANNEL_5 (7)
2916 * @arg @ref LL_ADC_CHANNEL_6
2917 * @arg @ref LL_ADC_CHANNEL_7
2918 * @arg @ref LL_ADC_CHANNEL_8
2919 * @arg @ref LL_ADC_CHANNEL_9
2920 * @arg @ref LL_ADC_CHANNEL_10
2921 * @arg @ref LL_ADC_CHANNEL_11
2922 * @arg @ref LL_ADC_CHANNEL_12
2923 * @arg @ref LL_ADC_CHANNEL_13
2924 * @arg @ref LL_ADC_CHANNEL_14
2925 * @arg @ref LL_ADC_CHANNEL_15
2926 * @arg @ref LL_ADC_CHANNEL_16
2927 * @arg @ref LL_ADC_CHANNEL_17
2928 * @arg @ref LL_ADC_CHANNEL_18
2929 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2930 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
2931 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
2932 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
2933 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
2934 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
2935 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
2936 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
2937 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
2938 *
2939 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
2940 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
2941 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
2942 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
2943 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
2944 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
2945 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
2946 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
2947 * (1, 2, 3, 4) For ADC channel read back from ADC register,
2948 * comparison with internal channel parameter to be done
2949 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2950 */
LL_ADC_GetOffsetChannel(ADC_TypeDef * ADCx,uint32_t Offsety)2951 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
2952 {
2953 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2954
2955 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
2956 }
2957
2958 /**
2959 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
2960 * Offset level (offset to be subtracted from the raw
2961 * converted data).
2962 * @note Caution: Offset format is dependent to ADC resolution:
2963 * offset has to be left-aligned on bit 11, the LSB (right bits)
2964 * are set to 0.
2965 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
2966 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
2967 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
2968 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
2969 * @param ADCx ADC instance
2970 * @param Offsety This parameter can be one of the following values:
2971 * @arg @ref LL_ADC_OFFSET_1
2972 * @arg @ref LL_ADC_OFFSET_2
2973 * @arg @ref LL_ADC_OFFSET_3
2974 * @arg @ref LL_ADC_OFFSET_4
2975 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2976 */
LL_ADC_GetOffsetLevel(ADC_TypeDef * ADCx,uint32_t Offsety)2977 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
2978 {
2979 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
2980
2981 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
2982 }
2983
2984 /**
2985 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
2986 * force offset state disable or enable
2987 * without modifying offset channel or offset value.
2988 * @note This function should be needed only in case of offset to be
2989 * enabled-disabled dynamically, and should not be needed in other cases:
2990 * function LL_ADC_SetOffset() automatically enables the offset.
2991 * @note On this STM32 serie, setting of this feature is conditioned to
2992 * ADC state:
2993 * ADC must be disabled or enabled without conversion on going
2994 * on either groups regular or injected.
2995 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
2996 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
2997 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
2998 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
2999 * @param ADCx ADC instance
3000 * @param Offsety This parameter can be one of the following values:
3001 * @arg @ref LL_ADC_OFFSET_1
3002 * @arg @ref LL_ADC_OFFSET_2
3003 * @arg @ref LL_ADC_OFFSET_3
3004 * @arg @ref LL_ADC_OFFSET_4
3005 * @param OffsetState This parameter can be one of the following values:
3006 * @arg @ref LL_ADC_OFFSET_DISABLE
3007 * @arg @ref LL_ADC_OFFSET_ENABLE
3008 * @retval None
3009 */
LL_ADC_SetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety,uint32_t OffsetState)3010 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3011 {
3012 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3013
3014 MODIFY_REG(*preg,
3015 ADC_OFR1_OFFSET1_EN,
3016 OffsetState);
3017 }
3018
3019 /**
3020 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3021 * offset state disabled or enabled.
3022 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3023 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3024 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3025 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3026 * @param ADCx ADC instance
3027 * @param Offsety This parameter can be one of the following values:
3028 * @arg @ref LL_ADC_OFFSET_1
3029 * @arg @ref LL_ADC_OFFSET_2
3030 * @arg @ref LL_ADC_OFFSET_3
3031 * @arg @ref LL_ADC_OFFSET_4
3032 * @retval Returned value can be one of the following values:
3033 * @arg @ref LL_ADC_OFFSET_DISABLE
3034 * @arg @ref LL_ADC_OFFSET_ENABLE
3035 */
LL_ADC_GetOffsetState(ADC_TypeDef * ADCx,uint32_t Offsety)3036 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3037 {
3038 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3039
3040 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3041 }
3042
3043 #if defined(ADC_SMPR1_SMPPLUS)
3044 /**
3045 * @brief Set ADC sampling time common configuration impacting
3046 * settings of sampling time channel wise.
3047 * @note On this STM32 serie, setting of this feature is conditioned to
3048 * ADC state:
3049 * ADC must be disabled or enabled without conversion on going
3050 * on either groups regular or injected.
3051 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3052 * @param ADCx ADC instance
3053 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3054 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3055 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3056 * @retval None
3057 */
LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef * ADCx,uint32_t SamplingTimeCommonConfig)3058 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3059 {
3060 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3061 }
3062
3063 /**
3064 * @brief Get ADC sampling time common configuration impacting
3065 * settings of sampling time channel wise.
3066 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3067 * @param ADCx ADC instance
3068 * @retval Returned value can be one of the following values:
3069 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3070 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3071 */
LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef * ADCx)3072 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3073 {
3074 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3075 }
3076 #endif /* ADC_SMPR1_SMPPLUS */
3077
3078 /**
3079 * @}
3080 */
3081
3082 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3083 * @{
3084 */
3085
3086 /**
3087 * @brief Set ADC group regular conversion trigger source:
3088 * internal (SW start) or from external IP (timer event,
3089 * external interrupt line).
3090 * @note On this STM32 serie, setting trigger source to external trigger
3091 * also set trigger polarity to rising edge
3092 * (default setting for compatibility with some ADC on other
3093 * STM32 families having this setting set by HW default value).
3094 * In case of need to modify trigger edge, use
3095 * function @ref LL_ADC_REG_SetTriggerEdge().
3096 * @note Availability of parameters of trigger sources from timer
3097 * depends on timers availability on the selected device.
3098 * @note On this STM32 serie, setting of this feature is conditioned to
3099 * ADC state:
3100 * ADC must be disabled or enabled without conversion on going
3101 * on group regular.
3102 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3103 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3104 * @param ADCx ADC instance
3105 * @param TriggerSource This parameter can be one of the following values:
3106 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3107 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3108 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3109 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3110 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3111 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3112 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3113 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3114 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3115 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3116 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3117 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3118 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3119 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3120 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3121 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3122 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3123 * @retval None
3124 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3125 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3126 {
3127 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3128 }
3129
3130 /**
3131 * @brief Get ADC group regular conversion trigger source:
3132 * internal (SW start) or from external IP (timer event,
3133 * external interrupt line).
3134 * @note To determine whether group regular trigger source is
3135 * internal (SW start) or external, without detail
3136 * of which peripheral is selected as external trigger,
3137 * (equivalent to
3138 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3139 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3140 * @note Availability of parameters of trigger sources from timer
3141 * depends on timers availability on the selected device.
3142 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3143 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3144 * @param ADCx ADC instance
3145 * @retval Returned value can be one of the following values:
3146 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3147 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3148 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3149 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
3150 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
3151 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3152 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3153 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
3154 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3155 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
3156 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3157 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
3158 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3159 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3160 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3161 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3162 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
3163 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)3164 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3165 {
3166 register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3167
3168 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3169 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3170 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3171
3172 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3173 /* to match with triggers literals definition. */
3174 return ((TriggerSource
3175 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3176 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3177 );
3178 }
3179
3180 /**
3181 * @brief Get ADC group regular conversion trigger source internal (SW start)
3182 * or external.
3183 * @note In case of group regular trigger source set to external trigger,
3184 * to determine which peripheral is selected as external trigger,
3185 * use function @ref LL_ADC_REG_GetTriggerSource().
3186 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3187 * @param ADCx ADC instance
3188 * @retval Value "0" if trigger source external trigger
3189 * Value "1" if trigger source SW start.
3190 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3191 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3192 {
3193 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3194 }
3195
3196 /**
3197 * @brief Set ADC group regular conversion trigger polarity.
3198 * @note Applicable only for trigger source set to external trigger.
3199 * @note On this STM32 serie, setting of this feature is conditioned to
3200 * ADC state:
3201 * ADC must be disabled or enabled without conversion on going
3202 * on group regular.
3203 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3204 * @param ADCx ADC instance
3205 * @param ExternalTriggerEdge This parameter can be one of the following values:
3206 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3207 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3208 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3209 * @retval None
3210 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3211 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3212 {
3213 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3214 }
3215
3216 /**
3217 * @brief Get ADC group regular conversion trigger polarity.
3218 * @note Applicable only for trigger source set to external trigger.
3219 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3220 * @param ADCx ADC instance
3221 * @retval Returned value can be one of the following values:
3222 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3223 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3224 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3225 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)3226 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3227 {
3228 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3229 }
3230
3231 /**
3232 * @brief Set ADC group regular sequencer length and scan direction.
3233 * @note Description of ADC group regular sequencer features:
3234 * - For devices with sequencer fully configurable
3235 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3236 * sequencer length and each rank affectation to a channel
3237 * are configurable.
3238 * This function performs configuration of:
3239 * - Sequence length: Number of ranks in the scan sequence.
3240 * - Sequence direction: Unless specified in parameters, sequencer
3241 * scan direction is forward (from rank 1 to rank n).
3242 * Sequencer ranks are selected using
3243 * function "LL_ADC_REG_SetSequencerRanks()".
3244 * - For devices with sequencer not fully configurable
3245 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3246 * sequencer length and each rank affectation to a channel
3247 * are defined by channel number.
3248 * This function performs configuration of:
3249 * - Sequence length: Number of ranks in the scan sequence is
3250 * defined by number of channels set in the sequence,
3251 * rank of each channel is fixed by channel HW number.
3252 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3253 * - Sequence direction: Unless specified in parameters, sequencer
3254 * scan direction is forward (from lowest channel number to
3255 * highest channel number).
3256 * Sequencer ranks are selected using
3257 * function "LL_ADC_REG_SetSequencerChannels()".
3258 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3259 * ADC conversion on only 1 channel.
3260 * @note On this STM32 serie, setting of this feature is conditioned to
3261 * ADC state:
3262 * ADC must be disabled or enabled without conversion on going
3263 * on group regular.
3264 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3265 * @param ADCx ADC instance
3266 * @param SequencerNbRanks This parameter can be one of the following values:
3267 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3268 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3269 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3270 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3271 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3272 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3273 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3274 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3275 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3276 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3277 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3278 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3279 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3280 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3281 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3282 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3283 * @retval None
3284 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3285 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3286 {
3287 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3288 }
3289
3290 /**
3291 * @brief Get ADC group regular sequencer length and scan direction.
3292 * @note Description of ADC group regular sequencer features:
3293 * - For devices with sequencer fully configurable
3294 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3295 * sequencer length and each rank affectation to a channel
3296 * are configurable.
3297 * This function retrieves:
3298 * - Sequence length: Number of ranks in the scan sequence.
3299 * - Sequence direction: Unless specified in parameters, sequencer
3300 * scan direction is forward (from rank 1 to rank n).
3301 * Sequencer ranks are selected using
3302 * function "LL_ADC_REG_SetSequencerRanks()".
3303 * - For devices with sequencer not fully configurable
3304 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3305 * sequencer length and each rank affectation to a channel
3306 * are defined by channel number.
3307 * This function retrieves:
3308 * - Sequence length: Number of ranks in the scan sequence is
3309 * defined by number of channels set in the sequence,
3310 * rank of each channel is fixed by channel HW number.
3311 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3312 * - Sequence direction: Unless specified in parameters, sequencer
3313 * scan direction is forward (from lowest channel number to
3314 * highest channel number).
3315 * Sequencer ranks are selected using
3316 * function "LL_ADC_REG_SetSequencerChannels()".
3317 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3318 * ADC conversion on only 1 channel.
3319 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3320 * @param ADCx ADC instance
3321 * @retval Returned value can be one of the following values:
3322 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3323 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3324 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3325 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3326 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3327 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3328 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3329 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3330 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3331 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3332 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3333 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3334 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3335 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3336 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3337 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3338 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)3339 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3340 {
3341 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3342 }
3343
3344 /**
3345 * @brief Set ADC group regular sequencer discontinuous mode:
3346 * sequence subdivided and scan conversions interrupted every selected
3347 * number of ranks.
3348 * @note It is not possible to enable both ADC group regular
3349 * continuous mode and sequencer discontinuous mode.
3350 * @note It is not possible to enable both ADC auto-injected mode
3351 * and ADC group regular sequencer discontinuous mode.
3352 * @note On this STM32 serie, setting of this feature is conditioned to
3353 * ADC state:
3354 * ADC must be disabled or enabled without conversion on going
3355 * on group regular.
3356 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3357 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3358 * @param ADCx ADC instance
3359 * @param SeqDiscont This parameter can be one of the following values:
3360 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3361 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3362 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3363 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3364 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3365 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3366 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3367 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3368 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3369 * @retval None
3370 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)3371 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3372 {
3373 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3374 }
3375
3376 /**
3377 * @brief Get ADC group regular sequencer discontinuous mode:
3378 * sequence subdivided and scan conversions interrupted every selected
3379 * number of ranks.
3380 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3381 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3382 * @param ADCx ADC instance
3383 * @retval Returned value can be one of the following values:
3384 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3385 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3386 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3387 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3388 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3389 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3390 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3391 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3392 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3393 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)3394 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3395 {
3396 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3397 }
3398
3399 /**
3400 * @brief Set ADC group regular sequence: channel on the selected
3401 * scan sequence rank.
3402 * @note This function performs configuration of:
3403 * - Channels ordering into each rank of scan sequence:
3404 * whatever channel can be placed into whatever rank.
3405 * @note On this STM32 serie, ADC group regular sequencer is
3406 * fully configurable: sequencer length and each rank
3407 * affectation to a channel are configurable.
3408 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3409 * @note Depending on devices and packages, some channels may not be available.
3410 * Refer to device datasheet for channels availability.
3411 * @note On this STM32 serie, to measure internal channels (VrefInt,
3412 * TempSensor, ...), measurement paths to internal channels must be
3413 * enabled separately.
3414 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3415 * @note On this STM32 serie, setting of this feature is conditioned to
3416 * ADC state:
3417 * ADC must be disabled or enabled without conversion on going
3418 * on group regular.
3419 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3420 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3421 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3422 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3423 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3424 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3425 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3426 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3427 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3428 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3429 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3430 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3431 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3432 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3433 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3434 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3435 * @param ADCx ADC instance
3436 * @param Rank This parameter can be one of the following values:
3437 * @arg @ref LL_ADC_REG_RANK_1
3438 * @arg @ref LL_ADC_REG_RANK_2
3439 * @arg @ref LL_ADC_REG_RANK_3
3440 * @arg @ref LL_ADC_REG_RANK_4
3441 * @arg @ref LL_ADC_REG_RANK_5
3442 * @arg @ref LL_ADC_REG_RANK_6
3443 * @arg @ref LL_ADC_REG_RANK_7
3444 * @arg @ref LL_ADC_REG_RANK_8
3445 * @arg @ref LL_ADC_REG_RANK_9
3446 * @arg @ref LL_ADC_REG_RANK_10
3447 * @arg @ref LL_ADC_REG_RANK_11
3448 * @arg @ref LL_ADC_REG_RANK_12
3449 * @arg @ref LL_ADC_REG_RANK_13
3450 * @arg @ref LL_ADC_REG_RANK_14
3451 * @arg @ref LL_ADC_REG_RANK_15
3452 * @arg @ref LL_ADC_REG_RANK_16
3453 * @param Channel This parameter can be one of the following values:
3454 * @arg @ref LL_ADC_CHANNEL_0
3455 * @arg @ref LL_ADC_CHANNEL_1 (7)
3456 * @arg @ref LL_ADC_CHANNEL_2 (7)
3457 * @arg @ref LL_ADC_CHANNEL_3 (7)
3458 * @arg @ref LL_ADC_CHANNEL_4 (7)
3459 * @arg @ref LL_ADC_CHANNEL_5 (7)
3460 * @arg @ref LL_ADC_CHANNEL_6
3461 * @arg @ref LL_ADC_CHANNEL_7
3462 * @arg @ref LL_ADC_CHANNEL_8
3463 * @arg @ref LL_ADC_CHANNEL_9
3464 * @arg @ref LL_ADC_CHANNEL_10
3465 * @arg @ref LL_ADC_CHANNEL_11
3466 * @arg @ref LL_ADC_CHANNEL_12
3467 * @arg @ref LL_ADC_CHANNEL_13
3468 * @arg @ref LL_ADC_CHANNEL_14
3469 * @arg @ref LL_ADC_CHANNEL_15
3470 * @arg @ref LL_ADC_CHANNEL_16
3471 * @arg @ref LL_ADC_CHANNEL_17
3472 * @arg @ref LL_ADC_CHANNEL_18
3473 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3474 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3475 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3476 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3477 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3478 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3479 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3480 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3481 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3482 *
3483 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3484 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3485 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3486 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3487 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3488 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3489 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3490 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
3491 * @retval None
3492 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)3493 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3494 {
3495 /* Set bits with content of parameter "Channel" with bits position */
3496 /* in register and register position depending on parameter "Rank". */
3497 /* Parameters "Rank" and "Channel" are used with masks because containing */
3498 /* other bits reserved for other purpose. */
3499 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3500
3501 MODIFY_REG(*preg,
3502 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3503 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3504 }
3505
3506 /**
3507 * @brief Get ADC group regular sequence: channel on the selected
3508 * scan sequence rank.
3509 * @note On this STM32 serie, ADC group regular sequencer is
3510 * fully configurable: sequencer length and each rank
3511 * affectation to a channel are configurable.
3512 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3513 * @note Depending on devices and packages, some channels may not be available.
3514 * Refer to device datasheet for channels availability.
3515 * @note Usage of the returned channel number:
3516 * - To reinject this channel into another function LL_ADC_xxx:
3517 * the returned channel number is only partly formatted on definition
3518 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3519 * with parts of literals LL_ADC_CHANNEL_x or using
3520 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3521 * Then the selected literal LL_ADC_CHANNEL_x can be used
3522 * as parameter for another function.
3523 * - To get the channel number in decimal format:
3524 * process the returned value with the helper macro
3525 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3526 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3527 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3528 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3529 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3530 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3531 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3532 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3533 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3534 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3535 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3536 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3537 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
3538 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3539 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3540 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
3541 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
3542 * @param ADCx ADC instance
3543 * @param Rank This parameter can be one of the following values:
3544 * @arg @ref LL_ADC_REG_RANK_1
3545 * @arg @ref LL_ADC_REG_RANK_2
3546 * @arg @ref LL_ADC_REG_RANK_3
3547 * @arg @ref LL_ADC_REG_RANK_4
3548 * @arg @ref LL_ADC_REG_RANK_5
3549 * @arg @ref LL_ADC_REG_RANK_6
3550 * @arg @ref LL_ADC_REG_RANK_7
3551 * @arg @ref LL_ADC_REG_RANK_8
3552 * @arg @ref LL_ADC_REG_RANK_9
3553 * @arg @ref LL_ADC_REG_RANK_10
3554 * @arg @ref LL_ADC_REG_RANK_11
3555 * @arg @ref LL_ADC_REG_RANK_12
3556 * @arg @ref LL_ADC_REG_RANK_13
3557 * @arg @ref LL_ADC_REG_RANK_14
3558 * @arg @ref LL_ADC_REG_RANK_15
3559 * @arg @ref LL_ADC_REG_RANK_16
3560 * @retval Returned value can be one of the following values:
3561 * @arg @ref LL_ADC_CHANNEL_0
3562 * @arg @ref LL_ADC_CHANNEL_1 (7)
3563 * @arg @ref LL_ADC_CHANNEL_2 (7)
3564 * @arg @ref LL_ADC_CHANNEL_3 (7)
3565 * @arg @ref LL_ADC_CHANNEL_4 (7)
3566 * @arg @ref LL_ADC_CHANNEL_5 (7)
3567 * @arg @ref LL_ADC_CHANNEL_6
3568 * @arg @ref LL_ADC_CHANNEL_7
3569 * @arg @ref LL_ADC_CHANNEL_8
3570 * @arg @ref LL_ADC_CHANNEL_9
3571 * @arg @ref LL_ADC_CHANNEL_10
3572 * @arg @ref LL_ADC_CHANNEL_11
3573 * @arg @ref LL_ADC_CHANNEL_12
3574 * @arg @ref LL_ADC_CHANNEL_13
3575 * @arg @ref LL_ADC_CHANNEL_14
3576 * @arg @ref LL_ADC_CHANNEL_15
3577 * @arg @ref LL_ADC_CHANNEL_16
3578 * @arg @ref LL_ADC_CHANNEL_17
3579 * @arg @ref LL_ADC_CHANNEL_18
3580 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
3581 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
3582 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
3583 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
3584 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
3585 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
3586 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
3587 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
3588 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
3589 *
3590 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
3591 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
3592 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
3593 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
3594 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
3595 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
3596 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
3597 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
3598 * (1, 2, 3, 4) For ADC channel read back from ADC register,
3599 * comparison with internal channel parameter to be done
3600 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3601 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)3602 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3603 {
3604 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3605
3606 return (uint32_t) ((READ_BIT(*preg,
3607 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3608 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
3609 );
3610 }
3611
3612 /**
3613 * @brief Set ADC continuous conversion mode on ADC group regular.
3614 * @note Description of ADC continuous conversion mode:
3615 * - single mode: one conversion per trigger
3616 * - continuous mode: after the first trigger, following
3617 * conversions launched successively automatically.
3618 * @note It is not possible to enable both ADC group regular
3619 * continuous mode and sequencer discontinuous mode.
3620 * @note On this STM32 serie, setting of this feature is conditioned to
3621 * ADC state:
3622 * ADC must be disabled or enabled without conversion on going
3623 * on group regular.
3624 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
3625 * @param ADCx ADC instance
3626 * @param Continuous This parameter can be one of the following values:
3627 * @arg @ref LL_ADC_REG_CONV_SINGLE
3628 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3629 * @retval None
3630 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3631 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3632 {
3633 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
3634 }
3635
3636 /**
3637 * @brief Get ADC continuous conversion mode on ADC group regular.
3638 * @note Description of ADC continuous conversion mode:
3639 * - single mode: one conversion per trigger
3640 * - continuous mode: after the first trigger, following
3641 * conversions launched successively automatically.
3642 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
3643 * @param ADCx ADC instance
3644 * @retval Returned value can be one of the following values:
3645 * @arg @ref LL_ADC_REG_CONV_SINGLE
3646 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3647 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3648 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3649 {
3650 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
3651 }
3652
3653 /**
3654 * @brief Set ADC group regular conversion data transfer: no transfer or
3655 * transfer by DMA, and DMA requests mode.
3656 * @note If transfer by DMA selected, specifies the DMA requests
3657 * mode:
3658 * - Limited mode (One shot mode): DMA transfer requests are stopped
3659 * when number of DMA data transfers (number of
3660 * ADC conversions) is reached.
3661 * This ADC mode is intended to be used with DMA mode non-circular.
3662 * - Unlimited mode: DMA transfer requests are unlimited,
3663 * whatever number of DMA data transfers (number of
3664 * ADC conversions).
3665 * This ADC mode is intended to be used with DMA mode circular.
3666 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3667 * mode non-circular:
3668 * when DMA transfers size will be reached, DMA will stop transfers of
3669 * ADC conversions data ADC will raise an overrun error
3670 * (overrun flag and interruption if enabled).
3671 * @note For devices with several ADC instances: ADC multimode DMA
3672 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
3673 * @note To configure DMA source address (peripheral address),
3674 * use function @ref LL_ADC_DMA_GetRegAddr().
3675 * @note On this STM32 serie, setting of this feature is conditioned to
3676 * ADC state:
3677 * ADC must be disabled or enabled without conversion on going
3678 * on either groups regular or injected.
3679 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
3680 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
3681 * @param ADCx ADC instance
3682 * @param DMATransfer This parameter can be one of the following values:
3683 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3684 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3685 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3686 * @retval None
3687 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3688 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3689 {
3690 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
3691 }
3692
3693 /**
3694 * @brief Get ADC group regular conversion data transfer: no transfer or
3695 * transfer by DMA, and DMA requests mode.
3696 * @note If transfer by DMA selected, specifies the DMA requests
3697 * mode:
3698 * - Limited mode (One shot mode): DMA transfer requests are stopped
3699 * when number of DMA data transfers (number of
3700 * ADC conversions) is reached.
3701 * This ADC mode is intended to be used with DMA mode non-circular.
3702 * - Unlimited mode: DMA transfer requests are unlimited,
3703 * whatever number of DMA data transfers (number of
3704 * ADC conversions).
3705 * This ADC mode is intended to be used with DMA mode circular.
3706 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3707 * mode non-circular:
3708 * when DMA transfers size will be reached, DMA will stop transfers of
3709 * ADC conversions data ADC will raise an overrun error
3710 * (overrun flag and interruption if enabled).
3711 * @note For devices with several ADC instances: ADC multimode DMA
3712 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
3713 * @note To configure DMA source address (peripheral address),
3714 * use function @ref LL_ADC_DMA_GetRegAddr().
3715 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
3716 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
3717 * @param ADCx ADC instance
3718 * @retval Returned value can be one of the following values:
3719 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3720 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3721 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3722 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3723 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3724 {
3725 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
3726 }
3727
3728 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
3729 /**
3730 * @brief Set ADC group regular conversion data transfer to DFSDM.
3731 * @note DFSDM transfer cannot be used if DMA transfer is enabled.
3732 * @note To configure DFSDM source address (peripheral address),
3733 * use the same function as for DMA transfer:
3734 * function @ref LL_ADC_DMA_GetRegAddr().
3735 * @note On this STM32 serie, setting of this feature is conditioned to
3736 * ADC state:
3737 * ADC must be disabled or enabled without conversion on going
3738 * on either groups regular or injected.
3739 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3740 * @param ADCx ADC instance
3741 * @param DFSDMTransfer This parameter can be one of the following values:
3742 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3743 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3744 * @retval None
3745 */
LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef * ADCx,uint32_t DFSDMTransfer)3746 __STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)
3747 {
3748 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);
3749 }
3750
3751 /**
3752 * @brief Get ADC group regular conversion data transfer to DFSDM.
3753 * @rmtoll CFGR DFSDMCFG LL_ADC_REG_GetDFSDMTransfer
3754 * @param ADCx ADC instance
3755 * @retval Returned value can be one of the following values:
3756 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE
3757 * @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE
3758 */
LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef * ADCx)3759 __STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)
3760 {
3761 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
3762 }
3763 #endif
3764
3765 /**
3766 * @brief Set ADC group regular behavior in case of overrun:
3767 * data preserved or overwritten.
3768 * @note Compatibility with devices without feature overrun:
3769 * other devices without this feature have a behavior
3770 * equivalent to data overwritten.
3771 * The default setting of overrun is data preserved.
3772 * Therefore, for compatibility with all devices, parameter
3773 * overrun should be set to data overwritten.
3774 * @note On this STM32 serie, setting of this feature is conditioned to
3775 * ADC state:
3776 * ADC must be disabled or enabled without conversion on going
3777 * on group regular.
3778 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
3779 * @param ADCx ADC instance
3780 * @param Overrun This parameter can be one of the following values:
3781 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3782 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3783 * @retval None
3784 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3785 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3786 {
3787 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
3788 }
3789
3790 /**
3791 * @brief Get ADC group regular behavior in case of overrun:
3792 * data preserved or overwritten.
3793 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
3794 * @param ADCx ADC instance
3795 * @retval Returned value can be one of the following values:
3796 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3797 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3798 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3799 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3800 {
3801 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
3802 }
3803
3804 /**
3805 * @}
3806 */
3807
3808 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3809 * @{
3810 */
3811
3812 /**
3813 * @brief Set ADC group injected conversion trigger source:
3814 * internal (SW start) or from external IP (timer event,
3815 * external interrupt line).
3816 * @note On this STM32 serie, setting trigger source to external trigger
3817 * also set trigger polarity to rising edge
3818 * (default setting for compatibility with some ADC on other
3819 * STM32 families having this setting set by HW default value).
3820 * In case of need to modify trigger edge, use
3821 * function @ref LL_ADC_INJ_SetTriggerEdge().
3822 * @note Availability of parameters of trigger sources from timer
3823 * depends on timers availability on the selected device.
3824 * @note On this STM32 serie, setting of this feature is conditioned to
3825 * ADC state:
3826 * ADC must not be disabled. Can be enabled with or without conversion
3827 * on going on either groups regular or injected.
3828 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3829 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
3830 * @param ADCx ADC instance
3831 * @param TriggerSource This parameter can be one of the following values:
3832 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3833 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3834 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3835 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3836 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3837 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3838 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3839 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3840 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3841 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3842 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3843 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3844 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3845 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3846 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3847 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3848 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3849 * @retval None
3850 */
LL_ADC_INJ_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)3851 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3852 {
3853 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
3854 }
3855
3856 /**
3857 * @brief Get ADC group injected conversion trigger source:
3858 * internal (SW start) or from external IP (timer event,
3859 * external interrupt line).
3860 * @note To determine whether group injected trigger source is
3861 * internal (SW start) or external, without detail
3862 * of which peripheral is selected as external trigger,
3863 * (equivalent to
3864 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3865 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3866 * @note Availability of parameters of trigger sources from timer
3867 * depends on timers availability on the selected device.
3868 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3869 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
3870 * @param ADCx ADC instance
3871 * @retval Returned value can be one of the following values:
3872 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3873 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
3874 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
3875 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
3876 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3877 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3878 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
3879 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
3880 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
3881 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3882 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3883 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
3884 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
3885 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
3886 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
3887 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
3888 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3889 */
LL_ADC_INJ_GetTriggerSource(ADC_TypeDef * ADCx)3890 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3891 {
3892 register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
3893
3894 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3895 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
3896 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3897
3898 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
3899 /* to match with triggers literals definition. */
3900 return ((TriggerSource
3901 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
3902 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
3903 );
3904 }
3905
3906 /**
3907 * @brief Get ADC group injected conversion trigger source internal (SW start)
3908 or external
3909 * @note In case of group injected trigger source set to external trigger,
3910 * to determine which peripheral is selected as external trigger,
3911 * use function @ref LL_ADC_INJ_GetTriggerSource.
3912 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
3913 * @param ADCx ADC instance
3914 * @retval Value "0" if trigger source external trigger
3915 * Value "1" if trigger source SW start.
3916 */
LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)3917 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3918 {
3919 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
3920 }
3921
3922 /**
3923 * @brief Set ADC group injected conversion trigger polarity.
3924 * Applicable only for trigger source set to external trigger.
3925 * @note On this STM32 serie, setting of this feature is conditioned to
3926 * ADC state:
3927 * ADC must not be disabled. Can be enabled with or without conversion
3928 * on going on either groups regular or injected.
3929 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
3930 * @param ADCx ADC instance
3931 * @param ExternalTriggerEdge This parameter can be one of the following values:
3932 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3933 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3934 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3935 * @retval None
3936 */
LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)3937 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3938 {
3939 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
3940 }
3941
3942 /**
3943 * @brief Get ADC group injected conversion trigger polarity.
3944 * Applicable only for trigger source set to external trigger.
3945 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
3946 * @param ADCx ADC instance
3947 * @retval Returned value can be one of the following values:
3948 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3949 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3950 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3951 */
LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef * ADCx)3952 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
3953 {
3954 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
3955 }
3956
3957 /**
3958 * @brief Set ADC group injected sequencer length and scan direction.
3959 * @note This function performs configuration of:
3960 * - Sequence length: Number of ranks in the scan sequence.
3961 * - Sequence direction: Unless specified in parameters, sequencer
3962 * scan direction is forward (from rank 1 to rank n).
3963 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3964 * ADC conversion on only 1 channel.
3965 * @note On this STM32 serie, setting of this feature is conditioned to
3966 * ADC state:
3967 * ADC must not be disabled. Can be enabled with or without conversion
3968 * on going on either groups regular or injected.
3969 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
3970 * @param ADCx ADC instance
3971 * @param SequencerNbRanks This parameter can be one of the following values:
3972 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3973 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3974 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3975 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3976 * @retval None
3977 */
LL_ADC_INJ_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)3978 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3979 {
3980 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
3981 }
3982
3983 /**
3984 * @brief Get ADC group injected sequencer length and scan direction.
3985 * @note This function retrieves:
3986 * - Sequence length: Number of ranks in the scan sequence.
3987 * - Sequence direction: Unless specified in parameters, sequencer
3988 * scan direction is forward (from rank 1 to rank n).
3989 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3990 * ADC conversion on only 1 channel.
3991 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
3992 * @param ADCx ADC instance
3993 * @retval Returned value can be one of the following values:
3994 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3995 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3996 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3997 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3998 */
LL_ADC_INJ_GetSequencerLength(ADC_TypeDef * ADCx)3999 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4000 {
4001 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4002 }
4003
4004 /**
4005 * @brief Set ADC group injected sequencer discontinuous mode:
4006 * sequence subdivided and scan conversions interrupted every selected
4007 * number of ranks.
4008 * @note It is not possible to enable both ADC group injected
4009 * auto-injected mode and sequencer discontinuous mode.
4010 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4011 * @param ADCx ADC instance
4012 * @param SeqDiscont This parameter can be one of the following values:
4013 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4014 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4015 * @retval None
4016 */
LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)4017 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4018 {
4019 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4020 }
4021
4022 /**
4023 * @brief Get ADC group injected sequencer discontinuous mode:
4024 * sequence subdivided and scan conversions interrupted every selected
4025 * number of ranks.
4026 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4027 * @param ADCx ADC instance
4028 * @retval Returned value can be one of the following values:
4029 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4030 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4031 */
LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef * ADCx)4032 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4033 {
4034 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4035 }
4036
4037 /**
4038 * @brief Set ADC group injected sequence: channel on the selected
4039 * sequence rank.
4040 * @note Depending on devices and packages, some channels may not be available.
4041 * Refer to device datasheet for channels availability.
4042 * @note On this STM32 serie, to measure internal channels (VrefInt,
4043 * TempSensor, ...), measurement paths to internal channels must be
4044 * enabled separately.
4045 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4046 * @note On STM32L4, some fast channels are available: fast analog inputs
4047 * coming from GPIO pads (ADC_IN1..5).
4048 * @note On this STM32 serie, setting of this feature is conditioned to
4049 * ADC state:
4050 * ADC must not be disabled. Can be enabled with or without conversion
4051 * on going on either groups regular or injected.
4052 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4053 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4054 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4055 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4056 * @param ADCx ADC instance
4057 * @param Rank This parameter can be one of the following values:
4058 * @arg @ref LL_ADC_INJ_RANK_1
4059 * @arg @ref LL_ADC_INJ_RANK_2
4060 * @arg @ref LL_ADC_INJ_RANK_3
4061 * @arg @ref LL_ADC_INJ_RANK_4
4062 * @param Channel This parameter can be one of the following values:
4063 * @arg @ref LL_ADC_CHANNEL_0
4064 * @arg @ref LL_ADC_CHANNEL_1 (7)
4065 * @arg @ref LL_ADC_CHANNEL_2 (7)
4066 * @arg @ref LL_ADC_CHANNEL_3 (7)
4067 * @arg @ref LL_ADC_CHANNEL_4 (7)
4068 * @arg @ref LL_ADC_CHANNEL_5 (7)
4069 * @arg @ref LL_ADC_CHANNEL_6
4070 * @arg @ref LL_ADC_CHANNEL_7
4071 * @arg @ref LL_ADC_CHANNEL_8
4072 * @arg @ref LL_ADC_CHANNEL_9
4073 * @arg @ref LL_ADC_CHANNEL_10
4074 * @arg @ref LL_ADC_CHANNEL_11
4075 * @arg @ref LL_ADC_CHANNEL_12
4076 * @arg @ref LL_ADC_CHANNEL_13
4077 * @arg @ref LL_ADC_CHANNEL_14
4078 * @arg @ref LL_ADC_CHANNEL_15
4079 * @arg @ref LL_ADC_CHANNEL_16
4080 * @arg @ref LL_ADC_CHANNEL_17
4081 * @arg @ref LL_ADC_CHANNEL_18
4082 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4083 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4084 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4085 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4086 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4087 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4088 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4089 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4090 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4091 *
4092 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4093 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4094 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4095 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4096 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4097 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4098 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4099 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4100 * @retval None
4101 */
LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)4102 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4103 {
4104 /* Set bits with content of parameter "Channel" with bits position */
4105 /* in register depending on parameter "Rank". */
4106 /* Parameters "Rank" and "Channel" are used with masks because containing */
4107 /* other bits reserved for other purpose. */
4108 MODIFY_REG(ADCx->JSQR,
4109 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4110 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4111 }
4112
4113 /**
4114 * @brief Get ADC group injected sequence: channel on the selected
4115 * sequence rank.
4116 * @note Depending on devices and packages, some channels may not be available.
4117 * Refer to device datasheet for channels availability.
4118 * @note Usage of the returned channel number:
4119 * - To reinject this channel into another function LL_ADC_xxx:
4120 * the returned channel number is only partly formatted on definition
4121 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4122 * with parts of literals LL_ADC_CHANNEL_x or using
4123 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4124 * Then the selected literal LL_ADC_CHANNEL_x can be used
4125 * as parameter for another function.
4126 * - To get the channel number in decimal format:
4127 * process the returned value with the helper macro
4128 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4129 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4130 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4131 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4132 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4133 * @param ADCx ADC instance
4134 * @param Rank This parameter can be one of the following values:
4135 * @arg @ref LL_ADC_INJ_RANK_1
4136 * @arg @ref LL_ADC_INJ_RANK_2
4137 * @arg @ref LL_ADC_INJ_RANK_3
4138 * @arg @ref LL_ADC_INJ_RANK_4
4139 * @retval Returned value can be one of the following values:
4140 * @arg @ref LL_ADC_CHANNEL_0
4141 * @arg @ref LL_ADC_CHANNEL_1 (7)
4142 * @arg @ref LL_ADC_CHANNEL_2 (7)
4143 * @arg @ref LL_ADC_CHANNEL_3 (7)
4144 * @arg @ref LL_ADC_CHANNEL_4 (7)
4145 * @arg @ref LL_ADC_CHANNEL_5 (7)
4146 * @arg @ref LL_ADC_CHANNEL_6
4147 * @arg @ref LL_ADC_CHANNEL_7
4148 * @arg @ref LL_ADC_CHANNEL_8
4149 * @arg @ref LL_ADC_CHANNEL_9
4150 * @arg @ref LL_ADC_CHANNEL_10
4151 * @arg @ref LL_ADC_CHANNEL_11
4152 * @arg @ref LL_ADC_CHANNEL_12
4153 * @arg @ref LL_ADC_CHANNEL_13
4154 * @arg @ref LL_ADC_CHANNEL_14
4155 * @arg @ref LL_ADC_CHANNEL_15
4156 * @arg @ref LL_ADC_CHANNEL_16
4157 * @arg @ref LL_ADC_CHANNEL_17
4158 * @arg @ref LL_ADC_CHANNEL_18
4159 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4160 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4161 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4162 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4163 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4164 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4165 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4166 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4167 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4168 *
4169 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4170 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4171 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4172 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4173 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4174 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4175 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4176 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n
4177 * (1, 2, 3, 4) For ADC channel read back from ADC register,
4178 * comparison with internal channel parameter to be done
4179 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4180 */
LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)4181 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4182 {
4183 return (uint32_t)((READ_BIT(ADCx->JSQR,
4184 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4185 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4186 );
4187 }
4188
4189 /**
4190 * @brief Set ADC group injected conversion trigger:
4191 * independent or from ADC group regular.
4192 * @note This mode can be used to extend number of data registers
4193 * updated after one ADC conversion trigger and with data
4194 * permanently kept (not erased by successive conversions of scan of
4195 * ADC sequencer ranks), up to 5 data registers:
4196 * 1 data register on ADC group regular, 4 data registers
4197 * on ADC group injected.
4198 * @note If ADC group injected injected trigger source is set to an
4199 * external trigger, this feature must be must be set to
4200 * independent trigger.
4201 * ADC group injected automatic trigger is compliant only with
4202 * group injected trigger source set to SW start, without any
4203 * further action on ADC group injected conversion start or stop:
4204 * in this case, ADC group injected is controlled only
4205 * from ADC group regular.
4206 * @note It is not possible to enable both ADC group injected
4207 * auto-injected mode and sequencer discontinuous mode.
4208 * @note On this STM32 serie, setting of this feature is conditioned to
4209 * ADC state:
4210 * ADC must be disabled or enabled without conversion on going
4211 * on either groups regular or injected.
4212 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4213 * @param ADCx ADC instance
4214 * @param TrigAuto This parameter can be one of the following values:
4215 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4216 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4217 * @retval None
4218 */
LL_ADC_INJ_SetTrigAuto(ADC_TypeDef * ADCx,uint32_t TrigAuto)4219 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4220 {
4221 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4222 }
4223
4224 /**
4225 * @brief Get ADC group injected conversion trigger:
4226 * independent or from ADC group regular.
4227 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4228 * @param ADCx ADC instance
4229 * @retval Returned value can be one of the following values:
4230 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4231 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4232 */
LL_ADC_INJ_GetTrigAuto(ADC_TypeDef * ADCx)4233 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4234 {
4235 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4236 }
4237
4238 /**
4239 * @brief Set ADC group injected contexts queue mode.
4240 * @note A context is a setting of group injected sequencer:
4241 * - group injected trigger
4242 * - sequencer length
4243 * - sequencer ranks
4244 * If contexts queue is disabled:
4245 * - only 1 sequence can be configured
4246 * and is active perpetually.
4247 * If contexts queue is enabled:
4248 * - up to 2 contexts can be queued
4249 * and are checked in and out as a FIFO stack (first-in, first-out).
4250 * - If a new context is set when queues is full, error is triggered
4251 * by interruption "Injected Queue Overflow".
4252 * - Two behaviors are possible when all contexts have been processed:
4253 * the contexts queue can maintain the last context active perpetually
4254 * or can be empty and injected group triggers are disabled.
4255 * - Triggers can be only external (not internal SW start)
4256 * - Caution: The sequence must be fully configured in one time
4257 * (one write of register JSQR makes a check-in of a new context
4258 * into the queue).
4259 * Therefore functions to set separately injected trigger and
4260 * sequencer channels cannot be used, register JSQR must be set
4261 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4262 * @note This parameter can be modified only when no conversion is on going
4263 * on either groups regular or injected.
4264 * @note A modification of the context mode (bit JQDIS) causes the contexts
4265 * queue to be flushed and the register JSQR is cleared.
4266 * @note On this STM32 serie, setting of this feature is conditioned to
4267 * ADC state:
4268 * ADC must be disabled or enabled without conversion on going
4269 * on either groups regular or injected.
4270 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4271 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4272 * @param ADCx ADC instance
4273 * @param QueueMode This parameter can be one of the following values:
4274 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4275 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4276 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4277 * @retval None
4278 */
LL_ADC_INJ_SetQueueMode(ADC_TypeDef * ADCx,uint32_t QueueMode)4279 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4280 {
4281 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4282 }
4283
4284 /**
4285 * @brief Get ADC group injected context queue mode.
4286 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4287 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4288 * @param ADCx ADC instance
4289 * @retval Returned value can be one of the following values:
4290 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4291 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4292 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4293 */
LL_ADC_INJ_GetQueueMode(ADC_TypeDef * ADCx)4294 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4295 {
4296 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4297 }
4298
4299 /**
4300 * @brief Set one context on ADC group injected that will be checked in
4301 * contexts queue.
4302 * @note A context is a setting of group injected sequencer:
4303 * - group injected trigger
4304 * - sequencer length
4305 * - sequencer ranks
4306 * This function is intended to be used when contexts queue is enabled,
4307 * because the sequence must be fully configured in one time
4308 * (functions to set separately injected trigger and sequencer channels
4309 * cannot be used):
4310 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4311 * @note In the contexts queue, only the active context can be read.
4312 * The parameters of this function can be read using functions:
4313 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4314 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4315 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4316 * @note On this STM32 serie, to measure internal channels (VrefInt,
4317 * TempSensor, ...), measurement paths to internal channels must be
4318 * enabled separately.
4319 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4320 * @note On STM32L4, some fast channels are available: fast analog inputs
4321 * coming from GPIO pads (ADC_IN1..5).
4322 * @note On this STM32 serie, setting of this feature is conditioned to
4323 * ADC state:
4324 * ADC must not be disabled. Can be enabled with or without conversion
4325 * on going on either groups regular or injected.
4326 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4327 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4328 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4329 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4330 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4331 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4332 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4333 * @param ADCx ADC instance
4334 * @param TriggerSource This parameter can be one of the following values:
4335 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4336 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4337 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4338 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4339 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4340 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
4341 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4342 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
4343 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
4344 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
4345 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4346 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4347 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4348 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4349 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4350 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4351 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
4352 * @param ExternalTriggerEdge This parameter can be one of the following values:
4353 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4354 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4355 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4356 *
4357 * Note: This parameter is discarded in case of SW start:
4358 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4359 * @param SequencerNbRanks This parameter can be one of the following values:
4360 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4361 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4362 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4363 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4364 * @param Rank1_Channel This parameter can be one of the following values:
4365 * @arg @ref LL_ADC_CHANNEL_0
4366 * @arg @ref LL_ADC_CHANNEL_1 (7)
4367 * @arg @ref LL_ADC_CHANNEL_2 (7)
4368 * @arg @ref LL_ADC_CHANNEL_3 (7)
4369 * @arg @ref LL_ADC_CHANNEL_4 (7)
4370 * @arg @ref LL_ADC_CHANNEL_5 (7)
4371 * @arg @ref LL_ADC_CHANNEL_6
4372 * @arg @ref LL_ADC_CHANNEL_7
4373 * @arg @ref LL_ADC_CHANNEL_8
4374 * @arg @ref LL_ADC_CHANNEL_9
4375 * @arg @ref LL_ADC_CHANNEL_10
4376 * @arg @ref LL_ADC_CHANNEL_11
4377 * @arg @ref LL_ADC_CHANNEL_12
4378 * @arg @ref LL_ADC_CHANNEL_13
4379 * @arg @ref LL_ADC_CHANNEL_14
4380 * @arg @ref LL_ADC_CHANNEL_15
4381 * @arg @ref LL_ADC_CHANNEL_16
4382 * @arg @ref LL_ADC_CHANNEL_17
4383 * @arg @ref LL_ADC_CHANNEL_18
4384 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4385 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4386 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4387 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4388 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4389 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4390 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4391 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4392 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4393 *
4394 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4395 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4396 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4397 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4398 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4399 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4400 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4401 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4402 * @param Rank2_Channel This parameter can be one of the following values:
4403 * @arg @ref LL_ADC_CHANNEL_0
4404 * @arg @ref LL_ADC_CHANNEL_1 (7)
4405 * @arg @ref LL_ADC_CHANNEL_2 (7)
4406 * @arg @ref LL_ADC_CHANNEL_3 (7)
4407 * @arg @ref LL_ADC_CHANNEL_4 (7)
4408 * @arg @ref LL_ADC_CHANNEL_5 (7)
4409 * @arg @ref LL_ADC_CHANNEL_6
4410 * @arg @ref LL_ADC_CHANNEL_7
4411 * @arg @ref LL_ADC_CHANNEL_8
4412 * @arg @ref LL_ADC_CHANNEL_9
4413 * @arg @ref LL_ADC_CHANNEL_10
4414 * @arg @ref LL_ADC_CHANNEL_11
4415 * @arg @ref LL_ADC_CHANNEL_12
4416 * @arg @ref LL_ADC_CHANNEL_13
4417 * @arg @ref LL_ADC_CHANNEL_14
4418 * @arg @ref LL_ADC_CHANNEL_15
4419 * @arg @ref LL_ADC_CHANNEL_16
4420 * @arg @ref LL_ADC_CHANNEL_17
4421 * @arg @ref LL_ADC_CHANNEL_18
4422 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4423 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4424 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4425 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4426 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4427 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4428 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4429 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4430 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4431 *
4432 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4433 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4434 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4435 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4436 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4437 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4438 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4439 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4440 * @param Rank3_Channel This parameter can be one of the following values:
4441 * @arg @ref LL_ADC_CHANNEL_0
4442 * @arg @ref LL_ADC_CHANNEL_1 (7)
4443 * @arg @ref LL_ADC_CHANNEL_2 (7)
4444 * @arg @ref LL_ADC_CHANNEL_3 (7)
4445 * @arg @ref LL_ADC_CHANNEL_4 (7)
4446 * @arg @ref LL_ADC_CHANNEL_5 (7)
4447 * @arg @ref LL_ADC_CHANNEL_6
4448 * @arg @ref LL_ADC_CHANNEL_7
4449 * @arg @ref LL_ADC_CHANNEL_8
4450 * @arg @ref LL_ADC_CHANNEL_9
4451 * @arg @ref LL_ADC_CHANNEL_10
4452 * @arg @ref LL_ADC_CHANNEL_11
4453 * @arg @ref LL_ADC_CHANNEL_12
4454 * @arg @ref LL_ADC_CHANNEL_13
4455 * @arg @ref LL_ADC_CHANNEL_14
4456 * @arg @ref LL_ADC_CHANNEL_15
4457 * @arg @ref LL_ADC_CHANNEL_16
4458 * @arg @ref LL_ADC_CHANNEL_17
4459 * @arg @ref LL_ADC_CHANNEL_18
4460 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4461 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4462 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4463 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4464 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4465 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4466 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4467 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4468 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4469 *
4470 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4471 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4472 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4473 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4474 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4475 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4476 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4477 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4478 * @param Rank4_Channel This parameter can be one of the following values:
4479 * @arg @ref LL_ADC_CHANNEL_0
4480 * @arg @ref LL_ADC_CHANNEL_1 (7)
4481 * @arg @ref LL_ADC_CHANNEL_2 (7)
4482 * @arg @ref LL_ADC_CHANNEL_3 (7)
4483 * @arg @ref LL_ADC_CHANNEL_4 (7)
4484 * @arg @ref LL_ADC_CHANNEL_5 (7)
4485 * @arg @ref LL_ADC_CHANNEL_6
4486 * @arg @ref LL_ADC_CHANNEL_7
4487 * @arg @ref LL_ADC_CHANNEL_8
4488 * @arg @ref LL_ADC_CHANNEL_9
4489 * @arg @ref LL_ADC_CHANNEL_10
4490 * @arg @ref LL_ADC_CHANNEL_11
4491 * @arg @ref LL_ADC_CHANNEL_12
4492 * @arg @ref LL_ADC_CHANNEL_13
4493 * @arg @ref LL_ADC_CHANNEL_14
4494 * @arg @ref LL_ADC_CHANNEL_15
4495 * @arg @ref LL_ADC_CHANNEL_16
4496 * @arg @ref LL_ADC_CHANNEL_17
4497 * @arg @ref LL_ADC_CHANNEL_18
4498 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4499 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4500 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4501 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4502 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4503 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4504 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4505 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4506 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4507 *
4508 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4509 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4510 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4511 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4512 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4513 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4514 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4515 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4516 * @retval None
4517 */
LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef * ADCx,uint32_t TriggerSource,uint32_t ExternalTriggerEdge,uint32_t SequencerNbRanks,uint32_t Rank1_Channel,uint32_t Rank2_Channel,uint32_t Rank3_Channel,uint32_t Rank4_Channel)4518 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
4519 uint32_t TriggerSource,
4520 uint32_t ExternalTriggerEdge,
4521 uint32_t SequencerNbRanks,
4522 uint32_t Rank1_Channel,
4523 uint32_t Rank2_Channel,
4524 uint32_t Rank3_Channel,
4525 uint32_t Rank4_Channel)
4526 {
4527 /* Set bits with content of parameter "Rankx_Channel" with bits position */
4528 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
4529 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
4530 /* because containing other bits reserved for other purpose. */
4531 /* If parameter "TriggerSource" is set to SW start, then parameter */
4532 /* "ExternalTriggerEdge" is discarded. */
4533 register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
4534 MODIFY_REG(ADCx->JSQR ,
4535 ADC_JSQR_JEXTSEL |
4536 ADC_JSQR_JEXTEN |
4537 ADC_JSQR_JSQ4 |
4538 ADC_JSQR_JSQ3 |
4539 ADC_JSQR_JSQ2 |
4540 ADC_JSQR_JSQ1 |
4541 ADC_JSQR_JL ,
4542 TriggerSource |
4543 (ExternalTriggerEdge * (is_trigger_not_sw)) |
4544 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4545 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4546 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4547 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
4548 SequencerNbRanks
4549 );
4550 }
4551
4552 /**
4553 * @}
4554 */
4555
4556 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
4557 * @{
4558 */
4559
4560 /**
4561 * @brief Set sampling time of the selected ADC channel
4562 * Unit: ADC clock cycles.
4563 * @note On this device, sampling time is on channel scope: independently
4564 * of channel mapped on ADC group regular or injected.
4565 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
4566 * converted:
4567 * sampling time constraints must be respected (sampling time can be
4568 * adjusted in function of ADC clock frequency and sampling time
4569 * setting).
4570 * Refer to device datasheet for timings values (parameters TS_vrefint,
4571 * TS_temp, ...).
4572 * @note Conversion time is the addition of sampling time and processing time.
4573 * On this STM32 serie, ADC processing time is:
4574 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4575 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4576 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4577 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4578 * @note In case of ADC conversion of internal channel (VrefInt,
4579 * temperature sensor, ...), a sampling time minimum value
4580 * is required.
4581 * Refer to device datasheet.
4582 * @note On this STM32 serie, setting of this feature is conditioned to
4583 * ADC state:
4584 * ADC must be disabled or enabled without conversion on going
4585 * on either groups regular or injected.
4586 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
4587 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
4588 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
4589 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
4590 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
4591 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
4592 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
4593 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
4594 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
4595 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
4596 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
4597 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
4598 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
4599 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
4600 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
4601 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
4602 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
4603 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
4604 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
4605 * @param ADCx ADC instance
4606 * @param Channel This parameter can be one of the following values:
4607 * @arg @ref LL_ADC_CHANNEL_0
4608 * @arg @ref LL_ADC_CHANNEL_1 (7)
4609 * @arg @ref LL_ADC_CHANNEL_2 (7)
4610 * @arg @ref LL_ADC_CHANNEL_3 (7)
4611 * @arg @ref LL_ADC_CHANNEL_4 (7)
4612 * @arg @ref LL_ADC_CHANNEL_5 (7)
4613 * @arg @ref LL_ADC_CHANNEL_6
4614 * @arg @ref LL_ADC_CHANNEL_7
4615 * @arg @ref LL_ADC_CHANNEL_8
4616 * @arg @ref LL_ADC_CHANNEL_9
4617 * @arg @ref LL_ADC_CHANNEL_10
4618 * @arg @ref LL_ADC_CHANNEL_11
4619 * @arg @ref LL_ADC_CHANNEL_12
4620 * @arg @ref LL_ADC_CHANNEL_13
4621 * @arg @ref LL_ADC_CHANNEL_14
4622 * @arg @ref LL_ADC_CHANNEL_15
4623 * @arg @ref LL_ADC_CHANNEL_16
4624 * @arg @ref LL_ADC_CHANNEL_17
4625 * @arg @ref LL_ADC_CHANNEL_18
4626 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4627 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4628 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4629 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4630 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4631 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4632 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4633 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4634 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4635 *
4636 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4637 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4638 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4639 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4640 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4641 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4642 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4643 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4644 * @param SamplingTime This parameter can be one of the following values:
4645 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4646 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4647 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4648 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4649 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4650 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4651 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4652 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4653 *
4654 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4655 * can be replaced by 3.5 ADC clock cycles.
4656 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4657 * @retval None
4658 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTime)4659 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
4660 {
4661 /* Set bits with content of parameter "SamplingTime" with bits position */
4662 /* in register and register position depending on parameter "Channel". */
4663 /* Parameter "Channel" is used with masks because containing */
4664 /* other bits reserved for other purpose. */
4665 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4666
4667 MODIFY_REG(*preg,
4668 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
4669 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
4670 }
4671
4672 /**
4673 * @brief Get sampling time of the selected ADC channel
4674 * Unit: ADC clock cycles.
4675 * @note On this device, sampling time is on channel scope: independently
4676 * of channel mapped on ADC group regular or injected.
4677 * @note Conversion time is the addition of sampling time and processing time.
4678 * On this STM32 serie, ADC processing time is:
4679 * - 12.5 ADC clock cycles at ADC resolution 12 bits
4680 * - 10.5 ADC clock cycles at ADC resolution 10 bits
4681 * - 8.5 ADC clock cycles at ADC resolution 8 bits
4682 * - 6.5 ADC clock cycles at ADC resolution 6 bits
4683 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
4684 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
4685 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
4686 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
4687 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
4688 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
4689 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
4690 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
4691 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
4692 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
4693 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
4694 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
4695 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
4696 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
4697 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
4698 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
4699 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
4700 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
4701 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
4702 * @param ADCx ADC instance
4703 * @param Channel This parameter can be one of the following values:
4704 * @arg @ref LL_ADC_CHANNEL_0
4705 * @arg @ref LL_ADC_CHANNEL_1 (7)
4706 * @arg @ref LL_ADC_CHANNEL_2 (7)
4707 * @arg @ref LL_ADC_CHANNEL_3 (7)
4708 * @arg @ref LL_ADC_CHANNEL_4 (7)
4709 * @arg @ref LL_ADC_CHANNEL_5 (7)
4710 * @arg @ref LL_ADC_CHANNEL_6
4711 * @arg @ref LL_ADC_CHANNEL_7
4712 * @arg @ref LL_ADC_CHANNEL_8
4713 * @arg @ref LL_ADC_CHANNEL_9
4714 * @arg @ref LL_ADC_CHANNEL_10
4715 * @arg @ref LL_ADC_CHANNEL_11
4716 * @arg @ref LL_ADC_CHANNEL_12
4717 * @arg @ref LL_ADC_CHANNEL_13
4718 * @arg @ref LL_ADC_CHANNEL_14
4719 * @arg @ref LL_ADC_CHANNEL_15
4720 * @arg @ref LL_ADC_CHANNEL_16
4721 * @arg @ref LL_ADC_CHANNEL_17
4722 * @arg @ref LL_ADC_CHANNEL_18
4723 * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
4724 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (4)
4725 * @arg @ref LL_ADC_CHANNEL_VBAT (4)
4726 * @arg @ref LL_ADC_CHANNEL_DAC1CH1 (5)
4727 * @arg @ref LL_ADC_CHANNEL_DAC1CH2 (5)
4728 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
4729 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
4730 * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)
4731 * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)
4732 *
4733 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
4734 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
4735 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
4736 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n
4737 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
4738 * (6) On STM32L4, parameter available on devices with several ADC instances.\n
4739 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
4740 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).
4741 * @retval Returned value can be one of the following values:
4742 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
4743 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
4744 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
4745 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
4746 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
4747 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
4748 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
4749 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
4750 *
4751 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
4752 * can be replaced by 3.5 ADC clock cycles.
4753 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
4754 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)4755 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
4756 {
4757 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
4758
4759 return (uint32_t)(READ_BIT(*preg,
4760 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
4761 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
4762 );
4763 }
4764
4765 /**
4766 * @brief Set mode single-ended or differential input of the selected
4767 * ADC channel.
4768 * @note Channel ending is on channel scope: independently of channel mapped
4769 * on ADC group regular or injected.
4770 * In differential mode: Differential measurement is carried out
4771 * between the selected channel 'i' (positive input) and
4772 * channel 'i+1' (negative input). Only channel 'i' has to be
4773 * configured, channel 'i+1' is configured automatically.
4774 * @note Refer to Reference Manual to ensure the selected channel is
4775 * available in differential mode.
4776 * For example, internal channels (VrefInt, TempSensor, ...) are
4777 * not available in differential mode.
4778 * @note When configuring a channel 'i' in differential mode,
4779 * the channel 'i+1' is not usable separately.
4780 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4781 * are internally fixed to single-ended inputs configuration.
4782 * @note For ADC channels configured in differential mode, both inputs
4783 * should be biased at (Vref+)/2 +/-200mV.
4784 * (Vref+ is the analog voltage reference)
4785 * @note On this STM32 serie, setting of this feature is conditioned to
4786 * ADC state:
4787 * ADC must be ADC disabled.
4788 * @note One or several values can be selected.
4789 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4790 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
4791 * @param ADCx ADC instance
4792 * @param Channel This parameter can be one of the following values:
4793 * @arg @ref LL_ADC_CHANNEL_1
4794 * @arg @ref LL_ADC_CHANNEL_2
4795 * @arg @ref LL_ADC_CHANNEL_3
4796 * @arg @ref LL_ADC_CHANNEL_4
4797 * @arg @ref LL_ADC_CHANNEL_5
4798 * @arg @ref LL_ADC_CHANNEL_6
4799 * @arg @ref LL_ADC_CHANNEL_7
4800 * @arg @ref LL_ADC_CHANNEL_8
4801 * @arg @ref LL_ADC_CHANNEL_9
4802 * @arg @ref LL_ADC_CHANNEL_10
4803 * @arg @ref LL_ADC_CHANNEL_11
4804 * @arg @ref LL_ADC_CHANNEL_12
4805 * @arg @ref LL_ADC_CHANNEL_13
4806 * @arg @ref LL_ADC_CHANNEL_14
4807 * @arg @ref LL_ADC_CHANNEL_15
4808 * @param SingleDiff This parameter can be a combination of the following values:
4809 * @arg @ref LL_ADC_SINGLE_ENDED
4810 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
4811 * @retval None
4812 */
LL_ADC_SetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SingleDiff)4813 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
4814 {
4815 /* Bits of channels in single or differential mode are set only for */
4816 /* differential mode (for single mode, mask of bits allowed to be set is */
4817 /* shifted out of range of bits of channels in single or differential mode. */
4818 MODIFY_REG(ADCx->DIFSEL,
4819 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
4820 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
4821 }
4822
4823 /**
4824 * @brief Get mode single-ended or differential input of the selected
4825 * ADC channel.
4826 * @note When configuring a channel 'i' in differential mode,
4827 * the channel 'i+1' is not usable separately.
4828 * Therefore, to ensure a channel is configured in single-ended mode,
4829 * the configuration of channel itself and the channel 'i-1' must be
4830 * read back (to ensure that the selected channel channel has not been
4831 * configured in differential mode by the previous channel).
4832 * @note Refer to Reference Manual to ensure the selected channel is
4833 * available in differential mode.
4834 * For example, internal channels (VrefInt, TempSensor, ...) are
4835 * not available in differential mode.
4836 * @note When configuring a channel 'i' in differential mode,
4837 * the channel 'i+1' is not usable separately.
4838 * @note On STM32L4, channels 16, 17, 18 of ADC1, ADC2, ADC3 (if available)
4839 * are internally fixed to single-ended inputs configuration.
4840 * @note One or several values can be selected. In this case, the value
4841 * returned is null if all channels are in single ended-mode.
4842 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
4843 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
4844 * @param ADCx ADC instance
4845 * @param Channel This parameter can be a combination of the following values:
4846 * @arg @ref LL_ADC_CHANNEL_1
4847 * @arg @ref LL_ADC_CHANNEL_2
4848 * @arg @ref LL_ADC_CHANNEL_3
4849 * @arg @ref LL_ADC_CHANNEL_4
4850 * @arg @ref LL_ADC_CHANNEL_5
4851 * @arg @ref LL_ADC_CHANNEL_6
4852 * @arg @ref LL_ADC_CHANNEL_7
4853 * @arg @ref LL_ADC_CHANNEL_8
4854 * @arg @ref LL_ADC_CHANNEL_9
4855 * @arg @ref LL_ADC_CHANNEL_10
4856 * @arg @ref LL_ADC_CHANNEL_11
4857 * @arg @ref LL_ADC_CHANNEL_12
4858 * @arg @ref LL_ADC_CHANNEL_13
4859 * @arg @ref LL_ADC_CHANNEL_14
4860 * @arg @ref LL_ADC_CHANNEL_15
4861 * @retval 0: channel in single-ended mode, else: channel in differential mode
4862 */
LL_ADC_GetChannelSingleDiff(ADC_TypeDef * ADCx,uint32_t Channel)4863 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
4864 {
4865 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
4866 }
4867
4868 /**
4869 * @}
4870 */
4871
4872 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
4873 * @{
4874 */
4875
4876 /**
4877 * @brief Set ADC analog watchdog monitored channels:
4878 * a single channel, multiple channels or all channels,
4879 * on ADC groups regular and-or injected.
4880 * @note Once monitored channels are selected, analog watchdog
4881 * is enabled.
4882 * @note In case of need to define a single channel to monitor
4883 * with analog watchdog from sequencer channel definition,
4884 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
4885 * @note On this STM32 serie, there are 2 kinds of analog watchdog
4886 * instance:
4887 * - AWD standard (instance AWD1):
4888 * - channels monitored: can monitor 1 channel or all channels.
4889 * - groups monitored: ADC groups regular and-or injected.
4890 * - resolution: resolution is not limited (corresponds to
4891 * ADC resolution configured).
4892 * - AWD flexible (instances AWD2, AWD3):
4893 * - channels monitored: flexible on channels monitored, selection is
4894 * channel wise, from from 1 to all channels.
4895 * Specificity of this analog watchdog: Multiple channels can
4896 * be selected. For example:
4897 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
4898 * - groups monitored: not selection possible (monitoring on both
4899 * groups regular and injected).
4900 * Channels selected are monitored on groups regular and injected:
4901 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
4902 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
4903 * - resolution: resolution is limited to 8 bits: if ADC resolution is
4904 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
4905 * the 2 LSB are ignored.
4906 * @note On this STM32 serie, setting of this feature is conditioned to
4907 * ADC state:
4908 * ADC must be disabled or enabled without conversion on going
4909 * on either groups regular or injected.
4910 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
4911 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
4912 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4913 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
4914 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
4915 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
4916 * @param ADCx ADC instance
4917 * @param AWDy This parameter can be one of the following values:
4918 * @arg @ref LL_ADC_AWD1
4919 * @arg @ref LL_ADC_AWD2
4920 * @arg @ref LL_ADC_AWD3
4921 * @param AWDChannelGroup This parameter can be one of the following values:
4922 * @arg @ref LL_ADC_AWD_DISABLE
4923 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
4924 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
4925 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4926 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
4927 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
4928 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
4929 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
4930 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
4931 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
4932 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
4933 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
4934 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
4935 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
4936 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
4937 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
4938 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
4939 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
4940 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
4941 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
4942 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
4943 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
4944 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
4945 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
4946 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
4947 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
4948 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
4949 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
4950 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
4951 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
4952 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
4953 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
4954 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
4955 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
4956 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
4957 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
4958 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
4959 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
4960 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
4961 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
4962 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
4963 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
4964 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
4965 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
4966 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
4967 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
4968 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
4969 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
4970 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
4971 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
4972 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
4973 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
4974 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
4975 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
4976 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
4977 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
4978 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
4979 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
4980 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
4981 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
4982 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
4983 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)(1)
4984 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)(1)
4985 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
4986 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (0)(4)
4987 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (0)(4)
4988 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (4)
4989 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(4)
4990 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(4)
4991 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (4)
4992 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG (0)(2)(5)
4993 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ (0)(2)(5)
4994 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ (2)(5)
4995 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG (0)(2)(5)
4996 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ (0)(2)(5)
4997 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ (2)(5)
4998 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG (0)(2)(6)
4999 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ (0)(2)(6)
5000 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ (2)(6)
5001 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)(6)
5002 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)(6)
5003 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)(6)
5004 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG (0)(3)(6)
5005 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ (0)(3)(6)
5006 * @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ (3)(6)
5007 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG (0)(3)(6)
5008 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ (0)(3)(6)
5009 * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ (3)(6)
5010 *
5011 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n
5012 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n
5013 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n
5014 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n
5015 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.
5016 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n
5017 * (6) On STM32L4, parameter available on devices with several ADC instances.
5018 * @retval None
5019 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)5020 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5021 {
5022 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5023 /* in register and register position depending on parameter "AWDy". */
5024 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5025 /* containing other bits reserved for other purpose. */
5026 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5027 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5028
5029 MODIFY_REG(*preg,
5030 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5031 AWDChannelGroup & AWDy);
5032 }
5033
5034 /**
5035 * @brief Get ADC analog watchdog monitored channel.
5036 * @note Usage of the returned channel number:
5037 * - To reinject this channel into another function LL_ADC_xxx:
5038 * the returned channel number is only partly formatted on definition
5039 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5040 * with parts of literals LL_ADC_CHANNEL_x or using
5041 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5042 * Then the selected literal LL_ADC_CHANNEL_x can be used
5043 * as parameter for another function.
5044 * - To get the channel number in decimal format:
5045 * process the returned value with the helper macro
5046 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5047 * Applicable only when the analog watchdog is set to monitor
5048 * one channel.
5049 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5050 * instance:
5051 * - AWD standard (instance AWD1):
5052 * - channels monitored: can monitor 1 channel or all channels.
5053 * - groups monitored: ADC groups regular and-or injected.
5054 * - resolution: resolution is not limited (corresponds to
5055 * ADC resolution configured).
5056 * - AWD flexible (instances AWD2, AWD3):
5057 * - channels monitored: flexible on channels monitored, selection is
5058 * channel wise, from from 1 to all channels.
5059 * Specificity of this analog watchdog: Multiple channels can
5060 * be selected. For example:
5061 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5062 * - groups monitored: not selection possible (monitoring on both
5063 * groups regular and injected).
5064 * Channels selected are monitored on groups regular and injected:
5065 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5066 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5067 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5068 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5069 * the 2 LSB are ignored.
5070 * @note On this STM32 serie, setting of this feature is conditioned to
5071 * ADC state:
5072 * ADC must be disabled or enabled without conversion on going
5073 * on either groups regular or injected.
5074 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5075 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5076 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5077 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5078 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5079 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5080 * @param ADCx ADC instance
5081 * @param AWDy This parameter can be one of the following values:
5082 * @arg @ref LL_ADC_AWD1
5083 * @arg @ref LL_ADC_AWD2 (1)
5084 * @arg @ref LL_ADC_AWD3 (1)
5085 *
5086 * (1) On this AWD number, monitored channel can be retrieved
5087 * if only 1 channel is programmed (or none or all channels).
5088 * This function cannot retrieve monitored channel if
5089 * multiple channels are programmed simultaneously
5090 * by bitfield.
5091 * @retval Returned value can be one of the following values:
5092 * @arg @ref LL_ADC_AWD_DISABLE
5093 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5094 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5095 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5096 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5097 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5098 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5099 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5100 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5101 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5102 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5103 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5104 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5105 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5106 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5107 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5108 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5109 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5110 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5111 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5112 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5113 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5114 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5115 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5116 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5117 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5118 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5119 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5120 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5121 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5122 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5123 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5124 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5125 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5126 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5127 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5128 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5129 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5130 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5131 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5132 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5133 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5134 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5135 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5136 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5137 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5138 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5139 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5140 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5141 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5142 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5143 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5144 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5145 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5146 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5147 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5148 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5149 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5150 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5151 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5152 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5153 *
5154 * (0) On STM32L4, parameter available only on analog watchdog number: AWD1.
5155 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)5156 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5157 {
5158 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5159 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5160
5161 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5162
5163 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5164 /* (parameter value LL_ADC_AWD_DISABLE). */
5165 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5166 /* or a single channel. */
5167 if(AnalogWDMonitChannels != 0UL)
5168 {
5169 if(AWDy == LL_ADC_AWD1)
5170 {
5171 if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5172 {
5173 /* AWD monitoring a group of channels */
5174 AnalogWDMonitChannels = (( AnalogWDMonitChannels
5175 | (ADC_AWD_CR23_CHANNEL_MASK)
5176 )
5177 & (~(ADC_CFGR_AWD1CH))
5178 );
5179 }
5180 else
5181 {
5182 /* AWD monitoring a single channel */
5183 AnalogWDMonitChannels = (AnalogWDMonitChannels
5184 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5185 );
5186 }
5187 }
5188 else
5189 {
5190 if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5191 {
5192 /* AWD monitoring a group of channels */
5193 AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK
5194 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5195 );
5196 }
5197 else
5198 {
5199 /* AWD monitoring a single channel */
5200 /* AWD monitoring a group of channels */
5201 AnalogWDMonitChannels = ( AnalogWDMonitChannels
5202 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5203 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5204 );
5205 }
5206 }
5207 }
5208
5209 return AnalogWDMonitChannels;
5210
5211 }
5212
5213 /**
5214 * @brief Set ADC analog watchdog thresholds value of both thresholds
5215 * high and low.
5216 * @note If value of only one threshold high or low must be set,
5217 * use function @ref LL_ADC_SetAnalogWDThresholds().
5218 * @note In case of ADC resolution different of 12 bits,
5219 * analog watchdog thresholds data require a specific shift.
5220 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5221 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5222 * instance:
5223 * - AWD standard (instance AWD1):
5224 * - channels monitored: can monitor 1 channel or all channels.
5225 * - groups monitored: ADC groups regular and-or injected.
5226 * - resolution: resolution is not limited (corresponds to
5227 * ADC resolution configured).
5228 * - AWD flexible (instances AWD2, AWD3):
5229 * - channels monitored: flexible on channels monitored, selection is
5230 * channel wise, from from 1 to all channels.
5231 * Specificity of this analog watchdog: Multiple channels can
5232 * be selected. For example:
5233 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5234 * - groups monitored: not selection possible (monitoring on both
5235 * groups regular and injected).
5236 * Channels selected are monitored on groups regular and injected:
5237 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5238 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5239 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5240 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5241 * the 2 LSB are ignored.
5242 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5243 * impacted: the comparison of analog watchdog thresholds is done on
5244 * oversampling final computation (after ratio and shift application):
5245 * ADC data register bitfield [15:4] (12 most significant bits).
5246 * @note On this STM32 serie, setting of this feature is conditioned to
5247 * ADC state:
5248 * ADC must be disabled or enabled without conversion on going
5249 * on either groups regular or injected.
5250 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5251 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5252 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5253 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5254 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5255 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5256 * @param ADCx ADC instance
5257 * @param AWDy This parameter can be one of the following values:
5258 * @arg @ref LL_ADC_AWD1
5259 * @arg @ref LL_ADC_AWD2
5260 * @arg @ref LL_ADC_AWD3
5261 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5262 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5263 * @retval None
5264 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)5265 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
5266 {
5267 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5268 /* position in register and register position depending on parameter */
5269 /* "AWDy". */
5270 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5271 /* containing other bits reserved for other purpose. */
5272 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5273
5274 MODIFY_REG(*preg,
5275 ADC_TR1_HT1 | ADC_TR1_LT1,
5276 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5277 }
5278
5279 /**
5280 * @brief Set ADC analog watchdog threshold value of threshold
5281 * high or low.
5282 * @note If values of both thresholds high or low must be set,
5283 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5284 * @note In case of ADC resolution different of 12 bits,
5285 * analog watchdog thresholds data require a specific shift.
5286 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5287 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5288 * instance:
5289 * - AWD standard (instance AWD1):
5290 * - channels monitored: can monitor 1 channel or all channels.
5291 * - groups monitored: ADC groups regular and-or injected.
5292 * - resolution: resolution is not limited (corresponds to
5293 * ADC resolution configured).
5294 * - AWD flexible (instances AWD2, AWD3):
5295 * - channels monitored: flexible on channels monitored, selection is
5296 * channel wise, from from 1 to all channels.
5297 * Specificity of this analog watchdog: Multiple channels can
5298 * be selected. For example:
5299 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5300 * - groups monitored: not selection possible (monitoring on both
5301 * groups regular and injected).
5302 * Channels selected are monitored on groups regular and injected:
5303 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5304 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5305 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5306 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5307 * the 2 LSB are ignored.
5308 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5309 * impacted: the comparison of analog watchdog thresholds is done on
5310 * oversampling final computation (after ratio and shift application):
5311 * ADC data register bitfield [15:4] (12 most significant bits).
5312 * @note On this STM32 serie, setting of this feature is conditioned to
5313 * ADC state:
5314 * ADC must be disabled or enabled without conversion on going
5315 * on either ADC groups regular or injected.
5316 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5317 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5318 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5319 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5320 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5321 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5322 * @param ADCx ADC instance
5323 * @param AWDy This parameter can be one of the following values:
5324 * @arg @ref LL_ADC_AWD1
5325 * @arg @ref LL_ADC_AWD2
5326 * @arg @ref LL_ADC_AWD3
5327 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5328 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5329 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5330 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5331 * @retval None
5332 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)5333 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
5334 {
5335 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5336 /* position in register and register position depending on parameters */
5337 /* "AWDThresholdsHighLow" and "AWDy". */
5338 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5339 /* containing other bits reserved for other purpose. */
5340 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5341
5342 MODIFY_REG(*preg,
5343 AWDThresholdsHighLow,
5344 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5345 }
5346
5347 /**
5348 * @brief Get ADC analog watchdog threshold value of threshold high,
5349 * threshold low or raw data with ADC thresholds high and low
5350 * concatenated.
5351 * @note If raw data with ADC thresholds high and low is retrieved,
5352 * the data of each threshold high or low can be isolated
5353 * using helper macro:
5354 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5355 * @note In case of ADC resolution different of 12 bits,
5356 * analog watchdog thresholds data require a specific shift.
5357 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5358 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5359 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5360 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5361 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5362 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5363 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5364 * @param ADCx ADC instance
5365 * @param AWDy This parameter can be one of the following values:
5366 * @arg @ref LL_ADC_AWD1
5367 * @arg @ref LL_ADC_AWD2
5368 * @arg @ref LL_ADC_AWD3
5369 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5370 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5371 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5372 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5373 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5374 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)5375 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5376 {
5377 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5378
5379 return (uint32_t)(READ_BIT(*preg,
5380 (AWDThresholdsHighLow | ADC_TR1_LT1))
5381 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
5382 );
5383 }
5384
5385 /**
5386 * @}
5387 */
5388
5389 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
5390 * @{
5391 */
5392
5393 /**
5394 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
5395 * (availability of ADC group injected depends on STM32 families).
5396 * @note If both groups regular and injected are selected,
5397 * specify behavior of ADC group injected interrupting
5398 * group regular: when ADC group injected is triggered,
5399 * the oversampling on ADC group regular is either
5400 * temporary stopped and continued, or resumed from start
5401 * (oversampler buffer reset).
5402 * @note On this STM32 serie, setting of this feature is conditioned to
5403 * ADC state:
5404 * ADC must be disabled or enabled without conversion on going
5405 * on either groups regular or injected.
5406 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
5407 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
5408 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
5409 * @param ADCx ADC instance
5410 * @param OvsScope This parameter can be one of the following values:
5411 * @arg @ref LL_ADC_OVS_DISABLE
5412 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5413 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5414 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5415 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5416 * @retval None
5417 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)5418 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
5419 {
5420 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
5421 }
5422
5423 /**
5424 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
5425 * (availability of ADC group injected depends on STM32 families).
5426 * @note If both groups regular and injected are selected,
5427 * specify behavior of ADC group injected interrupting
5428 * group regular: when ADC group injected is triggered,
5429 * the oversampling on ADC group regular is either
5430 * temporary stopped and continued, or resumed from start
5431 * (oversampler buffer reset).
5432 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
5433 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
5434 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
5435 * @param ADCx ADC instance
5436 * @retval Returned value can be one of the following values:
5437 * @arg @ref LL_ADC_OVS_DISABLE
5438 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
5439 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
5440 * @arg @ref LL_ADC_OVS_GRP_INJECTED
5441 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
5442 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)5443 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
5444 {
5445 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
5446 }
5447
5448 /**
5449 * @brief Set ADC oversampling discontinuous mode (triggered mode)
5450 * on the selected ADC group.
5451 * @note Number of oversampled conversions are done either in:
5452 * - continuous mode (all conversions of oversampling ratio
5453 * are done from 1 trigger)
5454 * - discontinuous mode (each conversion of oversampling ratio
5455 * needs a trigger)
5456 * @note On this STM32 serie, setting of this feature is conditioned to
5457 * ADC state:
5458 * ADC must be disabled or enabled without conversion on going
5459 * on group regular.
5460 * @note On this STM32 serie, oversampling discontinuous mode
5461 * (triggered mode) can be used only when oversampling is
5462 * set on group regular only and in resumed mode.
5463 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
5464 * @param ADCx ADC instance
5465 * @param OverSamplingDiscont This parameter can be one of the following values:
5466 * @arg @ref LL_ADC_OVS_REG_CONT
5467 * @arg @ref LL_ADC_OVS_REG_DISCONT
5468 * @retval None
5469 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)5470 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
5471 {
5472 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
5473 }
5474
5475 /**
5476 * @brief Get ADC oversampling discontinuous mode (triggered mode)
5477 * on the selected ADC group.
5478 * @note Number of oversampled conversions are done either in:
5479 * - continuous mode (all conversions of oversampling ratio
5480 * are done from 1 trigger)
5481 * - discontinuous mode (each conversion of oversampling ratio
5482 * needs a trigger)
5483 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
5484 * @param ADCx ADC instance
5485 * @retval Returned value can be one of the following values:
5486 * @arg @ref LL_ADC_OVS_REG_CONT
5487 * @arg @ref LL_ADC_OVS_REG_DISCONT
5488 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)5489 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
5490 {
5491 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
5492 }
5493
5494 /**
5495 * @brief Set ADC oversampling
5496 * (impacting both ADC groups regular and injected)
5497 * @note This function set the 2 items of oversampling configuration:
5498 * - ratio
5499 * - shift
5500 * @note On this STM32 serie, setting of this feature is conditioned to
5501 * ADC state:
5502 * ADC must be disabled or enabled without conversion on going
5503 * on either groups regular or injected.
5504 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
5505 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
5506 * @param ADCx ADC instance
5507 * @param Ratio This parameter can be one of the following values:
5508 * @arg @ref LL_ADC_OVS_RATIO_2
5509 * @arg @ref LL_ADC_OVS_RATIO_4
5510 * @arg @ref LL_ADC_OVS_RATIO_8
5511 * @arg @ref LL_ADC_OVS_RATIO_16
5512 * @arg @ref LL_ADC_OVS_RATIO_32
5513 * @arg @ref LL_ADC_OVS_RATIO_64
5514 * @arg @ref LL_ADC_OVS_RATIO_128
5515 * @arg @ref LL_ADC_OVS_RATIO_256
5516 * @param Shift This parameter can be one of the following values:
5517 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5518 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5519 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5520 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5521 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5522 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5523 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5524 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5525 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5526 * @retval None
5527 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)5528 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
5529 {
5530 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
5531 }
5532
5533 /**
5534 * @brief Get ADC oversampling ratio
5535 * (impacting both ADC groups regular and injected)
5536 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
5537 * @param ADCx ADC instance
5538 * @retval Ratio This parameter can be one of the following values:
5539 * @arg @ref LL_ADC_OVS_RATIO_2
5540 * @arg @ref LL_ADC_OVS_RATIO_4
5541 * @arg @ref LL_ADC_OVS_RATIO_8
5542 * @arg @ref LL_ADC_OVS_RATIO_16
5543 * @arg @ref LL_ADC_OVS_RATIO_32
5544 * @arg @ref LL_ADC_OVS_RATIO_64
5545 * @arg @ref LL_ADC_OVS_RATIO_128
5546 * @arg @ref LL_ADC_OVS_RATIO_256
5547 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)5548 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
5549 {
5550 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
5551 }
5552
5553 /**
5554 * @brief Get ADC oversampling shift
5555 * (impacting both ADC groups regular and injected)
5556 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
5557 * @param ADCx ADC instance
5558 * @retval Shift This parameter can be one of the following values:
5559 * @arg @ref LL_ADC_OVS_SHIFT_NONE
5560 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
5561 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
5562 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
5563 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
5564 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
5565 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
5566 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
5567 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
5568 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)5569 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
5570 {
5571 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
5572 }
5573
5574 /**
5575 * @}
5576 */
5577
5578 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
5579 * @{
5580 */
5581
5582 #if defined(ADC_MULTIMODE_SUPPORT)
5583 /**
5584 * @brief Set ADC multimode configuration to operate in independent mode
5585 * or multimode (for devices with several ADC instances).
5586 * @note If multimode configuration: the selected ADC instance is
5587 * either master or slave depending on hardware.
5588 * Refer to reference manual.
5589 * @note On this STM32 serie, setting of this feature is conditioned to
5590 * ADC state:
5591 * All ADC instances of the ADC common group must be disabled.
5592 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5593 * ADC instance or by using helper macro
5594 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5595 * @rmtoll CCR DUAL LL_ADC_SetMultimode
5596 * @param ADCxy_COMMON ADC common instance
5597 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5598 * @param Multimode This parameter can be one of the following values:
5599 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5600 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5601 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5602 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5603 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5604 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5605 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5606 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5607 * @retval None
5608 */
LL_ADC_SetMultimode(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t Multimode)5609 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
5610 {
5611 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
5612 }
5613
5614 /**
5615 * @brief Get ADC multimode configuration to operate in independent mode
5616 * or multimode (for devices with several ADC instances).
5617 * @note If multimode configuration: the selected ADC instance is
5618 * either master or slave depending on hardware.
5619 * Refer to reference manual.
5620 * @rmtoll CCR DUAL LL_ADC_GetMultimode
5621 * @param ADCxy_COMMON ADC common instance
5622 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5623 * @retval Returned value can be one of the following values:
5624 * @arg @ref LL_ADC_MULTI_INDEPENDENT
5625 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
5626 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
5627 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
5628 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
5629 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
5630 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
5631 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
5632 */
LL_ADC_GetMultimode(ADC_Common_TypeDef * ADCxy_COMMON)5633 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
5634 {
5635 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
5636 }
5637
5638 /**
5639 * @brief Set ADC multimode conversion data transfer: no transfer
5640 * or transfer by DMA.
5641 * @note If ADC multimode transfer by DMA is not selected:
5642 * each ADC uses its own DMA channel, with its individual
5643 * DMA transfer settings.
5644 * If ADC multimode transfer by DMA is selected:
5645 * One DMA channel is used for both ADC (DMA of ADC master)
5646 * Specifies the DMA requests mode:
5647 * - Limited mode (One shot mode): DMA transfer requests are stopped
5648 * when number of DMA data transfers (number of
5649 * ADC conversions) is reached.
5650 * This ADC mode is intended to be used with DMA mode non-circular.
5651 * - Unlimited mode: DMA transfer requests are unlimited,
5652 * whatever number of DMA data transfers (number of
5653 * ADC conversions).
5654 * This ADC mode is intended to be used with DMA mode circular.
5655 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5656 * mode non-circular:
5657 * when DMA transfers size will be reached, DMA will stop transfers of
5658 * ADC conversions data ADC will raise an overrun error
5659 * (overrun flag and interruption if enabled).
5660 * @note How to retrieve multimode conversion data:
5661 * Whatever multimode transfer by DMA setting: using function
5662 * @ref LL_ADC_REG_ReadMultiConversionData32().
5663 * If ADC multimode transfer by DMA is selected: conversion data
5664 * is a raw data with ADC master and slave concatenated.
5665 * A macro is available to get the conversion data of
5666 * ADC master or ADC slave: see helper macro
5667 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5668 * @note On this STM32 serie, setting of this feature is conditioned to
5669 * ADC state:
5670 * All ADC instances of the ADC common group must be disabled
5671 * or enabled without conversion on going on group regular.
5672 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
5673 * CCR DMACFG LL_ADC_SetMultiDMATransfer
5674 * @param ADCxy_COMMON ADC common instance
5675 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5676 * @param MultiDMATransfer This parameter can be one of the following values:
5677 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5678 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5679 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5680 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5681 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5682 * @retval None
5683 */
LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiDMATransfer)5684 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
5685 {
5686 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
5687 }
5688
5689 /**
5690 * @brief Get ADC multimode conversion data transfer: no transfer
5691 * or transfer by DMA.
5692 * @note If ADC multimode transfer by DMA is not selected:
5693 * each ADC uses its own DMA channel, with its individual
5694 * DMA transfer settings.
5695 * If ADC multimode transfer by DMA is selected:
5696 * One DMA channel is used for both ADC (DMA of ADC master)
5697 * Specifies the DMA requests mode:
5698 * - Limited mode (One shot mode): DMA transfer requests are stopped
5699 * when number of DMA data transfers (number of
5700 * ADC conversions) is reached.
5701 * This ADC mode is intended to be used with DMA mode non-circular.
5702 * - Unlimited mode: DMA transfer requests are unlimited,
5703 * whatever number of DMA data transfers (number of
5704 * ADC conversions).
5705 * This ADC mode is intended to be used with DMA mode circular.
5706 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
5707 * mode non-circular:
5708 * when DMA transfers size will be reached, DMA will stop transfers of
5709 * ADC conversions data ADC will raise an overrun error
5710 * (overrun flag and interruption if enabled).
5711 * @note How to retrieve multimode conversion data:
5712 * Whatever multimode transfer by DMA setting: using function
5713 * @ref LL_ADC_REG_ReadMultiConversionData32().
5714 * If ADC multimode transfer by DMA is selected: conversion data
5715 * is a raw data with ADC master and slave concatenated.
5716 * A macro is available to get the conversion data of
5717 * ADC master or ADC slave: see helper macro
5718 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
5719 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
5720 * CCR DMACFG LL_ADC_GetMultiDMATransfer
5721 * @param ADCxy_COMMON ADC common instance
5722 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5723 * @retval Returned value can be one of the following values:
5724 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
5725 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
5726 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
5727 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
5728 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
5729 */
LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef * ADCxy_COMMON)5730 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
5731 {
5732 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
5733 }
5734
5735 /**
5736 * @brief Set ADC multimode delay between 2 sampling phases.
5737 * @note The sampling delay range depends on ADC resolution:
5738 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
5739 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
5740 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
5741 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
5742 * @note On this STM32 serie, setting of this feature is conditioned to
5743 * ADC state:
5744 * All ADC instances of the ADC common group must be disabled.
5745 * This check can be done with function @ref LL_ADC_IsEnabled() for each
5746 * ADC instance or by using helper macro helper macro
5747 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
5748 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
5749 * @param ADCxy_COMMON ADC common instance
5750 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5751 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
5752 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5753 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5754 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5755 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5756 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5757 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5758 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5759 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5760 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5761 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5762 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5763 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5764 *
5765 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5766 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5767 * (3) Parameter available only if ADC resolution is 12 bits.
5768 * @retval None
5769 */
LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t MultiTwoSamplingDelay)5770 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
5771 {
5772 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
5773 }
5774
5775 /**
5776 * @brief Get ADC multimode delay between 2 sampling phases.
5777 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
5778 * @param ADCxy_COMMON ADC common instance
5779 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
5780 * @retval Returned value can be one of the following values:
5781 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
5782 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
5783 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
5784 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
5785 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
5786 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
5787 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
5788 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
5789 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
5790 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
5791 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
5792 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
5793 *
5794 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
5795 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
5796 * (3) Parameter available only if ADC resolution is 12 bits.
5797 */
LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef * ADCxy_COMMON)5798 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
5799 {
5800 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
5801 }
5802 #endif /* ADC_MULTIMODE_SUPPORT */
5803
5804 /**
5805 * @}
5806 */
5807 /** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name
5808 * @{
5809 */
5810 /* Old functions name kept for legacy purpose, to be replaced by the */
5811 /* current functions name. */
LL_ADC_REG_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5812 __STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5813 {
5814 LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);
5815 }
LL_ADC_INJ_SetTrigSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)5816 __STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
5817 {
5818 LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);
5819 }
5820
5821 /**
5822 * @}
5823 */
5824
5825 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
5826 * @{
5827 */
5828
5829 /**
5830 * @brief Put ADC instance in deep power down state.
5831 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5832 * state, the internal analog calibration is lost. After exiting from
5833 * deep power down, calibration must be relaunched or calibration factor
5834 * (preliminarily saved) must be set back into calibration register.
5835 * @note On this STM32 serie, setting of this feature is conditioned to
5836 * ADC state:
5837 * ADC must be ADC disabled.
5838 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
5839 * @param ADCx ADC instance
5840 * @retval None
5841 */
LL_ADC_EnableDeepPowerDown(ADC_TypeDef * ADCx)5842 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
5843 {
5844 /* Note: Write register with some additional bits forced to state reset */
5845 /* instead of modifying only the selected bit for this function, */
5846 /* to not interfere with bits with HW property "rs". */
5847 MODIFY_REG(ADCx->CR,
5848 ADC_CR_BITS_PROPERTY_RS,
5849 ADC_CR_DEEPPWD);
5850 }
5851
5852 /**
5853 * @brief Disable ADC deep power down mode.
5854 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
5855 * state, the internal analog calibration is lost. After exiting from
5856 * deep power down, calibration must be relaunched or calibration factor
5857 * (preliminarily saved) must be set back into calibration register.
5858 * @note On this STM32 serie, setting of this feature is conditioned to
5859 * ADC state:
5860 * ADC must be ADC disabled.
5861 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
5862 * @param ADCx ADC instance
5863 * @retval None
5864 */
LL_ADC_DisableDeepPowerDown(ADC_TypeDef * ADCx)5865 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
5866 {
5867 /* Note: Write register with some additional bits forced to state reset */
5868 /* instead of modifying only the selected bit for this function, */
5869 /* to not interfere with bits with HW property "rs". */
5870 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
5871 }
5872
5873 /**
5874 * @brief Get the selected ADC instance deep power down state.
5875 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
5876 * @param ADCx ADC instance
5877 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
5878 */
LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef * ADCx)5879 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
5880 {
5881 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
5882 }
5883
5884 /**
5885 * @brief Enable ADC instance internal voltage regulator.
5886 * @note On this STM32 serie, after ADC internal voltage regulator enable,
5887 * a delay for ADC internal voltage regulator stabilization
5888 * is required before performing a ADC calibration or ADC enable.
5889 * Refer to device datasheet, parameter tADCVREG_STUP.
5890 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
5891 * @note On this STM32 serie, setting of this feature is conditioned to
5892 * ADC state:
5893 * ADC must be ADC disabled.
5894 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
5895 * @param ADCx ADC instance
5896 * @retval None
5897 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)5898 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
5899 {
5900 /* Note: Write register with some additional bits forced to state reset */
5901 /* instead of modifying only the selected bit for this function, */
5902 /* to not interfere with bits with HW property "rs". */
5903 MODIFY_REG(ADCx->CR,
5904 ADC_CR_BITS_PROPERTY_RS,
5905 ADC_CR_ADVREGEN);
5906 }
5907
5908 /**
5909 * @brief Disable ADC internal voltage regulator.
5910 * @note On this STM32 serie, setting of this feature is conditioned to
5911 * ADC state:
5912 * ADC must be ADC disabled.
5913 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
5914 * @param ADCx ADC instance
5915 * @retval None
5916 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)5917 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
5918 {
5919 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
5920 }
5921
5922 /**
5923 * @brief Get the selected ADC instance internal voltage regulator state.
5924 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
5925 * @param ADCx ADC instance
5926 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
5927 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)5928 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
5929 {
5930 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
5931 }
5932
5933 /**
5934 * @brief Enable the selected ADC instance.
5935 * @note On this STM32 serie, after ADC enable, a delay for
5936 * ADC internal analog stabilization is required before performing a
5937 * ADC conversion start.
5938 * Refer to device datasheet, parameter tSTAB.
5939 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5940 * is enabled and when conversion clock is active.
5941 * (not only core clock: this ADC has a dual clock domain)
5942 * @note On this STM32 serie, setting of this feature is conditioned to
5943 * ADC state:
5944 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
5945 * @rmtoll CR ADEN LL_ADC_Enable
5946 * @param ADCx ADC instance
5947 * @retval None
5948 */
LL_ADC_Enable(ADC_TypeDef * ADCx)5949 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
5950 {
5951 /* Note: Write register with some additional bits forced to state reset */
5952 /* instead of modifying only the selected bit for this function, */
5953 /* to not interfere with bits with HW property "rs". */
5954 MODIFY_REG(ADCx->CR,
5955 ADC_CR_BITS_PROPERTY_RS,
5956 ADC_CR_ADEN);
5957 }
5958
5959 /**
5960 * @brief Disable the selected ADC instance.
5961 * @note On this STM32 serie, setting of this feature is conditioned to
5962 * ADC state:
5963 * ADC must be not disabled. Must be enabled without conversion on going
5964 * on either groups regular or injected.
5965 * @rmtoll CR ADDIS LL_ADC_Disable
5966 * @param ADCx ADC instance
5967 * @retval None
5968 */
LL_ADC_Disable(ADC_TypeDef * ADCx)5969 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
5970 {
5971 /* Note: Write register with some additional bits forced to state reset */
5972 /* instead of modifying only the selected bit for this function, */
5973 /* to not interfere with bits with HW property "rs". */
5974 MODIFY_REG(ADCx->CR,
5975 ADC_CR_BITS_PROPERTY_RS,
5976 ADC_CR_ADDIS);
5977 }
5978
5979 /**
5980 * @brief Get the selected ADC instance enable state.
5981 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
5982 * is enabled and when conversion clock is active.
5983 * (not only core clock: this ADC has a dual clock domain)
5984 * @rmtoll CR ADEN LL_ADC_IsEnabled
5985 * @param ADCx ADC instance
5986 * @retval 0: ADC is disabled, 1: ADC is enabled.
5987 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)5988 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
5989 {
5990 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
5991 }
5992
5993 /**
5994 * @brief Get the selected ADC instance disable state.
5995 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
5996 * @param ADCx ADC instance
5997 * @retval 0: no ADC disable command on going.
5998 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)5999 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6000 {
6001 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6002 }
6003
6004 /**
6005 * @brief Start ADC calibration in the mode single-ended
6006 * or differential (for devices with differential mode available).
6007 * @note On this STM32 serie, a minimum number of ADC clock cycles
6008 * are required between ADC end of calibration and ADC enable.
6009 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6010 * @note For devices with differential mode available:
6011 * Calibration of offset is specific to each of
6012 * single-ended and differential modes
6013 * (calibration run must be performed for each of these
6014 * differential modes, if used afterwards and if the application
6015 * requires their calibration).
6016 * @note On this STM32 serie, setting of this feature is conditioned to
6017 * ADC state:
6018 * ADC must be ADC disabled.
6019 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6020 * CR ADCALDIF LL_ADC_StartCalibration
6021 * @param ADCx ADC instance
6022 * @param SingleDiff This parameter can be one of the following values:
6023 * @arg @ref LL_ADC_SINGLE_ENDED
6024 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6025 * @retval None
6026 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx,uint32_t SingleDiff)6027 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6028 {
6029 /* Note: Write register with some additional bits forced to state reset */
6030 /* instead of modifying only the selected bit for this function, */
6031 /* to not interfere with bits with HW property "rs". */
6032 MODIFY_REG(ADCx->CR,
6033 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6034 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6035 }
6036
6037 /**
6038 * @brief Get ADC calibration state.
6039 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6040 * @param ADCx ADC instance
6041 * @retval 0: calibration complete, 1: calibration in progress.
6042 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)6043 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6044 {
6045 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6046 }
6047
6048 /**
6049 * @}
6050 */
6051
6052 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6053 * @{
6054 */
6055
6056 /**
6057 * @brief Start ADC group regular conversion.
6058 * @note On this STM32 serie, this function is relevant for both
6059 * internal trigger (SW start) and external trigger:
6060 * - If ADC trigger has been set to software start, ADC conversion
6061 * starts immediately.
6062 * - If ADC trigger has been set to external trigger, ADC conversion
6063 * will start at next trigger event (on the selected trigger edge)
6064 * following the ADC start conversion command.
6065 * @note On this STM32 serie, setting of this feature is conditioned to
6066 * ADC state:
6067 * ADC must be enabled without conversion on going on group regular,
6068 * without conversion stop command on going on group regular,
6069 * without ADC disable command on going.
6070 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6071 * @param ADCx ADC instance
6072 * @retval None
6073 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)6074 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6075 {
6076 /* Note: Write register with some additional bits forced to state reset */
6077 /* instead of modifying only the selected bit for this function, */
6078 /* to not interfere with bits with HW property "rs". */
6079 MODIFY_REG(ADCx->CR,
6080 ADC_CR_BITS_PROPERTY_RS,
6081 ADC_CR_ADSTART);
6082 }
6083
6084 /**
6085 * @brief Stop ADC group regular conversion.
6086 * @note On this STM32 serie, setting of this feature is conditioned to
6087 * ADC state:
6088 * ADC must be enabled with conversion on going on group regular,
6089 * without ADC disable command on going.
6090 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6091 * @param ADCx ADC instance
6092 * @retval None
6093 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)6094 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6095 {
6096 /* Note: Write register with some additional bits forced to state reset */
6097 /* instead of modifying only the selected bit for this function, */
6098 /* to not interfere with bits with HW property "rs". */
6099 MODIFY_REG(ADCx->CR,
6100 ADC_CR_BITS_PROPERTY_RS,
6101 ADC_CR_ADSTP);
6102 }
6103
6104 /**
6105 * @brief Get ADC group regular conversion state.
6106 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6107 * @param ADCx ADC instance
6108 * @retval 0: no conversion is on going on ADC group regular.
6109 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)6110 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6111 {
6112 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6113 }
6114
6115 /**
6116 * @brief Get ADC group regular command of conversion stop state
6117 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6118 * @param ADCx ADC instance
6119 * @retval 0: no command of conversion stop is on going on ADC group regular.
6120 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)6121 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6122 {
6123 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6124 }
6125
6126 /**
6127 * @brief Get ADC group regular conversion data, range fit for
6128 * all ADC configurations: all ADC resolutions and
6129 * all oversampling increased data width (for devices
6130 * with feature oversampling).
6131 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6132 * @param ADCx ADC instance
6133 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6134 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)6135 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6136 {
6137 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6138 }
6139
6140 /**
6141 * @brief Get ADC group regular conversion data, range fit for
6142 * ADC resolution 12 bits.
6143 * @note For devices with feature oversampling: Oversampling
6144 * can increase data width, function for extended range
6145 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6146 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6147 * @param ADCx ADC instance
6148 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6149 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)6150 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6151 {
6152 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6153 }
6154
6155 /**
6156 * @brief Get ADC group regular conversion data, range fit for
6157 * ADC resolution 10 bits.
6158 * @note For devices with feature oversampling: Oversampling
6159 * can increase data width, function for extended range
6160 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6161 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6162 * @param ADCx ADC instance
6163 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6164 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)6165 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6166 {
6167 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6168 }
6169
6170 /**
6171 * @brief Get ADC group regular conversion data, range fit for
6172 * ADC resolution 8 bits.
6173 * @note For devices with feature oversampling: Oversampling
6174 * can increase data width, function for extended range
6175 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6176 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6177 * @param ADCx ADC instance
6178 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6179 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)6180 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6181 {
6182 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6183 }
6184
6185 /**
6186 * @brief Get ADC group regular conversion data, range fit for
6187 * ADC resolution 6 bits.
6188 * @note For devices with feature oversampling: Oversampling
6189 * can increase data width, function for extended range
6190 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6191 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6192 * @param ADCx ADC instance
6193 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6194 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)6195 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6196 {
6197 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6198 }
6199
6200 #if defined(ADC_MULTIMODE_SUPPORT)
6201 /**
6202 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6203 * or raw data with ADC master and slave concatenated.
6204 * @note If raw data with ADC master and slave concatenated is retrieved,
6205 * a macro is available to get the conversion data of
6206 * ADC master or ADC slave: see helper macro
6207 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6208 * (however this macro is mainly intended for multimode
6209 * transfer by DMA, because this function can do the same
6210 * by getting multimode conversion data of ADC master or ADC slave
6211 * separately).
6212 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6213 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6214 * @param ADCxy_COMMON ADC common instance
6215 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6216 * @param ConversionData This parameter can be one of the following values:
6217 * @arg @ref LL_ADC_MULTI_MASTER
6218 * @arg @ref LL_ADC_MULTI_SLAVE
6219 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6220 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6221 */
LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t ConversionData)6222 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6223 {
6224 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6225 ConversionData)
6226 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6227 );
6228 }
6229 #endif /* ADC_MULTIMODE_SUPPORT */
6230
6231 /**
6232 * @}
6233 */
6234
6235 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6236 * @{
6237 */
6238
6239 /**
6240 * @brief Start ADC group injected conversion.
6241 * @note On this STM32 serie, this function is relevant for both
6242 * internal trigger (SW start) and external trigger:
6243 * - If ADC trigger has been set to software start, ADC conversion
6244 * starts immediately.
6245 * - If ADC trigger has been set to external trigger, ADC conversion
6246 * will start at next trigger event (on the selected trigger edge)
6247 * following the ADC start conversion command.
6248 * @note On this STM32 serie, setting of this feature is conditioned to
6249 * ADC state:
6250 * ADC must be enabled without conversion on going on group injected,
6251 * without conversion stop command on going on group injected,
6252 * without ADC disable command on going.
6253 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6254 * @param ADCx ADC instance
6255 * @retval None
6256 */
LL_ADC_INJ_StartConversion(ADC_TypeDef * ADCx)6257 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6258 {
6259 /* Note: Write register with some additional bits forced to state reset */
6260 /* instead of modifying only the selected bit for this function, */
6261 /* to not interfere with bits with HW property "rs". */
6262 MODIFY_REG(ADCx->CR,
6263 ADC_CR_BITS_PROPERTY_RS,
6264 ADC_CR_JADSTART);
6265 }
6266
6267 /**
6268 * @brief Stop ADC group injected conversion.
6269 * @note On this STM32 serie, setting of this feature is conditioned to
6270 * ADC state:
6271 * ADC must be enabled with conversion on going on group injected,
6272 * without ADC disable command on going.
6273 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6274 * @param ADCx ADC instance
6275 * @retval None
6276 */
LL_ADC_INJ_StopConversion(ADC_TypeDef * ADCx)6277 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6278 {
6279 /* Note: Write register with some additional bits forced to state reset */
6280 /* instead of modifying only the selected bit for this function, */
6281 /* to not interfere with bits with HW property "rs". */
6282 MODIFY_REG(ADCx->CR,
6283 ADC_CR_BITS_PROPERTY_RS,
6284 ADC_CR_JADSTP);
6285 }
6286
6287 /**
6288 * @brief Get ADC group injected conversion state.
6289 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6290 * @param ADCx ADC instance
6291 * @retval 0: no conversion is on going on ADC group injected.
6292 */
LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef * ADCx)6293 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6294 {
6295 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6296 }
6297
6298 /**
6299 * @brief Get ADC group injected command of conversion stop state
6300 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6301 * @param ADCx ADC instance
6302 * @retval 0: no command of conversion stop is on going on ADC group injected.
6303 */
LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef * ADCx)6304 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6305 {
6306 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6307 }
6308
6309 /**
6310 * @brief Get ADC group regular conversion data, range fit for
6311 * all ADC configurations: all ADC resolutions and
6312 * all oversampling increased data width (for devices
6313 * with feature oversampling).
6314 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6315 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6316 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6317 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6318 * @param ADCx ADC instance
6319 * @param Rank This parameter can be one of the following values:
6320 * @arg @ref LL_ADC_INJ_RANK_1
6321 * @arg @ref LL_ADC_INJ_RANK_2
6322 * @arg @ref LL_ADC_INJ_RANK_3
6323 * @arg @ref LL_ADC_INJ_RANK_4
6324 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6325 */
LL_ADC_INJ_ReadConversionData32(ADC_TypeDef * ADCx,uint32_t Rank)6326 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6327 {
6328 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6329
6330 return (uint32_t)(READ_BIT(*preg,
6331 ADC_JDR1_JDATA)
6332 );
6333 }
6334
6335 /**
6336 * @brief Get ADC group injected conversion data, range fit for
6337 * ADC resolution 12 bits.
6338 * @note For devices with feature oversampling: Oversampling
6339 * can increase data width, function for extended range
6340 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6341 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6342 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6343 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6344 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6345 * @param ADCx ADC instance
6346 * @param Rank This parameter can be one of the following values:
6347 * @arg @ref LL_ADC_INJ_RANK_1
6348 * @arg @ref LL_ADC_INJ_RANK_2
6349 * @arg @ref LL_ADC_INJ_RANK_3
6350 * @arg @ref LL_ADC_INJ_RANK_4
6351 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6352 */
LL_ADC_INJ_ReadConversionData12(ADC_TypeDef * ADCx,uint32_t Rank)6353 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6354 {
6355 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6356
6357 return (uint16_t)(READ_BIT(*preg,
6358 ADC_JDR1_JDATA)
6359 );
6360 }
6361
6362 /**
6363 * @brief Get ADC group injected conversion data, range fit for
6364 * ADC resolution 10 bits.
6365 * @note For devices with feature oversampling: Oversampling
6366 * can increase data width, function for extended range
6367 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6368 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
6369 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
6370 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
6371 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
6372 * @param ADCx ADC instance
6373 * @param Rank This parameter can be one of the following values:
6374 * @arg @ref LL_ADC_INJ_RANK_1
6375 * @arg @ref LL_ADC_INJ_RANK_2
6376 * @arg @ref LL_ADC_INJ_RANK_3
6377 * @arg @ref LL_ADC_INJ_RANK_4
6378 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6379 */
LL_ADC_INJ_ReadConversionData10(ADC_TypeDef * ADCx,uint32_t Rank)6380 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
6381 {
6382 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6383
6384 return (uint16_t)(READ_BIT(*preg,
6385 ADC_JDR1_JDATA)
6386 );
6387 }
6388
6389 /**
6390 * @brief Get ADC group injected conversion data, range fit for
6391 * ADC resolution 8 bits.
6392 * @note For devices with feature oversampling: Oversampling
6393 * can increase data width, function for extended range
6394 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6395 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
6396 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
6397 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
6398 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
6399 * @param ADCx ADC instance
6400 * @param Rank This parameter can be one of the following values:
6401 * @arg @ref LL_ADC_INJ_RANK_1
6402 * @arg @ref LL_ADC_INJ_RANK_2
6403 * @arg @ref LL_ADC_INJ_RANK_3
6404 * @arg @ref LL_ADC_INJ_RANK_4
6405 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6406 */
LL_ADC_INJ_ReadConversionData8(ADC_TypeDef * ADCx,uint32_t Rank)6407 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
6408 {
6409 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6410
6411 return (uint8_t)(READ_BIT(*preg,
6412 ADC_JDR1_JDATA)
6413 );
6414 }
6415
6416 /**
6417 * @brief Get ADC group injected conversion data, range fit for
6418 * ADC resolution 6 bits.
6419 * @note For devices with feature oversampling: Oversampling
6420 * can increase data width, function for extended range
6421 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6422 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
6423 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
6424 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
6425 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
6426 * @param ADCx ADC instance
6427 * @param Rank This parameter can be one of the following values:
6428 * @arg @ref LL_ADC_INJ_RANK_1
6429 * @arg @ref LL_ADC_INJ_RANK_2
6430 * @arg @ref LL_ADC_INJ_RANK_3
6431 * @arg @ref LL_ADC_INJ_RANK_4
6432 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6433 */
LL_ADC_INJ_ReadConversionData6(ADC_TypeDef * ADCx,uint32_t Rank)6434 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
6435 {
6436 register const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6437
6438 return (uint8_t)(READ_BIT(*preg,
6439 ADC_JDR1_JDATA)
6440 );
6441 }
6442
6443 /**
6444 * @}
6445 */
6446
6447 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
6448 * @{
6449 */
6450
6451 /**
6452 * @brief Get flag ADC ready.
6453 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6454 * is enabled and when conversion clock is active.
6455 * (not only core clock: this ADC has a dual clock domain)
6456 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
6457 * @param ADCx ADC instance
6458 * @retval State of bit (1 or 0).
6459 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)6460 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
6461 {
6462 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
6463 }
6464
6465 /**
6466 * @brief Get flag ADC group regular end of unitary conversion.
6467 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
6468 * @param ADCx ADC instance
6469 * @retval State of bit (1 or 0).
6470 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)6471 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
6472 {
6473 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
6474 }
6475
6476 /**
6477 * @brief Get flag ADC group regular end of sequence conversions.
6478 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
6479 * @param ADCx ADC instance
6480 * @retval State of bit (1 or 0).
6481 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)6482 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
6483 {
6484 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
6485 }
6486
6487 /**
6488 * @brief Get flag ADC group regular overrun.
6489 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
6490 * @param ADCx ADC instance
6491 * @retval State of bit (1 or 0).
6492 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)6493 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
6494 {
6495 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
6496 }
6497
6498 /**
6499 * @brief Get flag ADC group regular end of sampling phase.
6500 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
6501 * @param ADCx ADC instance
6502 * @retval State of bit (1 or 0).
6503 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)6504 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
6505 {
6506 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
6507 }
6508
6509 /**
6510 * @brief Get flag ADC group injected end of unitary conversion.
6511 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
6512 * @param ADCx ADC instance
6513 * @retval State of bit (1 or 0).
6514 */
LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef * ADCx)6515 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
6516 {
6517 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
6518 }
6519
6520 /**
6521 * @brief Get flag ADC group injected end of sequence conversions.
6522 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
6523 * @param ADCx ADC instance
6524 * @retval State of bit (1 or 0).
6525 */
LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef * ADCx)6526 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
6527 {
6528 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
6529 }
6530
6531 /**
6532 * @brief Get flag ADC group injected contexts queue overflow.
6533 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
6534 * @param ADCx ADC instance
6535 * @retval State of bit (1 or 0).
6536 */
LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef * ADCx)6537 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
6538 {
6539 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
6540 }
6541
6542 /**
6543 * @brief Get flag ADC analog watchdog 1 flag
6544 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
6545 * @param ADCx ADC instance
6546 * @retval State of bit (1 or 0).
6547 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)6548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
6549 {
6550 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
6551 }
6552
6553 /**
6554 * @brief Get flag ADC analog watchdog 2.
6555 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
6556 * @param ADCx ADC instance
6557 * @retval State of bit (1 or 0).
6558 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)6559 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
6560 {
6561 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
6562 }
6563
6564 /**
6565 * @brief Get flag ADC analog watchdog 3.
6566 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
6567 * @param ADCx ADC instance
6568 * @retval State of bit (1 or 0).
6569 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)6570 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
6571 {
6572 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
6573 }
6574
6575 /**
6576 * @brief Clear flag ADC ready.
6577 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6578 * is enabled and when conversion clock is active.
6579 * (not only core clock: this ADC has a dual clock domain)
6580 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
6581 * @param ADCx ADC instance
6582 * @retval None
6583 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)6584 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
6585 {
6586 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
6587 }
6588
6589 /**
6590 * @brief Clear flag ADC group regular end of unitary conversion.
6591 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
6592 * @param ADCx ADC instance
6593 * @retval None
6594 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)6595 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
6596 {
6597 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
6598 }
6599
6600 /**
6601 * @brief Clear flag ADC group regular end of sequence conversions.
6602 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
6603 * @param ADCx ADC instance
6604 * @retval None
6605 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)6606 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
6607 {
6608 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
6609 }
6610
6611 /**
6612 * @brief Clear flag ADC group regular overrun.
6613 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
6614 * @param ADCx ADC instance
6615 * @retval None
6616 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)6617 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
6618 {
6619 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
6620 }
6621
6622 /**
6623 * @brief Clear flag ADC group regular end of sampling phase.
6624 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
6625 * @param ADCx ADC instance
6626 * @retval None
6627 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)6628 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
6629 {
6630 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
6631 }
6632
6633 /**
6634 * @brief Clear flag ADC group injected end of unitary conversion.
6635 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
6636 * @param ADCx ADC instance
6637 * @retval None
6638 */
LL_ADC_ClearFlag_JEOC(ADC_TypeDef * ADCx)6639 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
6640 {
6641 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
6642 }
6643
6644 /**
6645 * @brief Clear flag ADC group injected end of sequence conversions.
6646 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
6647 * @param ADCx ADC instance
6648 * @retval None
6649 */
LL_ADC_ClearFlag_JEOS(ADC_TypeDef * ADCx)6650 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
6651 {
6652 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
6653 }
6654
6655 /**
6656 * @brief Clear flag ADC group injected contexts queue overflow.
6657 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
6658 * @param ADCx ADC instance
6659 * @retval None
6660 */
LL_ADC_ClearFlag_JQOVF(ADC_TypeDef * ADCx)6661 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
6662 {
6663 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
6664 }
6665
6666 /**
6667 * @brief Clear flag ADC analog watchdog 1.
6668 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
6669 * @param ADCx ADC instance
6670 * @retval None
6671 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)6672 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
6673 {
6674 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
6675 }
6676
6677 /**
6678 * @brief Clear flag ADC analog watchdog 2.
6679 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
6680 * @param ADCx ADC instance
6681 * @retval None
6682 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)6683 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
6684 {
6685 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
6686 }
6687
6688 /**
6689 * @brief Clear flag ADC analog watchdog 3.
6690 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
6691 * @param ADCx ADC instance
6692 * @retval None
6693 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)6694 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
6695 {
6696 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
6697 }
6698
6699 #if defined(ADC_MULTIMODE_SUPPORT)
6700 /**
6701 * @brief Get flag multimode ADC ready of the ADC master.
6702 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
6703 * @param ADCxy_COMMON ADC common instance
6704 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6705 * @retval State of bit (1 or 0).
6706 */
LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6707 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6708 {
6709 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
6710 }
6711
6712 /**
6713 * @brief Get flag multimode ADC ready of the ADC slave.
6714 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
6715 * @param ADCxy_COMMON ADC common instance
6716 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6717 * @retval State of bit (1 or 0).
6718 */
LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef * ADCxy_COMMON)6719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
6720 {
6721 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
6722 }
6723
6724 /**
6725 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
6726 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
6727 * @param ADCxy_COMMON ADC common instance
6728 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6729 * @retval State of bit (1 or 0).
6730 */
LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6732 {
6733 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6734 }
6735
6736 /**
6737 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
6738 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
6739 * @param ADCxy_COMMON ADC common instance
6740 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6741 * @retval State of bit (1 or 0).
6742 */
LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef * ADCxy_COMMON)6743 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
6744 {
6745 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
6746 }
6747
6748 /**
6749 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
6750 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
6751 * @param ADCxy_COMMON ADC common instance
6752 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6753 * @retval State of bit (1 or 0).
6754 */
LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6755 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6756 {
6757 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
6758 }
6759
6760 /**
6761 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
6762 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
6763 * @param ADCxy_COMMON ADC common instance
6764 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6765 * @retval State of bit (1 or 0).
6766 */
LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef * ADCxy_COMMON)6767 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
6768 {
6769 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
6770 }
6771
6772 /**
6773 * @brief Get flag multimode ADC group regular overrun of the ADC master.
6774 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
6775 * @param ADCxy_COMMON ADC common instance
6776 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6777 * @retval State of bit (1 or 0).
6778 */
LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6779 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6780 {
6781 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
6782 }
6783
6784 /**
6785 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
6786 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
6787 * @param ADCxy_COMMON ADC common instance
6788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6789 * @retval State of bit (1 or 0).
6790 */
LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef * ADCxy_COMMON)6791 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
6792 {
6793 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
6794 }
6795
6796 /**
6797 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
6798 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
6799 * @param ADCxy_COMMON ADC common instance
6800 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6801 * @retval State of bit (1 or 0).
6802 */
LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6803 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6804 {
6805 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
6806 }
6807
6808 /**
6809 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
6810 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
6811 * @param ADCxy_COMMON ADC common instance
6812 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6813 * @retval State of bit (1 or 0).
6814 */
LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef * ADCxy_COMMON)6815 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
6816 {
6817 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
6818 }
6819
6820 /**
6821 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
6822 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
6823 * @param ADCxy_COMMON ADC common instance
6824 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6825 * @retval State of bit (1 or 0).
6826 */
LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6827 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6828 {
6829 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
6830 }
6831
6832 /**
6833 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
6834 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
6835 * @param ADCxy_COMMON ADC common instance
6836 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6837 * @retval State of bit (1 or 0).
6838 */
LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef * ADCxy_COMMON)6839 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
6840 {
6841 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
6842 }
6843
6844 /**
6845 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
6846 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
6847 * @param ADCxy_COMMON ADC common instance
6848 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6849 * @retval State of bit (1 or 0).
6850 */
LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6851 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6852 {
6853 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
6854 }
6855
6856 /**
6857 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
6858 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
6859 * @param ADCxy_COMMON ADC common instance
6860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6861 * @retval State of bit (1 or 0).
6862 */
LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef * ADCxy_COMMON)6863 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
6864 {
6865 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
6866 }
6867
6868 /**
6869 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
6870 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
6871 * @param ADCxy_COMMON ADC common instance
6872 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6873 * @retval State of bit (1 or 0).
6874 */
LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6875 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6876 {
6877 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
6878 }
6879
6880 /**
6881 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
6882 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
6883 * @param ADCxy_COMMON ADC common instance
6884 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6885 * @retval State of bit (1 or 0).
6886 */
LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef * ADCxy_COMMON)6887 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
6888 {
6889 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
6890 }
6891
6892 /**
6893 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
6894 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
6895 * @param ADCxy_COMMON ADC common instance
6896 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6897 * @retval State of bit (1 or 0).
6898 */
LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6899 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6900 {
6901 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
6902 }
6903
6904 /**
6905 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
6906 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
6907 * @param ADCxy_COMMON ADC common instance
6908 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6909 * @retval State of bit (1 or 0).
6910 */
LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef * ADCxy_COMMON)6911 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
6912 {
6913 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
6914 }
6915
6916 /**
6917 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
6918 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
6919 * @param ADCxy_COMMON ADC common instance
6920 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6921 * @retval State of bit (1 or 0).
6922 */
LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6923 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6924 {
6925 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
6926 }
6927
6928 /**
6929 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
6930 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
6931 * @param ADCxy_COMMON ADC common instance
6932 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6933 * @retval State of bit (1 or 0).
6934 */
LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef * ADCxy_COMMON)6935 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
6936 {
6937 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
6938 }
6939
6940 /**
6941 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
6942 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
6943 * @param ADCxy_COMMON ADC common instance
6944 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6945 * @retval State of bit (1 or 0).
6946 */
LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6947 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6948 {
6949 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
6950 }
6951
6952 /**
6953 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
6954 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
6955 * @param ADCxy_COMMON ADC common instance
6956 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6957 * @retval State of bit (1 or 0).
6958 */
LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef * ADCxy_COMMON)6959 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
6960 {
6961 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
6962 }
6963 #endif /* ADC_MULTIMODE_SUPPORT */
6964
6965 /**
6966 * @}
6967 */
6968
6969 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
6970 * @{
6971 */
6972
6973 /**
6974 * @brief Enable ADC ready.
6975 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
6976 * @param ADCx ADC instance
6977 * @retval None
6978 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)6979 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
6980 {
6981 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
6982 }
6983
6984 /**
6985 * @brief Enable interruption ADC group regular end of unitary conversion.
6986 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
6987 * @param ADCx ADC instance
6988 * @retval None
6989 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)6990 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
6991 {
6992 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
6993 }
6994
6995 /**
6996 * @brief Enable interruption ADC group regular end of sequence conversions.
6997 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
6998 * @param ADCx ADC instance
6999 * @retval None
7000 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)7001 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7002 {
7003 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7004 }
7005
7006 /**
7007 * @brief Enable ADC group regular interruption overrun.
7008 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7009 * @param ADCx ADC instance
7010 * @retval None
7011 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)7012 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7013 {
7014 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7015 }
7016
7017 /**
7018 * @brief Enable interruption ADC group regular end of sampling.
7019 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7020 * @param ADCx ADC instance
7021 * @retval None
7022 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)7023 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7024 {
7025 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7026 }
7027
7028 /**
7029 * @brief Enable interruption ADC group injected end of unitary conversion.
7030 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7031 * @param ADCx ADC instance
7032 * @retval None
7033 */
LL_ADC_EnableIT_JEOC(ADC_TypeDef * ADCx)7034 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7035 {
7036 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7037 }
7038
7039 /**
7040 * @brief Enable interruption ADC group injected end of sequence conversions.
7041 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7042 * @param ADCx ADC instance
7043 * @retval None
7044 */
LL_ADC_EnableIT_JEOS(ADC_TypeDef * ADCx)7045 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7046 {
7047 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7048 }
7049
7050 /**
7051 * @brief Enable interruption ADC group injected context queue overflow.
7052 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7053 * @param ADCx ADC instance
7054 * @retval None
7055 */
LL_ADC_EnableIT_JQOVF(ADC_TypeDef * ADCx)7056 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7057 {
7058 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7059 }
7060
7061 /**
7062 * @brief Enable interruption ADC analog watchdog 1.
7063 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7064 * @param ADCx ADC instance
7065 * @retval None
7066 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)7067 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7068 {
7069 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7070 }
7071
7072 /**
7073 * @brief Enable interruption ADC analog watchdog 2.
7074 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7075 * @param ADCx ADC instance
7076 * @retval None
7077 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)7078 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7079 {
7080 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7081 }
7082
7083 /**
7084 * @brief Enable interruption ADC analog watchdog 3.
7085 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7086 * @param ADCx ADC instance
7087 * @retval None
7088 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)7089 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7090 {
7091 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7092 }
7093
7094 /**
7095 * @brief Disable interruption ADC ready.
7096 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7097 * @param ADCx ADC instance
7098 * @retval None
7099 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)7100 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7101 {
7102 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7103 }
7104
7105 /**
7106 * @brief Disable interruption ADC group regular end of unitary conversion.
7107 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7108 * @param ADCx ADC instance
7109 * @retval None
7110 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)7111 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7112 {
7113 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7114 }
7115
7116 /**
7117 * @brief Disable interruption ADC group regular end of sequence conversions.
7118 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7119 * @param ADCx ADC instance
7120 * @retval None
7121 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)7122 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7123 {
7124 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7125 }
7126
7127 /**
7128 * @brief Disable interruption ADC group regular overrun.
7129 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7130 * @param ADCx ADC instance
7131 * @retval None
7132 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)7133 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7134 {
7135 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7136 }
7137
7138 /**
7139 * @brief Disable interruption ADC group regular end of sampling.
7140 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7141 * @param ADCx ADC instance
7142 * @retval None
7143 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)7144 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7145 {
7146 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7147 }
7148
7149 /**
7150 * @brief Disable interruption ADC group regular end of unitary conversion.
7151 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7152 * @param ADCx ADC instance
7153 * @retval None
7154 */
LL_ADC_DisableIT_JEOC(ADC_TypeDef * ADCx)7155 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7156 {
7157 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7158 }
7159
7160 /**
7161 * @brief Disable interruption ADC group injected end of sequence conversions.
7162 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7163 * @param ADCx ADC instance
7164 * @retval None
7165 */
LL_ADC_DisableIT_JEOS(ADC_TypeDef * ADCx)7166 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7167 {
7168 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7169 }
7170
7171 /**
7172 * @brief Disable interruption ADC group injected context queue overflow.
7173 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7174 * @param ADCx ADC instance
7175 * @retval None
7176 */
LL_ADC_DisableIT_JQOVF(ADC_TypeDef * ADCx)7177 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7178 {
7179 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7180 }
7181
7182 /**
7183 * @brief Disable interruption ADC analog watchdog 1.
7184 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7185 * @param ADCx ADC instance
7186 * @retval None
7187 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)7188 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7189 {
7190 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7191 }
7192
7193 /**
7194 * @brief Disable interruption ADC analog watchdog 2.
7195 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7196 * @param ADCx ADC instance
7197 * @retval None
7198 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)7199 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7200 {
7201 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7202 }
7203
7204 /**
7205 * @brief Disable interruption ADC analog watchdog 3.
7206 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7207 * @param ADCx ADC instance
7208 * @retval None
7209 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)7210 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7211 {
7212 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7213 }
7214
7215 /**
7216 * @brief Get state of interruption ADC ready
7217 * (0: interrupt disabled, 1: interrupt enabled).
7218 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7219 * @param ADCx ADC instance
7220 * @retval State of bit (1 or 0).
7221 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)7222 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7223 {
7224 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7225 }
7226
7227 /**
7228 * @brief Get state of interruption ADC group regular end of unitary conversion
7229 * (0: interrupt disabled, 1: interrupt enabled).
7230 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7231 * @param ADCx ADC instance
7232 * @retval State of bit (1 or 0).
7233 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)7234 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7235 {
7236 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7237 }
7238
7239 /**
7240 * @brief Get state of interruption ADC group regular end of sequence conversions
7241 * (0: interrupt disabled, 1: interrupt enabled).
7242 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7243 * @param ADCx ADC instance
7244 * @retval State of bit (1 or 0).
7245 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)7246 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7247 {
7248 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7249 }
7250
7251 /**
7252 * @brief Get state of interruption ADC group regular overrun
7253 * (0: interrupt disabled, 1: interrupt enabled).
7254 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7255 * @param ADCx ADC instance
7256 * @retval State of bit (1 or 0).
7257 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)7258 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7259 {
7260 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7261 }
7262
7263 /**
7264 * @brief Get state of interruption ADC group regular end of sampling
7265 * (0: interrupt disabled, 1: interrupt enabled).
7266 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7267 * @param ADCx ADC instance
7268 * @retval State of bit (1 or 0).
7269 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)7270 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7271 {
7272 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7273 }
7274
7275 /**
7276 * @brief Get state of interruption ADC group injected end of unitary conversion
7277 * (0: interrupt disabled, 1: interrupt enabled).
7278 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7279 * @param ADCx ADC instance
7280 * @retval State of bit (1 or 0).
7281 */
LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef * ADCx)7282 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7283 {
7284 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7285 }
7286
7287 /**
7288 * @brief Get state of interruption ADC group injected end of sequence conversions
7289 * (0: interrupt disabled, 1: interrupt enabled).
7290 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7291 * @param ADCx ADC instance
7292 * @retval State of bit (1 or 0).
7293 */
LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef * ADCx)7294 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7295 {
7296 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7297 }
7298
7299 /**
7300 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7301 * (0: interrupt disabled, 1: interrupt enabled).
7302 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7303 * @param ADCx ADC instance
7304 * @retval State of bit (1 or 0).
7305 */
LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef * ADCx)7306 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7307 {
7308 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7309 }
7310
7311 /**
7312 * @brief Get state of interruption ADC analog watchdog 1
7313 * (0: interrupt disabled, 1: interrupt enabled).
7314 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7315 * @param ADCx ADC instance
7316 * @retval State of bit (1 or 0).
7317 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)7318 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7319 {
7320 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7321 }
7322
7323 /**
7324 * @brief Get state of interruption Get ADC analog watchdog 2
7325 * (0: interrupt disabled, 1: interrupt enabled).
7326 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7327 * @param ADCx ADC instance
7328 * @retval State of bit (1 or 0).
7329 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)7330 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7331 {
7332 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7333 }
7334
7335 /**
7336 * @brief Get state of interruption Get ADC analog watchdog 3
7337 * (0: interrupt disabled, 1: interrupt enabled).
7338 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7339 * @param ADCx ADC instance
7340 * @retval State of bit (1 or 0).
7341 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)7342 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7343 {
7344 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7345 }
7346
7347 /**
7348 * @}
7349 */
7350
7351 #if defined(USE_FULL_LL_DRIVER)
7352 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7353 * @{
7354 */
7355
7356 /* Initialization of some features of ADC common parameters and multimode */
7357 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7358 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7359 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7360
7361 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7362 /* (availability of ADC group injected depends on STM32 families) */
7363 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
7364
7365 /* Initialization of some features of ADC instance */
7366 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
7367 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
7368
7369 /* Initialization of some features of ADC instance and ADC group regular */
7370 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7371 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
7372
7373 /* Initialization of some features of ADC instance and ADC group injected */
7374 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7375 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
7376
7377 /**
7378 * @}
7379 */
7380 #endif /* USE_FULL_LL_DRIVER */
7381
7382 /**
7383 * @}
7384 */
7385
7386 /**
7387 * @}
7388 */
7389
7390 #endif /* ADC1 || ADC2 || ADC3 */
7391
7392 /**
7393 * @}
7394 */
7395
7396 #ifdef __cplusplus
7397 }
7398 #endif
7399
7400 #endif /* __STM32L4xx_LL_ADC_H */
7401
7402 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7403
