1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_TSC_H 38 #define STM32L4xx_HAL_TSC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup TSC 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup TSC_Exported_Types TSC Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief TSC state structure definition 62 */ 63 typedef enum 64 { 65 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 66 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 67 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 68 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 69 } HAL_TSC_StateTypeDef; 70 71 /** 72 * @brief TSC group status structure definition 73 */ 74 typedef enum 75 { 76 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 77 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 78 } TSC_GroupStatusTypeDef; 79 80 /** 81 * @brief TSC init structure definition 82 */ 83 typedef struct 84 { 85 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 86 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 87 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 88 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 89 uint32_t SpreadSpectrum; /*!< Spread spectrum activation 90 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 91 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 92 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 93 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 94 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 95 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 96 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 97 uint32_t MaxCountValue; /*!< Max count value 98 This parameter can be a value of @ref TSC_MaxCount_Value */ 99 uint32_t IODefaultMode; /*!< IO default mode 100 This parameter can be a value of @ref TSC_IO_Default_Mode */ 101 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 102 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 103 uint32_t AcquisitionMode; /*!< Acquisition mode 104 This parameter can be a value of @ref TSC_Acquisition_Mode */ 105 uint32_t MaxCountInterrupt; /*!< Max count interrupt activation 106 This parameter can be set to ENABLE or DISABLE. */ 107 uint32_t ChannelIOs; /*!< Channel IOs mask */ 108 uint32_t ShieldIOs; /*!< Shield IOs mask */ 109 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 110 } TSC_InitTypeDef; 111 112 /** 113 * @brief TSC IOs configuration structure definition 114 */ 115 typedef struct 116 { 117 uint32_t ChannelIOs; /*!< Channel IOs mask */ 118 uint32_t ShieldIOs; /*!< Shield IOs mask */ 119 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 120 } TSC_IOConfigTypeDef; 121 122 /** 123 * @brief TSC handle Structure definition 124 */ 125 typedef struct __TSC_HandleTypeDef 126 { 127 TSC_TypeDef *Instance; /*!< Register base address */ 128 TSC_InitTypeDef Init; /*!< Initialization parameters */ 129 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 130 HAL_LockTypeDef Lock; /*!< Lock feature */ 131 __IO uint32_t ErrorCode; /*!< I2C Error code */ 132 133 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 134 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 135 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 136 137 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 138 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 139 140 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 141 } TSC_HandleTypeDef; 142 143 /** 144 * @brief TSC Group Index Structure definition 145 */ 146 typedef enum 147 { 148 TSC_GROUP1_IDX = 0x00UL, 149 TSC_GROUP2_IDX, 150 TSC_GROUP3_IDX, 151 TSC_GROUP4_IDX, 152 #if defined(TSC_IOCCR_G5_IO1) 153 TSC_GROUP5_IDX, 154 #endif 155 #if defined(TSC_IOCCR_G6_IO1) 156 TSC_GROUP6_IDX, 157 #endif 158 #if defined(TSC_IOCCR_G7_IO1) 159 TSC_GROUP7_IDX, 160 #endif 161 #if defined(TSC_IOCCR_G8_IO1) 162 TSC_GROUP8_IDX, 163 #endif 164 TSC_NB_OF_GROUPS 165 }TSC_GroupIndexTypeDef; 166 167 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 168 /** 169 * @brief HAL TSC Callback ID enumeration definition 170 */ 171 typedef enum 172 { 173 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 174 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 175 176 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 177 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 178 179 } HAL_TSC_CallbackIDTypeDef; 180 181 /** 182 * @brief HAL TSC Callback pointer definition 183 */ 184 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 185 186 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 187 188 /** 189 * @} 190 */ 191 192 /* Exported constants --------------------------------------------------------*/ 193 /** @defgroup TSC_Exported_Constants TSC Exported Constants 194 * @{ 195 */ 196 197 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 198 * @brief TSC Error Code definition 199 * @{ 200 */ 201 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 202 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 203 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 204 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 205 /** 206 * @} 207 */ 208 209 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 210 * @{ 211 */ 212 #define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 213 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 214 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 215 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 216 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 217 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 218 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 219 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 220 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 221 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 222 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 223 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 224 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 225 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 226 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 227 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 228 /** 229 * @} 230 */ 231 232 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 233 * @{ 234 */ 235 #define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 236 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 237 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 238 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 239 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 240 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 241 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 242 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 243 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 244 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 245 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 246 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 247 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 248 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 249 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 250 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 251 /** 252 * @} 253 */ 254 255 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 256 * @{ 257 */ 258 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 259 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 260 /** 261 * @} 262 */ 263 264 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 265 * @{ 266 */ 267 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 268 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 269 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 270 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 271 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 272 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 273 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 274 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 275 /** 276 * @} 277 */ 278 279 /** @defgroup TSC_MaxCount_Value Max Count Value 280 * @{ 281 */ 282 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 283 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 284 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 285 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 286 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 287 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 288 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 289 /** 290 * @} 291 */ 292 293 /** @defgroup TSC_IO_Default_Mode IO Default Mode 294 * @{ 295 */ 296 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 297 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 298 /** 299 * @} 300 */ 301 302 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 303 * @{ 304 */ 305 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 306 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 312 * @{ 313 */ 314 #define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 315 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup TSC_interrupts_definition Interrupts definition 321 * @{ 322 */ 323 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 324 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup TSC_flags_definition Flags definition 330 * @{ 331 */ 332 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 333 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup TSC_Group_definition Group definition 339 * @{ 340 */ 341 #define TSC_GROUP1 (uint32_t)(0x1UL << TSC_GROUP1_IDX) 342 #define TSC_GROUP2 (uint32_t)(0x1UL << TSC_GROUP2_IDX) 343 #define TSC_GROUP3 (uint32_t)(0x1UL << TSC_GROUP3_IDX) 344 #define TSC_GROUP4 (uint32_t)(0x1UL << TSC_GROUP4_IDX) 345 #if defined(TSC_IOCCR_G5_IO1) 346 #define TSC_GROUP5 (uint32_t)(0x1UL << TSC_GROUP5_IDX) 347 #endif 348 #if defined(TSC_IOCCR_G6_IO1) 349 #define TSC_GROUP6 (uint32_t)(0x1UL << TSC_GROUP6_IDX) 350 #endif 351 #if defined(TSC_IOCCR_G7_IO1) 352 #define TSC_GROUP7 (uint32_t)(0x1UL << TSC_GROUP7_IDX) 353 #endif 354 #if defined(TSC_IOCCR_G8_IO1) 355 #define TSC_GROUP8 (uint32_t)(0x1UL << TSC_GROUP8_IDX) 356 #endif 357 358 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 359 360 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 361 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 362 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 363 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 364 365 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 366 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 367 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 368 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 369 370 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 371 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 372 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 373 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 374 375 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 376 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 377 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 378 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 379 #if defined(TSC_IOCCR_G5_IO1) 380 381 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 382 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 383 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 384 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 385 #else 386 387 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ 388 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ 389 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ 390 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ 391 #endif 392 #if defined(TSC_IOCCR_G6_IO1) 393 394 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 395 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 396 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 397 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 398 #else 399 400 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ 401 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ 402 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ 403 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ 404 #endif 405 #if defined(TSC_IOCCR_G7_IO1) 406 407 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 408 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 409 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 410 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 411 #else 412 413 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 414 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 415 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 416 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 417 #endif 418 #if defined(TSC_IOCCR_G8_IO1) 419 420 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 421 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 422 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 423 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 424 #else 425 426 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 427 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 428 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 429 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 430 #endif 431 /** 432 * @} 433 */ 434 435 /** 436 * @} 437 */ 438 439 /* Exported macros -----------------------------------------------------------*/ 440 441 /** @defgroup TSC_Exported_Macros TSC Exported Macros 442 * @{ 443 */ 444 445 /** @brief Reset TSC handle state. 446 * @param __HANDLE__ TSC handle 447 * @retval None 448 */ 449 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 450 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 451 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 452 (__HANDLE__)->MspInitCallback = NULL; \ 453 (__HANDLE__)->MspDeInitCallback = NULL; \ 454 } while(0) 455 #else 456 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 457 #endif 458 459 /** 460 * @brief Enable the TSC peripheral. 461 * @param __HANDLE__ TSC handle 462 * @retval None 463 */ 464 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 465 466 /** 467 * @brief Disable the TSC peripheral. 468 * @param __HANDLE__ TSC handle 469 * @retval None 470 */ 471 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE)) 472 473 /** 474 * @brief Start acquisition. 475 * @param __HANDLE__ TSC handle 476 * @retval None 477 */ 478 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 479 480 /** 481 * @brief Stop acquisition. 482 * @param __HANDLE__ TSC handle 483 * @retval None 484 */ 485 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START)) 486 487 /** 488 * @brief Set IO default mode to output push-pull low. 489 * @param __HANDLE__ TSC handle 490 * @retval None 491 */ 492 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF)) 493 494 /** 495 * @brief Set IO default mode to input floating. 496 * @param __HANDLE__ TSC handle 497 * @retval None 498 */ 499 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 500 501 /** 502 * @brief Set synchronization polarity to falling edge. 503 * @param __HANDLE__ TSC handle 504 * @retval None 505 */ 506 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL)) 507 508 /** 509 * @brief Set synchronization polarity to rising edge and high level. 510 * @param __HANDLE__ TSC handle 511 * @retval None 512 */ 513 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 514 515 /** 516 * @brief Enable TSC interrupt. 517 * @param __HANDLE__ TSC handle 518 * @param __INTERRUPT__ TSC interrupt 519 * @retval None 520 */ 521 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 522 523 /** 524 * @brief Disable TSC interrupt. 525 * @param __HANDLE__ TSC handle 526 * @param __INTERRUPT__ TSC interrupt 527 * @retval None 528 */ 529 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__))) 530 531 /** @brief Check whether the specified TSC interrupt source is enabled or not. 532 * @param __HANDLE__ TSC Handle 533 * @param __INTERRUPT__ TSC interrupt 534 * @retval SET or RESET 535 */ 536 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 537 538 /** 539 * @brief Check whether the specified TSC flag is set or not. 540 * @param __HANDLE__ TSC handle 541 * @param __FLAG__ TSC flag 542 * @retval SET or RESET 543 */ 544 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 545 546 /** 547 * @brief Clear the TSC's pending flag. 548 * @param __HANDLE__ TSC handle 549 * @param __FLAG__ TSC flag 550 * @retval None 551 */ 552 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 553 554 /** 555 * @brief Enable schmitt trigger hysteresis on a group of IOs. 556 * @param __HANDLE__ TSC handle 557 * @param __GX_IOY_MASK__ IOs mask 558 * @retval None 559 */ 560 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 561 562 /** 563 * @brief Disable schmitt trigger hysteresis on a group of IOs. 564 * @param __HANDLE__ TSC handle 565 * @param __GX_IOY_MASK__ IOs mask 566 * @retval None 567 */ 568 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__))) 569 570 /** 571 * @brief Open analog switch on a group of IOs. 572 * @param __HANDLE__ TSC handle 573 * @param __GX_IOY_MASK__ IOs mask 574 * @retval None 575 */ 576 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__))) 577 578 /** 579 * @brief Close analog switch on a group of IOs. 580 * @param __HANDLE__ TSC handle 581 * @param __GX_IOY_MASK__ IOs mask 582 * @retval None 583 */ 584 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 585 586 /** 587 * @brief Enable a group of IOs in channel mode. 588 * @param __HANDLE__ TSC handle 589 * @param __GX_IOY_MASK__ IOs mask 590 * @retval None 591 */ 592 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 593 594 /** 595 * @brief Disable a group of channel IOs. 596 * @param __HANDLE__ TSC handle 597 * @param __GX_IOY_MASK__ IOs mask 598 * @retval None 599 */ 600 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__))) 601 602 /** 603 * @brief Enable a group of IOs in sampling mode. 604 * @param __HANDLE__ TSC handle 605 * @param __GX_IOY_MASK__ IOs mask 606 * @retval None 607 */ 608 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 609 610 /** 611 * @brief Disable a group of sampling IOs. 612 * @param __HANDLE__ TSC handle 613 * @param __GX_IOY_MASK__ IOs mask 614 * @retval None 615 */ 616 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__))) 617 618 /** 619 * @brief Enable acquisition groups. 620 * @param __HANDLE__ TSC handle 621 * @param __GX_MASK__ Groups mask 622 * @retval None 623 */ 624 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 625 626 /** 627 * @brief Disable acquisition groups. 628 * @param __HANDLE__ TSC handle 629 * @param __GX_MASK__ Groups mask 630 * @retval None 631 */ 632 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__))) 633 634 /** @brief Gets acquisition group status. 635 * @param __HANDLE__ TSC Handle 636 * @param __GX_INDEX__ Group index 637 * @retval SET or RESET 638 */ 639 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 640 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & (uint32_t)TSC_NB_OF_GROUPS) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & (uint32_t)TSC_NB_OF_GROUPS) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 641 642 /** 643 * @} 644 */ 645 646 /* Private macros ------------------------------------------------------------*/ 647 648 /** @defgroup TSC_Private_Macros TSC Private Macros 649 * @{ 650 */ 651 652 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 653 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 654 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 655 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 656 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 657 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 658 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 659 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 660 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 661 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 662 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 663 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 664 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 665 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 666 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 667 ((__VALUE__) == TSC_CTPH_16CYCLES)) 668 669 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 670 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 671 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 672 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 673 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 674 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 675 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 676 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 677 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 678 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 679 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 680 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 681 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 682 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 683 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 684 ((__VALUE__) == TSC_CTPL_16CYCLES)) 685 686 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 687 688 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 689 690 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 691 692 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 693 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 694 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 695 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 696 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 697 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 698 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 699 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 700 701 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 702 ((__VALUE__) == TSC_MCV_511) || \ 703 ((__VALUE__) == TSC_MCV_1023) || \ 704 ((__VALUE__) == TSC_MCV_2047) || \ 705 ((__VALUE__) == TSC_MCV_4095) || \ 706 ((__VALUE__) == TSC_MCV_8191) || \ 707 ((__VALUE__) == TSC_MCV_16383)) 708 709 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 710 711 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 712 713 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 714 715 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE)) 716 717 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 718 719 720 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 721 ((((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 722 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 723 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 724 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 725 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 726 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 727 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 728 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 729 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 730 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 731 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 732 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 733 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 734 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 735 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 736 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 737 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 738 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 739 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 740 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 741 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 742 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 743 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 744 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 745 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 746 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 747 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 748 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 749 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 750 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 751 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 752 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 753 754 /** 755 * @} 756 */ 757 758 /* Exported functions --------------------------------------------------------*/ 759 /** @addtogroup TSC_Exported_Functions 760 * @{ 761 */ 762 763 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 764 * @{ 765 */ 766 /* Initialization and de-initialization functions *****************************/ 767 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 768 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 769 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 770 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 771 772 /* Callbacks Register/UnRegister functions ***********************************/ 773 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 774 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback); 775 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 776 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 777 /** 778 * @} 779 */ 780 781 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 782 * @{ 783 */ 784 /* IO operation functions *****************************************************/ 785 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 786 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 787 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 788 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 789 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 790 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 791 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 792 /** 793 * @} 794 */ 795 796 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 797 * @{ 798 */ 799 /* Peripheral Control functions ***********************************************/ 800 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 801 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, uint32_t choice); 802 /** 803 * @} 804 */ 805 806 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 807 * @{ 808 */ 809 /* Peripheral State and Error functions ***************************************/ 810 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 811 /** 812 * @} 813 */ 814 815 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 816 * @{ 817 */ 818 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 819 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 820 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 821 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 822 /** 823 * @} 824 */ 825 826 /** 827 * @} 828 */ 829 830 /** 831 * @} 832 */ 833 834 /** 835 * @} 836 */ 837 838 #ifdef __cplusplus 839 } 840 #endif 841 842 #endif /* STM32L4xx_HAL_TSC_H */ 843 844 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 845
