1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_TSC_H 21 #define STM32L4xx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TSC 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TSC_Exported_Types TSC Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TSC state structure definition 46 */ 47 typedef enum 48 { 49 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 50 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 51 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 52 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 53 } HAL_TSC_StateTypeDef; 54 55 /** 56 * @brief TSC group status structure definition 57 */ 58 typedef enum 59 { 60 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 61 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 62 } TSC_GroupStatusTypeDef; 63 64 /** 65 * @brief TSC init structure definition 66 */ 67 typedef struct 68 { 69 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 70 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 71 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 72 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 73 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 74 This parameter can be set to ENABLE or DISABLE. */ 75 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 76 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 77 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 78 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 79 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 80 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 81 uint32_t MaxCountValue; /*!< Max count value 82 This parameter can be a value of @ref TSC_MaxCount_Value */ 83 uint32_t IODefaultMode; /*!< IO default mode 84 This parameter can be a value of @ref TSC_IO_Default_Mode */ 85 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 86 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 87 uint32_t AcquisitionMode; /*!< Acquisition mode 88 This parameter can be a value of @ref TSC_Acquisition_Mode */ 89 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 90 This parameter can be set to ENABLE or DISABLE. */ 91 uint32_t ChannelIOs; /*!< Channel IOs mask */ 92 uint32_t ShieldIOs; /*!< Shield IOs mask */ 93 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 94 } TSC_InitTypeDef; 95 96 /** 97 * @brief TSC IOs configuration structure definition 98 */ 99 typedef struct 100 { 101 uint32_t ChannelIOs; /*!< Channel IOs mask */ 102 uint32_t ShieldIOs; /*!< Shield IOs mask */ 103 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 104 } TSC_IOConfigTypeDef; 105 106 /** 107 * @brief TSC handle Structure definition 108 */ 109 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 110 typedef struct __TSC_HandleTypeDef 111 #else 112 typedef struct 113 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 114 { 115 TSC_TypeDef *Instance; /*!< Register base address */ 116 TSC_InitTypeDef Init; /*!< Initialization parameters */ 117 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 118 HAL_LockTypeDef Lock; /*!< Lock feature */ 119 __IO uint32_t ErrorCode; /*!< TSC Error code */ 120 121 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 122 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 123 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 124 125 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 126 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 127 128 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 129 } TSC_HandleTypeDef; 130 131 enum 132 { 133 TSC_GROUP1_IDX = 0x00UL, 134 TSC_GROUP2_IDX, 135 TSC_GROUP3_IDX, 136 TSC_GROUP4_IDX, 137 #if defined(TSC_IOCCR_G5_IO1) 138 TSC_GROUP5_IDX, 139 #endif /* TSC_IOCCR_G5_IO1 */ 140 #if defined(TSC_IOCCR_G6_IO1) 141 TSC_GROUP6_IDX, 142 #endif /* TSC_IOCCR_G6_IO1 */ 143 #if defined(TSC_IOCCR_G7_IO1) 144 TSC_GROUP7_IDX, 145 #endif /* TSC_IOCCR_G7_IO1 */ 146 #if defined(TSC_IOCCR_G8_IO1) 147 TSC_GROUP8_IDX, 148 #endif /* TSC_IOCCR_G8_IO1 */ 149 TSC_NB_OF_GROUPS 150 }; 151 152 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 153 /** 154 * @brief HAL TSC Callback ID enumeration definition 155 */ 156 typedef enum 157 { 158 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 159 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 160 161 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 162 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 163 164 } HAL_TSC_CallbackIDTypeDef; 165 166 /** 167 * @brief HAL TSC Callback pointer definition 168 */ 169 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 170 171 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 172 173 /** 174 * @} 175 */ 176 177 /* Exported constants --------------------------------------------------------*/ 178 /** @defgroup TSC_Exported_Constants TSC Exported Constants 179 * @{ 180 */ 181 182 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 183 * @brief TSC Error Code definition 184 * @{ 185 */ 186 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 187 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 188 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 189 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 190 /** 191 * @} 192 */ 193 194 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 195 * @{ 196 */ 197 #define TSC_CTPH_1CYCLE 0x00000000UL 198 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 199 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 200 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 201 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 202 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 203 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 204 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 205 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 206 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 207 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 208 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 209 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 210 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 211 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 212 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 213 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 214 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 215 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 216 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 217 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 218 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 219 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 220 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 221 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 222 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 223 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 224 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 225 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 226 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 227 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 228 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 234 * @{ 235 */ 236 #define TSC_CTPL_1CYCLE 0x00000000UL 237 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 238 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 239 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 240 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 241 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 242 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 243 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 244 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 245 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 246 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 247 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 248 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 249 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 250 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 251 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 252 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 253 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 254 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 255 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 256 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 257 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 258 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 259 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 260 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 261 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 262 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 263 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 264 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 265 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 266 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 267 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 273 * @{ 274 */ 275 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 276 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 282 * @{ 283 */ 284 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 285 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 286 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 287 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 288 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 289 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 290 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 291 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup TSC_MaxCount_Value Max Count Value 297 * @{ 298 */ 299 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 300 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 301 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 302 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 303 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 304 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 305 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup TSC_IO_Default_Mode IO Default Mode 311 * @{ 312 */ 313 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 314 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 315 /** 316 * @} 317 */ 318 319 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 320 * @{ 321 */ 322 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 323 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 324 /** 325 * @} 326 */ 327 328 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 329 * @{ 330 */ 331 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 332 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 333 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 334 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 335 when the selected signal is detected on the SYNC input pin) */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup TSC_interrupts_definition Interrupts definition 341 * @{ 342 */ 343 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 344 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup TSC_flags_definition Flags definition 350 * @{ 351 */ 352 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 353 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup TSC_Group_definition Group definition 359 * @{ 360 */ 361 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 362 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 363 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 364 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 365 #if defined(TSC_IOCCR_G5_IO1) 366 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 367 #endif /* TSC_IOCCR_G5_IO1 */ 368 #if defined(TSC_IOCCR_G6_IO1) 369 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 370 #endif /* TSC_IOCCR_G6_IO1 */ 371 #if defined(TSC_IOCCR_G7_IO1) 372 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 373 #endif /* TSC_IOCCR_G7_IO1 */ 374 #if defined(TSC_IOCCR_G8_IO1) 375 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 376 #endif /* TSC_IOCCR_G8_IO1 */ 377 378 #define TSC_GROUPX_NOT_SUPPORTED 0xFF000000UL /*!< TSC GroupX not supported */ 379 380 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 381 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 382 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 383 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 384 385 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 386 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 387 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 388 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 389 390 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 391 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 392 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 393 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 394 395 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 396 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 397 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 398 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 399 #if defined(TSC_IOCCR_G5_IO1) 400 401 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 402 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 403 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 404 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 405 #else 406 407 #define TSC_GROUP5_IO1 (uint32_t)(0x00000010UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group5 IO1 not supported */ 408 #define TSC_GROUP5_IO2 TSC_GROUP5_IO1 /*!< TSC Group5 IO2 not supported */ 409 #define TSC_GROUP5_IO3 TSC_GROUP5_IO1 /*!< TSC Group5 IO3 not supported */ 410 #define TSC_GROUP5_IO4 TSC_GROUP5_IO1 /*!< TSC Group5 IO4 not supported */ 411 #endif /* TSC_IOCCR_G5_IO1 */ 412 #if defined(TSC_IOCCR_G6_IO1) 413 414 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 415 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 416 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 417 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 418 #else 419 420 #define TSC_GROUP6_IO1 (uint32_t)(0x00000020UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group6 IO1 not supported */ 421 #define TSC_GROUP6_IO2 TSC_GROUP6_IO1 /*!< TSC Group6 IO2 not supported */ 422 #define TSC_GROUP6_IO3 TSC_GROUP6_IO1 /*!< TSC Group6 IO3 not supported */ 423 #define TSC_GROUP6_IO4 TSC_GROUP6_IO1 /*!< TSC Group6 IO4 not supported */ 424 #endif /* TSC_IOCCR_G6_IO1 */ 425 #if defined(TSC_IOCCR_G7_IO1) 426 427 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 428 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 429 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 430 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 431 #else 432 433 #define TSC_GROUP7_IO1 (uint32_t)(0x00000040UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group7 IO1 not supported */ 434 #define TSC_GROUP7_IO2 TSC_GROUP7_IO1 /*!< TSC Group7 IO2 not supported */ 435 #define TSC_GROUP7_IO3 TSC_GROUP7_IO1 /*!< TSC Group7 IO3 not supported */ 436 #define TSC_GROUP7_IO4 TSC_GROUP7_IO1 /*!< TSC Group7 IO4 not supported */ 437 #endif /* TSC_IOCCR_G7_IO1 */ 438 #if defined(TSC_IOCCR_G8_IO1) 439 440 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 441 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 442 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 443 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 444 #else 445 446 #define TSC_GROUP8_IO1 (uint32_t)(0x00000080UL | TSC_GROUPX_NOT_SUPPORTED) /*!< TSC Group8 IO1 not supported */ 447 #define TSC_GROUP8_IO2 TSC_GROUP8_IO1 /*!< TSC Group8 IO2 not supported */ 448 #define TSC_GROUP8_IO3 TSC_GROUP8_IO1 /*!< TSC Group8 IO3 not supported */ 449 #define TSC_GROUP8_IO4 TSC_GROUP8_IO1 /*!< TSC Group8 IO4 not supported */ 450 #endif /* TSC_IOCCR_G8_IO1 */ 451 /** 452 * @} 453 */ 454 455 /** 456 * @} 457 */ 458 459 /* Exported macros -----------------------------------------------------------*/ 460 461 /** @defgroup TSC_Exported_Macros TSC Exported Macros 462 * @{ 463 */ 464 465 /** @brief Reset TSC handle state. 466 * @param __HANDLE__ TSC handle 467 * @retval None 468 */ 469 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 470 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 471 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 472 (__HANDLE__)->MspInitCallback = NULL; \ 473 (__HANDLE__)->MspDeInitCallback = NULL; \ 474 } while(0) 475 #else 476 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 477 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 478 479 /** 480 * @brief Enable the TSC peripheral. 481 * @param __HANDLE__ TSC handle 482 * @retval None 483 */ 484 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 485 486 /** 487 * @brief Disable the TSC peripheral. 488 * @param __HANDLE__ TSC handle 489 * @retval None 490 */ 491 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 492 493 /** 494 * @brief Start acquisition. 495 * @param __HANDLE__ TSC handle 496 * @retval None 497 */ 498 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 499 500 /** 501 * @brief Stop acquisition. 502 * @param __HANDLE__ TSC handle 503 * @retval None 504 */ 505 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 506 507 /** 508 * @brief Set IO default mode to output push-pull low. 509 * @param __HANDLE__ TSC handle 510 * @retval None 511 */ 512 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 513 514 /** 515 * @brief Set IO default mode to input floating. 516 * @param __HANDLE__ TSC handle 517 * @retval None 518 */ 519 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 520 521 /** 522 * @brief Set synchronization polarity to falling edge. 523 * @param __HANDLE__ TSC handle 524 * @retval None 525 */ 526 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 527 528 /** 529 * @brief Set synchronization polarity to rising edge and high level. 530 * @param __HANDLE__ TSC handle 531 * @retval None 532 */ 533 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 534 535 /** 536 * @brief Enable TSC interrupt. 537 * @param __HANDLE__ TSC handle 538 * @param __INTERRUPT__ TSC interrupt 539 * @retval None 540 */ 541 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 542 543 /** 544 * @brief Disable TSC interrupt. 545 * @param __HANDLE__ TSC handle 546 * @param __INTERRUPT__ TSC interrupt 547 * @retval None 548 */ 549 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 550 551 /** @brief Check whether the specified TSC interrupt source is enabled or not. 552 * @param __HANDLE__ TSC Handle 553 * @param __INTERRUPT__ TSC interrupt 554 * @retval SET or RESET 555 */ 556 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 557 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 558 RESET) 559 560 /** 561 * @brief Check whether the specified TSC flag is set or not. 562 * @param __HANDLE__ TSC handle 563 * @param __FLAG__ TSC flag 564 * @retval SET or RESET 565 */ 566 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 567 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 568 569 /** 570 * @brief Clear the TSC's pending flag. 571 * @param __HANDLE__ TSC handle 572 * @param __FLAG__ TSC flag 573 * @retval None 574 */ 575 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 576 577 /** 578 * @brief Enable schmitt trigger hysteresis on a group of IOs. 579 * @param __HANDLE__ TSC handle 580 * @param __GX_IOY_MASK__ IOs mask 581 * @retval None 582 */ 583 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 584 585 /** 586 * @brief Disable schmitt trigger hysteresis on a group of IOs. 587 * @param __HANDLE__ TSC handle 588 * @param __GX_IOY_MASK__ IOs mask 589 * @retval None 590 */ 591 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 592 &= (~(__GX_IOY_MASK__))) 593 594 /** 595 * @brief Open analog switch on a group of IOs. 596 * @param __HANDLE__ TSC handle 597 * @param __GX_IOY_MASK__ IOs mask 598 * @retval None 599 */ 600 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 601 &= (~(__GX_IOY_MASK__))) 602 603 /** 604 * @brief Close analog switch on a group of IOs. 605 * @param __HANDLE__ TSC handle 606 * @param __GX_IOY_MASK__ IOs mask 607 * @retval None 608 */ 609 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 610 611 /** 612 * @brief Enable a group of IOs in channel mode. 613 * @param __HANDLE__ TSC handle 614 * @param __GX_IOY_MASK__ IOs mask 615 * @retval None 616 */ 617 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 618 619 /** 620 * @brief Disable a group of channel IOs. 621 * @param __HANDLE__ TSC handle 622 * @param __GX_IOY_MASK__ IOs mask 623 * @retval None 624 */ 625 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 626 &= (~(__GX_IOY_MASK__))) 627 628 /** 629 * @brief Enable a group of IOs in sampling mode. 630 * @param __HANDLE__ TSC handle 631 * @param __GX_IOY_MASK__ IOs mask 632 * @retval None 633 */ 634 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 635 636 /** 637 * @brief Disable a group of sampling IOs. 638 * @param __HANDLE__ TSC handle 639 * @param __GX_IOY_MASK__ IOs mask 640 * @retval None 641 */ 642 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 643 644 /** 645 * @brief Enable acquisition groups. 646 * @param __HANDLE__ TSC handle 647 * @param __GX_MASK__ Groups mask 648 * @retval None 649 */ 650 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 651 652 /** 653 * @brief Disable acquisition groups. 654 * @param __HANDLE__ TSC handle 655 * @param __GX_MASK__ Groups mask 656 * @retval None 657 */ 658 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 659 660 /** @brief Gets acquisition group status. 661 * @param __HANDLE__ TSC Handle 662 * @param __GX_INDEX__ Group index 663 * @retval SET or RESET 664 */ 665 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 666 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 667 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 668 669 /** 670 * @} 671 */ 672 673 /* Private macros ------------------------------------------------------------*/ 674 675 /** @defgroup TSC_Private_Macros TSC Private Macros 676 * @{ 677 */ 678 679 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 680 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 681 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 682 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 683 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 684 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 685 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 686 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 687 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 688 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 689 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 690 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 691 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 692 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 693 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 694 ((__VALUE__) == TSC_CTPH_16CYCLES)) 695 696 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 697 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 698 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 699 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 700 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 701 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 702 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 703 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 704 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 705 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 706 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 707 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 708 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 709 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 710 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 711 ((__VALUE__) == TSC_CTPL_16CYCLES)) 712 713 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 714 || ((FunctionalState)(__VALUE__) == ENABLE)) 715 716 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 717 718 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 719 720 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 721 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 722 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 723 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 724 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 725 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 726 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 727 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 728 729 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 730 ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ 731 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 732 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 733 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 734 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 735 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 736 737 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 738 ((__VALUE__) == TSC_MCV_511) || \ 739 ((__VALUE__) == TSC_MCV_1023) || \ 740 ((__VALUE__) == TSC_MCV_2047) || \ 741 ((__VALUE__) == TSC_MCV_4095) || \ 742 ((__VALUE__) == TSC_MCV_8191) || \ 743 ((__VALUE__) == TSC_MCV_16383)) 744 745 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 746 747 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 748 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 749 750 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 751 752 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 753 || ((FunctionalState)(__VALUE__) == ENABLE)) 754 755 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 756 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 757 758 759 #define IS_TSC_GROUP(__VALUE__) ((((__VALUE__) & TSC_GROUPX_NOT_SUPPORTED) != TSC_GROUPX_NOT_SUPPORTED) && \ 760 (((__VALUE__) == 0UL) ||\ 761 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 762 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 763 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 764 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 765 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 766 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 767 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 768 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 769 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 770 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 771 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 772 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 773 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 774 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 775 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 776 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 777 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 778 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 779 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 780 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 781 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 782 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 783 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 784 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 785 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 786 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 787 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 788 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 789 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 790 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 791 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 792 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))) 793 794 /** 795 * @} 796 */ 797 798 /* Exported functions --------------------------------------------------------*/ 799 /** @addtogroup TSC_Exported_Functions 800 * @{ 801 */ 802 803 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 804 * @{ 805 */ 806 /* Initialization and de-initialization functions *****************************/ 807 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 808 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 809 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 810 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 811 812 /* Callbacks Register/UnRegister functions ***********************************/ 813 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 814 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 815 pTSC_CallbackTypeDef pCallback); 816 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 817 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 818 /** 819 * @} 820 */ 821 822 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 823 * @{ 824 */ 825 /* IO operation functions *****************************************************/ 826 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 827 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 828 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 829 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 830 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 831 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index); 832 uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index); 833 /** 834 * @} 835 */ 836 837 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 838 * @{ 839 */ 840 /* Peripheral Control functions ***********************************************/ 841 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config); 842 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 843 /** 844 * @} 845 */ 846 847 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 848 * @{ 849 */ 850 /* Peripheral State and Error functions ***************************************/ 851 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 852 /** 853 * @} 854 */ 855 856 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 857 * @{ 858 */ 859 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 860 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 861 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 862 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 863 /** 864 * @} 865 */ 866 867 /** 868 * @} 869 */ 870 871 /** 872 * @} 873 */ 874 875 /** 876 * @} 877 */ 878 879 #ifdef __cplusplus 880 } 881 #endif 882 883 #endif /* STM32L4xx_HAL_TSC_H */ 884
