1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_sram.h 4 * @author MCD Application Team 5 * @brief Header file of SRAM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_SRAM_H 38 #define __STM32L4xx_HAL_SRAM_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined(FMC_BANK1) 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l4xx_ll_fmc.h" 48 49 /** @addtogroup STM32L4xx_HAL_Driver 50 * @{ 51 */ 52 /** @addtogroup SRAM 53 * @{ 54 */ 55 56 /* Exported typedef ----------------------------------------------------------*/ 57 58 /** @defgroup SRAM_Exported_Types SRAM Exported Types 59 * @{ 60 */ 61 /** 62 * @brief HAL SRAM State structures definition 63 */ 64 typedef enum 65 { 66 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 67 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 68 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 69 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 70 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 71 }HAL_SRAM_StateTypeDef; 72 73 /** 74 * @brief SRAM handle Structure definition 75 */ 76 typedef struct 77 { 78 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 79 80 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 81 82 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 83 84 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 85 86 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 87 88 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 89 }SRAM_HandleTypeDef; 90 91 /** 92 * @} 93 */ 94 95 /* Exported constants --------------------------------------------------------*/ 96 /* Exported macro ------------------------------------------------------------*/ 97 98 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 99 * @{ 100 */ 101 102 /** @brief Reset SRAM handle state 103 * @param __HANDLE__ SRAM handle 104 * @retval None 105 */ 106 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 107 108 /** 109 * @} 110 */ 111 112 /* Exported functions --------------------------------------------------------*/ 113 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 114 * @{ 115 */ 116 117 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 118 * @{ 119 */ 120 121 /* Initialization/de-initialization functions ********************************/ 122 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); 123 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 124 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 125 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 126 127 /** 128 * @} 129 */ 130 131 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 132 * @{ 133 */ 134 135 /* I/O operation functions ***************************************************/ 136 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); 137 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); 138 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); 139 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); 140 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); 141 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); 142 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); 143 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); 144 145 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 146 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 147 148 /** 149 * @} 150 */ 151 152 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 153 * @{ 154 */ 155 156 /* SRAM Control functions ****************************************************/ 157 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 158 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 159 160 /** 161 * @} 162 */ 163 164 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 165 * @{ 166 */ 167 168 /* SRAM State functions ******************************************************/ 169 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 170 171 /** 172 * @} 173 */ 174 175 /** 176 * @} 177 */ 178 179 /** 180 * @} 181 */ 182 183 /** 184 * @} 185 */ 186 187 #endif /* FMC_BANK1 */ 188 189 #ifdef __cplusplus 190 } 191 #endif 192 193 #endif /* __STM32L4xx_HAL_SRAM_H */ 194 195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 196
