1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_sram.h 4 * @author MCD Application Team 5 * @brief Header file of SRAM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_SRAM_H 21 #define STM32L4xx_HAL_SRAM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMC_BANK1) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l4xx_ll_fmc.h" 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 /** @addtogroup SRAM 36 * @{ 37 */ 38 39 /* Exported typedef ----------------------------------------------------------*/ 40 41 /** @defgroup SRAM_Exported_Types SRAM Exported Types 42 * @{ 43 */ 44 /** 45 * @brief HAL SRAM State structures definition 46 */ 47 typedef enum 48 { 49 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 50 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 51 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 52 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 53 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 54 55 } HAL_SRAM_StateTypeDef; 56 57 /** 58 * @brief SRAM handle Structure definition 59 */ 60 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 61 typedef struct __SRAM_HandleTypeDef 62 #else 63 typedef struct 64 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 65 { 66 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 67 68 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 69 70 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 71 72 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 73 74 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 75 76 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 77 78 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 79 void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ 80 void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ 81 void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ 82 void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ 83 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 84 } SRAM_HandleTypeDef; 85 86 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 87 /** 88 * @brief HAL SRAM Callback ID enumeration definition 89 */ 90 typedef enum 91 { 92 HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ 93 HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ 94 HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ 95 HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ 96 } HAL_SRAM_CallbackIDTypeDef; 97 98 /** 99 * @brief HAL SRAM Callback pointer definition 100 */ 101 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); 102 typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); 103 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 104 /** 105 * @} 106 */ 107 108 /* Exported constants --------------------------------------------------------*/ 109 /* Exported macro ------------------------------------------------------------*/ 110 111 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 112 * @{ 113 */ 114 115 /** @brief Reset SRAM handle state 116 * @param __HANDLE__ SRAM handle 117 * @retval None 118 */ 119 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 120 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ 121 (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ 122 (__HANDLE__)->MspInitCallback = NULL; \ 123 (__HANDLE__)->MspDeInitCallback = NULL; \ 124 } while(0) 125 #else 126 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 127 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 128 129 /** 130 * @} 131 */ 132 133 /* Exported functions --------------------------------------------------------*/ 134 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 135 * @{ 136 */ 137 138 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 139 * @{ 140 */ 141 142 /* Initialization/de-initialization functions ********************************/ 143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, 144 FMC_NORSRAM_TimingTypeDef *ExtTiming); 145 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 146 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 147 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 148 149 /** 150 * @} 151 */ 152 153 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 154 * @{ 155 */ 156 157 /* I/O operation functions ***************************************************/ 158 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, 159 uint32_t BufferSize); 160 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, 161 uint32_t BufferSize); 162 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, 163 uint32_t BufferSize); 164 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, 165 uint32_t BufferSize); 166 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 167 uint32_t BufferSize); 168 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 169 uint32_t BufferSize); 170 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, 171 uint32_t BufferSize); 172 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, 173 uint32_t BufferSize); 174 175 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 176 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 177 178 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) 179 /* SRAM callback registering/unregistering */ 180 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 181 pSRAM_CallbackTypeDef pCallback); 182 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); 183 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, 184 pSRAM_DmaCallbackTypeDef pCallback); 185 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ 186 187 /** 188 * @} 189 */ 190 191 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 192 * @{ 193 */ 194 195 /* SRAM Control functions ****************************************************/ 196 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 197 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 198 199 /** 200 * @} 201 */ 202 203 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 204 * @{ 205 */ 206 207 /* SRAM State functions ******************************************************/ 208 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 209 210 /** 211 * @} 212 */ 213 214 /** 215 * @} 216 */ 217 218 /** 219 * @} 220 */ 221 222 /** 223 * @} 224 */ 225 226 #endif /* FMC_BANK1 */ 227 228 #ifdef __cplusplus 229 } 230 #endif 231 232 #endif /* STM32L4xx_HAL_SRAM_H */ 233
