1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_spi.h 4 * @author MCD Application Team 5 * @brief Header file of SPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_SPI_H 38 #define STM32L4xx_HAL_SPI_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup SPI 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup SPI_Exported_Types SPI Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief SPI Configuration Structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Mode; /*!< Specifies the SPI operating mode. 66 This parameter can be a value of @ref SPI_Mode */ 67 68 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 69 This parameter can be a value of @ref SPI_Direction */ 70 71 uint32_t DataSize; /*!< Specifies the SPI data size. 72 This parameter can be a value of @ref SPI_Data_Size */ 73 74 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 75 This parameter can be a value of @ref SPI_Clock_Polarity */ 76 77 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 78 This parameter can be a value of @ref SPI_Clock_Phase */ 79 80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 81 hardware (NSS pin) or by software using the SSI bit. 82 This parameter can be a value of @ref SPI_Slave_Select_management */ 83 84 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 85 used to configure the transmit and receive SCK clock. 86 This parameter can be a value of @ref SPI_BaudRate_Prescaler 87 @note The communication clock is derived from the master 88 clock. The slave clock does not need to be set. */ 89 90 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 91 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 92 93 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 94 This parameter can be a value of @ref SPI_TI_mode */ 95 96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 97 This parameter can be a value of @ref SPI_CRC_Calculation */ 98 99 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 100 This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ 101 102 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 103 CRC Length is only used with Data8 and Data16, not other data size 104 This parameter can be a value of @ref SPI_CRC_length */ 105 106 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 107 This parameter can be a value of @ref SPI_NSSP_Mode 108 This mode is activated by the NSSP bit in the SPIx_CR2 register and 109 it takes effect only if the SPI interface is configured as Motorola SPI 110 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, 111 CPOL setting is ignored).. */ 112 } SPI_InitTypeDef; 113 114 /** 115 * @brief HAL SPI State structure definition 116 */ 117 typedef enum 118 { 119 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ 120 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 121 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 122 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 123 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 124 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ 125 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ 126 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ 127 } HAL_SPI_StateTypeDef; 128 129 /** 130 * @brief SPI handle Structure definition 131 */ 132 typedef struct __SPI_HandleTypeDef 133 { 134 SPI_TypeDef *Instance; /*!< SPI registers base address */ 135 136 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 137 138 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 139 140 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 141 142 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 143 144 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 145 146 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 147 148 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 149 150 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 151 152 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 153 154 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 155 156 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 157 158 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 159 160 HAL_LockTypeDef Lock; /*!< Locking object */ 161 162 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 163 164 __IO uint32_t ErrorCode; /*!< SPI Error code */ 165 166 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 167 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 168 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 169 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 170 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 171 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 172 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 173 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 174 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 175 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 176 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 177 178 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 179 } SPI_HandleTypeDef; 180 181 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 182 /** 183 * @brief HAL SPI Callback ID enumeration definition 184 */ 185 typedef enum 186 { 187 HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ 188 HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ 189 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ 190 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ 191 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ 192 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ 193 HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ 194 HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ 195 HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ 196 HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ 197 198 } HAL_SPI_CallbackIDTypeDef; 199 200 /** 201 * @brief HAL SPI Callback pointer definition 202 */ 203 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 204 205 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 206 /** 207 * @} 208 */ 209 210 /* Exported constants --------------------------------------------------------*/ 211 /** @defgroup SPI_Exported_Constants SPI Exported Constants 212 * @{ 213 */ 214 215 /** @defgroup SPI_Error_Code SPI Error Code 216 * @{ 217 */ 218 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ 219 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ 220 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ 221 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ 222 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ 223 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ 224 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ 225 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ 226 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 227 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ 228 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup SPI_Mode SPI Mode 234 * @{ 235 */ 236 #define SPI_MODE_SLAVE (0x00000000U) 237 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) 238 /** 239 * @} 240 */ 241 242 /** @defgroup SPI_Direction SPI Direction Mode 243 * @{ 244 */ 245 #define SPI_DIRECTION_2LINES (0x00000000U) 246 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY 247 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE 248 /** 249 * @} 250 */ 251 252 /** @defgroup SPI_Data_Size SPI Data Size 253 * @{ 254 */ 255 #define SPI_DATASIZE_4BIT (0x00000300U) 256 #define SPI_DATASIZE_5BIT (0x00000400U) 257 #define SPI_DATASIZE_6BIT (0x00000500U) 258 #define SPI_DATASIZE_7BIT (0x00000600U) 259 #define SPI_DATASIZE_8BIT (0x00000700U) 260 #define SPI_DATASIZE_9BIT (0x00000800U) 261 #define SPI_DATASIZE_10BIT (0x00000900U) 262 #define SPI_DATASIZE_11BIT (0x00000A00U) 263 #define SPI_DATASIZE_12BIT (0x00000B00U) 264 #define SPI_DATASIZE_13BIT (0x00000C00U) 265 #define SPI_DATASIZE_14BIT (0x00000D00U) 266 #define SPI_DATASIZE_15BIT (0x00000E00U) 267 #define SPI_DATASIZE_16BIT (0x00000F00U) 268 /** 269 * @} 270 */ 271 272 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 273 * @{ 274 */ 275 #define SPI_POLARITY_LOW (0x00000000U) 276 #define SPI_POLARITY_HIGH SPI_CR1_CPOL 277 /** 278 * @} 279 */ 280 281 /** @defgroup SPI_Clock_Phase SPI Clock Phase 282 * @{ 283 */ 284 #define SPI_PHASE_1EDGE (0x00000000U) 285 #define SPI_PHASE_2EDGE SPI_CR1_CPHA 286 /** 287 * @} 288 */ 289 290 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management 291 * @{ 292 */ 293 #define SPI_NSS_SOFT SPI_CR1_SSM 294 #define SPI_NSS_HARD_INPUT (0x00000000U) 295 #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) 296 /** 297 * @} 298 */ 299 300 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 301 * @{ 302 */ 303 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP 304 #define SPI_NSS_PULSE_DISABLE (0x00000000U) 305 /** 306 * @} 307 */ 308 309 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 310 * @{ 311 */ 312 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) 313 #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) 314 #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) 315 #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) 316 #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) 317 #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) 318 #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) 319 #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) 320 /** 321 * @} 322 */ 323 324 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission 325 * @{ 326 */ 327 #define SPI_FIRSTBIT_MSB (0x00000000U) 328 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST 329 /** 330 * @} 331 */ 332 333 /** @defgroup SPI_TI_mode SPI TI Mode 334 * @{ 335 */ 336 #define SPI_TIMODE_DISABLE (0x00000000U) 337 #define SPI_TIMODE_ENABLE SPI_CR2_FRF 338 /** 339 * @} 340 */ 341 342 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 343 * @{ 344 */ 345 #define SPI_CRCCALCULATION_DISABLE (0x00000000U) 346 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN 347 /** 348 * @} 349 */ 350 351 /** @defgroup SPI_CRC_length SPI CRC Length 352 * @{ 353 * This parameter can be one of the following values: 354 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size 355 * SPI_CRC_LENGTH_8BIT : CRC 8bit 356 * SPI_CRC_LENGTH_16BIT : CRC 16bit 357 */ 358 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U) 359 #define SPI_CRC_LENGTH_8BIT (0x00000001U) 360 #define SPI_CRC_LENGTH_16BIT (0x00000002U) 361 /** 362 * @} 363 */ 364 365 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold 366 * @{ 367 * This parameter can be one of the following values: 368 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : 369 * RXNE event is generated if the FIFO 370 * level is greater or equal to 1/4(8-bits). 371 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO 372 * level is greater or equal to 1/2(16 bits). */ 373 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH 374 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH 375 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) 376 /** 377 * @} 378 */ 379 380 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 381 * @{ 382 */ 383 #define SPI_IT_TXE SPI_CR2_TXEIE 384 #define SPI_IT_RXNE SPI_CR2_RXNEIE 385 #define SPI_IT_ERR SPI_CR2_ERRIE 386 /** 387 * @} 388 */ 389 390 /** @defgroup SPI_Flags_definition SPI Flags Definition 391 * @{ 392 */ 393 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ 394 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ 395 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ 396 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ 397 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ 398 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ 399 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ 400 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ 401 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ 402 #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) 403 /** 404 * @} 405 */ 406 407 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level 408 * @{ 409 */ 410 #define SPI_FTLVL_EMPTY (0x00000000U) 411 #define SPI_FTLVL_QUARTER_FULL (0x00000800U) 412 #define SPI_FTLVL_HALF_FULL (0x00001000U) 413 #define SPI_FTLVL_FULL (0x00001800U) 414 415 /** 416 * @} 417 */ 418 419 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 420 * @{ 421 */ 422 #define SPI_FRLVL_EMPTY (0x00000000U) 423 #define SPI_FRLVL_QUARTER_FULL (0x00000200U) 424 #define SPI_FRLVL_HALF_FULL (0x00000400U) 425 #define SPI_FRLVL_FULL (0x00000600U) 426 /** 427 * @} 428 */ 429 430 /** 431 * @} 432 */ 433 434 /* Exported macros -----------------------------------------------------------*/ 435 /** @defgroup SPI_Exported_Macros SPI Exported Macros 436 * @{ 437 */ 438 439 /** @brief Reset SPI handle state. 440 * @param __HANDLE__ specifies the SPI Handle. 441 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 442 * @retval None 443 */ 444 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 445 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 446 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 447 (__HANDLE__)->MspInitCallback = NULL; \ 448 (__HANDLE__)->MspDeInitCallback = NULL; \ 449 } while(0) 450 #else 451 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 452 #endif 453 454 /** @brief Enable the specified SPI interrupts. 455 * @param __HANDLE__ specifies the SPI Handle. 456 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 457 * @param __INTERRUPT__ specifies the interrupt source to enable. 458 * This parameter can be one of the following values: 459 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 460 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 461 * @arg SPI_IT_ERR: Error interrupt enable 462 * @retval None 463 */ 464 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 465 466 /** @brief Disable the specified SPI interrupts. 467 * @param __HANDLE__ specifies the SPI handle. 468 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. 469 * @param __INTERRUPT__ specifies the interrupt source to disable. 470 * This parameter can be one of the following values: 471 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 472 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 473 * @arg SPI_IT_ERR: Error interrupt enable 474 * @retval None 475 */ 476 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 477 478 /** @brief Check whether the specified SPI interrupt source is enabled or not. 479 * @param __HANDLE__ specifies the SPI Handle. 480 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 481 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 482 * This parameter can be one of the following values: 483 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 484 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 485 * @arg SPI_IT_ERR: Error interrupt enable 486 * @retval The new state of __IT__ (TRUE or FALSE). 487 */ 488 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 489 490 /** @brief Check whether the specified SPI flag is set or not. 491 * @param __HANDLE__ specifies the SPI Handle. 492 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 493 * @param __FLAG__ specifies the flag to check. 494 * This parameter can be one of the following values: 495 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag 496 * @arg SPI_FLAG_TXE: Transmit buffer empty flag 497 * @arg SPI_FLAG_CRCERR: CRC error flag 498 * @arg SPI_FLAG_MODF: Mode fault flag 499 * @arg SPI_FLAG_OVR: Overrun flag 500 * @arg SPI_FLAG_BSY: Busy flag 501 * @arg SPI_FLAG_FRE: Frame format error flag 502 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level 503 * @arg SPI_FLAG_FRLVL: SPI fifo reception level 504 * @retval The new state of __FLAG__ (TRUE or FALSE). 505 */ 506 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 507 508 /** @brief Clear the SPI CRCERR pending flag. 509 * @param __HANDLE__ specifies the SPI Handle. 510 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 511 * @retval None 512 */ 513 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) 514 515 /** @brief Clear the SPI MODF pending flag. 516 * @param __HANDLE__ specifies the SPI Handle. 517 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 518 * @retval None 519 */ 520 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ 521 do{ \ 522 __IO uint32_t tmpreg_modf = 0x00U; \ 523 tmpreg_modf = (__HANDLE__)->Instance->SR; \ 524 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ 525 UNUSED(tmpreg_modf); \ 526 } while(0U) 527 528 /** @brief Clear the SPI OVR pending flag. 529 * @param __HANDLE__ specifies the SPI Handle. 530 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 531 * @retval None 532 */ 533 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ 534 do{ \ 535 __IO uint32_t tmpreg_ovr = 0x00U; \ 536 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 537 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 538 UNUSED(tmpreg_ovr); \ 539 } while(0U) 540 541 /** @brief Clear the SPI FRE pending flag. 542 * @param __HANDLE__ specifies the SPI Handle. 543 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 544 * @retval None 545 */ 546 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ 547 do{ \ 548 __IO uint32_t tmpreg_fre = 0x00U; \ 549 tmpreg_fre = (__HANDLE__)->Instance->SR; \ 550 UNUSED(tmpreg_fre); \ 551 }while(0U) 552 553 /** @brief Enable the SPI peripheral. 554 * @param __HANDLE__ specifies the SPI Handle. 555 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 556 * @retval None 557 */ 558 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 559 560 /** @brief Disable the SPI peripheral. 561 * @param __HANDLE__ specifies the SPI Handle. 562 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 563 * @retval None 564 */ 565 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 566 567 /** 568 * @} 569 */ 570 571 /* Private macros ------------------------------------------------------------*/ 572 /** @defgroup SPI_Private_Macros SPI Private Macros 573 * @{ 574 */ 575 576 /** @brief Set the SPI transmit-only mode. 577 * @param __HANDLE__ specifies the SPI Handle. 578 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 579 * @retval None 580 */ 581 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 582 583 /** @brief Set the SPI receive-only mode. 584 * @param __HANDLE__ specifies the SPI Handle. 585 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 586 * @retval None 587 */ 588 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 589 590 /** @brief Reset the CRC calculation of the SPI. 591 * @param __HANDLE__ specifies the SPI Handle. 592 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 593 * @retval None 594 */ 595 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ 596 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) 597 598 /** @brief Check whether the specified SPI flag is set or not. 599 * @param __SR__ copy of SPI SR regsiter. 600 * @param __FLAG__ specifies the flag to check. 601 * This parameter can be one of the following values: 602 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag 603 * @arg SPI_FLAG_TXE: Transmit buffer empty flag 604 * @arg SPI_FLAG_CRCERR: CRC error flag 605 * @arg SPI_FLAG_MODF: Mode fault flag 606 * @arg SPI_FLAG_OVR: Overrun flag 607 * @arg SPI_FLAG_BSY: Busy flag 608 * @arg SPI_FLAG_FRE: Frame format error flag 609 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level 610 * @arg SPI_FLAG_FRLVL: SPI fifo reception level 611 * @retval SET or RESET. 612 */ 613 #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) 614 615 /** @brief Check whether the specified SPI Interrupt is set or not. 616 * @param __CR2__ copy of SPI CR2 regsiter. 617 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 618 * This parameter can be one of the following values: 619 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 620 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 621 * @arg SPI_IT_ERR: Error interrupt enable 622 * @retval SET or RESET. 623 */ 624 #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 625 626 /** @brief Checks if SPI Mode parameter is in allowed range. 627 * @param __MODE__ specifies the SPI Mode. 628 * This parameter can be a value of @ref SPI_Mode 629 * @retval None 630 */ 631 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ 632 ((__MODE__) == SPI_MODE_MASTER)) 633 634 /** @brief Checks if SPI Direction Mode parameter is in allowed range. 635 * @param __MODE__ specifies the SPI Direction Mode. 636 * This parameter can be a value of @ref SPI_Direction 637 * @retval None 638 */ 639 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 640 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ 641 ((__MODE__) == SPI_DIRECTION_1LINE)) 642 643 /** @brief Checks if SPI Direction Mode parameter is 2 lines. 644 * @param __MODE__ specifies the SPI Direction Mode. 645 * @retval None 646 */ 647 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) 648 649 /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. 650 * @param __MODE__ specifies the SPI Direction Mode. 651 * @retval None 652 */ 653 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 654 ((__MODE__) == SPI_DIRECTION_1LINE)) 655 656 /** @brief Checks if SPI Data Size parameter is in allowed range. 657 * @param __DATASIZE__ specifies the SPI Data Size. 658 * This parameter can be a value of @ref SPI_Data_Size 659 * @retval None 660 */ 661 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ 662 ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ 663 ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ 664 ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ 665 ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ 666 ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ 667 ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ 668 ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ 669 ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ 670 ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ 671 ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ 672 ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ 673 ((__DATASIZE__) == SPI_DATASIZE_4BIT)) 674 675 /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. 676 * @param __CPOL__ specifies the SPI serial clock steady state. 677 * This parameter can be a value of @ref SPI_Clock_Polarity 678 * @retval None 679 */ 680 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ 681 ((__CPOL__) == SPI_POLARITY_HIGH)) 682 683 /** @brief Checks if SPI Clock Phase parameter is in allowed range. 684 * @param __CPHA__ specifies the SPI Clock Phase. 685 * This parameter can be a value of @ref SPI_Clock_Phase 686 * @retval None 687 */ 688 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ 689 ((__CPHA__) == SPI_PHASE_2EDGE)) 690 691 /** @brief Checks if SPI Slave Select parameter is in allowed range. 692 * @param __NSS__ specifies the SPI Slave Slelect management parameter. 693 * This parameter can be a value of @ref SPI_Slave_Select_management 694 * @retval None 695 */ 696 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ 697 ((__NSS__) == SPI_NSS_HARD_INPUT) || \ 698 ((__NSS__) == SPI_NSS_HARD_OUTPUT)) 699 700 /** @brief Checks if SPI NSS Pulse parameter is in allowed range. 701 * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. 702 * This parameter can be a value of @ref SPI_NSSP_Mode 703 * @retval None 704 */ 705 #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ 706 ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) 707 708 /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. 709 * @param __PRESCALER__ specifies the SPI Baudrate prescaler. 710 * This parameter can be a value of @ref SPI_BaudRate_Prescaler 711 * @retval None 712 */ 713 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ 714 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ 715 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ 716 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ 717 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ 718 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ 719 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ 720 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) 721 722 /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. 723 * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). 724 * This parameter can be a value of @ref SPI_MSB_LSB_transmission 725 * @retval None 726 */ 727 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ 728 ((__BIT__) == SPI_FIRSTBIT_LSB)) 729 730 /** @brief Checks if SPI TI mode parameter is in allowed range. 731 * @param __MODE__ specifies the SPI TI mode. 732 * This parameter can be a value of @ref SPI_TI_mode 733 * @retval None 734 */ 735 #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ 736 ((__MODE__) == SPI_TIMODE_ENABLE)) 737 738 /** @brief Checks if SPI CRC calculation enabled state is in allowed range. 739 * @param __CALCULATION__ specifies the SPI CRC calculation enable state. 740 * This parameter can be a value of @ref SPI_CRC_Calculation 741 * @retval None 742 */ 743 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ 744 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) 745 746 /** @brief Checks if SPI CRC length is in allowed range. 747 * @param __LENGTH__ specifies the SPI CRC length. 748 * This parameter can be a value of @ref SPI_CRC_length 749 * @retval None 750 */ 751 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ 752 ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ 753 ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) 754 755 /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. 756 * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. 757 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 758 * @retval None 759 */ 760 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) 761 762 /** @brief Checks if DMA handle is valid. 763 * @param __HANDLE__ specifies a DMA Handle. 764 * @retval None 765 */ 766 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) 767 768 /** 769 * @} 770 */ 771 772 /* Include SPI HAL Extended module */ 773 #include "stm32l4xx_hal_spi_ex.h" 774 775 /* Exported functions --------------------------------------------------------*/ 776 /** @addtogroup SPI_Exported_Functions 777 * @{ 778 */ 779 780 /** @addtogroup SPI_Exported_Functions_Group1 781 * @{ 782 */ 783 /* Initialization/de-initialization functions ********************************/ 784 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 785 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 786 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 787 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 788 789 /* Callbacks Register/UnRegister functions ***********************************/ 790 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 791 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); 792 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 793 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 794 /** 795 * @} 796 */ 797 798 /** @addtogroup SPI_Exported_Functions_Group2 799 * @{ 800 */ 801 /* I/O operation functions ***************************************************/ 802 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 803 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 804 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, 805 uint32_t Timeout); 806 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 807 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 808 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 809 uint16_t Size); 810 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 811 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 812 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 813 uint16_t Size); 814 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 815 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 816 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 817 /* Transfer Abort functions */ 818 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 819 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 820 821 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 822 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 823 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 824 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 825 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 826 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 827 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 828 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 829 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 830 /** 831 * @} 832 */ 833 834 /** @addtogroup SPI_Exported_Functions_Group3 835 * @{ 836 */ 837 /* Peripheral State and Error functions ***************************************/ 838 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); 839 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); 840 /** 841 * @} 842 */ 843 844 /** 845 * @} 846 */ 847 848 /** 849 * @} 850 */ 851 852 /** 853 * @} 854 */ 855 856 #ifdef __cplusplus 857 } 858 #endif 859 860 #endif /* STM32L4xx_HAL_SPI_H */ 861 862 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 863
