1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_smbus.h 4 * @author MCD Application Team 5 * @brief Header file of SMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_SMBUS_H 38 #define STM32L4xx_HAL_SMBUS_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup SMBUS 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 57 * @{ 58 */ 59 60 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 61 * @brief SMBUS Configuration Structure definition 62 * @{ 63 */ 64 typedef struct 65 { 66 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 67 This parameter calculated by referring to SMBUS initialization 68 section in Reference manual */ 69 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 70 This parameter can be a value of @ref SMBUS_Analog_Filter */ 71 72 uint32_t OwnAddress1; /*!< Specifies the first device own address. 73 This parameter can be a 7-bit or 10-bit address. */ 74 75 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 76 This parameter can be a value of @ref SMBUS_addressing_mode */ 77 78 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 79 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 80 81 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 82 This parameter can be a 7-bit address. */ 83 84 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 85 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 86 87 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 88 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 89 90 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 91 This parameter can be a value of @ref SMBUS_nostretch_mode */ 92 93 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 94 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 95 96 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 97 This parameter can be a value of @ref SMBUS_peripheral_mode */ 98 99 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 100 (Enable bits and different timeout values) 101 This parameter calculated by referring to SMBUS initialization 102 section in Reference manual */ 103 } SMBUS_InitTypeDef; 104 /** 105 * @} 106 */ 107 108 /** @defgroup HAL_state_definition HAL state definition 109 * @brief HAL State definition 110 * @{ 111 */ 112 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 113 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 114 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 115 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 116 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 117 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 118 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 119 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 120 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 121 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 122 /** 123 * @} 124 */ 125 126 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 127 * @brief SMBUS Error Code definition 128 * @{ 129 */ 130 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 131 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 132 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 133 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 134 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 135 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 136 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 137 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 138 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 139 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 140 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 141 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 142 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 143 /** 144 * @} 145 */ 146 147 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 148 * @brief SMBUS handle Structure definition 149 * @{ 150 */ 151 typedef struct __SMBUS_HandleTypeDef 152 { 153 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 154 155 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 156 157 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 158 159 uint16_t XferSize; /*!< SMBUS transfer size */ 160 161 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 162 163 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 164 165 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 166 167 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 168 169 __IO uint32_t State; /*!< SMBUS communication state */ 170 171 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 172 173 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 174 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ 175 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ 176 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ 177 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ 178 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ 179 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ 180 181 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ 182 183 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ 184 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ 185 186 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 187 } SMBUS_HandleTypeDef; 188 189 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 190 /** 191 * @brief HAL SMBUS Callback ID enumeration definition 192 */ 193 typedef enum 194 { 195 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 196 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 197 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 198 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 199 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 200 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 201 202 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 203 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 204 205 } HAL_SMBUS_CallbackIDTypeDef; 206 207 /** 208 * @brief HAL SMBUS Callback pointer definition 209 */ 210 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ 211 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ 212 213 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 214 /** 215 * @} 216 */ 217 218 /** 219 * @} 220 */ 221 /* Exported constants --------------------------------------------------------*/ 222 223 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 224 * @{ 225 */ 226 227 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 228 * @{ 229 */ 230 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 231 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 232 /** 233 * @} 234 */ 235 236 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 237 * @{ 238 */ 239 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 240 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 241 /** 242 * @} 243 */ 244 245 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 246 * @{ 247 */ 248 249 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 250 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 251 /** 252 * @} 253 */ 254 255 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 256 * @{ 257 */ 258 259 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 260 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 261 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 262 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 263 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 264 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 265 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 266 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 267 /** 268 * @} 269 */ 270 271 272 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 273 * @{ 274 */ 275 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 276 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 277 /** 278 * @} 279 */ 280 281 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 282 * @{ 283 */ 284 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 285 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 286 /** 287 * @} 288 */ 289 290 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 291 * @{ 292 */ 293 #define SMBUS_PEC_DISABLE (0x00000000U) 294 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 295 /** 296 * @} 297 */ 298 299 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 300 * @{ 301 */ 302 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 304 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 305 /** 306 * @} 307 */ 308 309 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 310 * @{ 311 */ 312 313 #define SMBUS_SOFTEND_MODE (0x00000000U) 314 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 315 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 316 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 317 /** 318 * @} 319 */ 320 321 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 322 * @{ 323 */ 324 325 #define SMBUS_NO_STARTSTOP (0x00000000U) 326 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 327 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 328 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 329 /** 330 * @} 331 */ 332 333 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 334 * @{ 335 */ 336 337 /* List of XferOptions in usage of : 338 * 1- Restart condition when direction change 339 * 2- No Restart condition in other use cases 340 */ 341 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 342 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 343 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 344 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 345 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 346 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 347 348 /* List of XferOptions in usage of : 349 * 1- Restart condition in all use cases (direction change or not) 350 */ 351 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 352 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 353 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 354 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 355 /** 356 * @} 357 */ 358 359 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 360 * @brief SMBUS Interrupt definition 361 * Elements values convention: 0xXXXXXXXX 362 * - XXXXXXXX : Interrupt control mask 363 * @{ 364 */ 365 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 366 #define SMBUS_IT_TCI I2C_CR1_TCIE 367 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 368 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 369 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 370 #define SMBUS_IT_RXI I2C_CR1_RXIE 371 #define SMBUS_IT_TXI I2C_CR1_TXIE 372 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) 373 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) 374 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 375 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 376 /** 377 * @} 378 */ 379 380 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 381 * @brief Flag definition 382 * Elements values convention: 0xXXXXYYYY 383 * - XXXXXXXX : Flag mask 384 * @{ 385 */ 386 387 #define SMBUS_FLAG_TXE I2C_ISR_TXE 388 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 389 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 390 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 391 #define SMBUS_FLAG_AF I2C_ISR_NACKF 392 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 393 #define SMBUS_FLAG_TC I2C_ISR_TC 394 #define SMBUS_FLAG_TCR I2C_ISR_TCR 395 #define SMBUS_FLAG_BERR I2C_ISR_BERR 396 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 397 #define SMBUS_FLAG_OVR I2C_ISR_OVR 398 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 399 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 400 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 401 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 402 #define SMBUS_FLAG_DIR I2C_ISR_DIR 403 /** 404 * @} 405 */ 406 407 /** 408 * @} 409 */ 410 411 /* Exported macros ------------------------------------------------------------*/ 412 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 413 * @{ 414 */ 415 416 /** @brief Reset SMBUS handle state. 417 * @param __HANDLE__ specifies the SMBUS Handle. 418 * @retval None 419 */ 420 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 421 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 422 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 423 (__HANDLE__)->MspInitCallback = NULL; \ 424 (__HANDLE__)->MspDeInitCallback = NULL; \ 425 } while(0) 426 #else 427 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 428 #endif 429 430 /** @brief Enable the specified SMBUS interrupts. 431 * @param __HANDLE__ specifies the SMBUS Handle. 432 * @param __INTERRUPT__ specifies the interrupt source to enable. 433 * This parameter can be one of the following values: 434 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 435 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 436 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 437 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 438 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 439 * @arg @ref SMBUS_IT_RXI RX interrupt enable 440 * @arg @ref SMBUS_IT_TXI TX interrupt enable 441 * 442 * @retval None 443 */ 444 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 445 446 /** @brief Disable the specified SMBUS interrupts. 447 * @param __HANDLE__ specifies the SMBUS Handle. 448 * @param __INTERRUPT__ specifies the interrupt source to disable. 449 * This parameter can be one of the following values: 450 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 451 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 452 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 453 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 454 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 455 * @arg @ref SMBUS_IT_RXI RX interrupt enable 456 * @arg @ref SMBUS_IT_TXI TX interrupt enable 457 * 458 * @retval None 459 */ 460 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 461 462 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 463 * @param __HANDLE__ specifies the SMBUS Handle. 464 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 465 * This parameter can be one of the following values: 466 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 467 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 468 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 469 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 470 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 471 * @arg @ref SMBUS_IT_RXI RX interrupt enable 472 * @arg @ref SMBUS_IT_TXI TX interrupt enable 473 * 474 * @retval The new state of __IT__ (SET or RESET). 475 */ 476 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 477 478 /** @brief Check whether the specified SMBUS flag is set or not. 479 * @param __HANDLE__ specifies the SMBUS Handle. 480 * @param __FLAG__ specifies the flag to check. 481 * This parameter can be one of the following values: 482 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 483 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 484 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 485 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 486 * @arg @ref SMBUS_FLAG_AF NACK received flag 487 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 488 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 489 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 490 * @arg @ref SMBUS_FLAG_BERR Bus error 491 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 492 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 493 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 494 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 495 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 496 * @arg @ref SMBUS_FLAG_BUSY Bus busy 497 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 498 * 499 * @retval The new state of __FLAG__ (SET or RESET). 500 */ 501 #define SMBUS_FLAG_MASK (0x0001FFFFU) 502 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 503 504 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 505 * @param __HANDLE__ specifies the SMBUS Handle. 506 * @param __FLAG__ specifies the flag to clear. 507 * This parameter can be any combination of the following values: 508 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 509 * @arg @ref SMBUS_FLAG_AF NACK received flag 510 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 511 * @arg @ref SMBUS_FLAG_BERR Bus error 512 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 513 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 514 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 515 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 516 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 517 * 518 * @retval None 519 */ 520 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 521 522 /** @brief Enable the specified SMBUS peripheral. 523 * @param __HANDLE__ specifies the SMBUS Handle. 524 * @retval None 525 */ 526 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 527 528 /** @brief Disable the specified SMBUS peripheral. 529 * @param __HANDLE__ specifies the SMBUS Handle. 530 * @retval None 531 */ 532 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 533 534 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 535 * @param __HANDLE__ specifies the SMBUS Handle. 536 * @retval None 537 */ 538 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 539 540 /** 541 * @} 542 */ 543 544 545 /* Private constants ---------------------------------------------------------*/ 546 547 /* Private macros ------------------------------------------------------------*/ 548 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 549 * @{ 550 */ 551 552 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 553 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 554 555 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 556 557 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 558 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 559 560 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 561 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 562 563 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 564 ((MASK) == SMBUS_OA2_MASK01) || \ 565 ((MASK) == SMBUS_OA2_MASK02) || \ 566 ((MASK) == SMBUS_OA2_MASK03) || \ 567 ((MASK) == SMBUS_OA2_MASK04) || \ 568 ((MASK) == SMBUS_OA2_MASK05) || \ 569 ((MASK) == SMBUS_OA2_MASK06) || \ 570 ((MASK) == SMBUS_OA2_MASK07)) 571 572 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 573 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 574 575 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 576 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 577 578 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 579 ((PEC) == SMBUS_PEC_ENABLE)) 580 581 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 582 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 583 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 584 585 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 586 ((MODE) == SMBUS_AUTOEND_MODE) || \ 587 ((MODE) == SMBUS_SOFTEND_MODE) || \ 588 ((MODE) == SMBUS_SENDPEC_MODE) || \ 589 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 590 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 591 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 592 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) 593 594 595 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 596 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 597 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 598 ((REQUEST) == SMBUS_NO_STARTSTOP)) 599 600 601 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 602 ((REQUEST) == SMBUS_FIRST_FRAME) || \ 603 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 604 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 605 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 606 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 607 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 608 609 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 610 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 611 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 612 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 613 614 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) 615 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 616 617 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ 618 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 619 620 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 621 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 622 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 623 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 624 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 625 626 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 627 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 628 629 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 630 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 631 632 /** 633 * @} 634 */ 635 636 /* Exported functions --------------------------------------------------------*/ 637 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 638 * @{ 639 */ 640 641 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 642 * @{ 643 */ 644 645 /* Initialization and de-initialization functions ****************************/ 646 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 647 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 648 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 649 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 650 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 651 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 652 653 /* Callbacks Register/UnRegister functions ***********************************/ 654 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 655 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); 656 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); 657 658 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); 659 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 660 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 661 /** 662 * @} 663 */ 664 665 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 666 * @{ 667 */ 668 669 /* IO operation functions *****************************************************/ 670 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 671 * @{ 672 */ 673 /******* Blocking mode: Polling */ 674 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 675 /** 676 * @} 677 */ 678 679 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 680 * @{ 681 */ 682 /******* Non-Blocking mode: Interrupt */ 683 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 684 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 685 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 686 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 687 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 688 689 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 690 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 691 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 692 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 693 /** 694 * @} 695 */ 696 697 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 698 * @{ 699 */ 700 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 701 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 702 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 703 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 704 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 705 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 706 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 707 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 708 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 709 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 710 711 /** 712 * @} 713 */ 714 715 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 716 * @{ 717 */ 718 719 /* Peripheral State and Errors functions **************************************************/ 720 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 721 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 722 723 /** 724 * @} 725 */ 726 727 /** 728 * @} 729 */ 730 731 /* Private Functions ---------------------------------------------------------*/ 732 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 733 * @{ 734 */ 735 /* Private functions are defined in stm32l4xx_hal_smbus.c file */ 736 /** 737 * @} 738 */ 739 740 /** 741 * @} 742 */ 743 744 /** 745 * @} 746 */ 747 748 /** 749 * @} 750 */ 751 752 #ifdef __cplusplus 753 } 754 #endif 755 756 757 #endif /* STM32L4xx_HAL_SMBUS_H */ 758 759 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 760
