1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_sai.h 4 * @author MCD Application Team 5 * @brief Header file of SAI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_SAI_H 21 #define STM32L4xx_HAL_SAI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if !defined(STM32L412xx) && !defined(STM32L422xx) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l4xx_hal_def.h" 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup SAI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup SAI_Exported_Types SAI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL State structures definition 47 */ 48 typedef enum 49 { 50 HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ 51 HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ 52 HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ 53 HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ 54 HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ 55 } HAL_SAI_StateTypeDef; 56 57 /** 58 * @brief SAI Callback prototype 59 */ 60 typedef void (*SAIcallback)(void); 61 62 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 63 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 64 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition 65 * @brief SAI PDM Init structure definition 66 * @{ 67 */ 68 typedef struct 69 { 70 FunctionalState Activation; /*!< Enable/disable PDM interface */ 71 uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. 72 This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ 73 uint32_t ClockEnable; /*!< Specifies which clock must be enabled. 74 This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ 75 } SAI_PdmInitTypeDef; 76 /** 77 * @} 78 */ 79 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 80 /* STM32L4P5xx || STM32L4Q5xx */ 81 82 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition 83 * @brief SAI Init Structure definition 84 * @{ 85 */ 86 typedef struct 87 { 88 uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. 89 This parameter can be a value of @ref SAI_Block_Mode */ 90 91 uint32_t Synchro; /*!< Specifies SAI Block synchronization 92 This parameter can be a value of @ref SAI_Block_Synchronization */ 93 94 uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common 95 for BlockA and BlockB 96 This parameter can be a value of @ref SAI_Block_SyncExt 97 @note If both audio blocks of same SAI are used, this parameter has 98 to be set to the same value for each audio block */ 99 100 uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. 101 This parameter can be a value of @ref SAI_Block_Output_Drive 102 @note This value has to be set before enabling the audio block 103 but after the audio block configuration. */ 104 105 uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. 106 This parameter can be a value of @ref SAI_Block_NoDivider 107 @note For STM32L4Rx/STM32L4Sx devices : 108 If bit NOMCK in the SAI_xCR1 register is cleared, the frame length 109 should be aligned to a number equal to a power of 2, from 8 to 256. 110 If bit NOMCK in the SAI_xCR1 register is set, the frame length can 111 take any of the values without constraint. There is no MCLK_x clock 112 which can be output. 113 For other devices : 114 If bit NODIV in the SAI_xCR1 register is cleared, the frame length 115 should be aligned to a number equal to a power of 2, from 8 to 256. 116 If bit NODIV in the SAI_xCR1 register is set, the frame length can 117 take any of the values without constraint since the input clock of 118 the audio block should be equal to the bit clock. 119 There is no MCLK_x clock which can be output. */ 120 121 uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. 122 This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ 123 124 uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. 125 This parameter can be a value of @ref SAI_Audio_Frequency */ 126 127 uint32_t Mckdiv; /*!< Specifies the master clock divider. 128 This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. 129 This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. 130 @note This parameter is used only if AudioFrequency is set to 131 SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ 132 133 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 134 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 135 uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. 136 This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ 137 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 138 /* STM32L4P5xx || STM32L4Q5xx */ 139 140 uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. 141 This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ 142 143 uint32_t CompandingMode; /*!< Specifies the companding mode type. 144 This parameter can be a value of @ref SAI_Block_Companding_Mode */ 145 146 uint32_t TriState; /*!< Specifies the companding mode type. 147 This parameter can be a value of @ref SAI_TRIState_Management */ 148 149 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 150 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 151 SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ 152 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 153 /* STM32L4P5xx || STM32L4Q5xx */ 154 155 /* This part of the structure is automatically filled if your are using the high level initialisation 156 function HAL_SAI_InitProtocol */ 157 158 uint32_t Protocol; /*!< Specifies the SAI Block protocol. 159 This parameter can be a value of @ref SAI_Block_Protocol */ 160 161 uint32_t DataSize; /*!< Specifies the SAI Block data size. 162 This parameter can be a value of @ref SAI_Block_Data_Size */ 163 164 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 165 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ 166 167 uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. 168 This parameter can be a value of @ref SAI_Block_Clock_Strobing */ 169 } SAI_InitTypeDef; 170 /** 171 * @} 172 */ 173 174 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition 175 * @brief SAI Frame Init structure definition 176 * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). 177 * @{ 178 */ 179 typedef struct 180 { 181 182 uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. 183 This parameter must be a number between Min_Data = 8 and Max_Data = 256. 184 @note If master clock MCLK_x pin is declared as an output, the frame length 185 should be aligned to a number equal to power of 2 in order to keep 186 in an audio frame, an integer number of MCLK pulses by bit Clock. */ 187 188 uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. 189 This Parameter specifies the length in number of bit clock (SCK + 1) 190 of the active level of FS signal in audio frame. 191 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 192 193 uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. 194 This parameter can be a value of @ref SAI_Block_FS_Definition */ 195 196 uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. 197 This parameter can be a value of @ref SAI_Block_FS_Polarity */ 198 199 uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. 200 This parameter can be a value of @ref SAI_Block_FS_Offset */ 201 202 } SAI_FrameInitTypeDef; 203 /** 204 * @} 205 */ 206 207 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition 208 * @brief SAI Block Slot Init Structure definition 209 * @note For SPDIF protocol, these parameters are not used (set by hardware). 210 * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). 211 * @{ 212 */ 213 typedef struct 214 { 215 uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. 216 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ 217 218 uint32_t SlotSize; /*!< Specifies the Slot Size. 219 This parameter can be a value of @ref SAI_Block_Slot_Size */ 220 221 uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. 222 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 223 224 uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. 225 This parameter can be a value of @ref SAI_Block_Slot_Active */ 226 } SAI_SlotInitTypeDef; 227 /** 228 * @} 229 */ 230 231 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition 232 * @brief SAI handle Structure definition 233 * @{ 234 */ 235 typedef struct __SAI_HandleTypeDef 236 { 237 SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ 238 239 SAI_InitTypeDef Init; /*!< SAI communication parameters */ 240 241 SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ 242 243 SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ 244 245 uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ 246 247 uint16_t XferSize; /*!< SAI transfer size */ 248 249 uint16_t XferCount; /*!< SAI transfer counter */ 250 251 DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ 252 253 DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ 254 255 SAIcallback mutecallback; /*!< SAI mute callback */ 256 257 void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ 258 259 HAL_LockTypeDef Lock; /*!< SAI locking object */ 260 261 __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ 262 263 __IO uint32_t ErrorCode; /*!< SAI Error code */ 264 265 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 266 void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ 267 void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ 268 void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ 269 void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ 270 void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ 271 void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ 272 void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ 273 #endif 274 } SAI_HandleTypeDef; 275 /** 276 * @} 277 */ 278 279 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 280 /** 281 * @brief SAI callback ID enumeration definition 282 */ 283 typedef enum 284 { 285 HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ 286 HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ 287 HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ 288 HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ 289 HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ 290 HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ 291 HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ 292 } HAL_SAI_CallbackIDTypeDef; 293 294 /** 295 * @brief SAI callback pointer definition 296 */ 297 typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); 298 #endif 299 300 /** 301 * @} 302 */ 303 304 /* Exported constants --------------------------------------------------------*/ 305 /** @defgroup SAI_Exported_Constants SAI Exported Constants 306 * @{ 307 */ 308 309 /** @defgroup SAI_Error_Code SAI Error Code 310 * @{ 311 */ 312 #define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ 313 #define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ 314 #define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ 315 #define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ 316 #define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ 317 #define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ 318 #define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ 319 #define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ 320 #define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ 321 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 322 #define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ 323 #endif 324 /** 325 * @} 326 */ 327 328 /** @defgroup SAI_Block_SyncExt SAI External synchronisation 329 * @{ 330 */ 331 #define SAI_SYNCEXT_DISABLE 0U 332 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U 333 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U 334 /** 335 * @} 336 */ 337 338 /** @defgroup SAI_Protocol SAI Supported protocol 339 * @{ 340 */ 341 #define SAI_I2S_STANDARD 0U 342 #define SAI_I2S_MSBJUSTIFIED 1U 343 #define SAI_I2S_LSBJUSTIFIED 2U 344 #define SAI_PCM_LONG 3U 345 #define SAI_PCM_SHORT 4U 346 /** 347 * @} 348 */ 349 350 /** @defgroup SAI_Protocol_DataSize SAI protocol data size 351 * @{ 352 */ 353 #define SAI_PROTOCOL_DATASIZE_16BIT 0U 354 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U 355 #define SAI_PROTOCOL_DATASIZE_24BIT 2U 356 #define SAI_PROTOCOL_DATASIZE_32BIT 3U 357 /** 358 * @} 359 */ 360 361 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency 362 * @{ 363 */ 364 #define SAI_AUDIO_FREQUENCY_192K 192000U 365 #define SAI_AUDIO_FREQUENCY_96K 96000U 366 #define SAI_AUDIO_FREQUENCY_48K 48000U 367 #define SAI_AUDIO_FREQUENCY_44K 44100U 368 #define SAI_AUDIO_FREQUENCY_32K 32000U 369 #define SAI_AUDIO_FREQUENCY_22K 22050U 370 #define SAI_AUDIO_FREQUENCY_16K 16000U 371 #define SAI_AUDIO_FREQUENCY_11K 11025U 372 #define SAI_AUDIO_FREQUENCY_8K 8000U 373 #define SAI_AUDIO_FREQUENCY_MCKDIV 0U 374 /** 375 * @} 376 */ 377 378 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 379 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 380 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling 381 * @{ 382 */ 383 #define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U 384 #define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR 385 /** 386 * @} 387 */ 388 389 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable 390 * @{ 391 */ 392 #define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 393 #define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 394 /** 395 * @} 396 */ 397 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 398 /* STM32L4P5xx || STM32L4Q5xx */ 399 400 /** @defgroup SAI_Block_Mode SAI Block Mode 401 * @{ 402 */ 403 #define SAI_MODEMASTER_TX 0x00000000U 404 #define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 405 #define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 406 #define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) 407 408 /** 409 * @} 410 */ 411 412 /** @defgroup SAI_Block_Protocol SAI Block Protocol 413 * @{ 414 */ 415 #define SAI_FREE_PROTOCOL 0x00000000U 416 #define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 417 #define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 418 /** 419 * @} 420 */ 421 422 /** @defgroup SAI_Block_Data_Size SAI Block Data Size 423 * @{ 424 */ 425 #define SAI_DATASIZE_8 SAI_xCR1_DS_1 426 #define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) 427 #define SAI_DATASIZE_16 SAI_xCR1_DS_2 428 #define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) 429 #define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) 430 #define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) 431 /** 432 * @} 433 */ 434 435 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission 436 * @{ 437 */ 438 #define SAI_FIRSTBIT_MSB 0x00000000U 439 #define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST 440 /** 441 * @} 442 */ 443 444 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing 445 * @{ 446 */ 447 #define SAI_CLOCKSTROBING_FALLINGEDGE 0U 448 #define SAI_CLOCKSTROBING_RISINGEDGE 1U 449 /** 450 * @} 451 */ 452 453 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization 454 * @{ 455 */ 456 #define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ 457 #define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ 458 #define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ 459 #define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ 460 /** 461 * @} 462 */ 463 464 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive 465 * @{ 466 */ 467 #define SAI_OUTPUTDRIVE_DISABLE 0x00000000U 468 #define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV 469 /** 470 * @} 471 */ 472 473 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider 474 * @{ 475 */ 476 #define SAI_MASTERDIVIDER_ENABLE 0x00000000U 477 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 478 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 479 #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK 480 #else 481 #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV 482 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 483 /* STM32L4P5xx || STM32L4Q5xx */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition 489 * @{ 490 */ 491 #define SAI_FS_STARTFRAME 0x00000000U 492 #define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF 493 /** 494 * @} 495 */ 496 497 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity 498 * @{ 499 */ 500 #define SAI_FS_ACTIVE_LOW 0x00000000U 501 #define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL 502 /** 503 * @} 504 */ 505 506 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset 507 * @{ 508 */ 509 #define SAI_FS_FIRSTBIT 0x00000000U 510 #define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF 511 /** 512 * @} 513 */ 514 515 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size 516 * @{ 517 */ 518 #define SAI_SLOTSIZE_DATASIZE 0x00000000U 519 #define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 520 #define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 521 /** 522 * @} 523 */ 524 525 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active 526 * @{ 527 */ 528 #define SAI_SLOT_NOTACTIVE 0x00000000U 529 #define SAI_SLOTACTIVE_0 0x00000001U 530 #define SAI_SLOTACTIVE_1 0x00000002U 531 #define SAI_SLOTACTIVE_2 0x00000004U 532 #define SAI_SLOTACTIVE_3 0x00000008U 533 #define SAI_SLOTACTIVE_4 0x00000010U 534 #define SAI_SLOTACTIVE_5 0x00000020U 535 #define SAI_SLOTACTIVE_6 0x00000040U 536 #define SAI_SLOTACTIVE_7 0x00000080U 537 #define SAI_SLOTACTIVE_8 0x00000100U 538 #define SAI_SLOTACTIVE_9 0x00000200U 539 #define SAI_SLOTACTIVE_10 0x00000400U 540 #define SAI_SLOTACTIVE_11 0x00000800U 541 #define SAI_SLOTACTIVE_12 0x00001000U 542 #define SAI_SLOTACTIVE_13 0x00002000U 543 #define SAI_SLOTACTIVE_14 0x00004000U 544 #define SAI_SLOTACTIVE_15 0x00008000U 545 #define SAI_SLOTACTIVE_ALL 0x0000FFFFU 546 /** 547 * @} 548 */ 549 550 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode 551 * @{ 552 */ 553 #define SAI_STEREOMODE 0x00000000U 554 #define SAI_MONOMODE SAI_xCR1_MONO 555 /** 556 * @} 557 */ 558 559 /** @defgroup SAI_TRIState_Management SAI TRIState Management 560 * @{ 561 */ 562 #define SAI_OUTPUT_NOTRELEASED 0x00000000U 563 #define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS 564 /** 565 * @} 566 */ 567 568 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold 569 * @{ 570 */ 571 #define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U 572 #define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 573 #define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 574 #define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) 575 #define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 576 /** 577 * @} 578 */ 579 580 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode 581 * @{ 582 */ 583 #define SAI_NOCOMPANDING 0x00000000U 584 #define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 585 #define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) 586 #define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) 587 #define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) 588 /** 589 * @} 590 */ 591 592 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value 593 * @{ 594 */ 595 #define SAI_ZERO_VALUE 0x00000000U 596 #define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL 597 /** 598 * @} 599 */ 600 601 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition 602 * @{ 603 */ 604 #define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE 605 #define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE 606 #define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE 607 #define SAI_IT_FREQ SAI_xIMR_FREQIE 608 #define SAI_IT_CNRDY SAI_xIMR_CNRDYIE 609 #define SAI_IT_AFSDET SAI_xIMR_AFSDETIE 610 #define SAI_IT_LFSDET SAI_xIMR_LFSDETIE 611 /** 612 * @} 613 */ 614 615 /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition 616 * @{ 617 */ 618 #define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR 619 #define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET 620 #define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG 621 #define SAI_FLAG_FREQ SAI_xSR_FREQ 622 #define SAI_FLAG_CNRDY SAI_xSR_CNRDY 623 #define SAI_FLAG_AFSDET SAI_xSR_AFSDET 624 #define SAI_FLAG_LFSDET SAI_xSR_LFSDET 625 /** 626 * @} 627 */ 628 629 /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level 630 * @{ 631 */ 632 #define SAI_FIFOSTATUS_EMPTY 0x00000000U 633 #define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U 634 #define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U 635 #define SAI_FIFOSTATUS_HALFFULL 0x00030000U 636 #define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U 637 #define SAI_FIFOSTATUS_FULL 0x00050000U 638 /** 639 * @} 640 */ 641 642 /** 643 * @} 644 */ 645 646 /* Exported macro ------------------------------------------------------------*/ 647 /** @defgroup SAI_Exported_Macros SAI Exported Macros 648 * @brief macros to handle interrupts and specific configurations 649 * @{ 650 */ 651 652 /** @brief Reset SAI handle state. 653 * @param __HANDLE__ specifies the SAI Handle. 654 * @retval None 655 */ 656 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 657 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 658 (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ 659 (__HANDLE__)->MspInitCallback = NULL; \ 660 (__HANDLE__)->MspDeInitCallback = NULL; \ 661 } while(0) 662 #else 663 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) 664 #endif 665 666 /** @brief Enable the specified SAI interrupts. 667 * @param __HANDLE__ specifies the SAI Handle. 668 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 669 * This parameter can be one of the following values: 670 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 671 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 672 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 673 * @arg SAI_IT_FREQ: FIFO request interrupt enable 674 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 675 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 676 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 677 * @retval None 678 */ 679 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) 680 681 /** @brief Disable the specified SAI interrupts. 682 * @param __HANDLE__ specifies the SAI Handle. 683 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 684 * This parameter can be one of the following values: 685 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 686 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 687 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 688 * @arg SAI_IT_FREQ: FIFO request interrupt enable 689 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 690 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 691 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 692 * @retval None 693 */ 694 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) 695 696 /** @brief Check whether the specified SAI interrupt source is enabled or not. 697 * @param __HANDLE__ specifies the SAI Handle. 698 * @param __INTERRUPT__ specifies the SAI interrupt source to check. 699 * This parameter can be one of the following values: 700 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 701 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 702 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 703 * @arg SAI_IT_FREQ: FIFO request interrupt enable 704 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 705 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 706 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 707 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 708 */ 709 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 710 711 /** @brief Check whether the specified SAI flag is set or not. 712 * @param __HANDLE__ specifies the SAI Handle. 713 * @param __FLAG__ specifies the flag to check. 714 * This parameter can be one of the following values: 715 * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. 716 * @arg SAI_FLAG_MUTEDET: Mute detection flag. 717 * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. 718 * @arg SAI_FLAG_FREQ: FIFO request flag. 719 * @arg SAI_FLAG_CNRDY: Codec not ready flag. 720 * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. 721 * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. 722 * @retval The new state of __FLAG__ (TRUE or FALSE). 723 */ 724 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 725 726 /** @brief Clear the specified SAI pending flag. 727 * @param __HANDLE__ specifies the SAI Handle. 728 * @param __FLAG__ specifies the flag to check. 729 * This parameter can be any combination of the following values: 730 * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun 731 * @arg SAI_FLAG_MUTEDET: Clear Mute detection 732 * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration 733 * @arg SAI_FLAG_FREQ: Clear FIFO request 734 * @arg SAI_FLAG_CNRDY: Clear Codec not ready 735 * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection 736 * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection 737 * 738 * @retval None 739 */ 740 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) 741 742 /** @brief Enable SAI. 743 * @param __HANDLE__ specifies the SAI Handle. 744 * @retval None 745 */ 746 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) 747 748 /** @brief Disable SAI. 749 * @param __HANDLE__ specifies the SAI Handle. 750 * @retval None 751 */ 752 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) 753 754 /** 755 * @} 756 */ 757 758 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 759 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 760 /* Include SAI HAL Extension module */ 761 #include "stm32l4xx_hal_sai_ex.h" 762 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 763 /* STM32L4P5xx || STM32L4Q5xx */ 764 765 /* Exported functions --------------------------------------------------------*/ 766 /** @addtogroup SAI_Exported_Functions 767 * @{ 768 */ 769 770 /* Initialization/de-initialization functions ********************************/ 771 /** @addtogroup SAI_Exported_Functions_Group1 772 * @{ 773 */ 774 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); 775 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); 776 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); 777 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); 778 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); 779 780 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 781 /* SAI callbacks register/unregister functions ********************************/ 782 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, 783 HAL_SAI_CallbackIDTypeDef CallbackID, 784 pSAI_CallbackTypeDef pCallback); 785 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, 786 HAL_SAI_CallbackIDTypeDef CallbackID); 787 #endif 788 /** 789 * @} 790 */ 791 792 /* I/O operation functions ***************************************************/ 793 /** @addtogroup SAI_Exported_Functions_Group2 794 * @{ 795 */ 796 /* Blocking mode: Polling */ 797 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); 798 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); 799 800 /* Non-Blocking mode: Interrupt */ 801 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 802 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 803 804 /* Non-Blocking mode: DMA */ 805 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 806 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 807 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); 808 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); 809 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); 810 811 /* Abort function */ 812 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); 813 814 /* Mute management */ 815 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); 816 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); 817 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); 818 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); 819 820 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ 821 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); 822 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); 823 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); 824 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); 825 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); 826 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); 827 /** 828 * @} 829 */ 830 831 /** @addtogroup SAI_Exported_Functions_Group3 832 * @{ 833 */ 834 /* Peripheral State functions ************************************************/ 835 HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); 836 uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); 837 /** 838 * @} 839 */ 840 841 /** 842 * @} 843 */ 844 845 /* Private macros ------------------------------------------------------------*/ 846 /** @defgroup SAI_Private_Macros SAI Private Macros 847 * @{ 848 */ 849 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ 850 ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ 851 ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) 852 853 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ 854 ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ 855 ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ 856 ((PROTOCOL) == SAI_PCM_LONG) ||\ 857 ((PROTOCOL) == SAI_PCM_SHORT)) 858 859 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ 860 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ 861 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ 862 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) 863 864 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ 865 ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ 866 ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ 867 ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ 868 ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) 869 870 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 871 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 872 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ 873 ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) 874 875 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) 876 877 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ 878 (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) 879 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 880 /* STM32L4P5xx || STM32L4Q5xx */ 881 882 #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ 883 ((MODE) == SAI_MODEMASTER_RX) || \ 884 ((MODE) == SAI_MODESLAVE_TX) || \ 885 ((MODE) == SAI_MODESLAVE_RX)) 886 887 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ 888 ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ 889 ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) 890 891 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ 892 ((DATASIZE) == SAI_DATASIZE_10) || \ 893 ((DATASIZE) == SAI_DATASIZE_16) || \ 894 ((DATASIZE) == SAI_DATASIZE_20) || \ 895 ((DATASIZE) == SAI_DATASIZE_24) || \ 896 ((DATASIZE) == SAI_DATASIZE_32)) 897 898 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ 899 ((BIT) == SAI_FIRSTBIT_LSB)) 900 901 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ 902 ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) 903 904 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ 905 ((SYNCHRO) == SAI_SYNCHRONOUS) || \ 906 ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ 907 ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) 908 909 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ 910 ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) 911 912 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ 913 ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) 914 915 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) 916 917 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ 918 ((VALUE) == SAI_LAST_SENT_VALUE)) 919 920 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ 921 ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ 922 ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ 923 ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ 924 ((MODE) == SAI_ALAW_2CPL_COMPANDING)) 925 926 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ 927 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ 928 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ 929 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ 930 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) 931 932 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ 933 ((STATE) == SAI_OUTPUT_RELEASED)) 934 935 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ 936 ((MODE) == SAI_STEREOMODE)) 937 938 #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) 939 940 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) 941 942 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ 943 ((SIZE) == SAI_SLOTSIZE_16B) || \ 944 ((SIZE) == SAI_SLOTSIZE_32B)) 945 946 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) 947 948 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ 949 ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) 950 951 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ 952 ((POLARITY) == SAI_FS_ACTIVE_HIGH)) 953 954 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ 955 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) 956 957 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 958 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 959 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) 960 #else 961 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) 962 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 963 /* STM32L4P5xx || STM32L4Q5xx */ 964 965 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) 966 967 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) 968 969 /** 970 * @} 971 */ 972 973 /* Private functions ---------------------------------------------------------*/ 974 /** @defgroup SAI_Private_Functions SAI Private Functions 975 * @{ 976 */ 977 978 /** 979 * @} 980 */ 981 982 /** 983 * @} 984 */ 985 986 /** 987 * @} 988 */ 989 990 #endif /* !STM32L412xx && !STM32L422xx */ 991 992 #ifdef __cplusplus 993 } 994 #endif 995 996 #endif /* STM32L4xx_HAL_SAI_H */ 997 998
