1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_QSPI_H 21 #define STM32L4xx_HAL_QSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 #if defined(QUADSPI) 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup QSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup QSPI_Exported_Types QSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief QSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 51 This parameter can be a number between 0 and 255 */ 52 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 53 This parameter can be a value between 1 and 16 */ 54 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 55 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 56 This parameter can be a value of @ref QSPI_SampleShifting */ 57 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 58 required to address the flash memory. The flash capacity can be up to 4GB 59 (addressed using 32 bits) in indirect mode, but the addressable space in 60 memory-mapped mode is limited to 256MB 61 This parameter can be a number between 0 and 31 */ 62 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 63 of clock cycles which the chip select must remain high between commands. 64 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 65 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 66 This parameter can be a value of @ref QSPI_ClockMode */ 67 #if defined(QUADSPI_CR_DFM) 68 uint32_t FlashID; /* Specifies the Flash which will be used, 69 This parameter can be a value of @ref QSPI_Flash_Select */ 70 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 71 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 72 #endif 73 }QSPI_InitTypeDef; 74 75 /** 76 * @brief HAL QSPI State structures definition 77 */ 78 typedef enum 79 { 80 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 81 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 82 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 83 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 84 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 85 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 86 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 87 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 88 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 89 }HAL_QSPI_StateTypeDef; 90 91 /** 92 * @brief QSPI Handle Structure definition 93 */ 94 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 95 typedef struct __QSPI_HandleTypeDef 96 #else 97 typedef struct 98 #endif 99 { 100 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 101 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 102 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 103 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 104 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 105 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 106 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 107 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 108 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 109 __IO HAL_LockTypeDef Lock; /* Locking object */ 110 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 111 __IO uint32_t ErrorCode; /* QSPI Error code */ 112 uint32_t Timeout; /* Timeout for the QSPI memory access */ 113 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 114 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 115 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 116 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 117 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 118 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 124 125 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 126 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 127 #endif 128 }QSPI_HandleTypeDef; 129 130 /** 131 * @brief QSPI Command structure definition 132 */ 133 typedef struct 134 { 135 uint32_t Instruction; /* Specifies the Instruction to be sent 136 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 137 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 139 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 140 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 141 uint32_t AddressSize; /* Specifies the Address Size 142 This parameter can be a value of @ref QSPI_AddressSize */ 143 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 144 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 145 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 146 This parameter can be a number between 0 and 31 */ 147 uint32_t InstructionMode; /* Specifies the Instruction Mode 148 This parameter can be a value of @ref QSPI_InstructionMode */ 149 uint32_t AddressMode; /* Specifies the Address Mode 150 This parameter can be a value of @ref QSPI_AddressMode */ 151 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 152 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 153 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 154 This parameter can be a value of @ref QSPI_DataMode */ 155 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 156 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 157 until end of memory)*/ 158 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 159 This parameter can be a value of @ref QSPI_DdrMode */ 160 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 161 output by one half of system clock in DDR mode. 162 Not available on all devices. 163 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 164 uint32_t SIOOMode; /* Specifies the send instruction only once mode 165 This parameter can be a value of @ref QSPI_SIOOMode */ 166 }QSPI_CommandTypeDef; 167 168 /** 169 * @brief QSPI Auto Polling mode configuration structure definition 170 */ 171 typedef struct 172 { 173 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 174 This parameter can be any value between 0 and 0xFFFFFFFF */ 175 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 176 This parameter can be any value between 0 and 0xFFFFFFFF */ 177 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 178 This parameter can be any value between 0 and 0xFFFF */ 179 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 180 This parameter can be any value between 1 and 4 */ 181 uint32_t MatchMode; /* Specifies the method used for determining a match. 182 This parameter can be a value of @ref QSPI_MatchMode */ 183 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 184 This parameter can be a value of @ref QSPI_AutomaticStop */ 185 }QSPI_AutoPollingTypeDef; 186 187 /** 188 * @brief QSPI Memory Mapped mode configuration structure definition 189 */ 190 typedef struct 191 { 192 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 193 This parameter can be any value between 0 and 0xFFFF */ 194 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 195 This parameter can be a value of @ref QSPI_TimeOutActivation */ 196 }QSPI_MemoryMappedTypeDef; 197 198 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 199 /** 200 * @brief HAL QSPI Callback ID enumeration definition 201 */ 202 typedef enum 203 { 204 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 205 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 206 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 207 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 208 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 209 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 210 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 211 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 212 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 213 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 214 215 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 216 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 217 }HAL_QSPI_CallbackIDTypeDef; 218 219 /** 220 * @brief HAL QSPI Callback pointer definition 221 */ 222 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 223 #endif 224 /** 225 * @} 226 */ 227 228 /* Exported constants --------------------------------------------------------*/ 229 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 230 * @{ 231 */ 232 233 /** @defgroup QSPI_ErrorCode QSPI Error Code 234 * @{ 235 */ 236 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 237 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 238 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 239 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 240 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 241 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 242 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 243 #endif 244 /** 245 * @} 246 */ 247 248 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 249 * @{ 250 */ 251 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 252 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 253 /** 254 * @} 255 */ 256 257 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 258 * @{ 259 */ 260 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 261 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 262 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 263 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 264 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 265 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 266 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 267 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 268 /** 269 * @} 270 */ 271 272 /** @defgroup QSPI_ClockMode QSPI Clock Mode 273 * @{ 274 */ 275 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 276 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 277 /** 278 * @} 279 */ 280 281 #if defined(QUADSPI_CR_DFM) 282 /** @defgroup QSPI_Flash_Select QSPI Flash Select 283 * @{ 284 */ 285 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 286 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 287 /** 288 * @} 289 */ 290 291 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 292 * @{ 293 */ 294 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 295 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 296 /** 297 * @} 298 */ 299 300 #endif 301 /** @defgroup QSPI_AddressSize QSPI Address Size 302 * @{ 303 */ 304 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 305 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 306 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 307 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 308 /** 309 * @} 310 */ 311 312 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 313 * @{ 314 */ 315 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 316 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 317 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 318 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 319 /** 320 * @} 321 */ 322 323 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 324 * @{ 325 */ 326 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 327 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 328 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 329 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 330 /** 331 * @} 332 */ 333 334 /** @defgroup QSPI_AddressMode QSPI Address Mode 335 * @{ 336 */ 337 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 338 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 339 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 340 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 341 /** 342 * @} 343 */ 344 345 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 346 * @{ 347 */ 348 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 349 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 350 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 351 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 352 /** 353 * @} 354 */ 355 356 /** @defgroup QSPI_DataMode QSPI Data Mode 357 * @{ 358 */ 359 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 360 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 361 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 362 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 363 /** 364 * @} 365 */ 366 367 /** @defgroup QSPI_DdrMode QSPI DDR Mode 368 * @{ 369 */ 370 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 371 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 372 /** 373 * @} 374 */ 375 376 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 377 * @{ 378 */ 379 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 380 #if defined(QUADSPI_CCR_DHHC) 381 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 382 #endif 383 /** 384 * @} 385 */ 386 387 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 388 * @{ 389 */ 390 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 391 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 392 /** 393 * @} 394 */ 395 396 /** @defgroup QSPI_MatchMode QSPI Match Mode 397 * @{ 398 */ 399 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 400 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 401 /** 402 * @} 403 */ 404 405 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 406 * @{ 407 */ 408 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 409 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 410 /** 411 * @} 412 */ 413 414 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 415 * @{ 416 */ 417 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 418 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 419 /** 420 * @} 421 */ 422 423 /** @defgroup QSPI_Flags QSPI Flags 424 * @{ 425 */ 426 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 427 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 428 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 429 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 430 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 431 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 432 /** 433 * @} 434 */ 435 436 /** @defgroup QSPI_Interrupts QSPI Interrupts 437 * @{ 438 */ 439 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 440 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 441 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 442 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 443 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 444 /** 445 * @} 446 */ 447 448 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 449 * @brief QSPI Timeout definition 450 * @{ 451 */ 452 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 453 /** 454 * @} 455 */ 456 457 /** 458 * @} 459 */ 460 461 /* Exported macros -----------------------------------------------------------*/ 462 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 463 * @{ 464 */ 465 /** @brief Reset QSPI handle state. 466 * @param __HANDLE__ QSPI handle. 467 * @retval None 468 */ 469 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 470 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 471 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 472 (__HANDLE__)->MspInitCallback = NULL; \ 473 (__HANDLE__)->MspDeInitCallback = NULL; \ 474 } while(0) 475 #else 476 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 477 #endif 478 479 /** @brief Enable the QSPI peripheral. 480 * @param __HANDLE__ specifies the QSPI Handle. 481 * @retval None 482 */ 483 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 484 485 /** @brief Disable the QSPI peripheral. 486 * @param __HANDLE__ specifies the QSPI Handle. 487 * @retval None 488 */ 489 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 490 491 /** @brief Enable the specified QSPI interrupt. 492 * @param __HANDLE__ specifies the QSPI Handle. 493 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 494 * This parameter can be one of the following values: 495 * @arg QSPI_IT_TO: QSPI Timeout interrupt 496 * @arg QSPI_IT_SM: QSPI Status match interrupt 497 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 498 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 499 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 500 * @retval None 501 */ 502 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 503 504 505 /** @brief Disable the specified QSPI interrupt. 506 * @param __HANDLE__ specifies the QSPI Handle. 507 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 508 * This parameter can be one of the following values: 509 * @arg QSPI_IT_TO: QSPI Timeout interrupt 510 * @arg QSPI_IT_SM: QSPI Status match interrupt 511 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 512 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 513 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 514 * @retval None 515 */ 516 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 517 518 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 519 * @param __HANDLE__ specifies the QSPI Handle. 520 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 521 * This parameter can be one of the following values: 522 * @arg QSPI_IT_TO: QSPI Timeout interrupt 523 * @arg QSPI_IT_SM: QSPI Status match interrupt 524 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 525 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 526 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 527 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 528 */ 529 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 530 531 /** 532 * @brief Check whether the selected QSPI flag is set or not. 533 * @param __HANDLE__ specifies the QSPI Handle. 534 * @param __FLAG__ specifies the QSPI flag to check. 535 * This parameter can be one of the following values: 536 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 537 * @arg QSPI_FLAG_TO: QSPI Timeout flag 538 * @arg QSPI_FLAG_SM: QSPI Status match flag 539 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 540 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 541 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 542 * @retval None 543 */ 544 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 545 546 /** @brief Clears the specified QSPI's flag status. 547 * @param __HANDLE__ specifies the QSPI Handle. 548 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 549 * This parameter can be one of the following values: 550 * @arg QSPI_FLAG_TO: QSPI Timeout flag 551 * @arg QSPI_FLAG_SM: QSPI Status match flag 552 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 553 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 554 * @retval None 555 */ 556 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 557 /** 558 * @} 559 */ 560 561 /* Exported functions --------------------------------------------------------*/ 562 /** @addtogroup QSPI_Exported_Functions 563 * @{ 564 */ 565 566 /** @addtogroup QSPI_Exported_Functions_Group1 567 * @{ 568 */ 569 /* Initialization/de-initialization functions ********************************/ 570 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 571 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 572 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 573 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 574 /** 575 * @} 576 */ 577 578 /** @addtogroup QSPI_Exported_Functions_Group2 579 * @{ 580 */ 581 /* IO operation functions *****************************************************/ 582 /* QSPI IRQ handler method */ 583 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 584 585 /* QSPI indirect mode */ 586 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 587 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 588 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 589 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 590 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 591 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 592 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 593 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 594 595 /* QSPI status flag polling mode */ 596 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 597 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 598 599 /* QSPI memory-mapped mode */ 600 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 601 602 /* Callback functions in non-blocking modes ***********************************/ 603 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 604 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 605 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 606 607 /* QSPI indirect mode */ 608 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 609 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 610 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 611 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 612 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 613 614 /* QSPI status flag polling mode */ 615 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 616 617 /* QSPI memory-mapped mode */ 618 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 619 620 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 621 /* QSPI callback registering/unregistering */ 622 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 623 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 624 #endif 625 /** 626 * @} 627 */ 628 629 /** @addtogroup QSPI_Exported_Functions_Group3 630 * @{ 631 */ 632 /* Peripheral Control and State functions ************************************/ 633 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 634 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 635 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 636 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 637 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 638 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 639 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 640 #if defined(QUADSPI_CR_DFM) 641 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 642 #endif 643 /** 644 * @} 645 */ 646 647 /** 648 * @} 649 */ 650 /* End of exported functions -------------------------------------------------*/ 651 652 /* Private macros ------------------------------------------------------------*/ 653 /** @defgroup QSPI_Private_Macros QSPI Private Macros 654 * @{ 655 */ 656 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 657 658 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 659 660 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 661 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 662 663 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 664 665 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 666 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 667 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 668 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 669 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 670 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 671 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 672 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 673 674 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 675 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 676 677 #if defined(QUADSPI_CR_DFM) 678 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 679 ((FLASH_ID) == QSPI_FLASH_ID_2)) 680 681 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 682 ((MODE) == QSPI_DUALFLASH_DISABLE)) 683 684 #endif 685 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 686 687 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 688 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 689 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 690 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 691 692 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 693 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 694 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 695 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 696 697 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 698 699 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 700 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 701 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 702 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 703 704 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 705 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 706 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 707 ((MODE) == QSPI_ADDRESS_4_LINES)) 708 709 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 710 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 711 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 712 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 713 714 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 715 ((MODE) == QSPI_DATA_1_LINE) || \ 716 ((MODE) == QSPI_DATA_2_LINES) || \ 717 ((MODE) == QSPI_DATA_4_LINES)) 718 719 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 720 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 721 722 #if defined(QUADSPI_CCR_DHHC) 723 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 724 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 725 726 #else 727 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 728 729 #endif 730 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 731 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 732 733 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 734 735 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 736 737 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 738 ((MODE) == QSPI_MATCH_MODE_OR)) 739 740 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 741 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 742 743 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 744 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 745 746 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 747 /** 748 * @} 749 */ 750 /* End of private macros -----------------------------------------------------*/ 751 752 /** 753 * @} 754 */ 755 756 /** 757 * @} 758 */ 759 760 #endif /* defined(QUADSPI) */ 761 762 #ifdef __cplusplus 763 } 764 #endif 765 766 #endif /* STM32L4xx_HAL_QSPI_H */ 767
