1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_OSPI_H 21 #define STM32L4xx_HAL_OSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 31 32 /** @addtogroup STM32L4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup OSPI 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup OSPI_Exported_Types OSPI Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief OSPI Init structure definition 47 */ 48 typedef struct 49 { 50 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 51 indicating that data are available in reception or free place 52 is available in transmission. 53 This parameter can be a value between 1 and 32 */ 54 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 55 quad mode on two different devices to increase the throughput. 56 This parameter can be a value of @ref OSPI_DualQuad */ 57 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 58 This parameter can be a value of @ref OSPI_MemoryType */ 59 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 60 it corresponds to the number of address bits required to access 61 the external device. 62 This parameter can be a value between 1 and 32 */ 63 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 64 must remain high between commands. 65 This parameter can be a value between 1 and 8 */ 66 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 67 This parameter can be a value of @ref OSPI_FreeRunningClock */ 68 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 69 This parameter can be a value of @ref OSPI_ClockMode */ 70 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 71 the external clock based on the AHB clock. 72 This parameter can be a value between 1 and 256 */ 73 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 74 to take in account external signal delays. 75 This parameter can be a value of @ref OSPI_SampleShifting */ 76 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 77 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 78 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 79 defines the boundary of bytes to release the chip select. 80 This parameter can be a value between 0 and 31 */ 81 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 82 by the delay block. 83 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 84 #if defined (OCTOSPI_DCR3_MAXTRAN) 85 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 86 released every MaxTran+1 bytes when the other OctoSPI request the access 87 to the bus. 88 This parameter can be a value between 0 and 255 */ 89 #endif 90 #if defined (OCTOSPI_DCR4_REFRESH) 91 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 92 Refresh+1 clock cycles. 93 This parameter can be a value between 0 and 0xFFFFFFFF */ 94 #endif 95 }OSPI_InitTypeDef; 96 97 /** 98 * @brief HAL OSPI Handle Structure definition 99 */ 100 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 101 typedef struct __OSPI_HandleTypeDef 102 #else 103 typedef struct 104 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 105 { 106 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 107 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 108 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 109 __IO uint32_t XferSize; /*!< Number of data to transfer */ 110 __IO uint32_t XferCount; /*!< Counter of data transferred */ 111 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 112 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 113 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 114 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 115 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 116 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 117 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 118 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 119 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 120 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 121 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 122 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 123 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 124 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 125 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 126 127 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 128 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 129 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 130 }OSPI_HandleTypeDef; 131 132 /** 133 * @brief HAL OSPI Regular Command Structure definition 134 */ 135 typedef struct 136 { 137 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 138 to the registers for the write operation (these registers are only 139 used for memory-mapped mode). 140 This parameter can be a value of @ref OSPI_OperationType */ 141 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 142 applies only if Dualquad is disabled in the initialization structure). 143 This parameter can be a value of @ref OSPI_FlashID */ 144 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 145 This parameter can be a value between 0 and 0xFFFFFFFF */ 146 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 147 This parameter can be a value of @ref OSPI_InstructionMode */ 148 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 149 This parameter can be a value of @ref OSPI_InstructionSize */ 150 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 151 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 152 uint32_t Address; /*!< It contains the address to be sent to the device. 153 This parameter can be a value between 0 and 0xFFFFFFFF */ 154 uint32_t AddressMode; /*!< It indicates the mode of the address. 155 This parameter can be a value of @ref OSPI_AddressMode */ 156 uint32_t AddressSize; /*!< It indicates the size of the address. 157 This parameter can be a value of @ref OSPI_AddressSize */ 158 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 159 This parameter can be a value of @ref OSPI_AddressDtrMode */ 160 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 161 This parameter can be a value between 0 and 0xFFFFFFFF */ 162 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 163 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 164 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 165 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 166 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 167 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 168 uint32_t DataMode; /*!< It indicates the mode of the data. 169 This parameter can be a value of @ref OSPI_DataMode */ 170 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 171 This field is only used for indirect mode. 172 This parameter can be a value between 1 and 0xFFFFFFFF */ 173 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 174 This parameter can be a value of @ref OSPI_DataDtrMode */ 175 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 176 This parameter can be a value between 0 and 31 */ 177 uint32_t DQSMode; /*!< It enables or not the data strobe management. 178 This parameter can be a value of @ref OSPI_DQSMode */ 179 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 180 This parameter can be a value of @ref OSPI_SIOOMode */ 181 }OSPI_RegularCmdTypeDef; 182 183 /** 184 * @brief HAL OSPI Hyperbus Configuration Structure definition 185 */ 186 typedef struct 187 { 188 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 189 This parameter can be a value between 0 and 255 */ 190 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 191 This parameter can be a value between 0 and 255 */ 192 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 193 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 194 uint32_t LatencyMode; /*!< It configures the latency mode. 195 This parameter can be a value of @ref OSPI_LatencyMode */ 196 }OSPI_HyperbusCfgTypeDef; 197 198 /** 199 * @brief HAL OSPI Hyperbus Command Structure definition 200 */ 201 typedef struct 202 { 203 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 204 This parameter can be a value of @ref OSPI_AddressSpace */ 205 uint32_t Address; /*!< It contains the address to be sent tot he device. 206 This parameter can be a value between 0 and 0xFFFFFFFF */ 207 uint32_t AddressSize; /*!< It indicates the size of the address. 208 This parameter can be a value of @ref OSPI_AddressSize */ 209 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 210 This field is only used for indirect mode. 211 This parameter can be a value between 1 and 0xFFFFFFFF 212 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 213 uint32_t DQSMode; /*!< It enables or not the data strobe management. 214 This parameter can be a value of @ref OSPI_DQSMode */ 215 }OSPI_HyperbusCmdTypeDef; 216 217 /** 218 * @brief HAL OSPI Auto Polling mode configuration structure definition 219 */ 220 typedef struct 221 { 222 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 223 This parameter can be any value between 0 and 0xFFFFFFFF */ 224 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 225 This parameter can be any value between 0 and 0xFFFFFFFF */ 226 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 227 This parameter can be a value of @ref OSPI_MatchMode */ 228 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 229 This parameter can be a value of @ref OSPI_AutomaticStop */ 230 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 231 This parameter can be any value between 0 and 0xFFFF */ 232 }OSPI_AutoPollingTypeDef; 233 234 /** 235 * @brief HAL OSPI Memory Mapped mode configuration structure definition 236 */ 237 typedef struct 238 { 239 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 240 This parameter can be a value of @ref OSPI_TimeOutActivation */ 241 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 242 This parameter can be any value between 0 and 0xFFFF */ 243 }OSPI_MemoryMappedTypeDef; 244 245 /** 246 * @brief HAL OSPI IO Manager Configuration structure definition 247 */ 248 typedef struct 249 { 250 uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. 251 This parameter can be a value between 1 and 8 */ 252 uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. 253 This parameter can be a value between 0 and 8, 0 means that signal not used */ 254 uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. 255 This parameter can be a value between 1 and 8 */ 256 uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 257 This parameter can be a value of @ref OSPIM_IOPort */ 258 uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 259 This parameter can be a value of @ref OSPIM_IOPort */ 260 #if defined (OCTOSPIM_CR_MUXEN) 261 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected 262 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 263 This parameter can be a value between 1 and 256 */ 264 #endif 265 }OSPIM_CfgTypeDef; 266 267 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 268 /** 269 * @brief HAL OSPI Callback ID enumeration definition 270 */ 271 typedef enum 272 { 273 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 274 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 275 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 276 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 277 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 278 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 279 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 280 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 281 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 282 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 283 284 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 285 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 286 }HAL_OSPI_CallbackIDTypeDef; 287 288 /** 289 * @brief HAL OSPI Callback pointer definition 290 */ 291 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 292 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 293 /** 294 * @} 295 */ 296 297 /* Exported constants --------------------------------------------------------*/ 298 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 299 * @{ 300 */ 301 302 /** @defgroup OSPI_State OSPI State 303 * @{ 304 */ 305 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 306 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 307 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 308 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 309 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 310 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 311 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 312 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 313 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 314 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 315 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 316 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 317 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup OSPI_ErrorCode OSPI Error Code 323 * @{ 324 */ 325 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 326 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 327 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 328 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 329 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 330 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 331 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 332 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 333 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 334 /** 335 * @} 336 */ 337 338 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 339 * @{ 340 */ 341 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 342 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 343 /** 344 * @} 345 */ 346 347 /** @defgroup OSPI_MemoryType OSPI Memory Type 348 * @{ 349 */ 350 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 351 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 352 #if !defined(STM32L4R5xx)&&!defined(STM32L4R7xx)&&!defined(STM32L4R9xx)&&!defined(STM32L4S5xx)&&!defined(STM32L4S7xx)&&!defined(STM32L4S9xx) 353 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 354 #endif 355 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 356 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 357 /** 358 * @} 359 */ 360 361 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 362 * @{ 363 */ 364 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 365 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 366 /** 367 * @} 368 */ 369 370 /** @defgroup OSPI_ClockMode OSPI Clock Mode 371 * @{ 372 */ 373 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 374 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 375 /** 376 * @} 377 */ 378 379 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 380 * @{ 381 */ 382 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 383 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 384 /** 385 * @} 386 */ 387 388 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 389 * @{ 390 */ 391 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 392 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 398 * @{ 399 */ 400 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 401 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup OSPI_OperationType OSPI Operation Type 407 * @{ 408 */ 409 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 410 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 411 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 412 /** 413 * @} 414 */ 415 416 /** @defgroup OSPI_FlashID OSPI Flash Id 417 * @{ 418 */ 419 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 420 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 421 /** 422 * @} 423 */ 424 425 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 426 * @{ 427 */ 428 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 429 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 430 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 431 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 432 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 433 /** 434 * @} 435 */ 436 437 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 438 * @{ 439 */ 440 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 441 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 442 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 443 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 449 * @{ 450 */ 451 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 452 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 453 /** 454 * @} 455 */ 456 457 /** @defgroup OSPI_AddressMode OSPI Address Mode 458 * @{ 459 */ 460 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 461 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 462 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 463 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 464 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup OSPI_AddressSize OSPI Address Size 470 * @{ 471 */ 472 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 473 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 474 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 475 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 481 * @{ 482 */ 483 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 484 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 485 /** 486 * @} 487 */ 488 489 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 490 * @{ 491 */ 492 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 493 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 494 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 495 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 496 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 497 /** 498 * @} 499 */ 500 501 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 502 * @{ 503 */ 504 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 505 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 506 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 507 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 513 * @{ 514 */ 515 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 516 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 517 /** 518 * @} 519 */ 520 521 /** @defgroup OSPI_DataMode OSPI Data Mode 522 * @{ 523 */ 524 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 525 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 526 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 527 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 528 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 534 * @{ 535 */ 536 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 537 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup OSPI_DQSMode OSPI DQS Mode 543 * @{ 544 */ 545 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 546 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 552 * @{ 553 */ 554 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 555 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 556 /** 557 * @} 558 */ 559 560 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 561 * @{ 562 */ 563 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 564 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 565 /** 566 * @} 567 */ 568 569 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 570 * @{ 571 */ 572 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 573 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 574 /** 575 * @} 576 */ 577 578 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 579 * @{ 580 */ 581 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 582 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 583 /** 584 * @} 585 */ 586 587 /** @defgroup OSPI_MatchMode OSPI Match Mode 588 * @{ 589 */ 590 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 591 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 592 /** 593 * @} 594 */ 595 596 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 597 * @{ 598 */ 599 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 600 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 601 /** 602 * @} 603 */ 604 605 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 606 * @{ 607 */ 608 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 609 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 610 /** 611 * @} 612 */ 613 614 /** @defgroup OSPI_Flags OSPI Flags 615 * @{ 616 */ 617 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 618 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 619 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 620 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 621 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 622 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup OSPI_Interrupts OSPI Interrupts 628 * @{ 629 */ 630 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 631 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 632 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 633 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 634 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 635 /** 636 * @} 637 */ 638 639 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 640 * @{ 641 */ 642 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 643 /** 644 * @} 645 */ 646 647 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 648 * @{ 649 */ 650 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ 651 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 652 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 653 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 654 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 655 /** 656 * @} 657 */ 658 /** 659 * @} 660 */ 661 662 /* Exported macros -----------------------------------------------------------*/ 663 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 664 * @{ 665 */ 666 /** @brief Reset OSPI handle state. 667 * @param __HANDLE__ specifies the OSPI Handle. 668 * @retval None 669 */ 670 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 671 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 672 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 673 (__HANDLE__)->MspInitCallback = NULL; \ 674 (__HANDLE__)->MspDeInitCallback = NULL; \ 675 } while(0) 676 #else 677 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 678 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 679 680 /** @brief Enable the OSPI peripheral. 681 * @param __HANDLE__ specifies the OSPI Handle. 682 * @retval None 683 */ 684 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 685 686 /** @brief Disable the OSPI peripheral. 687 * @param __HANDLE__ specifies the OSPI Handle. 688 * @retval None 689 */ 690 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 691 692 /** @brief Enable the specified OSPI interrupt. 693 * @param __HANDLE__ specifies the OSPI Handle. 694 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 695 * This parameter can be one of the following values: 696 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 697 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 698 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 699 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 700 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 701 * @retval None 702 */ 703 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 704 705 706 /** @brief Disable the specified OSPI interrupt. 707 * @param __HANDLE__ specifies the OSPI Handle. 708 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 709 * This parameter can be one of the following values: 710 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 711 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 712 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 713 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 714 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 715 * @retval None 716 */ 717 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 718 719 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 720 * @param __HANDLE__ specifies the OSPI Handle. 721 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 722 * This parameter can be one of the following values: 723 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 724 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 725 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 726 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 727 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 728 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 729 */ 730 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ 731 == (__INTERRUPT__)) 732 733 /** 734 * @brief Check whether the selected OSPI flag is set or not. 735 * @param __HANDLE__ specifies the OSPI Handle. 736 * @param __FLAG__ specifies the OSPI flag to check. 737 * This parameter can be one of the following values: 738 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 739 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 740 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 741 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 742 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 743 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 744 * @retval None 745 */ 746 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 747 != 0U) ? SET : RESET) 748 749 /** @brief Clears the specified OSPI's flag status. 750 * @param __HANDLE__ specifies the OSPI Handle. 751 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 752 * This parameter can be one of the following values: 753 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 754 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 755 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 756 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 757 * @retval None 758 */ 759 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 760 761 /** 762 * @} 763 */ 764 765 /* Exported functions --------------------------------------------------------*/ 766 /** @addtogroup OSPI_Exported_Functions 767 * @{ 768 */ 769 770 /* Initialization/de-initialization functions ********************************/ 771 /** @addtogroup OSPI_Exported_Functions_Group1 772 * @{ 773 */ 774 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 775 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 776 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 777 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 778 779 /** 780 * @} 781 */ 782 783 /* IO operation functions *****************************************************/ 784 /** @addtogroup OSPI_Exported_Functions_Group2 785 * @{ 786 */ 787 /* OSPI IRQ handler function */ 788 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 789 790 /* OSPI command configuration functions */ 791 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 792 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 793 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 794 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 795 796 /* OSPI indirect mode functions */ 797 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 798 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 799 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 800 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 801 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 802 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 803 804 /* OSPI status flag polling mode functions */ 805 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 806 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 807 808 /* OSPI memory-mapped mode functions */ 809 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 810 811 /* Callback functions in non-blocking modes ***********************************/ 812 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 813 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 814 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 815 816 /* OSPI indirect mode functions */ 817 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 818 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 819 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 820 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 821 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 822 823 /* OSPI status flag polling mode functions */ 824 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 825 826 /* OSPI memory-mapped mode functions */ 827 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 828 829 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 830 /* OSPI callback registering/unregistering */ 831 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 832 pOSPI_CallbackTypeDef pCallback); 833 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 834 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 835 /** 836 * @} 837 */ 838 839 /* Peripheral Control and State functions ************************************/ 840 /** @addtogroup OSPI_Exported_Functions_Group3 841 * @{ 842 */ 843 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 844 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 845 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 846 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 847 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 848 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 849 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 850 851 /** 852 * @} 853 */ 854 855 /* OSPI IO Manager configuration function ************************************/ 856 /** @addtogroup OSPI_Exported_Functions_Group4 857 * @{ 858 */ 859 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 860 861 /** 862 * @} 863 */ 864 865 /** 866 * @} 867 */ 868 /* End of exported functions -------------------------------------------------*/ 869 870 /* Private macros ------------------------------------------------------------*/ 871 /** 872 @cond 0 873 */ 874 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 875 876 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 877 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 878 879 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 880 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 881 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 882 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 883 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 884 #else 885 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 886 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 887 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 888 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 889 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 890 #endif 891 892 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 893 894 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 895 896 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 897 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 898 899 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 900 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 901 902 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 903 904 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 905 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 906 907 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 908 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 909 910 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 911 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 912 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) 913 914 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 915 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 916 917 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 918 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 919 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 920 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 921 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 922 923 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 924 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 925 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 926 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 927 928 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 929 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 930 931 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 932 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 933 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 934 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 935 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 936 937 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 938 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 939 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 940 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 941 942 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 943 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 944 945 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 946 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 947 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 948 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 949 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 950 951 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 952 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 953 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 954 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 955 956 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 957 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 958 959 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 960 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 961 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 962 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 963 ((MODE) == HAL_OSPI_DATA_8_LINES)) 964 965 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 966 967 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 968 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 969 970 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 971 972 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 973 ((MODE) == HAL_OSPI_DQS_ENABLE)) 974 975 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 976 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 977 978 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 979 980 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 981 982 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 983 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 984 985 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 986 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 987 988 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 989 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 990 991 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 992 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 993 994 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 995 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 996 997 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 998 999 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1000 1001 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 1002 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 1003 1004 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1005 1006 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 1007 1008 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 1009 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 1010 #if defined (OCTOSPI_DCR3_MAXTRAN) 1011 1012 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1013 #endif 1014 1015 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) 1016 1017 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 2U) 1018 1019 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ 1020 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 1021 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 1022 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 1023 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) 1024 1025 #if defined (OCTOSPIM_CR_MUXEN) 1026 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1027 #endif /*(OCTOSPIM_CR_MUXEN)*/ 1028 /** 1029 @endcond 1030 */ 1031 1032 /* End of private macros -----------------------------------------------------*/ 1033 1034 /** 1035 * @} 1036 */ 1037 1038 /** 1039 * @} 1040 */ 1041 1042 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1043 1044 #ifdef __cplusplus 1045 } 1046 #endif 1047 1048 #endif /* STM32L4xx_HAL_OSPI_H */ 1049
