1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_nand.h 4 * @author MCD Application Team 5 * @brief Header file of NAND HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_NAND_H 38 #define __STM32L4xx_HAL_NAND_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined(FMC_BANK3) 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l4xx_ll_fmc.h" 48 49 /** @addtogroup STM32L4xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup NAND 54 * @{ 55 */ 56 57 /* Exported typedef ----------------------------------------------------------*/ 58 /* Exported types ------------------------------------------------------------*/ 59 /** @defgroup NAND_Exported_Types NAND Exported Types 60 * @{ 61 */ 62 63 /** 64 * @brief HAL NAND State structures definition 65 */ 66 typedef enum 67 { 68 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 69 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 70 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 71 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 72 }HAL_NAND_StateTypeDef; 73 74 /** 75 * @brief NAND Memory electronic signature Structure definition 76 */ 77 typedef struct 78 { 79 /*<! NAND memory electronic signature maker and device IDs */ 80 uint8_t Maker_Id; 81 82 uint8_t Device_Id; 83 84 uint8_t Third_Id; 85 86 uint8_t Fourth_Id; 87 }NAND_IDTypeDef; 88 89 /** 90 * @brief NAND Memory address Structure definition 91 */ 92 typedef struct 93 { 94 uint16_t Page; /*!< NAND memory Page address */ 95 96 uint16_t Plane; /*!< NAND memory Zone address */ 97 98 uint16_t Block; /*!< NAND memory Block address */ 99 }NAND_AddressTypeDef; 100 101 /** 102 * @brief NAND Memory info Structure definition 103 */ 104 typedef struct 105 { 106 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 107 for 8 bits adressing or words for 16 bits addressing */ 108 109 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 110 for 8 bits adressing or words for 16 bits addressing */ 111 112 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 113 114 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 115 116 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 117 118 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 119 120 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 121 parameter is mandatory for some NAND parts after the read 122 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 123 Example: Toshiba THTH58BYG3S0HBAI6. 124 This parameter could be ENABLE or DISABLE 125 Please check the Read Mode sequnece in the NAND device datasheet */ 126 } NAND_DeviceConfigTypeDef; 127 128 /** 129 * @brief NAND handle Structure definition 130 */ 131 typedef struct 132 { 133 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 134 135 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 136 137 HAL_LockTypeDef Lock; /*!< NAND locking object */ 138 139 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 140 141 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 142 143 } NAND_HandleTypeDef; 144 /** 145 * @} 146 */ 147 148 /* Exported constants --------------------------------------------------------*/ 149 /* Exported macro ------------------------------------------------------------*/ 150 /** @defgroup NAND_Exported_Macros NAND Exported Macros 151 * @{ 152 */ 153 154 /** @brief Reset NAND handle state 155 * @param __HANDLE__ specifies the NAND handle. 156 * @retval None 157 */ 158 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 159 160 /** 161 * @} 162 */ 163 164 /* Exported functions --------------------------------------------------------*/ 165 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 166 * @{ 167 */ 168 169 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 170 * @{ 171 */ 172 173 /* Initialization/de-initialization functions ********************************/ 174 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 175 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 176 177 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 178 179 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 180 181 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 182 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 183 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 184 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 185 186 /** 187 * @} 188 */ 189 190 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 191 * @{ 192 */ 193 194 /* IO operation functions ****************************************************/ 195 196 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 197 198 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); 199 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); 200 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 201 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 202 203 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); 204 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); 205 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 206 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 207 208 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 209 210 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 211 212 /** 213 * @} 214 */ 215 216 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 217 * @{ 218 */ 219 220 /* NAND Control functions ****************************************************/ 221 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 222 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 223 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 224 225 /** 226 * @} 227 */ 228 229 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 230 * @{ 231 */ 232 /* NAND State functions *******************************************************/ 233 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 234 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 235 /** 236 * @} 237 */ 238 239 /** 240 * @} 241 */ 242 /* Private types -------------------------------------------------------------*/ 243 /* Private variables ---------------------------------------------------------*/ 244 /* Private constants ---------------------------------------------------------*/ 245 /** @defgroup NAND_Private_Constants NAND Private Constants 246 * @{ 247 */ 248 #define NAND_DEVICE FMC_BANK3 249 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) 250 251 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ 252 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ 253 254 #define NAND_CMD_AREA_A ((uint8_t)0x00U) 255 #define NAND_CMD_AREA_B ((uint8_t)0x01U) 256 #define NAND_CMD_AREA_C ((uint8_t)0x50U) 257 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) 258 259 #define NAND_CMD_WRITE0 ((uint8_t)0x80U) 260 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) 261 #define NAND_CMD_ERASE0 ((uint8_t)0x60U) 262 #define NAND_CMD_ERASE1 ((uint8_t)0xD0U) 263 #define NAND_CMD_READID ((uint8_t)0x90U) 264 #define NAND_CMD_STATUS ((uint8_t)0x70U) 265 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) 266 #define NAND_CMD_RESET ((uint8_t)0xFFU) 267 268 /* NAND memory status */ 269 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) 270 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) 271 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) 272 #define NAND_BUSY ((uint32_t)0x00000000U) 273 #define NAND_ERROR ((uint32_t)0x00000001U) 274 #define NAND_READY ((uint32_t)0x00000040U) 275 /** 276 * @} 277 */ 278 279 /* Private macros ------------------------------------------------------------*/ 280 /** @defgroup NAND_Private_Macros NAND Private Macros 281 * @{ 282 */ 283 284 /** 285 * @brief NAND memory address computation. 286 * @param __ADDRESS__ NAND memory address. 287 * @param __HANDLE__ NAND handle. 288 * @retval NAND Raw address value 289 */ 290 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ 291 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) 292 293 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 294 295 /** 296 * @brief NAND memory address cycling. 297 * @param __ADDRESS__ NAND memory address. 298 * @retval NAND address cycling value. 299 */ 300 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 301 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 302 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 303 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 304 305 /** 306 * @brief NAND memory Columns cycling. 307 * @param __ADDRESS__ NAND memory address. 308 * @retval NAND Column address cycling value. 309 */ 310 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ 311 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 312 313 /** 314 * @} 315 */ 316 317 /** 318 * @} 319 */ 320 321 /** 322 * @} 323 */ 324 325 /** 326 * @} 327 */ 328 329 #endif /* FMC_BANK3 */ 330 331 #ifdef __cplusplus 332 } 333 #endif 334 335 #endif /* __STM32L4xx_HAL_NAND_H */ 336 337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 338
