1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_mmc.h 4 * @author MCD Application Team 5 * @brief Header file of MMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_MMC_H 21 #define STM32L4xx_HAL_MMC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 #include "stm32l4xx_ll_sdmmc.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 #if defined(SDMMC1) 36 37 /** @addtogroup MMC 38 * @brief MMC HAL module driver 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup MMC_Exported_Types MMC Exported Types 44 * @{ 45 */ 46 47 /** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure 48 * @{ 49 */ 50 typedef enum 51 { 52 HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ 53 HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ 54 HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ 55 HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ 56 HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ 57 HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ 58 HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */ 59 HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ 60 }HAL_MMC_StateTypeDef; 61 /** 62 * @} 63 */ 64 65 /** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure 66 * @{ 67 */ 68 typedef uint32_t HAL_MMC_CardStateTypeDef; 69 70 #define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */ 71 #define HAL_MMC_CARD_READY 0x00000001U /*!< Card is in ready state (can't be checked by CMD13) */ 72 #define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */ 73 #define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ 74 #define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ 75 #define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ 76 #define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ 77 #define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ 78 #define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ 79 #define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */ 80 #define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */ 81 #define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */ 82 /** 83 * @} 84 */ 85 86 /** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition 87 * @{ 88 */ 89 #define MMC_InitTypeDef SDMMC_InitTypeDef 90 #define MMC_TypeDef SDMMC_TypeDef 91 92 /** 93 * @brief MMC Card Information Structure definition 94 */ 95 typedef struct 96 { 97 uint32_t CardType; /*!< Specifies the card Type */ 98 99 uint32_t Class; /*!< Specifies the class of the card class */ 100 101 uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ 102 103 uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ 104 105 uint32_t BlockSize; /*!< Specifies one block size in bytes */ 106 107 uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ 108 109 uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ 110 111 }HAL_MMC_CardInfoTypeDef; 112 113 /** 114 * @brief MMC handle Structure definition 115 */ 116 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 117 typedef struct __MMC_HandleTypeDef 118 #else 119 typedef struct 120 #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ 121 { 122 MMC_TypeDef *Instance; /*!< MMC registers base address */ 123 124 MMC_InitTypeDef Init; /*!< MMC required parameters */ 125 126 HAL_LockTypeDef Lock; /*!< MMC locking object */ 127 128 uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ 129 130 uint32_t TxXferSize; /*!< MMC Tx Transfer size */ 131 132 uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ 133 134 uint32_t RxXferSize; /*!< MMC Rx Transfer size */ 135 136 __IO uint32_t Context; /*!< MMC transfer context */ 137 138 __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ 139 140 __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ 141 142 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 143 DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ 144 145 DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ 146 #endif /* !STM32L4P5xx && !STM32L4Q5xx && !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 147 148 HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ 149 150 uint32_t CSD[4U]; /*!< MMC card specific data table */ 151 152 uint32_t CID[4U]; /*!< MMC card identification number table */ 153 154 uint32_t Ext_CSD[128]; 155 156 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 157 void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); 158 void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); 159 void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); 160 void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); 161 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 162 void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); 163 void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); 164 void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); 165 void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); 166 #endif 167 168 void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); 169 void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); 170 #endif 171 }MMC_HandleTypeDef; 172 173 174 /** 175 * @} 176 */ 177 178 /** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register 179 * @{ 180 */ 181 typedef struct 182 { 183 __IO uint8_t CSDStruct; /*!< CSD structure */ 184 __IO uint8_t SysSpecVersion; /*!< System specification version */ 185 __IO uint8_t Reserved1; /*!< Reserved */ 186 __IO uint8_t TAAC; /*!< Data read access time 1 */ 187 __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ 188 __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ 189 __IO uint16_t CardComdClasses; /*!< Card command classes */ 190 __IO uint8_t RdBlockLen; /*!< Max. read data block length */ 191 __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ 192 __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ 193 __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ 194 __IO uint8_t DSRImpl; /*!< DSR implemented */ 195 __IO uint8_t Reserved2; /*!< Reserved */ 196 __IO uint32_t DeviceSize; /*!< Device Size */ 197 __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ 198 __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ 199 __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ 200 __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ 201 __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ 202 __IO uint8_t EraseGrSize; /*!< Erase group size */ 203 __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ 204 __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ 205 __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ 206 __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ 207 __IO uint8_t WrSpeedFact; /*!< Write speed factor */ 208 __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ 209 __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ 210 __IO uint8_t Reserved3; /*!< Reserved */ 211 __IO uint8_t ContentProtectAppli; /*!< Content protection application */ 212 __IO uint8_t FileFormatGroup; /*!< File format group */ 213 __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ 214 __IO uint8_t PermWrProtect; /*!< Permanent write protection */ 215 __IO uint8_t TempWrProtect; /*!< Temporary write protection */ 216 __IO uint8_t FileFormat; /*!< File format */ 217 __IO uint8_t ECC; /*!< ECC code */ 218 __IO uint8_t CSD_CRC; /*!< CSD CRC */ 219 __IO uint8_t Reserved4; /*!< Always 1 */ 220 221 }HAL_MMC_CardCSDTypeDef; 222 /** 223 * @} 224 */ 225 226 /** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register 227 * @{ 228 */ 229 typedef struct 230 { 231 __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ 232 __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ 233 __IO uint32_t ProdName1; /*!< Product Name part1 */ 234 __IO uint8_t ProdName2; /*!< Product Name part2 */ 235 __IO uint8_t ProdRev; /*!< Product Revision */ 236 __IO uint32_t ProdSN; /*!< Product Serial Number */ 237 __IO uint8_t Reserved1; /*!< Reserved1 */ 238 __IO uint16_t ManufactDate; /*!< Manufacturing Date */ 239 __IO uint8_t CID_CRC; /*!< CID CRC */ 240 __IO uint8_t Reserved2; /*!< Always 1 */ 241 242 }HAL_MMC_CardCIDTypeDef; 243 /** 244 * @} 245 */ 246 247 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 248 /** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition 249 * @{ 250 */ 251 typedef enum 252 { 253 HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ 254 HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ 255 HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ 256 HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ 257 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 258 HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID = 0x04U, /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */ 259 HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID = 0x05U, /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */ 260 HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U, /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */ 261 HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U, /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */ 262 #endif 263 264 HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ 265 HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ 266 }HAL_MMC_CallbackIDTypeDef; 267 /** 268 * @} 269 */ 270 271 /** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition 272 * @{ 273 */ 274 typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); 275 /** 276 * @} 277 */ 278 #endif 279 280 /** 281 * @} 282 */ 283 284 /* Exported constants --------------------------------------------------------*/ 285 /** @defgroup MMC_Exported_Constants Exported Constants 286 * @{ 287 */ 288 289 #define MMC_BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ 290 291 /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition 292 * @{ 293 */ 294 #define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ 295 #define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ 296 #define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ 297 #define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ 298 #define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ 299 #define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ 300 #define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ 301 #define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ 302 #define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the 303 number of transferred bytes does not match the block length */ 304 #define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ 305 #define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ 306 #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ 307 #define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock 308 command or if there was an attempt to access a locked card */ 309 #define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ 310 #define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ 311 #define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ 312 #define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ 313 #define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ 314 #define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ 315 #define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ 316 #define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ 317 #define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ 318 #define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ 319 #define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out 320 of erase sequence command was received */ 321 #define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ 322 #define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ 323 #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ 324 #define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ 325 #define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ 326 #define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ 327 #define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ 328 #define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ 329 #define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ 330 331 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 332 #define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ 333 #endif 334 /** 335 * @} 336 */ 337 338 /** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration 339 * @{ 340 */ 341 #define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ 342 #define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ 343 #define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ 344 #define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ 345 #define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ 346 #define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ 347 #define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ 348 349 /** 350 * @} 351 */ 352 353 /** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode 354 * @{ 355 */ 356 /** 357 * @brief 358 */ 359 #define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ 360 #define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ 361 #define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ 362 #define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ 363 #define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ 364 #define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ 365 #define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U 366 /** 367 * @} 368 */ 369 370 /** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards 371 * @{ 372 */ 373 #define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */ 374 #define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ 375 376 /** 377 * @} 378 */ 379 380 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 381 /** @defgroup MMC_Exported_Constansts_Group5 MMC Erase Type 382 * @{ 383 */ 384 #define HAL_MMC_ERASE 0x00000000U /*!< Erase the erase groups identified by CMD35 & 36 */ 385 #define HAL_MMC_TRIM 0x00000001U /*!< Erase the write blocks identified by CMD35 & 36 */ 386 #define HAL_MMC_DISCARD 0x00000003U /*!< Discard the write blocks identified by CMD35 & 36 */ 387 #define HAL_MMC_SECURE_ERASE 0x80000000U /*!< Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 */ 388 #define HAL_MMC_SECURE_TRIM_STEP1 0x80000001U /*!< Mark the write blocks identified by CMD35 & 36 for secure erase */ 389 #define HAL_MMC_SECURE_TRIM_STEP2 0x80008000U /*!< Perform a secure purge according SRT on the write blocks previously identified */ 390 391 #define IS_MMC_ERASE_TYPE(TYPE) (((TYPE) == HAL_MMC_ERASE) || \ 392 ((TYPE) == HAL_MMC_TRIM) || \ 393 ((TYPE) == HAL_MMC_DISCARD) || \ 394 ((TYPE) == HAL_MMC_SECURE_ERASE) || \ 395 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP1) || \ 396 ((TYPE) == HAL_MMC_SECURE_TRIM_STEP2)) 397 /** 398 * @} 399 */ 400 401 /** @defgroup MMC_Exported_Constansts_Group6 MMC Secure Removal Type 402 * @{ 403 */ 404 #define HAL_MMC_SRT_ERASE 0x00000001U /*!< Information removed by an erase */ 405 #define HAL_MMC_SRT_WRITE_CHAR_ERASE 0x00000002U /*!< Information removed by an overwriting with a character followed by an erase */ 406 #define HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM 0x00000004U /*!< Information removed by an overwriting with a character, its complement then a random character */ 407 #define HAL_MMC_SRT_VENDOR_DEFINED 0x00000008U /*!< Information removed using a vendor defined */ 408 409 410 #define IS_MMC_SRT_TYPE(TYPE) (((TYPE) == HAL_MMC_SRT_ERASE) || \ 411 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_ERASE) || \ 412 ((TYPE) == HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM) || \ 413 ((TYPE) == HAL_MMC_SRT_VENDOR_DEFINED)) 414 /** 415 * @} 416 */ 417 #endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ 418 419 /** 420 * @} 421 */ 422 423 /* Exported macro ------------------------------------------------------------*/ 424 /** @defgroup MMC_Exported_macros MMC Exported Macros 425 * @brief macros to handle interrupts and specific clock configurations 426 * @{ 427 */ 428 /** @brief Reset MMC handle state. 429 * @param __HANDLE__ : MMC handle. 430 * @retval None 431 */ 432 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 433 #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ 434 (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ 435 (__HANDLE__)->MspInitCallback = NULL; \ 436 (__HANDLE__)->MspDeInitCallback = NULL; \ 437 } while(0) 438 #else 439 #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) 440 #endif 441 442 #if !defined(STM32L4P5xx) && !defined(STM32L4Q5xx) && !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 443 /** 444 * @brief Enable the MMC device. 445 * @retval None 446 */ 447 #define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) 448 449 /** 450 * @brief Disable the MMC device. 451 * @retval None 452 */ 453 #define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) 454 455 /** 456 * @brief Enable the SDMMC DMA transfer. 457 * @retval None 458 */ 459 #define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) 460 461 /** 462 * @brief Disable the SDMMC DMA transfer. 463 * @retval None 464 */ 465 #define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) 466 #endif 467 468 /** 469 * @brief Enable the MMC device interrupt. 470 * @param __HANDLE__ MMC Handle 471 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. 472 * This parameter can be one or a combination of the following values: 473 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 474 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 475 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 476 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 477 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 478 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 479 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 480 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 481 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 482 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 483 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 484 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 485 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 486 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 487 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 488 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 489 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 490 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 491 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 492 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 493 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 494 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 495 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 496 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 497 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 498 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 499 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 500 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 501 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 502 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 503 * @retval None 504 */ 505 #define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 506 507 /** 508 * @brief Disable the MMC device interrupt. 509 * @param __HANDLE__ MMC Handle 510 * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. 511 * This parameter can be one or a combination of the following values: 512 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 513 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 514 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 515 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 516 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 517 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 518 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 519 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 520 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 521 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 522 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 523 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 524 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 525 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 526 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 527 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 528 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 529 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 530 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 531 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 532 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 533 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 534 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 535 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 536 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 537 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 538 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 539 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 540 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 541 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 542 * @retval None 543 */ 544 #define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 545 546 /** 547 * @brief Check whether the specified MMC flag is set or not. 548 * @param __HANDLE__ MMC Handle 549 * @param __FLAG__ specifies the flag to check. 550 * This parameter can be one of the following values: 551 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 552 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 553 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 554 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 555 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 556 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 557 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 558 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 559 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 560 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 561 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 562 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 563 * @arg SDMMC_FLAG_DPSMACT: Data path state machine active 564 * @arg SDMMC_FLAG_CPSMACT: Command path state machine active 565 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 566 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 567 * @arg SDMMC_FLAG_RXACT: Data receive in progress 568 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 569 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 570 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 571 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 572 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 573 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 574 * @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy) 575 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 576 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 577 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 578 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received 579 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 580 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 581 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 582 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 583 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 584 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 585 * @retval The new state of MMC FLAG (SET or RESET). 586 */ 587 #define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) 588 589 /** 590 * @brief Clear the MMC's pending flags. 591 * @param __HANDLE__ MMC Handle 592 * @param __FLAG__ specifies the flag to clear. 593 * This parameter can be one or a combination of the following values: 594 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 595 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 596 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 597 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 598 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 599 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 600 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 601 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 602 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) 603 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 604 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 605 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 606 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 607 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received 608 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 609 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 610 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 611 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 612 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 613 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 614 * @retval None 615 */ 616 #define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) 617 618 /** 619 * @brief Check whether the specified MMC interrupt has occurred or not. 620 * @param __HANDLE__ MMC Handle 621 * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. 622 * This parameter can be one of the following values: 623 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 624 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 625 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 626 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 627 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 628 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 629 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 630 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 631 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 632 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 633 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 634 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 635 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 636 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 637 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 638 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 639 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 640 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 641 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 642 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 643 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 644 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 645 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 646 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 647 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 648 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 649 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 650 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 651 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 652 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 653 * @retval The new state of MMC IT (SET or RESET). 654 */ 655 #define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 656 657 /** 658 * @brief Clear the MMC's interrupt pending bits. 659 * @param __HANDLE__ MMC Handle 660 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 661 * This parameter can be one or a combination of the following values: 662 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 663 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 664 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 665 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 666 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 667 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 668 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 669 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 670 * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt 671 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 672 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 673 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 674 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 675 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 676 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 677 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 678 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 679 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 680 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 681 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 682 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 683 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 684 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 685 * @retval None 686 */ 687 #define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) 688 689 /** 690 * @} 691 */ 692 693 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 694 /* Include MMC HAL Extension module */ 695 #include "stm32l4xx_hal_mmc_ex.h" 696 #endif 697 698 /* Exported functions --------------------------------------------------------*/ 699 /** @addtogroup MMC_Exported_Functions 700 * @{ 701 */ 702 703 /** @addtogroup MMC_Exported_Functions_Group1 704 * @{ 705 */ 706 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); 707 HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); 708 HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); 709 void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); 710 void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); 711 712 /** 713 * @} 714 */ 715 716 /** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions 717 * @{ 718 */ 719 /* Blocking mode: Polling */ 720 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); 721 HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); 722 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); 723 /* Non-Blocking mode: IT */ 724 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); 725 HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); 726 /* Non-Blocking mode: DMA */ 727 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); 728 HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); 729 730 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); 731 732 /* Callback in non blocking modes (DMA) */ 733 void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); 734 void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); 735 void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); 736 void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); 737 738 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) 739 /* MMC callback registering/unregistering */ 740 HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); 741 HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); 742 #endif 743 /** 744 * @} 745 */ 746 747 /** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions 748 * @{ 749 */ 750 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); 751 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 752 HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); 753 #endif 754 /** 755 * @} 756 */ 757 758 /** @defgroup MMC_Exported_Functions_Group4 MMC card related functions 759 * @{ 760 */ 761 HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); 762 HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); 763 HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); 764 HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); 765 HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); 766 /** 767 * @} 768 */ 769 770 /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions 771 * @{ 772 */ 773 HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); 774 uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); 775 /** 776 * @} 777 */ 778 779 /** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management 780 * @{ 781 */ 782 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); 783 HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); 784 /** 785 * @} 786 */ 787 #if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 788 /** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management 789 * @{ 790 */ 791 HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd); 792 HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc); 793 HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode); 794 HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT); 795 /** 796 * @} 797 */ 798 799 /** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management 800 * @{ 801 */ 802 HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc); 803 HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); 804 /** 805 * @} 806 */ 807 #endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) */ 808 809 /** 810 * @} 811 */ 812 813 /* Private types -------------------------------------------------------------*/ 814 /** @defgroup MMC_Private_Types MMC Private Types 815 * @{ 816 */ 817 818 /** 819 * @} 820 */ 821 822 /* Private defines -----------------------------------------------------------*/ 823 /** @defgroup MMC_Private_Defines MMC Private Defines 824 * @{ 825 */ 826 827 /** 828 * @} 829 */ 830 831 /* Private variables ---------------------------------------------------------*/ 832 /** @defgroup MMC_Private_Variables MMC Private Variables 833 * @{ 834 */ 835 836 /** 837 * @} 838 */ 839 840 /* Private constants ---------------------------------------------------------*/ 841 /** @defgroup MMC_Private_Constants MMC Private Constants 842 * @{ 843 */ 844 845 /** 846 * @} 847 */ 848 849 /* Private macros ------------------------------------------------------------*/ 850 /** @defgroup MMC_Private_Macros MMC Private Macros 851 * @{ 852 */ 853 854 /** 855 * @} 856 */ 857 858 /* Private functions prototypes ----------------------------------------------*/ 859 /** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes 860 * @{ 861 */ 862 863 /** 864 * @} 865 */ 866 867 /* Private functions ---------------------------------------------------------*/ 868 /** @defgroup MMC_Private_Functions MMC Private Functions 869 * @{ 870 */ 871 872 /** 873 * @} 874 */ 875 876 877 /** 878 * @} 879 */ 880 881 /** 882 * @} 883 */ 884 885 #endif /* SDMMC1 */ 886 887 /** 888 * @} 889 */ 890 891 #ifdef __cplusplus 892 } 893 #endif 894 895 896 #endif /* STM32L4xx_HAL_MMC_H */ 897
