1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2017 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32l4xx_hal.h"
324
325 /** @addtogroup STM32L4xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macro -------------------------------------------------------------*/
404 /* Macro to get remaining data to transfer on DMA side */
405 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
406
407 /* Private variables ---------------------------------------------------------*/
408 /* Private function prototypes -----------------------------------------------*/
409
410 /** @defgroup I2C_Private_Functions I2C Private Functions
411 * @{
412 */
413 /* Private functions to handle DMA transfer */
414 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
415 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
416 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
417 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
418 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
419 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
420
421 /* Private functions to handle IT transfer */
422 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
423 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
424 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
425 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
426 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
427 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
428 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
429
430 /* Private functions to handle IT transfer */
431 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
432 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
433 uint32_t Tickstart);
434 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
435 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
436 uint32_t Tickstart);
437
438 /* Private functions for I2C transfer IRQ handler */
439 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
440 uint32_t ITSources);
441 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
442 uint32_t ITSources);
443 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
444 uint32_t ITSources);
445 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
446 uint32_t ITSources);
447 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
448 uint32_t ITSources);
449 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
450 uint32_t ITSources);
451
452 /* Private functions to handle flags during polling transfer */
453 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
454 uint32_t Timeout, uint32_t Tickstart);
455 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
456 uint32_t Tickstart);
457 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
458 uint32_t Tickstart);
459 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
460 uint32_t Tickstart);
461 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
462 uint32_t Tickstart);
463
464 /* Private functions to centralize the enable/disable of Interrupts */
465 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
466 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
467
468 /* Private function to treat different error callback */
469 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
470
471 /* Private function to flush TXDR register */
472 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
473
474 /* Private function to handle start, restart or stop a transfer */
475 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
476 uint32_t Request);
477
478 /* Private function to Convert Specific options */
479 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
480 /**
481 * @}
482 */
483
484 /* Exported functions --------------------------------------------------------*/
485
486 /** @defgroup I2C_Exported_Functions I2C Exported Functions
487 * @{
488 */
489
490 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
491 * @brief Initialization and Configuration functions
492 *
493 @verbatim
494 ===============================================================================
495 ##### Initialization and de-initialization functions #####
496 ===============================================================================
497 [..] This subsection provides a set of functions allowing to initialize and
498 deinitialize the I2Cx peripheral:
499
500 (+) User must Implement HAL_I2C_MspInit() function in which he configures
501 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
502
503 (+) Call the function HAL_I2C_Init() to configure the selected device with
504 the selected configuration:
505 (++) Clock Timing
506 (++) Own Address 1
507 (++) Addressing mode (Master, Slave)
508 (++) Dual Addressing mode
509 (++) Own Address 2
510 (++) Own Address 2 Mask
511 (++) General call mode
512 (++) Nostretch mode
513
514 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
515 of the selected I2Cx peripheral.
516
517 @endverbatim
518 * @{
519 */
520
521 /**
522 * @brief Initializes the I2C according to the specified parameters
523 * in the I2C_InitTypeDef and initialize the associated handle.
524 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
525 * the configuration information for the specified I2C.
526 * @retval HAL status
527 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)528 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
529 {
530 /* Check the I2C handle allocation */
531 if (hi2c == NULL)
532 {
533 return HAL_ERROR;
534 }
535
536 /* Check the parameters */
537 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
538 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
539 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
540 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
541 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
542 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
543 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
544 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
545
546 if (hi2c->State == HAL_I2C_STATE_RESET)
547 {
548 /* Allocate lock resource and initialize it */
549 hi2c->Lock = HAL_UNLOCKED;
550
551 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
552 /* Init the I2C Callback settings */
553 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
554 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
555 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
556 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
557 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
558 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
559 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
560 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
561 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
562 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
563
564 if (hi2c->MspInitCallback == NULL)
565 {
566 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
567 }
568
569 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
570 hi2c->MspInitCallback(hi2c);
571 #else
572 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
573 HAL_I2C_MspInit(hi2c);
574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
575 }
576
577 hi2c->State = HAL_I2C_STATE_BUSY;
578
579 /* Disable the selected I2C peripheral */
580 __HAL_I2C_DISABLE(hi2c);
581
582 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
583 /* Configure I2Cx: Frequency range */
584 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
585
586 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
587 /* Disable Own Address1 before set the Own Address1 configuration */
588 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
589
590 /* Configure I2Cx: Own Address1 and ack own address1 mode */
591 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
592 {
593 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
594 }
595 else /* I2C_ADDRESSINGMODE_10BIT */
596 {
597 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
598 }
599
600 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
601 /* Configure I2Cx: Addressing Master mode */
602 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
603 {
604 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
605 }
606 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
607 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
608
609 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
610 /* Disable Own Address2 before set the Own Address2 configuration */
611 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
612
613 /* Configure I2Cx: Dual mode and Own Address2 */
614 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
615 (hi2c->Init.OwnAddress2Masks << 8));
616
617 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
618 /* Configure I2Cx: Generalcall and NoStretch mode */
619 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
620
621 /* Enable the selected I2C peripheral */
622 __HAL_I2C_ENABLE(hi2c);
623
624 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
625 hi2c->State = HAL_I2C_STATE_READY;
626 hi2c->PreviousState = I2C_STATE_NONE;
627 hi2c->Mode = HAL_I2C_MODE_NONE;
628
629 return HAL_OK;
630 }
631
632 /**
633 * @brief DeInitialize the I2C peripheral.
634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
635 * the configuration information for the specified I2C.
636 * @retval HAL status
637 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)638 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
639 {
640 /* Check the I2C handle allocation */
641 if (hi2c == NULL)
642 {
643 return HAL_ERROR;
644 }
645
646 /* Check the parameters */
647 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
648
649 hi2c->State = HAL_I2C_STATE_BUSY;
650
651 /* Disable the I2C Peripheral Clock */
652 __HAL_I2C_DISABLE(hi2c);
653
654 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
655 if (hi2c->MspDeInitCallback == NULL)
656 {
657 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
658 }
659
660 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
661 hi2c->MspDeInitCallback(hi2c);
662 #else
663 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
664 HAL_I2C_MspDeInit(hi2c);
665 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
666
667 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
668 hi2c->State = HAL_I2C_STATE_RESET;
669 hi2c->PreviousState = I2C_STATE_NONE;
670 hi2c->Mode = HAL_I2C_MODE_NONE;
671
672 /* Release Lock */
673 __HAL_UNLOCK(hi2c);
674
675 return HAL_OK;
676 }
677
678 /**
679 * @brief Initialize the I2C MSP.
680 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
681 * the configuration information for the specified I2C.
682 * @retval None
683 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)684 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
685 {
686 /* Prevent unused argument(s) compilation warning */
687 UNUSED(hi2c);
688
689 /* NOTE : This function should not be modified, when the callback is needed,
690 the HAL_I2C_MspInit could be implemented in the user file
691 */
692 }
693
694 /**
695 * @brief DeInitialize the I2C MSP.
696 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
697 * the configuration information for the specified I2C.
698 * @retval None
699 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)700 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
701 {
702 /* Prevent unused argument(s) compilation warning */
703 UNUSED(hi2c);
704
705 /* NOTE : This function should not be modified, when the callback is needed,
706 the HAL_I2C_MspDeInit could be implemented in the user file
707 */
708 }
709
710 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
711 /**
712 * @brief Register a User I2C Callback
713 * To be used instead of the weak predefined callback
714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
715 * the configuration information for the specified I2C.
716 * @param CallbackID ID of the callback to be registered
717 * This parameter can be one of the following values:
718 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
719 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
720 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
721 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
722 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
723 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
724 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
725 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
726 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
727 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
728 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
729 * @param pCallback pointer to the Callback function
730 * @retval HAL status
731 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)732 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
733 pI2C_CallbackTypeDef pCallback)
734 {
735 HAL_StatusTypeDef status = HAL_OK;
736
737 if (pCallback == NULL)
738 {
739 /* Update the error code */
740 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
741
742 return HAL_ERROR;
743 }
744 /* Process locked */
745 __HAL_LOCK(hi2c);
746
747 if (HAL_I2C_STATE_READY == hi2c->State)
748 {
749 switch (CallbackID)
750 {
751 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
752 hi2c->MasterTxCpltCallback = pCallback;
753 break;
754
755 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
756 hi2c->MasterRxCpltCallback = pCallback;
757 break;
758
759 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
760 hi2c->SlaveTxCpltCallback = pCallback;
761 break;
762
763 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
764 hi2c->SlaveRxCpltCallback = pCallback;
765 break;
766
767 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
768 hi2c->ListenCpltCallback = pCallback;
769 break;
770
771 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
772 hi2c->MemTxCpltCallback = pCallback;
773 break;
774
775 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
776 hi2c->MemRxCpltCallback = pCallback;
777 break;
778
779 case HAL_I2C_ERROR_CB_ID :
780 hi2c->ErrorCallback = pCallback;
781 break;
782
783 case HAL_I2C_ABORT_CB_ID :
784 hi2c->AbortCpltCallback = pCallback;
785 break;
786
787 case HAL_I2C_MSPINIT_CB_ID :
788 hi2c->MspInitCallback = pCallback;
789 break;
790
791 case HAL_I2C_MSPDEINIT_CB_ID :
792 hi2c->MspDeInitCallback = pCallback;
793 break;
794
795 default :
796 /* Update the error code */
797 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
798
799 /* Return error status */
800 status = HAL_ERROR;
801 break;
802 }
803 }
804 else if (HAL_I2C_STATE_RESET == hi2c->State)
805 {
806 switch (CallbackID)
807 {
808 case HAL_I2C_MSPINIT_CB_ID :
809 hi2c->MspInitCallback = pCallback;
810 break;
811
812 case HAL_I2C_MSPDEINIT_CB_ID :
813 hi2c->MspDeInitCallback = pCallback;
814 break;
815
816 default :
817 /* Update the error code */
818 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
819
820 /* Return error status */
821 status = HAL_ERROR;
822 break;
823 }
824 }
825 else
826 {
827 /* Update the error code */
828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
829
830 /* Return error status */
831 status = HAL_ERROR;
832 }
833
834 /* Release Lock */
835 __HAL_UNLOCK(hi2c);
836 return status;
837 }
838
839 /**
840 * @brief Unregister an I2C Callback
841 * I2C callback is redirected to the weak predefined callback
842 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
843 * the configuration information for the specified I2C.
844 * @param CallbackID ID of the callback to be unregistered
845 * This parameter can be one of the following values:
846 * This parameter can be one of the following values:
847 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
848 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
849 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
850 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
851 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
852 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
853 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
854 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
855 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
856 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
857 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
858 * @retval HAL status
859 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)860 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
861 {
862 HAL_StatusTypeDef status = HAL_OK;
863
864 /* Process locked */
865 __HAL_LOCK(hi2c);
866
867 if (HAL_I2C_STATE_READY == hi2c->State)
868 {
869 switch (CallbackID)
870 {
871 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
872 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
873 break;
874
875 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
876 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
877 break;
878
879 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
880 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
881 break;
882
883 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
884 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
885 break;
886
887 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
888 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
889 break;
890
891 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
892 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
893 break;
894
895 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
896 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
897 break;
898
899 case HAL_I2C_ERROR_CB_ID :
900 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
901 break;
902
903 case HAL_I2C_ABORT_CB_ID :
904 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
905 break;
906
907 case HAL_I2C_MSPINIT_CB_ID :
908 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
909 break;
910
911 case HAL_I2C_MSPDEINIT_CB_ID :
912 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
913 break;
914
915 default :
916 /* Update the error code */
917 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
918
919 /* Return error status */
920 status = HAL_ERROR;
921 break;
922 }
923 }
924 else if (HAL_I2C_STATE_RESET == hi2c->State)
925 {
926 switch (CallbackID)
927 {
928 case HAL_I2C_MSPINIT_CB_ID :
929 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
930 break;
931
932 case HAL_I2C_MSPDEINIT_CB_ID :
933 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
934 break;
935
936 default :
937 /* Update the error code */
938 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
939
940 /* Return error status */
941 status = HAL_ERROR;
942 break;
943 }
944 }
945 else
946 {
947 /* Update the error code */
948 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
949
950 /* Return error status */
951 status = HAL_ERROR;
952 }
953
954 /* Release Lock */
955 __HAL_UNLOCK(hi2c);
956 return status;
957 }
958
959 /**
960 * @brief Register the Slave Address Match I2C Callback
961 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
962 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
963 * the configuration information for the specified I2C.
964 * @param pCallback pointer to the Address Match Callback function
965 * @retval HAL status
966 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)967 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
968 {
969 HAL_StatusTypeDef status = HAL_OK;
970
971 if (pCallback == NULL)
972 {
973 /* Update the error code */
974 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
975
976 return HAL_ERROR;
977 }
978 /* Process locked */
979 __HAL_LOCK(hi2c);
980
981 if (HAL_I2C_STATE_READY == hi2c->State)
982 {
983 hi2c->AddrCallback = pCallback;
984 }
985 else
986 {
987 /* Update the error code */
988 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
989
990 /* Return error status */
991 status = HAL_ERROR;
992 }
993
994 /* Release Lock */
995 __HAL_UNLOCK(hi2c);
996 return status;
997 }
998
999 /**
1000 * @brief UnRegister the Slave Address Match I2C Callback
1001 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1002 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1003 * the configuration information for the specified I2C.
1004 * @retval HAL status
1005 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1006 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1007 {
1008 HAL_StatusTypeDef status = HAL_OK;
1009
1010 /* Process locked */
1011 __HAL_LOCK(hi2c);
1012
1013 if (HAL_I2C_STATE_READY == hi2c->State)
1014 {
1015 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1016 }
1017 else
1018 {
1019 /* Update the error code */
1020 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1021
1022 /* Return error status */
1023 status = HAL_ERROR;
1024 }
1025
1026 /* Release Lock */
1027 __HAL_UNLOCK(hi2c);
1028 return status;
1029 }
1030
1031 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1032
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1038 * @brief Data transfers functions
1039 *
1040 @verbatim
1041 ===============================================================================
1042 ##### IO operation functions #####
1043 ===============================================================================
1044 [..]
1045 This subsection provides a set of functions allowing to manage the I2C data
1046 transfers.
1047
1048 (#) There are two modes of transfer:
1049 (++) Blocking mode : The communication is performed in the polling mode.
1050 The status of all data processing is returned by the same function
1051 after finishing transfer.
1052 (++) No-Blocking mode : The communication is performed using Interrupts
1053 or DMA. These functions return the status of the transfer startup.
1054 The end of the data processing will be indicated through the
1055 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1056 using DMA mode.
1057
1058 (#) Blocking mode functions are :
1059 (++) HAL_I2C_Master_Transmit()
1060 (++) HAL_I2C_Master_Receive()
1061 (++) HAL_I2C_Slave_Transmit()
1062 (++) HAL_I2C_Slave_Receive()
1063 (++) HAL_I2C_Mem_Write()
1064 (++) HAL_I2C_Mem_Read()
1065 (++) HAL_I2C_IsDeviceReady()
1066
1067 (#) No-Blocking mode functions with Interrupt are :
1068 (++) HAL_I2C_Master_Transmit_IT()
1069 (++) HAL_I2C_Master_Receive_IT()
1070 (++) HAL_I2C_Slave_Transmit_IT()
1071 (++) HAL_I2C_Slave_Receive_IT()
1072 (++) HAL_I2C_Mem_Write_IT()
1073 (++) HAL_I2C_Mem_Read_IT()
1074 (++) HAL_I2C_Master_Seq_Transmit_IT()
1075 (++) HAL_I2C_Master_Seq_Receive_IT()
1076 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1077 (++) HAL_I2C_Slave_Seq_Receive_IT()
1078 (++) HAL_I2C_EnableListen_IT()
1079 (++) HAL_I2C_DisableListen_IT()
1080 (++) HAL_I2C_Master_Abort_IT()
1081
1082 (#) No-Blocking mode functions with DMA are :
1083 (++) HAL_I2C_Master_Transmit_DMA()
1084 (++) HAL_I2C_Master_Receive_DMA()
1085 (++) HAL_I2C_Slave_Transmit_DMA()
1086 (++) HAL_I2C_Slave_Receive_DMA()
1087 (++) HAL_I2C_Mem_Write_DMA()
1088 (++) HAL_I2C_Mem_Read_DMA()
1089 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1090 (++) HAL_I2C_Master_Seq_Receive_DMA()
1091 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1092 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1093
1094 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1095 (++) HAL_I2C_MasterTxCpltCallback()
1096 (++) HAL_I2C_MasterRxCpltCallback()
1097 (++) HAL_I2C_SlaveTxCpltCallback()
1098 (++) HAL_I2C_SlaveRxCpltCallback()
1099 (++) HAL_I2C_MemTxCpltCallback()
1100 (++) HAL_I2C_MemRxCpltCallback()
1101 (++) HAL_I2C_AddrCallback()
1102 (++) HAL_I2C_ListenCpltCallback()
1103 (++) HAL_I2C_ErrorCallback()
1104 (++) HAL_I2C_AbortCpltCallback()
1105
1106 @endverbatim
1107 * @{
1108 */
1109
1110 /**
1111 * @brief Transmits in master mode an amount of data in blocking mode.
1112 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1113 * the configuration information for the specified I2C.
1114 * @param DevAddress Target device address: The device 7 bits address value
1115 * in datasheet must be shifted to the left before calling the interface
1116 * @param pData Pointer to data buffer
1117 * @param Size Amount of data to be sent
1118 * @param Timeout Timeout duration
1119 * @retval HAL status
1120 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1121 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1122 uint16_t Size, uint32_t Timeout)
1123 {
1124 uint32_t tickstart;
1125
1126 if (hi2c->State == HAL_I2C_STATE_READY)
1127 {
1128 /* Process Locked */
1129 __HAL_LOCK(hi2c);
1130
1131 /* Init tickstart for timeout management*/
1132 tickstart = HAL_GetTick();
1133
1134 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1135 {
1136 return HAL_ERROR;
1137 }
1138
1139 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1140 hi2c->Mode = HAL_I2C_MODE_MASTER;
1141 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1142
1143 /* Prepare transfer parameters */
1144 hi2c->pBuffPtr = pData;
1145 hi2c->XferCount = Size;
1146 hi2c->XferISR = NULL;
1147
1148 /* Send Slave Address */
1149 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1150 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1151 {
1152 hi2c->XferSize = MAX_NBYTE_SIZE;
1153 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1154 I2C_GENERATE_START_WRITE);
1155 }
1156 else
1157 {
1158 hi2c->XferSize = hi2c->XferCount;
1159 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1160 I2C_GENERATE_START_WRITE);
1161 }
1162
1163 while (hi2c->XferCount > 0U)
1164 {
1165 /* Wait until TXIS flag is set */
1166 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1167 {
1168 return HAL_ERROR;
1169 }
1170 /* Write data to TXDR */
1171 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1172
1173 /* Increment Buffer pointer */
1174 hi2c->pBuffPtr++;
1175
1176 hi2c->XferCount--;
1177 hi2c->XferSize--;
1178
1179 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1180 {
1181 /* Wait until TCR flag is set */
1182 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1183 {
1184 return HAL_ERROR;
1185 }
1186
1187 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1188 {
1189 hi2c->XferSize = MAX_NBYTE_SIZE;
1190 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1191 I2C_NO_STARTSTOP);
1192 }
1193 else
1194 {
1195 hi2c->XferSize = hi2c->XferCount;
1196 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1197 I2C_NO_STARTSTOP);
1198 }
1199 }
1200 }
1201
1202 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1203 /* Wait until STOPF flag is set */
1204 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1205 {
1206 return HAL_ERROR;
1207 }
1208
1209 /* Clear STOP Flag */
1210 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1211
1212 /* Clear Configuration Register 2 */
1213 I2C_RESET_CR2(hi2c);
1214
1215 hi2c->State = HAL_I2C_STATE_READY;
1216 hi2c->Mode = HAL_I2C_MODE_NONE;
1217
1218 /* Process Unlocked */
1219 __HAL_UNLOCK(hi2c);
1220
1221 return HAL_OK;
1222 }
1223 else
1224 {
1225 return HAL_BUSY;
1226 }
1227 }
1228
1229 /**
1230 * @brief Receives in master mode an amount of data in blocking mode.
1231 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1232 * the configuration information for the specified I2C.
1233 * @param DevAddress Target device address: The device 7 bits address value
1234 * in datasheet must be shifted to the left before calling the interface
1235 * @param pData Pointer to data buffer
1236 * @param Size Amount of data to be sent
1237 * @param Timeout Timeout duration
1238 * @retval HAL status
1239 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1240 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1241 uint16_t Size, uint32_t Timeout)
1242 {
1243 uint32_t tickstart;
1244
1245 if (hi2c->State == HAL_I2C_STATE_READY)
1246 {
1247 /* Process Locked */
1248 __HAL_LOCK(hi2c);
1249
1250 /* Init tickstart for timeout management*/
1251 tickstart = HAL_GetTick();
1252
1253 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1254 {
1255 return HAL_ERROR;
1256 }
1257
1258 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1259 hi2c->Mode = HAL_I2C_MODE_MASTER;
1260 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1261
1262 /* Prepare transfer parameters */
1263 hi2c->pBuffPtr = pData;
1264 hi2c->XferCount = Size;
1265 hi2c->XferISR = NULL;
1266
1267 /* Send Slave Address */
1268 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1269 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1270 {
1271 hi2c->XferSize = MAX_NBYTE_SIZE;
1272 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1273 I2C_GENERATE_START_READ);
1274 }
1275 else
1276 {
1277 hi2c->XferSize = hi2c->XferCount;
1278 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1279 I2C_GENERATE_START_READ);
1280 }
1281
1282 while (hi2c->XferCount > 0U)
1283 {
1284 /* Wait until RXNE flag is set */
1285 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1286 {
1287 return HAL_ERROR;
1288 }
1289
1290 /* Read data from RXDR */
1291 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1292
1293 /* Increment Buffer pointer */
1294 hi2c->pBuffPtr++;
1295
1296 hi2c->XferSize--;
1297 hi2c->XferCount--;
1298
1299 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1300 {
1301 /* Wait until TCR flag is set */
1302 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1303 {
1304 return HAL_ERROR;
1305 }
1306
1307 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1308 {
1309 hi2c->XferSize = MAX_NBYTE_SIZE;
1310 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1311 I2C_NO_STARTSTOP);
1312 }
1313 else
1314 {
1315 hi2c->XferSize = hi2c->XferCount;
1316 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1317 I2C_NO_STARTSTOP);
1318 }
1319 }
1320 }
1321
1322 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1323 /* Wait until STOPF flag is set */
1324 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1325 {
1326 return HAL_ERROR;
1327 }
1328
1329 /* Clear STOP Flag */
1330 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1331
1332 /* Clear Configuration Register 2 */
1333 I2C_RESET_CR2(hi2c);
1334
1335 hi2c->State = HAL_I2C_STATE_READY;
1336 hi2c->Mode = HAL_I2C_MODE_NONE;
1337
1338 /* Process Unlocked */
1339 __HAL_UNLOCK(hi2c);
1340
1341 return HAL_OK;
1342 }
1343 else
1344 {
1345 return HAL_BUSY;
1346 }
1347 }
1348
1349 /**
1350 * @brief Transmits in slave mode an amount of data in blocking mode.
1351 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1352 * the configuration information for the specified I2C.
1353 * @param pData Pointer to data buffer
1354 * @param Size Amount of data to be sent
1355 * @param Timeout Timeout duration
1356 * @retval HAL status
1357 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1358 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1359 uint32_t Timeout)
1360 {
1361 uint32_t tickstart;
1362
1363 if (hi2c->State == HAL_I2C_STATE_READY)
1364 {
1365 if ((pData == NULL) || (Size == 0U))
1366 {
1367 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1368 return HAL_ERROR;
1369 }
1370 /* Process Locked */
1371 __HAL_LOCK(hi2c);
1372
1373 /* Init tickstart for timeout management*/
1374 tickstart = HAL_GetTick();
1375
1376 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1377 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1378 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1379
1380 /* Prepare transfer parameters */
1381 hi2c->pBuffPtr = pData;
1382 hi2c->XferCount = Size;
1383 hi2c->XferISR = NULL;
1384
1385 /* Enable Address Acknowledge */
1386 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1387
1388 /* Wait until ADDR flag is set */
1389 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1390 {
1391 /* Disable Address Acknowledge */
1392 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1393 return HAL_ERROR;
1394 }
1395
1396 /* Clear ADDR flag */
1397 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1398
1399 /* If 10bit addressing mode is selected */
1400 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1401 {
1402 /* Wait until ADDR flag is set */
1403 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1404 {
1405 /* Disable Address Acknowledge */
1406 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1407 return HAL_ERROR;
1408 }
1409
1410 /* Clear ADDR flag */
1411 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1412 }
1413
1414 /* Wait until DIR flag is set Transmitter mode */
1415 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1416 {
1417 /* Disable Address Acknowledge */
1418 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1419 return HAL_ERROR;
1420 }
1421
1422 while (hi2c->XferCount > 0U)
1423 {
1424 /* Wait until TXIS flag is set */
1425 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1426 {
1427 /* Disable Address Acknowledge */
1428 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1429 return HAL_ERROR;
1430 }
1431
1432 /* Write data to TXDR */
1433 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1434
1435 /* Increment Buffer pointer */
1436 hi2c->pBuffPtr++;
1437
1438 hi2c->XferCount--;
1439 }
1440
1441 /* Wait until AF flag is set */
1442 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446 return HAL_ERROR;
1447 }
1448
1449 /* Flush TX register */
1450 I2C_Flush_TXDR(hi2c);
1451
1452 /* Clear AF flag */
1453 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1454
1455 /* Wait until STOP flag is set */
1456 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1457 {
1458 /* Disable Address Acknowledge */
1459 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1460
1461 return HAL_ERROR;
1462 }
1463
1464 /* Clear STOP flag */
1465 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1466
1467 /* Wait until BUSY flag is reset */
1468 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1469 {
1470 /* Disable Address Acknowledge */
1471 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1472 return HAL_ERROR;
1473 }
1474
1475 /* Disable Address Acknowledge */
1476 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1477
1478 hi2c->State = HAL_I2C_STATE_READY;
1479 hi2c->Mode = HAL_I2C_MODE_NONE;
1480
1481 /* Process Unlocked */
1482 __HAL_UNLOCK(hi2c);
1483
1484 return HAL_OK;
1485 }
1486 else
1487 {
1488 return HAL_BUSY;
1489 }
1490 }
1491
1492 /**
1493 * @brief Receive in slave mode an amount of data in blocking mode
1494 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1495 * the configuration information for the specified I2C.
1496 * @param pData Pointer to data buffer
1497 * @param Size Amount of data to be sent
1498 * @param Timeout Timeout duration
1499 * @retval HAL status
1500 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1501 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1502 uint32_t Timeout)
1503 {
1504 uint32_t tickstart;
1505
1506 if (hi2c->State == HAL_I2C_STATE_READY)
1507 {
1508 if ((pData == NULL) || (Size == 0U))
1509 {
1510 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1511 return HAL_ERROR;
1512 }
1513 /* Process Locked */
1514 __HAL_LOCK(hi2c);
1515
1516 /* Init tickstart for timeout management*/
1517 tickstart = HAL_GetTick();
1518
1519 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1520 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1521 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1522
1523 /* Prepare transfer parameters */
1524 hi2c->pBuffPtr = pData;
1525 hi2c->XferCount = Size;
1526 hi2c->XferSize = hi2c->XferCount;
1527 hi2c->XferISR = NULL;
1528
1529 /* Enable Address Acknowledge */
1530 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1531
1532 /* Wait until ADDR flag is set */
1533 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1534 {
1535 /* Disable Address Acknowledge */
1536 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1537 return HAL_ERROR;
1538 }
1539
1540 /* Clear ADDR flag */
1541 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1542
1543 /* Wait until DIR flag is reset Receiver mode */
1544 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1545 {
1546 /* Disable Address Acknowledge */
1547 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1548 return HAL_ERROR;
1549 }
1550
1551 while (hi2c->XferCount > 0U)
1552 {
1553 /* Wait until RXNE flag is set */
1554 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1555 {
1556 /* Disable Address Acknowledge */
1557 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1558
1559 /* Store Last receive data if any */
1560 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1561 {
1562 /* Read data from RXDR */
1563 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1564
1565 /* Increment Buffer pointer */
1566 hi2c->pBuffPtr++;
1567
1568 hi2c->XferCount--;
1569 hi2c->XferSize--;
1570 }
1571
1572 return HAL_ERROR;
1573 }
1574
1575 /* Read data from RXDR */
1576 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1577
1578 /* Increment Buffer pointer */
1579 hi2c->pBuffPtr++;
1580
1581 hi2c->XferCount--;
1582 hi2c->XferSize--;
1583 }
1584
1585 /* Wait until STOP flag is set */
1586 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1587 {
1588 /* Disable Address Acknowledge */
1589 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1590 return HAL_ERROR;
1591 }
1592
1593 /* Clear STOP flag */
1594 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1595
1596 /* Wait until BUSY flag is reset */
1597 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1598 {
1599 /* Disable Address Acknowledge */
1600 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1601 return HAL_ERROR;
1602 }
1603
1604 /* Disable Address Acknowledge */
1605 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1606
1607 hi2c->State = HAL_I2C_STATE_READY;
1608 hi2c->Mode = HAL_I2C_MODE_NONE;
1609
1610 /* Process Unlocked */
1611 __HAL_UNLOCK(hi2c);
1612
1613 return HAL_OK;
1614 }
1615 else
1616 {
1617 return HAL_BUSY;
1618 }
1619 }
1620
1621 /**
1622 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1623 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1624 * the configuration information for the specified I2C.
1625 * @param DevAddress Target device address: The device 7 bits address value
1626 * in datasheet must be shifted to the left before calling the interface
1627 * @param pData Pointer to data buffer
1628 * @param Size Amount of data to be sent
1629 * @retval HAL status
1630 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1631 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1632 uint16_t Size)
1633 {
1634 uint32_t xfermode;
1635
1636 if (hi2c->State == HAL_I2C_STATE_READY)
1637 {
1638 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1639 {
1640 return HAL_BUSY;
1641 }
1642
1643 /* Process Locked */
1644 __HAL_LOCK(hi2c);
1645
1646 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1647 hi2c->Mode = HAL_I2C_MODE_MASTER;
1648 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1649
1650 /* Prepare transfer parameters */
1651 hi2c->pBuffPtr = pData;
1652 hi2c->XferCount = Size;
1653 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1654 hi2c->XferISR = I2C_Master_ISR_IT;
1655
1656 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1657 {
1658 hi2c->XferSize = MAX_NBYTE_SIZE;
1659 xfermode = I2C_RELOAD_MODE;
1660 }
1661 else
1662 {
1663 hi2c->XferSize = hi2c->XferCount;
1664 xfermode = I2C_AUTOEND_MODE;
1665 }
1666
1667 /* Send Slave Address */
1668 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1669 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1670
1671 /* Process Unlocked */
1672 __HAL_UNLOCK(hi2c);
1673
1674 /* Note : The I2C interrupts must be enabled after unlocking current process
1675 to avoid the risk of I2C interrupt handle execution before current
1676 process unlock */
1677
1678 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1679 /* possible to enable all of these */
1680 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1681 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1682 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1683
1684 return HAL_OK;
1685 }
1686 else
1687 {
1688 return HAL_BUSY;
1689 }
1690 }
1691
1692 /**
1693 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1694 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1695 * the configuration information for the specified I2C.
1696 * @param DevAddress Target device address: The device 7 bits address value
1697 * in datasheet must be shifted to the left before calling the interface
1698 * @param pData Pointer to data buffer
1699 * @param Size Amount of data to be sent
1700 * @retval HAL status
1701 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1702 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1703 uint16_t Size)
1704 {
1705 uint32_t xfermode;
1706
1707 if (hi2c->State == HAL_I2C_STATE_READY)
1708 {
1709 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1710 {
1711 return HAL_BUSY;
1712 }
1713
1714 /* Process Locked */
1715 __HAL_LOCK(hi2c);
1716
1717 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1718 hi2c->Mode = HAL_I2C_MODE_MASTER;
1719 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1720
1721 /* Prepare transfer parameters */
1722 hi2c->pBuffPtr = pData;
1723 hi2c->XferCount = Size;
1724 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1725 hi2c->XferISR = I2C_Master_ISR_IT;
1726
1727 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1728 {
1729 hi2c->XferSize = MAX_NBYTE_SIZE;
1730 xfermode = I2C_RELOAD_MODE;
1731 }
1732 else
1733 {
1734 hi2c->XferSize = hi2c->XferCount;
1735 xfermode = I2C_AUTOEND_MODE;
1736 }
1737
1738 /* Send Slave Address */
1739 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1740 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1741
1742 /* Process Unlocked */
1743 __HAL_UNLOCK(hi2c);
1744
1745 /* Note : The I2C interrupts must be enabled after unlocking current process
1746 to avoid the risk of I2C interrupt handle execution before current
1747 process unlock */
1748
1749 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1750 /* possible to enable all of these */
1751 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1752 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1753 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1754
1755 return HAL_OK;
1756 }
1757 else
1758 {
1759 return HAL_BUSY;
1760 }
1761 }
1762
1763 /**
1764 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1765 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1766 * the configuration information for the specified I2C.
1767 * @param pData Pointer to data buffer
1768 * @param Size Amount of data to be sent
1769 * @retval HAL status
1770 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1771 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1772 {
1773 if (hi2c->State == HAL_I2C_STATE_READY)
1774 {
1775 /* Process Locked */
1776 __HAL_LOCK(hi2c);
1777
1778 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1779 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1780 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1781
1782 /* Enable Address Acknowledge */
1783 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1784
1785 /* Prepare transfer parameters */
1786 hi2c->pBuffPtr = pData;
1787 hi2c->XferCount = Size;
1788 hi2c->XferSize = hi2c->XferCount;
1789 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1790 hi2c->XferISR = I2C_Slave_ISR_IT;
1791
1792 /* Process Unlocked */
1793 __HAL_UNLOCK(hi2c);
1794
1795 /* Note : The I2C interrupts must be enabled after unlocking current process
1796 to avoid the risk of I2C interrupt handle execution before current
1797 process unlock */
1798
1799 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1800 /* possible to enable all of these */
1801 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1802 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1803 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1804
1805 return HAL_OK;
1806 }
1807 else
1808 {
1809 return HAL_BUSY;
1810 }
1811 }
1812
1813 /**
1814 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1815 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1816 * the configuration information for the specified I2C.
1817 * @param pData Pointer to data buffer
1818 * @param Size Amount of data to be sent
1819 * @retval HAL status
1820 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1821 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1822 {
1823 if (hi2c->State == HAL_I2C_STATE_READY)
1824 {
1825 /* Process Locked */
1826 __HAL_LOCK(hi2c);
1827
1828 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1829 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1830 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1831
1832 /* Enable Address Acknowledge */
1833 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1834
1835 /* Prepare transfer parameters */
1836 hi2c->pBuffPtr = pData;
1837 hi2c->XferCount = Size;
1838 hi2c->XferSize = hi2c->XferCount;
1839 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1840 hi2c->XferISR = I2C_Slave_ISR_IT;
1841
1842 /* Process Unlocked */
1843 __HAL_UNLOCK(hi2c);
1844
1845 /* Note : The I2C interrupts must be enabled after unlocking current process
1846 to avoid the risk of I2C interrupt handle execution before current
1847 process unlock */
1848
1849 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1850 /* possible to enable all of these */
1851 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1852 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1853 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1854
1855 return HAL_OK;
1856 }
1857 else
1858 {
1859 return HAL_BUSY;
1860 }
1861 }
1862
1863 /**
1864 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1865 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1866 * the configuration information for the specified I2C.
1867 * @param DevAddress Target device address: The device 7 bits address value
1868 * in datasheet must be shifted to the left before calling the interface
1869 * @param pData Pointer to data buffer
1870 * @param Size Amount of data to be sent
1871 * @retval HAL status
1872 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1873 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1874 uint16_t Size)
1875 {
1876 uint32_t xfermode;
1877 HAL_StatusTypeDef dmaxferstatus;
1878
1879 if (hi2c->State == HAL_I2C_STATE_READY)
1880 {
1881 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1882 {
1883 return HAL_BUSY;
1884 }
1885
1886 /* Process Locked */
1887 __HAL_LOCK(hi2c);
1888
1889 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1890 hi2c->Mode = HAL_I2C_MODE_MASTER;
1891 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1892
1893 /* Prepare transfer parameters */
1894 hi2c->pBuffPtr = pData;
1895 hi2c->XferCount = Size;
1896 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1897 hi2c->XferISR = I2C_Master_ISR_DMA;
1898
1899 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1900 {
1901 hi2c->XferSize = MAX_NBYTE_SIZE;
1902 xfermode = I2C_RELOAD_MODE;
1903 }
1904 else
1905 {
1906 hi2c->XferSize = hi2c->XferCount;
1907 xfermode = I2C_AUTOEND_MODE;
1908 }
1909
1910 if (hi2c->XferSize > 0U)
1911 {
1912 if (hi2c->hdmatx != NULL)
1913 {
1914 /* Set the I2C DMA transfer complete callback */
1915 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1916
1917 /* Set the DMA error callback */
1918 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1919
1920 /* Set the unused DMA callbacks to NULL */
1921 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1922 hi2c->hdmatx->XferAbortCallback = NULL;
1923
1924 /* Enable the DMA channel */
1925 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
1926 hi2c->XferSize);
1927 }
1928 else
1929 {
1930 /* Update I2C state */
1931 hi2c->State = HAL_I2C_STATE_READY;
1932 hi2c->Mode = HAL_I2C_MODE_NONE;
1933
1934 /* Update I2C error code */
1935 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1936
1937 /* Process Unlocked */
1938 __HAL_UNLOCK(hi2c);
1939
1940 return HAL_ERROR;
1941 }
1942
1943 if (dmaxferstatus == HAL_OK)
1944 {
1945 /* Send Slave Address */
1946 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1947 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1948
1949 /* Update XferCount value */
1950 hi2c->XferCount -= hi2c->XferSize;
1951
1952 /* Process Unlocked */
1953 __HAL_UNLOCK(hi2c);
1954
1955 /* Note : The I2C interrupts must be enabled after unlocking current process
1956 to avoid the risk of I2C interrupt handle execution before current
1957 process unlock */
1958 /* Enable ERR and NACK interrupts */
1959 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1960
1961 /* Enable DMA Request */
1962 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1963 }
1964 else
1965 {
1966 /* Update I2C state */
1967 hi2c->State = HAL_I2C_STATE_READY;
1968 hi2c->Mode = HAL_I2C_MODE_NONE;
1969
1970 /* Update I2C error code */
1971 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
1972
1973 /* Process Unlocked */
1974 __HAL_UNLOCK(hi2c);
1975
1976 return HAL_ERROR;
1977 }
1978 }
1979 else
1980 {
1981 /* Update Transfer ISR function pointer */
1982 hi2c->XferISR = I2C_Master_ISR_IT;
1983
1984 /* Send Slave Address */
1985 /* Set NBYTES to write and generate START condition */
1986 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1987 I2C_GENERATE_START_WRITE);
1988
1989 /* Process Unlocked */
1990 __HAL_UNLOCK(hi2c);
1991
1992 /* Note : The I2C interrupts must be enabled after unlocking current process
1993 to avoid the risk of I2C interrupt handle execution before current
1994 process unlock */
1995 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1996 /* possible to enable all of these */
1997 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1998 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1999 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2000 }
2001
2002 return HAL_OK;
2003 }
2004 else
2005 {
2006 return HAL_BUSY;
2007 }
2008 }
2009
2010 /**
2011 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2012 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2013 * the configuration information for the specified I2C.
2014 * @param DevAddress Target device address: The device 7 bits address value
2015 * in datasheet must be shifted to the left before calling the interface
2016 * @param pData Pointer to data buffer
2017 * @param Size Amount of data to be sent
2018 * @retval HAL status
2019 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2020 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2021 uint16_t Size)
2022 {
2023 uint32_t xfermode;
2024 HAL_StatusTypeDef dmaxferstatus;
2025
2026 if (hi2c->State == HAL_I2C_STATE_READY)
2027 {
2028 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2029 {
2030 return HAL_BUSY;
2031 }
2032
2033 /* Process Locked */
2034 __HAL_LOCK(hi2c);
2035
2036 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2037 hi2c->Mode = HAL_I2C_MODE_MASTER;
2038 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2039
2040 /* Prepare transfer parameters */
2041 hi2c->pBuffPtr = pData;
2042 hi2c->XferCount = Size;
2043 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2044 hi2c->XferISR = I2C_Master_ISR_DMA;
2045
2046 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2047 {
2048 hi2c->XferSize = MAX_NBYTE_SIZE;
2049 xfermode = I2C_RELOAD_MODE;
2050 }
2051 else
2052 {
2053 hi2c->XferSize = hi2c->XferCount;
2054 xfermode = I2C_AUTOEND_MODE;
2055 }
2056
2057 if (hi2c->XferSize > 0U)
2058 {
2059 if (hi2c->hdmarx != NULL)
2060 {
2061 /* Set the I2C DMA transfer complete callback */
2062 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2063
2064 /* Set the DMA error callback */
2065 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2066
2067 /* Set the unused DMA callbacks to NULL */
2068 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2069 hi2c->hdmarx->XferAbortCallback = NULL;
2070
2071 /* Enable the DMA channel */
2072 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2073 hi2c->XferSize);
2074 }
2075 else
2076 {
2077 /* Update I2C state */
2078 hi2c->State = HAL_I2C_STATE_READY;
2079 hi2c->Mode = HAL_I2C_MODE_NONE;
2080
2081 /* Update I2C error code */
2082 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2083
2084 /* Process Unlocked */
2085 __HAL_UNLOCK(hi2c);
2086
2087 return HAL_ERROR;
2088 }
2089
2090 if (dmaxferstatus == HAL_OK)
2091 {
2092 /* Send Slave Address */
2093 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2094 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2095
2096 /* Update XferCount value */
2097 hi2c->XferCount -= hi2c->XferSize;
2098
2099 /* Process Unlocked */
2100 __HAL_UNLOCK(hi2c);
2101
2102 /* Note : The I2C interrupts must be enabled after unlocking current process
2103 to avoid the risk of I2C interrupt handle execution before current
2104 process unlock */
2105 /* Enable ERR and NACK interrupts */
2106 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2107
2108 /* Enable DMA Request */
2109 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2110 }
2111 else
2112 {
2113 /* Update I2C state */
2114 hi2c->State = HAL_I2C_STATE_READY;
2115 hi2c->Mode = HAL_I2C_MODE_NONE;
2116
2117 /* Update I2C error code */
2118 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2119
2120 /* Process Unlocked */
2121 __HAL_UNLOCK(hi2c);
2122
2123 return HAL_ERROR;
2124 }
2125 }
2126 else
2127 {
2128 /* Update Transfer ISR function pointer */
2129 hi2c->XferISR = I2C_Master_ISR_IT;
2130
2131 /* Send Slave Address */
2132 /* Set NBYTES to read and generate START condition */
2133 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2134 I2C_GENERATE_START_READ);
2135
2136 /* Process Unlocked */
2137 __HAL_UNLOCK(hi2c);
2138
2139 /* Note : The I2C interrupts must be enabled after unlocking current process
2140 to avoid the risk of I2C interrupt handle execution before current
2141 process unlock */
2142 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2143 /* possible to enable all of these */
2144 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2145 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2146 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2147 }
2148
2149 return HAL_OK;
2150 }
2151 else
2152 {
2153 return HAL_BUSY;
2154 }
2155 }
2156
2157 /**
2158 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2159 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2160 * the configuration information for the specified I2C.
2161 * @param pData Pointer to data buffer
2162 * @param Size Amount of data to be sent
2163 * @retval HAL status
2164 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2165 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2166 {
2167 HAL_StatusTypeDef dmaxferstatus;
2168
2169 if (hi2c->State == HAL_I2C_STATE_READY)
2170 {
2171 if ((pData == NULL) || (Size == 0U))
2172 {
2173 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2174 return HAL_ERROR;
2175 }
2176 /* Process Locked */
2177 __HAL_LOCK(hi2c);
2178
2179 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2180 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2182
2183 /* Prepare transfer parameters */
2184 hi2c->pBuffPtr = pData;
2185 hi2c->XferCount = Size;
2186 hi2c->XferSize = hi2c->XferCount;
2187 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2188 hi2c->XferISR = I2C_Slave_ISR_DMA;
2189
2190 if (hi2c->hdmatx != NULL)
2191 {
2192 /* Set the I2C DMA transfer complete callback */
2193 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2194
2195 /* Set the DMA error callback */
2196 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2197
2198 /* Set the unused DMA callbacks to NULL */
2199 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2200 hi2c->hdmatx->XferAbortCallback = NULL;
2201
2202 /* Enable the DMA channel */
2203 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2204 hi2c->XferSize);
2205 }
2206 else
2207 {
2208 /* Update I2C state */
2209 hi2c->State = HAL_I2C_STATE_LISTEN;
2210 hi2c->Mode = HAL_I2C_MODE_NONE;
2211
2212 /* Update I2C error code */
2213 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2214
2215 /* Process Unlocked */
2216 __HAL_UNLOCK(hi2c);
2217
2218 return HAL_ERROR;
2219 }
2220
2221 if (dmaxferstatus == HAL_OK)
2222 {
2223 /* Enable Address Acknowledge */
2224 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2225
2226 /* Process Unlocked */
2227 __HAL_UNLOCK(hi2c);
2228
2229 /* Note : The I2C interrupts must be enabled after unlocking current process
2230 to avoid the risk of I2C interrupt handle execution before current
2231 process unlock */
2232 /* Enable ERR, STOP, NACK, ADDR interrupts */
2233 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2234
2235 /* Enable DMA Request */
2236 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2237 }
2238 else
2239 {
2240 /* Update I2C state */
2241 hi2c->State = HAL_I2C_STATE_LISTEN;
2242 hi2c->Mode = HAL_I2C_MODE_NONE;
2243
2244 /* Update I2C error code */
2245 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2246
2247 /* Process Unlocked */
2248 __HAL_UNLOCK(hi2c);
2249
2250 return HAL_ERROR;
2251 }
2252
2253 return HAL_OK;
2254 }
2255 else
2256 {
2257 return HAL_BUSY;
2258 }
2259 }
2260
2261 /**
2262 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2263 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2264 * the configuration information for the specified I2C.
2265 * @param pData Pointer to data buffer
2266 * @param Size Amount of data to be sent
2267 * @retval HAL status
2268 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2269 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2270 {
2271 HAL_StatusTypeDef dmaxferstatus;
2272
2273 if (hi2c->State == HAL_I2C_STATE_READY)
2274 {
2275 if ((pData == NULL) || (Size == 0U))
2276 {
2277 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2278 return HAL_ERROR;
2279 }
2280 /* Process Locked */
2281 __HAL_LOCK(hi2c);
2282
2283 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2284 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2285 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2286
2287 /* Prepare transfer parameters */
2288 hi2c->pBuffPtr = pData;
2289 hi2c->XferCount = Size;
2290 hi2c->XferSize = hi2c->XferCount;
2291 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2292 hi2c->XferISR = I2C_Slave_ISR_DMA;
2293
2294 if (hi2c->hdmarx != NULL)
2295 {
2296 /* Set the I2C DMA transfer complete callback */
2297 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2298
2299 /* Set the DMA error callback */
2300 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2301
2302 /* Set the unused DMA callbacks to NULL */
2303 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2304 hi2c->hdmarx->XferAbortCallback = NULL;
2305
2306 /* Enable the DMA channel */
2307 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2308 hi2c->XferSize);
2309 }
2310 else
2311 {
2312 /* Update I2C state */
2313 hi2c->State = HAL_I2C_STATE_LISTEN;
2314 hi2c->Mode = HAL_I2C_MODE_NONE;
2315
2316 /* Update I2C error code */
2317 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2318
2319 /* Process Unlocked */
2320 __HAL_UNLOCK(hi2c);
2321
2322 return HAL_ERROR;
2323 }
2324
2325 if (dmaxferstatus == HAL_OK)
2326 {
2327 /* Enable Address Acknowledge */
2328 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2329
2330 /* Process Unlocked */
2331 __HAL_UNLOCK(hi2c);
2332
2333 /* Note : The I2C interrupts must be enabled after unlocking current process
2334 to avoid the risk of I2C interrupt handle execution before current
2335 process unlock */
2336 /* Enable ERR, STOP, NACK, ADDR interrupts */
2337 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2338
2339 /* Enable DMA Request */
2340 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2341 }
2342 else
2343 {
2344 /* Update I2C state */
2345 hi2c->State = HAL_I2C_STATE_LISTEN;
2346 hi2c->Mode = HAL_I2C_MODE_NONE;
2347
2348 /* Update I2C error code */
2349 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2350
2351 /* Process Unlocked */
2352 __HAL_UNLOCK(hi2c);
2353
2354 return HAL_ERROR;
2355 }
2356
2357 return HAL_OK;
2358 }
2359 else
2360 {
2361 return HAL_BUSY;
2362 }
2363 }
2364 /**
2365 * @brief Write an amount of data in blocking mode to a specific memory address
2366 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2367 * the configuration information for the specified I2C.
2368 * @param DevAddress Target device address: The device 7 bits address value
2369 * in datasheet must be shifted to the left before calling the interface
2370 * @param MemAddress Internal memory address
2371 * @param MemAddSize Size of internal memory address
2372 * @param pData Pointer to data buffer
2373 * @param Size Amount of data to be sent
2374 * @param Timeout Timeout duration
2375 * @retval HAL status
2376 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2377 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2378 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2379 {
2380 uint32_t tickstart;
2381
2382 /* Check the parameters */
2383 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2384
2385 if (hi2c->State == HAL_I2C_STATE_READY)
2386 {
2387 if ((pData == NULL) || (Size == 0U))
2388 {
2389 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2390 return HAL_ERROR;
2391 }
2392
2393 /* Process Locked */
2394 __HAL_LOCK(hi2c);
2395
2396 /* Init tickstart for timeout management*/
2397 tickstart = HAL_GetTick();
2398
2399 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2400 {
2401 return HAL_ERROR;
2402 }
2403
2404 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2405 hi2c->Mode = HAL_I2C_MODE_MEM;
2406 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2407
2408 /* Prepare transfer parameters */
2409 hi2c->pBuffPtr = pData;
2410 hi2c->XferCount = Size;
2411 hi2c->XferISR = NULL;
2412
2413 /* Send Slave Address and Memory Address */
2414 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2415 {
2416 /* Process Unlocked */
2417 __HAL_UNLOCK(hi2c);
2418 return HAL_ERROR;
2419 }
2420
2421 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2422 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2423 {
2424 hi2c->XferSize = MAX_NBYTE_SIZE;
2425 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2426 }
2427 else
2428 {
2429 hi2c->XferSize = hi2c->XferCount;
2430 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2431 }
2432
2433 do
2434 {
2435 /* Wait until TXIS flag is set */
2436 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2437 {
2438 return HAL_ERROR;
2439 }
2440
2441 /* Write data to TXDR */
2442 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2443
2444 /* Increment Buffer pointer */
2445 hi2c->pBuffPtr++;
2446
2447 hi2c->XferCount--;
2448 hi2c->XferSize--;
2449
2450 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2451 {
2452 /* Wait until TCR flag is set */
2453 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2454 {
2455 return HAL_ERROR;
2456 }
2457
2458 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2459 {
2460 hi2c->XferSize = MAX_NBYTE_SIZE;
2461 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2462 I2C_NO_STARTSTOP);
2463 }
2464 else
2465 {
2466 hi2c->XferSize = hi2c->XferCount;
2467 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2468 I2C_NO_STARTSTOP);
2469 }
2470 }
2471
2472 } while (hi2c->XferCount > 0U);
2473
2474 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2475 /* Wait until STOPF flag is reset */
2476 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2477 {
2478 return HAL_ERROR;
2479 }
2480
2481 /* Clear STOP Flag */
2482 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2483
2484 /* Clear Configuration Register 2 */
2485 I2C_RESET_CR2(hi2c);
2486
2487 hi2c->State = HAL_I2C_STATE_READY;
2488 hi2c->Mode = HAL_I2C_MODE_NONE;
2489
2490 /* Process Unlocked */
2491 __HAL_UNLOCK(hi2c);
2492
2493 return HAL_OK;
2494 }
2495 else
2496 {
2497 return HAL_BUSY;
2498 }
2499 }
2500
2501 /**
2502 * @brief Read an amount of data in blocking mode from a specific memory address
2503 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2504 * the configuration information for the specified I2C.
2505 * @param DevAddress Target device address: The device 7 bits address value
2506 * in datasheet must be shifted to the left before calling the interface
2507 * @param MemAddress Internal memory address
2508 * @param MemAddSize Size of internal memory address
2509 * @param pData Pointer to data buffer
2510 * @param Size Amount of data to be sent
2511 * @param Timeout Timeout duration
2512 * @retval HAL status
2513 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2514 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2515 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2516 {
2517 uint32_t tickstart;
2518
2519 /* Check the parameters */
2520 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2521
2522 if (hi2c->State == HAL_I2C_STATE_READY)
2523 {
2524 if ((pData == NULL) || (Size == 0U))
2525 {
2526 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2527 return HAL_ERROR;
2528 }
2529
2530 /* Process Locked */
2531 __HAL_LOCK(hi2c);
2532
2533 /* Init tickstart for timeout management*/
2534 tickstart = HAL_GetTick();
2535
2536 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2537 {
2538 return HAL_ERROR;
2539 }
2540
2541 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2542 hi2c->Mode = HAL_I2C_MODE_MEM;
2543 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2544
2545 /* Prepare transfer parameters */
2546 hi2c->pBuffPtr = pData;
2547 hi2c->XferCount = Size;
2548 hi2c->XferISR = NULL;
2549
2550 /* Send Slave Address and Memory Address */
2551 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2552 {
2553 /* Process Unlocked */
2554 __HAL_UNLOCK(hi2c);
2555 return HAL_ERROR;
2556 }
2557
2558 /* Send Slave Address */
2559 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2560 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2561 {
2562 hi2c->XferSize = MAX_NBYTE_SIZE;
2563 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2564 I2C_GENERATE_START_READ);
2565 }
2566 else
2567 {
2568 hi2c->XferSize = hi2c->XferCount;
2569 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2570 I2C_GENERATE_START_READ);
2571 }
2572
2573 do
2574 {
2575 /* Wait until RXNE flag is set */
2576 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2577 {
2578 return HAL_ERROR;
2579 }
2580
2581 /* Read data from RXDR */
2582 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2583
2584 /* Increment Buffer pointer */
2585 hi2c->pBuffPtr++;
2586
2587 hi2c->XferSize--;
2588 hi2c->XferCount--;
2589
2590 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2591 {
2592 /* Wait until TCR flag is set */
2593 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2594 {
2595 return HAL_ERROR;
2596 }
2597
2598 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2599 {
2600 hi2c->XferSize = MAX_NBYTE_SIZE;
2601 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2602 I2C_NO_STARTSTOP);
2603 }
2604 else
2605 {
2606 hi2c->XferSize = hi2c->XferCount;
2607 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2608 I2C_NO_STARTSTOP);
2609 }
2610 }
2611 } while (hi2c->XferCount > 0U);
2612
2613 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2614 /* Wait until STOPF flag is reset */
2615 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2616 {
2617 return HAL_ERROR;
2618 }
2619
2620 /* Clear STOP Flag */
2621 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2622
2623 /* Clear Configuration Register 2 */
2624 I2C_RESET_CR2(hi2c);
2625
2626 hi2c->State = HAL_I2C_STATE_READY;
2627 hi2c->Mode = HAL_I2C_MODE_NONE;
2628
2629 /* Process Unlocked */
2630 __HAL_UNLOCK(hi2c);
2631
2632 return HAL_OK;
2633 }
2634 else
2635 {
2636 return HAL_BUSY;
2637 }
2638 }
2639 /**
2640 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2641 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2642 * the configuration information for the specified I2C.
2643 * @param DevAddress Target device address: The device 7 bits address value
2644 * in datasheet must be shifted to the left before calling the interface
2645 * @param MemAddress Internal memory address
2646 * @param MemAddSize Size of internal memory address
2647 * @param pData Pointer to data buffer
2648 * @param Size Amount of data to be sent
2649 * @retval HAL status
2650 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2651 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2652 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2653 {
2654 /* Check the parameters */
2655 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2656
2657 if (hi2c->State == HAL_I2C_STATE_READY)
2658 {
2659 if ((pData == NULL) || (Size == 0U))
2660 {
2661 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2662 return HAL_ERROR;
2663 }
2664
2665 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2666 {
2667 return HAL_BUSY;
2668 }
2669
2670 /* Process Locked */
2671 __HAL_LOCK(hi2c);
2672
2673 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2674 hi2c->Mode = HAL_I2C_MODE_MEM;
2675 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2676
2677 /* Prepare transfer parameters */
2678 hi2c->pBuffPtr = pData;
2679 hi2c->XferCount = Size;
2680 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2681 hi2c->XferISR = I2C_Mem_ISR_IT;
2682 hi2c->Devaddress = DevAddress;
2683
2684 /* If Memory address size is 8Bit */
2685 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2686 {
2687 /* Prefetch Memory Address */
2688 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2689
2690 /* Reset Memaddress content */
2691 hi2c->Memaddress = 0xFFFFFFFFU;
2692 }
2693 /* If Memory address size is 16Bit */
2694 else
2695 {
2696 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2697 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2698
2699 /* Prepare Memaddress buffer for LSB part */
2700 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2701 }
2702 /* Send Slave Address and Memory Address */
2703 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2704
2705 /* Process Unlocked */
2706 __HAL_UNLOCK(hi2c);
2707
2708 /* Note : The I2C interrupts must be enabled after unlocking current process
2709 to avoid the risk of I2C interrupt handle execution before current
2710 process unlock */
2711
2712 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2713 /* possible to enable all of these */
2714 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2715 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2716 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2717
2718 return HAL_OK;
2719 }
2720 else
2721 {
2722 return HAL_BUSY;
2723 }
2724 }
2725
2726 /**
2727 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2728 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2729 * the configuration information for the specified I2C.
2730 * @param DevAddress Target device address: The device 7 bits address value
2731 * in datasheet must be shifted to the left before calling the interface
2732 * @param MemAddress Internal memory address
2733 * @param MemAddSize Size of internal memory address
2734 * @param pData Pointer to data buffer
2735 * @param Size Amount of data to be sent
2736 * @retval HAL status
2737 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2738 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2739 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2740 {
2741 /* Check the parameters */
2742 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2743
2744 if (hi2c->State == HAL_I2C_STATE_READY)
2745 {
2746 if ((pData == NULL) || (Size == 0U))
2747 {
2748 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2749 return HAL_ERROR;
2750 }
2751
2752 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2753 {
2754 return HAL_BUSY;
2755 }
2756
2757 /* Process Locked */
2758 __HAL_LOCK(hi2c);
2759
2760 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2761 hi2c->Mode = HAL_I2C_MODE_MEM;
2762 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2763
2764 /* Prepare transfer parameters */
2765 hi2c->pBuffPtr = pData;
2766 hi2c->XferCount = Size;
2767 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2768 hi2c->XferISR = I2C_Mem_ISR_IT;
2769 hi2c->Devaddress = DevAddress;
2770
2771 /* If Memory address size is 8Bit */
2772 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2773 {
2774 /* Prefetch Memory Address */
2775 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2776
2777 /* Reset Memaddress content */
2778 hi2c->Memaddress = 0xFFFFFFFFU;
2779 }
2780 /* If Memory address size is 16Bit */
2781 else
2782 {
2783 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2784 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2785
2786 /* Prepare Memaddress buffer for LSB part */
2787 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2788 }
2789 /* Send Slave Address and Memory Address */
2790 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
2791
2792 /* Process Unlocked */
2793 __HAL_UNLOCK(hi2c);
2794
2795 /* Note : The I2C interrupts must be enabled after unlocking current process
2796 to avoid the risk of I2C interrupt handle execution before current
2797 process unlock */
2798
2799 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2800 /* possible to enable all of these */
2801 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2802 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2803 I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
2804
2805 return HAL_OK;
2806 }
2807 else
2808 {
2809 return HAL_BUSY;
2810 }
2811 }
2812 /**
2813 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2814 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2815 * the configuration information for the specified I2C.
2816 * @param DevAddress Target device address: The device 7 bits address value
2817 * in datasheet must be shifted to the left before calling the interface
2818 * @param MemAddress Internal memory address
2819 * @param MemAddSize Size of internal memory address
2820 * @param pData Pointer to data buffer
2821 * @param Size Amount of data to be sent
2822 * @retval HAL status
2823 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2824 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2825 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2826 {
2827 HAL_StatusTypeDef dmaxferstatus;
2828
2829 /* Check the parameters */
2830 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2831
2832 if (hi2c->State == HAL_I2C_STATE_READY)
2833 {
2834 if ((pData == NULL) || (Size == 0U))
2835 {
2836 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2837 return HAL_ERROR;
2838 }
2839
2840 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2841 {
2842 return HAL_BUSY;
2843 }
2844
2845 /* Process Locked */
2846 __HAL_LOCK(hi2c);
2847
2848 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2849 hi2c->Mode = HAL_I2C_MODE_MEM;
2850 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2851
2852 /* Prepare transfer parameters */
2853 hi2c->pBuffPtr = pData;
2854 hi2c->XferCount = Size;
2855 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2856 hi2c->XferISR = I2C_Mem_ISR_DMA;
2857 hi2c->Devaddress = DevAddress;
2858
2859 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2860 {
2861 hi2c->XferSize = MAX_NBYTE_SIZE;
2862 }
2863 else
2864 {
2865 hi2c->XferSize = hi2c->XferCount;
2866 }
2867
2868 /* If Memory address size is 8Bit */
2869 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2870 {
2871 /* Prefetch Memory Address */
2872 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2873
2874 /* Reset Memaddress content */
2875 hi2c->Memaddress = 0xFFFFFFFFU;
2876 }
2877 /* If Memory address size is 16Bit */
2878 else
2879 {
2880 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2881 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2882
2883 /* Prepare Memaddress buffer for LSB part */
2884 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2885 }
2886
2887 if (hi2c->hdmatx != NULL)
2888 {
2889 /* Set the I2C DMA transfer complete callback */
2890 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2891
2892 /* Set the DMA error callback */
2893 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2894
2895 /* Set the unused DMA callbacks to NULL */
2896 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2897 hi2c->hdmatx->XferAbortCallback = NULL;
2898
2899 /* Enable the DMA channel */
2900 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2901 hi2c->XferSize);
2902 }
2903 else
2904 {
2905 /* Update I2C state */
2906 hi2c->State = HAL_I2C_STATE_READY;
2907 hi2c->Mode = HAL_I2C_MODE_NONE;
2908
2909 /* Update I2C error code */
2910 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2911
2912 /* Process Unlocked */
2913 __HAL_UNLOCK(hi2c);
2914
2915 return HAL_ERROR;
2916 }
2917
2918 if (dmaxferstatus == HAL_OK)
2919 {
2920 /* Send Slave Address and Memory Address */
2921 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2922
2923 /* Process Unlocked */
2924 __HAL_UNLOCK(hi2c);
2925
2926 /* Note : The I2C interrupts must be enabled after unlocking current process
2927 to avoid the risk of I2C interrupt handle execution before current
2928 process unlock */
2929 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2930 /* possible to enable all of these */
2931 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2932 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2933 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2934 }
2935 else
2936 {
2937 /* Update I2C state */
2938 hi2c->State = HAL_I2C_STATE_READY;
2939 hi2c->Mode = HAL_I2C_MODE_NONE;
2940
2941 /* Update I2C error code */
2942 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2943
2944 /* Process Unlocked */
2945 __HAL_UNLOCK(hi2c);
2946
2947 return HAL_ERROR;
2948 }
2949
2950 return HAL_OK;
2951 }
2952 else
2953 {
2954 return HAL_BUSY;
2955 }
2956 }
2957
2958 /**
2959 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
2960 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2961 * the configuration information for the specified I2C.
2962 * @param DevAddress Target device address: The device 7 bits address value
2963 * in datasheet must be shifted to the left before calling the interface
2964 * @param MemAddress Internal memory address
2965 * @param MemAddSize Size of internal memory address
2966 * @param pData Pointer to data buffer
2967 * @param Size Amount of data to be read
2968 * @retval HAL status
2969 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2970 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2971 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2972 {
2973 HAL_StatusTypeDef dmaxferstatus;
2974
2975 /* Check the parameters */
2976 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2977
2978 if (hi2c->State == HAL_I2C_STATE_READY)
2979 {
2980 if ((pData == NULL) || (Size == 0U))
2981 {
2982 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2983 return HAL_ERROR;
2984 }
2985
2986 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2987 {
2988 return HAL_BUSY;
2989 }
2990
2991 /* Process Locked */
2992 __HAL_LOCK(hi2c);
2993
2994 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2995 hi2c->Mode = HAL_I2C_MODE_MEM;
2996 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2997
2998 /* Prepare transfer parameters */
2999 hi2c->pBuffPtr = pData;
3000 hi2c->XferCount = Size;
3001 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3002 hi2c->XferISR = I2C_Mem_ISR_DMA;
3003 hi2c->Devaddress = DevAddress;
3004
3005 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3006 {
3007 hi2c->XferSize = MAX_NBYTE_SIZE;
3008 }
3009 else
3010 {
3011 hi2c->XferSize = hi2c->XferCount;
3012 }
3013
3014 /* If Memory address size is 8Bit */
3015 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3016 {
3017 /* Prefetch Memory Address */
3018 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3019
3020 /* Reset Memaddress content */
3021 hi2c->Memaddress = 0xFFFFFFFFU;
3022 }
3023 /* If Memory address size is 16Bit */
3024 else
3025 {
3026 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3027 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3028
3029 /* Prepare Memaddress buffer for LSB part */
3030 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3031 }
3032
3033 if (hi2c->hdmarx != NULL)
3034 {
3035 /* Set the I2C DMA transfer complete callback */
3036 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3037
3038 /* Set the DMA error callback */
3039 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3040
3041 /* Set the unused DMA callbacks to NULL */
3042 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3043 hi2c->hdmarx->XferAbortCallback = NULL;
3044
3045 /* Enable the DMA channel */
3046 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3047 hi2c->XferSize);
3048 }
3049 else
3050 {
3051 /* Update I2C state */
3052 hi2c->State = HAL_I2C_STATE_READY;
3053 hi2c->Mode = HAL_I2C_MODE_NONE;
3054
3055 /* Update I2C error code */
3056 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3057
3058 /* Process Unlocked */
3059 __HAL_UNLOCK(hi2c);
3060
3061 return HAL_ERROR;
3062 }
3063
3064 if (dmaxferstatus == HAL_OK)
3065 {
3066 /* Send Slave Address and Memory Address */
3067 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3068
3069 /* Process Unlocked */
3070 __HAL_UNLOCK(hi2c);
3071
3072 /* Note : The I2C interrupts must be enabled after unlocking current process
3073 to avoid the risk of I2C interrupt handle execution before current
3074 process unlock */
3075 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3076 /* possible to enable all of these */
3077 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3078 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3079 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3080 }
3081 else
3082 {
3083 /* Update I2C state */
3084 hi2c->State = HAL_I2C_STATE_READY;
3085 hi2c->Mode = HAL_I2C_MODE_NONE;
3086
3087 /* Update I2C error code */
3088 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3089
3090 /* Process Unlocked */
3091 __HAL_UNLOCK(hi2c);
3092
3093 return HAL_ERROR;
3094 }
3095
3096 return HAL_OK;
3097 }
3098 else
3099 {
3100 return HAL_BUSY;
3101 }
3102 }
3103
3104 /**
3105 * @brief Checks if target device is ready for communication.
3106 * @note This function is used with Memory devices
3107 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3108 * the configuration information for the specified I2C.
3109 * @param DevAddress Target device address: The device 7 bits address value
3110 * in datasheet must be shifted to the left before calling the interface
3111 * @param Trials Number of trials
3112 * @param Timeout Timeout duration
3113 * @retval HAL status
3114 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3115 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3116 uint32_t Timeout)
3117 {
3118 uint32_t tickstart;
3119
3120 __IO uint32_t I2C_Trials = 0UL;
3121
3122 FlagStatus tmp1;
3123 FlagStatus tmp2;
3124
3125 if (hi2c->State == HAL_I2C_STATE_READY)
3126 {
3127 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3128 {
3129 return HAL_BUSY;
3130 }
3131
3132 /* Process Locked */
3133 __HAL_LOCK(hi2c);
3134
3135 hi2c->State = HAL_I2C_STATE_BUSY;
3136 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3137
3138 do
3139 {
3140 /* Generate Start */
3141 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3142
3143 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3144 /* Wait until STOPF flag is set or a NACK flag is set*/
3145 tickstart = HAL_GetTick();
3146
3147 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3148 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3149
3150 while ((tmp1 == RESET) && (tmp2 == RESET))
3151 {
3152 if (Timeout != HAL_MAX_DELAY)
3153 {
3154 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3155 {
3156 /* Update I2C state */
3157 hi2c->State = HAL_I2C_STATE_READY;
3158
3159 /* Update I2C error code */
3160 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3161
3162 /* Process Unlocked */
3163 __HAL_UNLOCK(hi2c);
3164
3165 return HAL_ERROR;
3166 }
3167 }
3168
3169 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3170 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3171 }
3172
3173 /* Check if the NACKF flag has not been set */
3174 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3175 {
3176 /* Wait until STOPF flag is reset */
3177 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3178 {
3179 return HAL_ERROR;
3180 }
3181
3182 /* Clear STOP Flag */
3183 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3184
3185 /* Device is ready */
3186 hi2c->State = HAL_I2C_STATE_READY;
3187
3188 /* Process Unlocked */
3189 __HAL_UNLOCK(hi2c);
3190
3191 return HAL_OK;
3192 }
3193 else
3194 {
3195 /* Wait until STOPF flag is reset */
3196 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3197 {
3198 return HAL_ERROR;
3199 }
3200
3201 /* Clear NACK Flag */
3202 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3203
3204 /* Clear STOP Flag, auto generated with autoend*/
3205 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3206 }
3207
3208 /* Check if the maximum allowed number of trials has been reached */
3209 if (I2C_Trials == Trials)
3210 {
3211 /* Generate Stop */
3212 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3213
3214 /* Wait until STOPF flag is reset */
3215 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3216 {
3217 return HAL_ERROR;
3218 }
3219
3220 /* Clear STOP Flag */
3221 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3222 }
3223
3224 /* Increment Trials */
3225 I2C_Trials++;
3226 } while (I2C_Trials < Trials);
3227
3228 /* Update I2C state */
3229 hi2c->State = HAL_I2C_STATE_READY;
3230
3231 /* Update I2C error code */
3232 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3233
3234 /* Process Unlocked */
3235 __HAL_UNLOCK(hi2c);
3236
3237 return HAL_ERROR;
3238 }
3239 else
3240 {
3241 return HAL_BUSY;
3242 }
3243 }
3244
3245 /**
3246 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3247 * @note This interface allow to manage repeated start condition when a direction change during transfer
3248 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3249 * the configuration information for the specified I2C.
3250 * @param DevAddress Target device address: The device 7 bits address value
3251 * in datasheet must be shifted to the left before calling the interface
3252 * @param pData Pointer to data buffer
3253 * @param Size Amount of data to be sent
3254 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3255 * @retval HAL status
3256 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3257 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3258 uint16_t Size, uint32_t XferOptions)
3259 {
3260 uint32_t xfermode;
3261 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3262
3263 /* Check the parameters */
3264 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3265
3266 if (hi2c->State == HAL_I2C_STATE_READY)
3267 {
3268 /* Process Locked */
3269 __HAL_LOCK(hi2c);
3270
3271 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3272 hi2c->Mode = HAL_I2C_MODE_MASTER;
3273 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3274
3275 /* Prepare transfer parameters */
3276 hi2c->pBuffPtr = pData;
3277 hi2c->XferCount = Size;
3278 hi2c->XferOptions = XferOptions;
3279 hi2c->XferISR = I2C_Master_ISR_IT;
3280
3281 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3282 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3283 {
3284 hi2c->XferSize = MAX_NBYTE_SIZE;
3285 xfermode = I2C_RELOAD_MODE;
3286 }
3287 else
3288 {
3289 hi2c->XferSize = hi2c->XferCount;
3290 xfermode = hi2c->XferOptions;
3291 }
3292
3293 /* If transfer direction not change and there is no request to start another frame,
3294 do not generate Restart Condition */
3295 /* Mean Previous state is same as current state */
3296 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3297 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3298 {
3299 xferrequest = I2C_NO_STARTSTOP;
3300 }
3301 else
3302 {
3303 /* Convert OTHER_xxx XferOptions if any */
3304 I2C_ConvertOtherXferOptions(hi2c);
3305
3306 /* Update xfermode accordingly if no reload is necessary */
3307 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3308 {
3309 xfermode = hi2c->XferOptions;
3310 }
3311 }
3312
3313 /* Send Slave Address and set NBYTES to write */
3314 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3315
3316 /* Process Unlocked */
3317 __HAL_UNLOCK(hi2c);
3318
3319 /* Note : The I2C interrupts must be enabled after unlocking current process
3320 to avoid the risk of I2C interrupt handle execution before current
3321 process unlock */
3322 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3323 /* possible to enable all of these */
3324 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3325 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3326 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3327
3328 return HAL_OK;
3329 }
3330 else
3331 {
3332 return HAL_BUSY;
3333 }
3334 }
3335
3336 /**
3337 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3338 * @note This interface allow to manage repeated start condition when a direction change during transfer
3339 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3340 * the configuration information for the specified I2C.
3341 * @param DevAddress Target device address: The device 7 bits address value
3342 * in datasheet must be shifted to the left before calling the interface
3343 * @param pData Pointer to data buffer
3344 * @param Size Amount of data to be sent
3345 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3346 * @retval HAL status
3347 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3348 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3349 uint16_t Size, uint32_t XferOptions)
3350 {
3351 uint32_t xfermode;
3352 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3353 HAL_StatusTypeDef dmaxferstatus;
3354
3355 /* Check the parameters */
3356 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3357
3358 if (hi2c->State == HAL_I2C_STATE_READY)
3359 {
3360 /* Process Locked */
3361 __HAL_LOCK(hi2c);
3362
3363 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3364 hi2c->Mode = HAL_I2C_MODE_MASTER;
3365 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3366
3367 /* Prepare transfer parameters */
3368 hi2c->pBuffPtr = pData;
3369 hi2c->XferCount = Size;
3370 hi2c->XferOptions = XferOptions;
3371 hi2c->XferISR = I2C_Master_ISR_DMA;
3372
3373 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3374 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3375 {
3376 hi2c->XferSize = MAX_NBYTE_SIZE;
3377 xfermode = I2C_RELOAD_MODE;
3378 }
3379 else
3380 {
3381 hi2c->XferSize = hi2c->XferCount;
3382 xfermode = hi2c->XferOptions;
3383 }
3384
3385 /* If transfer direction not change and there is no request to start another frame,
3386 do not generate Restart Condition */
3387 /* Mean Previous state is same as current state */
3388 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3389 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3390 {
3391 xferrequest = I2C_NO_STARTSTOP;
3392 }
3393 else
3394 {
3395 /* Convert OTHER_xxx XferOptions if any */
3396 I2C_ConvertOtherXferOptions(hi2c);
3397
3398 /* Update xfermode accordingly if no reload is necessary */
3399 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3400 {
3401 xfermode = hi2c->XferOptions;
3402 }
3403 }
3404
3405 if (hi2c->XferSize > 0U)
3406 {
3407 if (hi2c->hdmatx != NULL)
3408 {
3409 /* Set the I2C DMA transfer complete callback */
3410 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3411
3412 /* Set the DMA error callback */
3413 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3414
3415 /* Set the unused DMA callbacks to NULL */
3416 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3417 hi2c->hdmatx->XferAbortCallback = NULL;
3418
3419 /* Enable the DMA channel */
3420 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3421 hi2c->XferSize);
3422 }
3423 else
3424 {
3425 /* Update I2C state */
3426 hi2c->State = HAL_I2C_STATE_READY;
3427 hi2c->Mode = HAL_I2C_MODE_NONE;
3428
3429 /* Update I2C error code */
3430 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3431
3432 /* Process Unlocked */
3433 __HAL_UNLOCK(hi2c);
3434
3435 return HAL_ERROR;
3436 }
3437
3438 if (dmaxferstatus == HAL_OK)
3439 {
3440 /* Send Slave Address and set NBYTES to write */
3441 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3442
3443 /* Update XferCount value */
3444 hi2c->XferCount -= hi2c->XferSize;
3445
3446 /* Process Unlocked */
3447 __HAL_UNLOCK(hi2c);
3448
3449 /* Note : The I2C interrupts must be enabled after unlocking current process
3450 to avoid the risk of I2C interrupt handle execution before current
3451 process unlock */
3452 /* Enable ERR and NACK interrupts */
3453 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3454
3455 /* Enable DMA Request */
3456 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3457 }
3458 else
3459 {
3460 /* Update I2C state */
3461 hi2c->State = HAL_I2C_STATE_READY;
3462 hi2c->Mode = HAL_I2C_MODE_NONE;
3463
3464 /* Update I2C error code */
3465 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3466
3467 /* Process Unlocked */
3468 __HAL_UNLOCK(hi2c);
3469
3470 return HAL_ERROR;
3471 }
3472 }
3473 else
3474 {
3475 /* Update Transfer ISR function pointer */
3476 hi2c->XferISR = I2C_Master_ISR_IT;
3477
3478 /* Send Slave Address */
3479 /* Set NBYTES to write and generate START condition */
3480 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3481 I2C_GENERATE_START_WRITE);
3482
3483 /* Process Unlocked */
3484 __HAL_UNLOCK(hi2c);
3485
3486 /* Note : The I2C interrupts must be enabled after unlocking current process
3487 to avoid the risk of I2C interrupt handle execution before current
3488 process unlock */
3489 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3490 /* possible to enable all of these */
3491 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3492 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3493 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3494 }
3495
3496 return HAL_OK;
3497 }
3498 else
3499 {
3500 return HAL_BUSY;
3501 }
3502 }
3503
3504 /**
3505 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3506 * @note This interface allow to manage repeated start condition when a direction change during transfer
3507 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3508 * the configuration information for the specified I2C.
3509 * @param DevAddress Target device address: The device 7 bits address value
3510 * in datasheet must be shifted to the left before calling the interface
3511 * @param pData Pointer to data buffer
3512 * @param Size Amount of data to be sent
3513 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3514 * @retval HAL status
3515 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3516 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3517 uint16_t Size, uint32_t XferOptions)
3518 {
3519 uint32_t xfermode;
3520 uint32_t xferrequest = I2C_GENERATE_START_READ;
3521
3522 /* Check the parameters */
3523 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3524
3525 if (hi2c->State == HAL_I2C_STATE_READY)
3526 {
3527 /* Process Locked */
3528 __HAL_LOCK(hi2c);
3529
3530 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3531 hi2c->Mode = HAL_I2C_MODE_MASTER;
3532 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3533
3534 /* Prepare transfer parameters */
3535 hi2c->pBuffPtr = pData;
3536 hi2c->XferCount = Size;
3537 hi2c->XferOptions = XferOptions;
3538 hi2c->XferISR = I2C_Master_ISR_IT;
3539
3540 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3541 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3542 {
3543 hi2c->XferSize = MAX_NBYTE_SIZE;
3544 xfermode = I2C_RELOAD_MODE;
3545 }
3546 else
3547 {
3548 hi2c->XferSize = hi2c->XferCount;
3549 xfermode = hi2c->XferOptions;
3550 }
3551
3552 /* If transfer direction not change and there is no request to start another frame,
3553 do not generate Restart Condition */
3554 /* Mean Previous state is same as current state */
3555 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3556 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3557 {
3558 xferrequest = I2C_NO_STARTSTOP;
3559 }
3560 else
3561 {
3562 /* Convert OTHER_xxx XferOptions if any */
3563 I2C_ConvertOtherXferOptions(hi2c);
3564
3565 /* Update xfermode accordingly if no reload is necessary */
3566 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3567 {
3568 xfermode = hi2c->XferOptions;
3569 }
3570 }
3571
3572 /* Send Slave Address and set NBYTES to read */
3573 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3574
3575 /* Process Unlocked */
3576 __HAL_UNLOCK(hi2c);
3577
3578 /* Note : The I2C interrupts must be enabled after unlocking current process
3579 to avoid the risk of I2C interrupt handle execution before current
3580 process unlock */
3581 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3582
3583 return HAL_OK;
3584 }
3585 else
3586 {
3587 return HAL_BUSY;
3588 }
3589 }
3590
3591 /**
3592 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3593 * @note This interface allow to manage repeated start condition when a direction change during transfer
3594 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3595 * the configuration information for the specified I2C.
3596 * @param DevAddress Target device address: The device 7 bits address value
3597 * in datasheet must be shifted to the left before calling the interface
3598 * @param pData Pointer to data buffer
3599 * @param Size Amount of data to be sent
3600 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3601 * @retval HAL status
3602 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3603 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3604 uint16_t Size, uint32_t XferOptions)
3605 {
3606 uint32_t xfermode;
3607 uint32_t xferrequest = I2C_GENERATE_START_READ;
3608 HAL_StatusTypeDef dmaxferstatus;
3609
3610 /* Check the parameters */
3611 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3612
3613 if (hi2c->State == HAL_I2C_STATE_READY)
3614 {
3615 /* Process Locked */
3616 __HAL_LOCK(hi2c);
3617
3618 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3619 hi2c->Mode = HAL_I2C_MODE_MASTER;
3620 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3621
3622 /* Prepare transfer parameters */
3623 hi2c->pBuffPtr = pData;
3624 hi2c->XferCount = Size;
3625 hi2c->XferOptions = XferOptions;
3626 hi2c->XferISR = I2C_Master_ISR_DMA;
3627
3628 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3629 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3630 {
3631 hi2c->XferSize = MAX_NBYTE_SIZE;
3632 xfermode = I2C_RELOAD_MODE;
3633 }
3634 else
3635 {
3636 hi2c->XferSize = hi2c->XferCount;
3637 xfermode = hi2c->XferOptions;
3638 }
3639
3640 /* If transfer direction not change and there is no request to start another frame,
3641 do not generate Restart Condition */
3642 /* Mean Previous state is same as current state */
3643 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3644 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3645 {
3646 xferrequest = I2C_NO_STARTSTOP;
3647 }
3648 else
3649 {
3650 /* Convert OTHER_xxx XferOptions if any */
3651 I2C_ConvertOtherXferOptions(hi2c);
3652
3653 /* Update xfermode accordingly if no reload is necessary */
3654 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3655 {
3656 xfermode = hi2c->XferOptions;
3657 }
3658 }
3659
3660 if (hi2c->XferSize > 0U)
3661 {
3662 if (hi2c->hdmarx != NULL)
3663 {
3664 /* Set the I2C DMA transfer complete callback */
3665 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3666
3667 /* Set the DMA error callback */
3668 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3669
3670 /* Set the unused DMA callbacks to NULL */
3671 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3672 hi2c->hdmarx->XferAbortCallback = NULL;
3673
3674 /* Enable the DMA channel */
3675 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3676 hi2c->XferSize);
3677 }
3678 else
3679 {
3680 /* Update I2C state */
3681 hi2c->State = HAL_I2C_STATE_READY;
3682 hi2c->Mode = HAL_I2C_MODE_NONE;
3683
3684 /* Update I2C error code */
3685 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3686
3687 /* Process Unlocked */
3688 __HAL_UNLOCK(hi2c);
3689
3690 return HAL_ERROR;
3691 }
3692
3693 if (dmaxferstatus == HAL_OK)
3694 {
3695 /* Send Slave Address and set NBYTES to read */
3696 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3697
3698 /* Update XferCount value */
3699 hi2c->XferCount -= hi2c->XferSize;
3700
3701 /* Process Unlocked */
3702 __HAL_UNLOCK(hi2c);
3703
3704 /* Note : The I2C interrupts must be enabled after unlocking current process
3705 to avoid the risk of I2C interrupt handle execution before current
3706 process unlock */
3707 /* Enable ERR and NACK interrupts */
3708 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3709
3710 /* Enable DMA Request */
3711 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3712 }
3713 else
3714 {
3715 /* Update I2C state */
3716 hi2c->State = HAL_I2C_STATE_READY;
3717 hi2c->Mode = HAL_I2C_MODE_NONE;
3718
3719 /* Update I2C error code */
3720 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3721
3722 /* Process Unlocked */
3723 __HAL_UNLOCK(hi2c);
3724
3725 return HAL_ERROR;
3726 }
3727 }
3728 else
3729 {
3730 /* Update Transfer ISR function pointer */
3731 hi2c->XferISR = I2C_Master_ISR_IT;
3732
3733 /* Send Slave Address */
3734 /* Set NBYTES to read and generate START condition */
3735 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3736 I2C_GENERATE_START_READ);
3737
3738 /* Process Unlocked */
3739 __HAL_UNLOCK(hi2c);
3740
3741 /* Note : The I2C interrupts must be enabled after unlocking current process
3742 to avoid the risk of I2C interrupt handle execution before current
3743 process unlock */
3744 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3745 /* possible to enable all of these */
3746 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3747 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3748 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3749 }
3750
3751 return HAL_OK;
3752 }
3753 else
3754 {
3755 return HAL_BUSY;
3756 }
3757 }
3758
3759 /**
3760 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
3761 * @note This interface allow to manage repeated start condition when a direction change during transfer
3762 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3763 * the configuration information for the specified I2C.
3764 * @param pData Pointer to data buffer
3765 * @param Size Amount of data to be sent
3766 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3767 * @retval HAL status
3768 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3769 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3770 uint32_t XferOptions)
3771 {
3772 /* Check the parameters */
3773 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3774
3775 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3776 {
3777 if ((pData == NULL) || (Size == 0U))
3778 {
3779 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3780 return HAL_ERROR;
3781 }
3782
3783 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3784 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3785
3786 /* Process Locked */
3787 __HAL_LOCK(hi2c);
3788
3789 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3790 /* and then toggle the HAL slave RX state to TX state */
3791 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3792 {
3793 /* Disable associated Interrupts */
3794 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3795
3796 /* Abort DMA Xfer if any */
3797 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3798 {
3799 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3800
3801 if (hi2c->hdmarx != NULL)
3802 {
3803 /* Set the I2C DMA Abort callback :
3804 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3805 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3806
3807 /* Abort DMA RX */
3808 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3809 {
3810 /* Call Directly XferAbortCallback function in case of error */
3811 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3812 }
3813 }
3814 }
3815 }
3816
3817 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3818 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3819 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3820
3821 /* Enable Address Acknowledge */
3822 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3823
3824 /* Prepare transfer parameters */
3825 hi2c->pBuffPtr = pData;
3826 hi2c->XferCount = Size;
3827 hi2c->XferSize = hi2c->XferCount;
3828 hi2c->XferOptions = XferOptions;
3829 hi2c->XferISR = I2C_Slave_ISR_IT;
3830
3831 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
3832 {
3833 /* Clear ADDR flag after prepare the transfer parameters */
3834 /* This action will generate an acknowledge to the Master */
3835 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3836 }
3837
3838 /* Process Unlocked */
3839 __HAL_UNLOCK(hi2c);
3840
3841 /* Note : The I2C interrupts must be enabled after unlocking current process
3842 to avoid the risk of I2C interrupt handle execution before current
3843 process unlock */
3844 /* REnable ADDR interrupt */
3845 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
3846
3847 return HAL_OK;
3848 }
3849 else
3850 {
3851 return HAL_ERROR;
3852 }
3853 }
3854
3855 /**
3856 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
3857 * @note This interface allow to manage repeated start condition when a direction change during transfer
3858 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3859 * the configuration information for the specified I2C.
3860 * @param pData Pointer to data buffer
3861 * @param Size Amount of data to be sent
3862 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3863 * @retval HAL status
3864 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3865 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
3866 uint32_t XferOptions)
3867 {
3868 HAL_StatusTypeDef dmaxferstatus;
3869
3870 /* Check the parameters */
3871 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3872
3873 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
3874 {
3875 if ((pData == NULL) || (Size == 0U))
3876 {
3877 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3878 return HAL_ERROR;
3879 }
3880
3881 /* Process Locked */
3882 __HAL_LOCK(hi2c);
3883
3884 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
3885 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
3886
3887 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
3888 /* and then toggle the HAL slave RX state to TX state */
3889 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3890 {
3891 /* Disable associated Interrupts */
3892 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3893
3894 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
3895 {
3896 /* Abort DMA Xfer if any */
3897 if (hi2c->hdmarx != NULL)
3898 {
3899 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
3900
3901 /* Set the I2C DMA Abort callback :
3902 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3903 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
3904
3905 /* Abort DMA RX */
3906 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
3907 {
3908 /* Call Directly XferAbortCallback function in case of error */
3909 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
3910 }
3911 }
3912 }
3913 }
3914 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3915 {
3916 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
3917 {
3918 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
3919
3920 /* Abort DMA Xfer if any */
3921 if (hi2c->hdmatx != NULL)
3922 {
3923 /* Set the I2C DMA Abort callback :
3924 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
3925 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
3926
3927 /* Abort DMA TX */
3928 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
3929 {
3930 /* Call Directly XferAbortCallback function in case of error */
3931 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
3932 }
3933 }
3934 }
3935 }
3936 else
3937 {
3938 /* Nothing to do */
3939 }
3940
3941 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
3942 hi2c->Mode = HAL_I2C_MODE_SLAVE;
3943 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3944
3945 /* Enable Address Acknowledge */
3946 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
3947
3948 /* Prepare transfer parameters */
3949 hi2c->pBuffPtr = pData;
3950 hi2c->XferCount = Size;
3951 hi2c->XferSize = hi2c->XferCount;
3952 hi2c->XferOptions = XferOptions;
3953 hi2c->XferISR = I2C_Slave_ISR_DMA;
3954
3955 if (hi2c->hdmatx != NULL)
3956 {
3957 /* Set the I2C DMA transfer complete callback */
3958 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
3959
3960 /* Set the DMA error callback */
3961 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3962
3963 /* Set the unused DMA callbacks to NULL */
3964 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3965 hi2c->hdmatx->XferAbortCallback = NULL;
3966
3967 /* Enable the DMA channel */
3968 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3969 hi2c->XferSize);
3970 }
3971 else
3972 {
3973 /* Update I2C state */
3974 hi2c->State = HAL_I2C_STATE_LISTEN;
3975 hi2c->Mode = HAL_I2C_MODE_NONE;
3976
3977 /* Update I2C error code */
3978 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3979
3980 /* Process Unlocked */
3981 __HAL_UNLOCK(hi2c);
3982
3983 return HAL_ERROR;
3984 }
3985
3986 if (dmaxferstatus == HAL_OK)
3987 {
3988 /* Update XferCount value */
3989 hi2c->XferCount -= hi2c->XferSize;
3990
3991 /* Reset XferSize */
3992 hi2c->XferSize = 0;
3993 }
3994 else
3995 {
3996 /* Update I2C state */
3997 hi2c->State = HAL_I2C_STATE_LISTEN;
3998 hi2c->Mode = HAL_I2C_MODE_NONE;
3999
4000 /* Update I2C error code */
4001 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4002
4003 /* Process Unlocked */
4004 __HAL_UNLOCK(hi2c);
4005
4006 return HAL_ERROR;
4007 }
4008
4009 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
4010 {
4011 /* Clear ADDR flag after prepare the transfer parameters */
4012 /* This action will generate an acknowledge to the Master */
4013 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4014 }
4015
4016 /* Process Unlocked */
4017 __HAL_UNLOCK(hi2c);
4018
4019 /* Enable DMA Request */
4020 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4021
4022 /* Note : The I2C interrupts must be enabled after unlocking current process
4023 to avoid the risk of I2C interrupt handle execution before current
4024 process unlock */
4025 /* Enable ERR, STOP, NACK, ADDR interrupts */
4026 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4027
4028 return HAL_OK;
4029 }
4030 else
4031 {
4032 return HAL_ERROR;
4033 }
4034 }
4035
4036 /**
4037 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4038 * @note This interface allow to manage repeated start condition when a direction change during transfer
4039 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4040 * the configuration information for the specified I2C.
4041 * @param pData Pointer to data buffer
4042 * @param Size Amount of data to be sent
4043 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4044 * @retval HAL status
4045 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4046 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4047 uint32_t XferOptions)
4048 {
4049 /* Check the parameters */
4050 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4051
4052 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4053 {
4054 if ((pData == NULL) || (Size == 0U))
4055 {
4056 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4057 return HAL_ERROR;
4058 }
4059
4060 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4061 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4062
4063 /* Process Locked */
4064 __HAL_LOCK(hi2c);
4065
4066 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4067 /* and then toggle the HAL slave TX state to RX state */
4068 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4069 {
4070 /* Disable associated Interrupts */
4071 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4072
4073 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4074 {
4075 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4076
4077 /* Abort DMA Xfer if any */
4078 if (hi2c->hdmatx != NULL)
4079 {
4080 /* Set the I2C DMA Abort callback :
4081 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4082 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4083
4084 /* Abort DMA TX */
4085 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4086 {
4087 /* Call Directly XferAbortCallback function in case of error */
4088 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4089 }
4090 }
4091 }
4092 }
4093
4094 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4095 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4096 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4097
4098 /* Enable Address Acknowledge */
4099 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4100
4101 /* Prepare transfer parameters */
4102 hi2c->pBuffPtr = pData;
4103 hi2c->XferCount = Size;
4104 hi2c->XferSize = hi2c->XferCount;
4105 hi2c->XferOptions = XferOptions;
4106 hi2c->XferISR = I2C_Slave_ISR_IT;
4107
4108 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
4109 {
4110 /* Clear ADDR flag after prepare the transfer parameters */
4111 /* This action will generate an acknowledge to the Master */
4112 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4113 }
4114
4115 /* Process Unlocked */
4116 __HAL_UNLOCK(hi2c);
4117
4118 /* Note : The I2C interrupts must be enabled after unlocking current process
4119 to avoid the risk of I2C interrupt handle execution before current
4120 process unlock */
4121 /* REnable ADDR interrupt */
4122 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4123
4124 return HAL_OK;
4125 }
4126 else
4127 {
4128 return HAL_ERROR;
4129 }
4130 }
4131
4132 /**
4133 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4134 * @note This interface allow to manage repeated start condition when a direction change during transfer
4135 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4136 * the configuration information for the specified I2C.
4137 * @param pData Pointer to data buffer
4138 * @param Size Amount of data to be sent
4139 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4140 * @retval HAL status
4141 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4142 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4143 uint32_t XferOptions)
4144 {
4145 HAL_StatusTypeDef dmaxferstatus;
4146
4147 /* Check the parameters */
4148 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4149
4150 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4151 {
4152 if ((pData == NULL) || (Size == 0U))
4153 {
4154 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4155 return HAL_ERROR;
4156 }
4157
4158 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4159 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4160
4161 /* Process Locked */
4162 __HAL_LOCK(hi2c);
4163
4164 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4165 /* and then toggle the HAL slave TX state to RX state */
4166 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4167 {
4168 /* Disable associated Interrupts */
4169 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4170
4171 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4172 {
4173 /* Abort DMA Xfer if any */
4174 if (hi2c->hdmatx != NULL)
4175 {
4176 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4177
4178 /* Set the I2C DMA Abort callback :
4179 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4180 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4181
4182 /* Abort DMA TX */
4183 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4184 {
4185 /* Call Directly XferAbortCallback function in case of error */
4186 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4187 }
4188 }
4189 }
4190 }
4191 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4192 {
4193 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4194 {
4195 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4196
4197 /* Abort DMA Xfer if any */
4198 if (hi2c->hdmarx != NULL)
4199 {
4200 /* Set the I2C DMA Abort callback :
4201 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4202 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4203
4204 /* Abort DMA RX */
4205 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4206 {
4207 /* Call Directly XferAbortCallback function in case of error */
4208 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4209 }
4210 }
4211 }
4212 }
4213 else
4214 {
4215 /* Nothing to do */
4216 }
4217
4218 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4219 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4220 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4221
4222 /* Enable Address Acknowledge */
4223 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4224
4225 /* Prepare transfer parameters */
4226 hi2c->pBuffPtr = pData;
4227 hi2c->XferCount = Size;
4228 hi2c->XferSize = hi2c->XferCount;
4229 hi2c->XferOptions = XferOptions;
4230 hi2c->XferISR = I2C_Slave_ISR_DMA;
4231
4232 if (hi2c->hdmarx != NULL)
4233 {
4234 /* Set the I2C DMA transfer complete callback */
4235 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4236
4237 /* Set the DMA error callback */
4238 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4239
4240 /* Set the unused DMA callbacks to NULL */
4241 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4242 hi2c->hdmarx->XferAbortCallback = NULL;
4243
4244 /* Enable the DMA channel */
4245 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
4246 (uint32_t)pData, hi2c->XferSize);
4247 }
4248 else
4249 {
4250 /* Update I2C state */
4251 hi2c->State = HAL_I2C_STATE_LISTEN;
4252 hi2c->Mode = HAL_I2C_MODE_NONE;
4253
4254 /* Update I2C error code */
4255 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4256
4257 /* Process Unlocked */
4258 __HAL_UNLOCK(hi2c);
4259
4260 return HAL_ERROR;
4261 }
4262
4263 if (dmaxferstatus == HAL_OK)
4264 {
4265 /* Update XferCount value */
4266 hi2c->XferCount -= hi2c->XferSize;
4267
4268 /* Reset XferSize */
4269 hi2c->XferSize = 0;
4270 }
4271 else
4272 {
4273 /* Update I2C state */
4274 hi2c->State = HAL_I2C_STATE_LISTEN;
4275 hi2c->Mode = HAL_I2C_MODE_NONE;
4276
4277 /* Update I2C error code */
4278 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4279
4280 /* Process Unlocked */
4281 __HAL_UNLOCK(hi2c);
4282
4283 return HAL_ERROR;
4284 }
4285
4286 if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
4287 {
4288 /* Clear ADDR flag after prepare the transfer parameters */
4289 /* This action will generate an acknowledge to the Master */
4290 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4291 }
4292
4293 /* Process Unlocked */
4294 __HAL_UNLOCK(hi2c);
4295
4296 /* Enable DMA Request */
4297 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4298
4299 /* Note : The I2C interrupts must be enabled after unlocking current process
4300 to avoid the risk of I2C interrupt handle execution before current
4301 process unlock */
4302 /* REnable ADDR interrupt */
4303 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4304
4305 return HAL_OK;
4306 }
4307 else
4308 {
4309 return HAL_ERROR;
4310 }
4311 }
4312
4313 /**
4314 * @brief Enable the Address listen mode with Interrupt.
4315 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4316 * the configuration information for the specified I2C.
4317 * @retval HAL status
4318 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4319 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4320 {
4321 if (hi2c->State == HAL_I2C_STATE_READY)
4322 {
4323 hi2c->State = HAL_I2C_STATE_LISTEN;
4324 hi2c->XferISR = I2C_Slave_ISR_IT;
4325
4326 /* Enable the Address Match interrupt */
4327 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4328
4329 return HAL_OK;
4330 }
4331 else
4332 {
4333 return HAL_BUSY;
4334 }
4335 }
4336
4337 /**
4338 * @brief Disable the Address listen mode with Interrupt.
4339 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4340 * the configuration information for the specified I2C
4341 * @retval HAL status
4342 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4343 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4344 {
4345 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4346 uint32_t tmp;
4347
4348 /* Disable Address listen mode only if a transfer is not ongoing */
4349 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4350 {
4351 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4352 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4353 hi2c->State = HAL_I2C_STATE_READY;
4354 hi2c->Mode = HAL_I2C_MODE_NONE;
4355 hi2c->XferISR = NULL;
4356
4357 /* Disable the Address Match interrupt */
4358 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4359
4360 return HAL_OK;
4361 }
4362 else
4363 {
4364 return HAL_BUSY;
4365 }
4366 }
4367
4368 /**
4369 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4370 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4371 * the configuration information for the specified I2C.
4372 * @param DevAddress Target device address: The device 7 bits address value
4373 * in datasheet must be shifted to the left before calling the interface
4374 * @retval HAL status
4375 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4376 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4377 {
4378 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4379 {
4380 /* Process Locked */
4381 __HAL_LOCK(hi2c);
4382
4383 /* Disable Interrupts and Store Previous state */
4384 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4385 {
4386 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4387 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4388 }
4389 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4390 {
4391 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4392 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4393 }
4394 else
4395 {
4396 /* Do nothing */
4397 }
4398
4399 /* Set State at HAL_I2C_STATE_ABORT */
4400 hi2c->State = HAL_I2C_STATE_ABORT;
4401
4402 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4403 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4404 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4405
4406 /* Process Unlocked */
4407 __HAL_UNLOCK(hi2c);
4408
4409 /* Note : The I2C interrupts must be enabled after unlocking current process
4410 to avoid the risk of I2C interrupt handle execution before current
4411 process unlock */
4412 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4413
4414 return HAL_OK;
4415 }
4416 else
4417 {
4418 /* Wrong usage of abort function */
4419 /* This function should be used only in case of abort monitored by master device */
4420 return HAL_ERROR;
4421 }
4422 }
4423
4424 /**
4425 * @}
4426 */
4427
4428 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4429 * @{
4430 */
4431
4432 /**
4433 * @brief This function handles I2C event interrupt request.
4434 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4435 * the configuration information for the specified I2C.
4436 * @retval None
4437 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4438 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4439 {
4440 /* Get current IT Flags and IT sources value */
4441 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4442 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4443
4444 /* I2C events treatment -------------------------------------*/
4445 if (hi2c->XferISR != NULL)
4446 {
4447 hi2c->XferISR(hi2c, itflags, itsources);
4448 }
4449 }
4450
4451 /**
4452 * @brief This function handles I2C error interrupt request.
4453 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4454 * the configuration information for the specified I2C.
4455 * @retval None
4456 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4457 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4458 {
4459 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4460 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4461 uint32_t tmperror;
4462
4463 /* I2C Bus error interrupt occurred ------------------------------------*/
4464 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4465 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4466 {
4467 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4468
4469 /* Clear BERR flag */
4470 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4471 }
4472
4473 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4474 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4475 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4476 {
4477 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4478
4479 /* Clear OVR flag */
4480 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4481 }
4482
4483 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4484 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4485 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4486 {
4487 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4488
4489 /* Clear ARLO flag */
4490 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4491 }
4492
4493 /* Store current volatile hi2c->ErrorCode, misra rule */
4494 tmperror = hi2c->ErrorCode;
4495
4496 /* Call the Error Callback in case of Error detected */
4497 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4498 {
4499 I2C_ITError(hi2c, tmperror);
4500 }
4501 }
4502
4503 /**
4504 * @brief Master Tx Transfer completed callback.
4505 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4506 * the configuration information for the specified I2C.
4507 * @retval None
4508 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4509 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4510 {
4511 /* Prevent unused argument(s) compilation warning */
4512 UNUSED(hi2c);
4513
4514 /* NOTE : This function should not be modified, when the callback is needed,
4515 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4516 */
4517 }
4518
4519 /**
4520 * @brief Master Rx Transfer completed callback.
4521 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4522 * the configuration information for the specified I2C.
4523 * @retval None
4524 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4525 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4526 {
4527 /* Prevent unused argument(s) compilation warning */
4528 UNUSED(hi2c);
4529
4530 /* NOTE : This function should not be modified, when the callback is needed,
4531 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
4532 */
4533 }
4534
4535 /** @brief Slave Tx Transfer completed callback.
4536 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4537 * the configuration information for the specified I2C.
4538 * @retval None
4539 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)4540 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
4541 {
4542 /* Prevent unused argument(s) compilation warning */
4543 UNUSED(hi2c);
4544
4545 /* NOTE : This function should not be modified, when the callback is needed,
4546 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
4547 */
4548 }
4549
4550 /**
4551 * @brief Slave Rx Transfer completed callback.
4552 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4553 * the configuration information for the specified I2C.
4554 * @retval None
4555 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)4556 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
4557 {
4558 /* Prevent unused argument(s) compilation warning */
4559 UNUSED(hi2c);
4560
4561 /* NOTE : This function should not be modified, when the callback is needed,
4562 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
4563 */
4564 }
4565
4566 /**
4567 * @brief Slave Address Match callback.
4568 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4569 * the configuration information for the specified I2C.
4570 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
4571 * @param AddrMatchCode Address Match Code
4572 * @retval None
4573 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)4574 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
4575 {
4576 /* Prevent unused argument(s) compilation warning */
4577 UNUSED(hi2c);
4578 UNUSED(TransferDirection);
4579 UNUSED(AddrMatchCode);
4580
4581 /* NOTE : This function should not be modified, when the callback is needed,
4582 the HAL_I2C_AddrCallback() could be implemented in the user file
4583 */
4584 }
4585
4586 /**
4587 * @brief Listen Complete callback.
4588 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4589 * the configuration information for the specified I2C.
4590 * @retval None
4591 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)4592 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
4593 {
4594 /* Prevent unused argument(s) compilation warning */
4595 UNUSED(hi2c);
4596
4597 /* NOTE : This function should not be modified, when the callback is needed,
4598 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
4599 */
4600 }
4601
4602 /**
4603 * @brief Memory Tx Transfer completed callback.
4604 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4605 * the configuration information for the specified I2C.
4606 * @retval None
4607 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)4608 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
4609 {
4610 /* Prevent unused argument(s) compilation warning */
4611 UNUSED(hi2c);
4612
4613 /* NOTE : This function should not be modified, when the callback is needed,
4614 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
4615 */
4616 }
4617
4618 /**
4619 * @brief Memory Rx Transfer completed callback.
4620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4621 * the configuration information for the specified I2C.
4622 * @retval None
4623 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)4624 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
4625 {
4626 /* Prevent unused argument(s) compilation warning */
4627 UNUSED(hi2c);
4628
4629 /* NOTE : This function should not be modified, when the callback is needed,
4630 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
4631 */
4632 }
4633
4634 /**
4635 * @brief I2C error callback.
4636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4637 * the configuration information for the specified I2C.
4638 * @retval None
4639 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)4640 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
4641 {
4642 /* Prevent unused argument(s) compilation warning */
4643 UNUSED(hi2c);
4644
4645 /* NOTE : This function should not be modified, when the callback is needed,
4646 the HAL_I2C_ErrorCallback could be implemented in the user file
4647 */
4648 }
4649
4650 /**
4651 * @brief I2C abort callback.
4652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4653 * the configuration information for the specified I2C.
4654 * @retval None
4655 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)4656 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
4657 {
4658 /* Prevent unused argument(s) compilation warning */
4659 UNUSED(hi2c);
4660
4661 /* NOTE : This function should not be modified, when the callback is needed,
4662 the HAL_I2C_AbortCpltCallback could be implemented in the user file
4663 */
4664 }
4665
4666 /**
4667 * @}
4668 */
4669
4670 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
4671 * @brief Peripheral State, Mode and Error functions
4672 *
4673 @verbatim
4674 ===============================================================================
4675 ##### Peripheral State, Mode and Error functions #####
4676 ===============================================================================
4677 [..]
4678 This subsection permit to get in run-time the status of the peripheral
4679 and the data flow.
4680
4681 @endverbatim
4682 * @{
4683 */
4684
4685 /**
4686 * @brief Return the I2C handle state.
4687 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4688 * the configuration information for the specified I2C.
4689 * @retval HAL state
4690 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)4691 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
4692 {
4693 /* Return I2C handle state */
4694 return hi2c->State;
4695 }
4696
4697 /**
4698 * @brief Returns the I2C Master, Slave, Memory or no mode.
4699 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4700 * the configuration information for I2C module
4701 * @retval HAL mode
4702 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)4703 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
4704 {
4705 return hi2c->Mode;
4706 }
4707
4708 /**
4709 * @brief Return the I2C error code.
4710 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4711 * the configuration information for the specified I2C.
4712 * @retval I2C Error Code
4713 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)4714 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
4715 {
4716 return hi2c->ErrorCode;
4717 }
4718
4719 /**
4720 * @}
4721 */
4722
4723 /**
4724 * @}
4725 */
4726
4727 /** @addtogroup I2C_Private_Functions
4728 * @{
4729 */
4730
4731 /**
4732 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
4733 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4734 * the configuration information for the specified I2C.
4735 * @param ITFlags Interrupt flags to handle.
4736 * @param ITSources Interrupt sources enabled.
4737 * @retval HAL status
4738 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4739 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4740 uint32_t ITSources)
4741 {
4742 uint16_t devaddress;
4743 uint32_t tmpITFlags = ITFlags;
4744
4745 /* Process Locked */
4746 __HAL_LOCK(hi2c);
4747
4748 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4749 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4750 {
4751 /* Clear NACK Flag */
4752 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4753
4754 /* Set corresponding Error Code */
4755 /* No need to generate STOP, it is automatically done */
4756 /* Error callback will be send during stop flag treatment */
4757 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4758
4759 /* Flush TX register */
4760 I2C_Flush_TXDR(hi2c);
4761 }
4762 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4763 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4764 {
4765 /* Remove RXNE flag on temporary variable as read done */
4766 tmpITFlags &= ~I2C_FLAG_RXNE;
4767
4768 /* Read data from RXDR */
4769 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4770
4771 /* Increment Buffer pointer */
4772 hi2c->pBuffPtr++;
4773
4774 hi2c->XferSize--;
4775 hi2c->XferCount--;
4776 }
4777 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4778 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4779 {
4780 /* Write data to TXDR */
4781 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4782
4783 /* Increment Buffer pointer */
4784 hi2c->pBuffPtr++;
4785
4786 hi2c->XferSize--;
4787 hi2c->XferCount--;
4788 }
4789 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4790 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4791 {
4792 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4793 {
4794 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
4795
4796 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4797 {
4798 hi2c->XferSize = MAX_NBYTE_SIZE;
4799 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4800 }
4801 else
4802 {
4803 hi2c->XferSize = hi2c->XferCount;
4804 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4805 {
4806 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4807 hi2c->XferOptions, I2C_NO_STARTSTOP);
4808 }
4809 else
4810 {
4811 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
4812 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4813 }
4814 }
4815 }
4816 else
4817 {
4818 /* Call TxCpltCallback() if no stop mode is set */
4819 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4820 {
4821 /* Call I2C Master Sequential complete process */
4822 I2C_ITMasterSeqCplt(hi2c);
4823 }
4824 else
4825 {
4826 /* Wrong size Status regarding TCR flag event */
4827 /* Call the corresponding callback to inform upper layer of End of Transfer */
4828 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4829 }
4830 }
4831 }
4832 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4833 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4834 {
4835 if (hi2c->XferCount == 0U)
4836 {
4837 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
4838 {
4839 /* Generate a stop condition in case of no transfer option */
4840 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
4841 {
4842 /* Generate Stop */
4843 hi2c->Instance->CR2 |= I2C_CR2_STOP;
4844 }
4845 else
4846 {
4847 /* Call I2C Master Sequential complete process */
4848 I2C_ITMasterSeqCplt(hi2c);
4849 }
4850 }
4851 }
4852 else
4853 {
4854 /* Wrong size Status regarding TC flag event */
4855 /* Call the corresponding callback to inform upper layer of End of Transfer */
4856 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4857 }
4858 }
4859 else
4860 {
4861 /* Nothing to do */
4862 }
4863
4864 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
4865 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
4866 {
4867 /* Call I2C Master complete process */
4868 I2C_ITMasterCplt(hi2c, tmpITFlags);
4869 }
4870
4871 /* Process Unlocked */
4872 __HAL_UNLOCK(hi2c);
4873
4874 return HAL_OK;
4875 }
4876
4877 /**
4878 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
4879 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4880 * the configuration information for the specified I2C.
4881 * @param ITFlags Interrupt flags to handle.
4882 * @param ITSources Interrupt sources enabled.
4883 * @retval HAL status
4884 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)4885 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
4886 uint32_t ITSources)
4887 {
4888 uint32_t direction = I2C_GENERATE_START_WRITE;
4889 uint32_t tmpITFlags = ITFlags;
4890
4891 /* Process Locked */
4892 __HAL_LOCK(hi2c);
4893
4894 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
4895 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
4896 {
4897 /* Clear NACK Flag */
4898 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4899
4900 /* Set corresponding Error Code */
4901 /* No need to generate STOP, it is automatically done */
4902 /* Error callback will be send during stop flag treatment */
4903 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4904
4905 /* Flush TX register */
4906 I2C_Flush_TXDR(hi2c);
4907 }
4908 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
4909 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
4910 {
4911 /* Remove RXNE flag on temporary variable as read done */
4912 tmpITFlags &= ~I2C_FLAG_RXNE;
4913
4914 /* Read data from RXDR */
4915 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
4916
4917 /* Increment Buffer pointer */
4918 hi2c->pBuffPtr++;
4919
4920 hi2c->XferSize--;
4921 hi2c->XferCount--;
4922 }
4923 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
4924 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
4925 {
4926 if (hi2c->Memaddress == 0xFFFFFFFFU)
4927 {
4928 /* Write data to TXDR */
4929 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
4930
4931 /* Increment Buffer pointer */
4932 hi2c->pBuffPtr++;
4933
4934 hi2c->XferSize--;
4935 hi2c->XferCount--;
4936 }
4937 else
4938 {
4939 /* Write LSB part of Memory Address */
4940 hi2c->Instance->TXDR = hi2c->Memaddress;
4941
4942 /* Reset Memaddress content */
4943 hi2c->Memaddress = 0xFFFFFFFFU;
4944 }
4945 }
4946 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
4947 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4948 {
4949 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
4950 {
4951 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4952 {
4953 hi2c->XferSize = MAX_NBYTE_SIZE;
4954 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4955 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
4956 }
4957 else
4958 {
4959 hi2c->XferSize = hi2c->XferCount;
4960 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4961 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
4962 }
4963 }
4964 else
4965 {
4966 /* Wrong size Status regarding TCR flag event */
4967 /* Call the corresponding callback to inform upper layer of End of Transfer */
4968 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
4969 }
4970 }
4971 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
4972 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
4973 {
4974 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4975 {
4976 direction = I2C_GENERATE_START_READ;
4977 }
4978
4979 if (hi2c->XferCount > MAX_NBYTE_SIZE)
4980 {
4981 hi2c->XferSize = MAX_NBYTE_SIZE;
4982
4983 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
4984 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4985 I2C_RELOAD_MODE, direction);
4986 }
4987 else
4988 {
4989 hi2c->XferSize = hi2c->XferCount;
4990
4991 /* Set NBYTES to write and generate RESTART */
4992 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
4993 I2C_AUTOEND_MODE, direction);
4994 }
4995 }
4996 else
4997 {
4998 /* Nothing to do */
4999 }
5000
5001 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5002 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5003 {
5004 /* Call I2C Master complete process */
5005 I2C_ITMasterCplt(hi2c, tmpITFlags);
5006 }
5007
5008 /* Process Unlocked */
5009 __HAL_UNLOCK(hi2c);
5010
5011 return HAL_OK;
5012 }
5013
5014 /**
5015 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5016 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5017 * the configuration information for the specified I2C.
5018 * @param ITFlags Interrupt flags to handle.
5019 * @param ITSources Interrupt sources enabled.
5020 * @retval HAL status
5021 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5022 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5023 uint32_t ITSources)
5024 {
5025 uint32_t tmpoptions = hi2c->XferOptions;
5026 uint32_t tmpITFlags = ITFlags;
5027
5028 /* Process locked */
5029 __HAL_LOCK(hi2c);
5030
5031 /* Check if STOPF is set */
5032 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5033 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5034 {
5035 /* Call I2C Slave complete process */
5036 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5037 }
5038
5039 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5040 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5041 {
5042 /* Check that I2C transfer finished */
5043 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5044 /* Mean XferCount == 0*/
5045 /* So clear Flag NACKF only */
5046 if (hi2c->XferCount == 0U)
5047 {
5048 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5049 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5050 Warning[Pa134]: left and right operands are identical */
5051 {
5052 /* Call I2C Listen complete process */
5053 I2C_ITListenCplt(hi2c, tmpITFlags);
5054 }
5055 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5056 {
5057 /* Clear NACK Flag */
5058 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5059
5060 /* Flush TX register */
5061 I2C_Flush_TXDR(hi2c);
5062
5063 /* Last Byte is Transmitted */
5064 /* Call I2C Slave Sequential complete process */
5065 I2C_ITSlaveSeqCplt(hi2c);
5066 }
5067 else
5068 {
5069 /* Clear NACK Flag */
5070 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5071 }
5072 }
5073 else
5074 {
5075 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5076 /* Clear NACK Flag */
5077 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5078
5079 /* Set ErrorCode corresponding to a Non-Acknowledge */
5080 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5081
5082 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5083 {
5084 /* Call the corresponding callback to inform upper layer of End of Transfer */
5085 I2C_ITError(hi2c, hi2c->ErrorCode);
5086 }
5087 }
5088 }
5089 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5090 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5091 {
5092 if (hi2c->XferCount > 0U)
5093 {
5094 /* Read data from RXDR */
5095 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5096
5097 /* Increment Buffer pointer */
5098 hi2c->pBuffPtr++;
5099
5100 hi2c->XferSize--;
5101 hi2c->XferCount--;
5102 }
5103
5104 if ((hi2c->XferCount == 0U) && \
5105 (tmpoptions != I2C_NO_OPTION_FRAME))
5106 {
5107 /* Call I2C Slave Sequential complete process */
5108 I2C_ITSlaveSeqCplt(hi2c);
5109 }
5110 }
5111 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5112 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5113 {
5114 I2C_ITAddrCplt(hi2c, tmpITFlags);
5115 }
5116 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5117 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5118 {
5119 /* Write data to TXDR only if XferCount not reach "0" */
5120 /* A TXIS flag can be set, during STOP treatment */
5121 /* Check if all Data have already been sent */
5122 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5123 if (hi2c->XferCount > 0U)
5124 {
5125 /* Write data to TXDR */
5126 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5127
5128 /* Increment Buffer pointer */
5129 hi2c->pBuffPtr++;
5130
5131 hi2c->XferCount--;
5132 hi2c->XferSize--;
5133 }
5134 else
5135 {
5136 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5137 {
5138 /* Last Byte is Transmitted */
5139 /* Call I2C Slave Sequential complete process */
5140 I2C_ITSlaveSeqCplt(hi2c);
5141 }
5142 }
5143 }
5144 else
5145 {
5146 /* Nothing to do */
5147 }
5148
5149 /* Process Unlocked */
5150 __HAL_UNLOCK(hi2c);
5151
5152 return HAL_OK;
5153 }
5154
5155 /**
5156 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5157 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5158 * the configuration information for the specified I2C.
5159 * @param ITFlags Interrupt flags to handle.
5160 * @param ITSources Interrupt sources enabled.
5161 * @retval HAL status
5162 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5163 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5164 uint32_t ITSources)
5165 {
5166 uint16_t devaddress;
5167 uint32_t xfermode;
5168
5169 /* Process Locked */
5170 __HAL_LOCK(hi2c);
5171
5172 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5173 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5174 {
5175 /* Clear NACK Flag */
5176 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5177
5178 /* Set corresponding Error Code */
5179 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5180
5181 /* No need to generate STOP, it is automatically done */
5182 /* But enable STOP interrupt, to treat it */
5183 /* Error callback will be send during stop flag treatment */
5184 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5185
5186 /* Flush TX register */
5187 I2C_Flush_TXDR(hi2c);
5188 }
5189 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5190 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5191 {
5192 /* Disable TC interrupt */
5193 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5194
5195 if (hi2c->XferCount != 0U)
5196 {
5197 /* Recover Slave address */
5198 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5199
5200 /* Prepare the new XferSize to transfer */
5201 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5202 {
5203 hi2c->XferSize = MAX_NBYTE_SIZE;
5204 xfermode = I2C_RELOAD_MODE;
5205 }
5206 else
5207 {
5208 hi2c->XferSize = hi2c->XferCount;
5209 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5210 {
5211 xfermode = hi2c->XferOptions;
5212 }
5213 else
5214 {
5215 xfermode = I2C_AUTOEND_MODE;
5216 }
5217 }
5218
5219 /* Set the new XferSize in Nbytes register */
5220 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5221
5222 /* Update XferCount value */
5223 hi2c->XferCount -= hi2c->XferSize;
5224
5225 /* Enable DMA Request */
5226 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5227 {
5228 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5229 }
5230 else
5231 {
5232 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5233 }
5234 }
5235 else
5236 {
5237 /* Call TxCpltCallback() if no stop mode is set */
5238 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5239 {
5240 /* Call I2C Master Sequential complete process */
5241 I2C_ITMasterSeqCplt(hi2c);
5242 }
5243 else
5244 {
5245 /* Wrong size Status regarding TCR flag event */
5246 /* Call the corresponding callback to inform upper layer of End of Transfer */
5247 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5248 }
5249 }
5250 }
5251 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5252 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5253 {
5254 if (hi2c->XferCount == 0U)
5255 {
5256 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5257 {
5258 /* Generate a stop condition in case of no transfer option */
5259 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5260 {
5261 /* Generate Stop */
5262 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5263 }
5264 else
5265 {
5266 /* Call I2C Master Sequential complete process */
5267 I2C_ITMasterSeqCplt(hi2c);
5268 }
5269 }
5270 }
5271 else
5272 {
5273 /* Wrong size Status regarding TC flag event */
5274 /* Call the corresponding callback to inform upper layer of End of Transfer */
5275 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5276 }
5277 }
5278 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5279 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5280 {
5281 /* Call I2C Master complete process */
5282 I2C_ITMasterCplt(hi2c, ITFlags);
5283 }
5284 else
5285 {
5286 /* Nothing to do */
5287 }
5288
5289 /* Process Unlocked */
5290 __HAL_UNLOCK(hi2c);
5291
5292 return HAL_OK;
5293 }
5294
5295 /**
5296 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5297 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5298 * the configuration information for the specified I2C.
5299 * @param ITFlags Interrupt flags to handle.
5300 * @param ITSources Interrupt sources enabled.
5301 * @retval HAL status
5302 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5303 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5304 uint32_t ITSources)
5305 {
5306 uint32_t direction = I2C_GENERATE_START_WRITE;
5307
5308 /* Process Locked */
5309 __HAL_LOCK(hi2c);
5310
5311 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5312 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5313 {
5314 /* Clear NACK Flag */
5315 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5316
5317 /* Set corresponding Error Code */
5318 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5319
5320 /* No need to generate STOP, it is automatically done */
5321 /* But enable STOP interrupt, to treat it */
5322 /* Error callback will be send during stop flag treatment */
5323 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5324
5325 /* Flush TX register */
5326 I2C_Flush_TXDR(hi2c);
5327 }
5328 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5329 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5330 {
5331 /* Write LSB part of Memory Address */
5332 hi2c->Instance->TXDR = hi2c->Memaddress;
5333
5334 /* Reset Memaddress content */
5335 hi2c->Memaddress = 0xFFFFFFFFU;
5336 }
5337 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5338 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5339 {
5340 /* Enable only Error interrupt */
5341 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5342
5343 if (hi2c->XferCount != 0U)
5344 {
5345 /* Prepare the new XferSize to transfer */
5346 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5347 {
5348 hi2c->XferSize = MAX_NBYTE_SIZE;
5349 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5350 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5351 }
5352 else
5353 {
5354 hi2c->XferSize = hi2c->XferCount;
5355 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5356 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5357 }
5358
5359 /* Update XferCount value */
5360 hi2c->XferCount -= hi2c->XferSize;
5361
5362 /* Enable DMA Request */
5363 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5364 {
5365 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5366 }
5367 else
5368 {
5369 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5370 }
5371 }
5372 else
5373 {
5374 /* Wrong size Status regarding TCR flag event */
5375 /* Call the corresponding callback to inform upper layer of End of Transfer */
5376 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5377 }
5378 }
5379 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5380 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5381 {
5382 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5383 {
5384 direction = I2C_GENERATE_START_READ;
5385 }
5386
5387 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5388 {
5389 hi2c->XferSize = MAX_NBYTE_SIZE;
5390
5391 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5392 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5393 I2C_RELOAD_MODE, direction);
5394 }
5395 else
5396 {
5397 hi2c->XferSize = hi2c->XferCount;
5398
5399 /* Set NBYTES to write and generate RESTART */
5400 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5401 I2C_AUTOEND_MODE, direction);
5402 }
5403
5404 /* Update XferCount value */
5405 hi2c->XferCount -= hi2c->XferSize;
5406
5407 /* Enable DMA Request */
5408 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5409 {
5410 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5411 }
5412 else
5413 {
5414 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5415 }
5416 }
5417 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5418 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5419 {
5420 /* Call I2C Master complete process */
5421 I2C_ITMasterCplt(hi2c, ITFlags);
5422 }
5423 else
5424 {
5425 /* Nothing to do */
5426 }
5427
5428 /* Process Unlocked */
5429 __HAL_UNLOCK(hi2c);
5430
5431 return HAL_OK;
5432 }
5433
5434 /**
5435 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5436 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5437 * the configuration information for the specified I2C.
5438 * @param ITFlags Interrupt flags to handle.
5439 * @param ITSources Interrupt sources enabled.
5440 * @retval HAL status
5441 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5442 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5443 uint32_t ITSources)
5444 {
5445 uint32_t tmpoptions = hi2c->XferOptions;
5446 uint32_t treatdmanack = 0U;
5447 HAL_I2C_StateTypeDef tmpstate;
5448
5449 /* Process locked */
5450 __HAL_LOCK(hi2c);
5451
5452 /* Check if STOPF is set */
5453 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5454 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5455 {
5456 /* Call I2C Slave complete process */
5457 I2C_ITSlaveCplt(hi2c, ITFlags);
5458 }
5459
5460 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5461 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5462 {
5463 /* Check that I2C transfer finished */
5464 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5465 /* Mean XferCount == 0 */
5466 /* So clear Flag NACKF only */
5467 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5468 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5469 {
5470 /* Split check of hdmarx, for MISRA compliance */
5471 if (hi2c->hdmarx != NULL)
5472 {
5473 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5474 {
5475 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5476 {
5477 treatdmanack = 1U;
5478 }
5479 }
5480 }
5481
5482 /* Split check of hdmatx, for MISRA compliance */
5483 if (hi2c->hdmatx != NULL)
5484 {
5485 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5486 {
5487 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5488 {
5489 treatdmanack = 1U;
5490 }
5491 }
5492 }
5493
5494 if (treatdmanack == 1U)
5495 {
5496 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5497 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5498 Warning[Pa134]: left and right operands are identical */
5499 {
5500 /* Call I2C Listen complete process */
5501 I2C_ITListenCplt(hi2c, ITFlags);
5502 }
5503 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5504 {
5505 /* Clear NACK Flag */
5506 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5507
5508 /* Flush TX register */
5509 I2C_Flush_TXDR(hi2c);
5510
5511 /* Last Byte is Transmitted */
5512 /* Call I2C Slave Sequential complete process */
5513 I2C_ITSlaveSeqCplt(hi2c);
5514 }
5515 else
5516 {
5517 /* Clear NACK Flag */
5518 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5519 }
5520 }
5521 else
5522 {
5523 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5524 /* Clear NACK Flag */
5525 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5526
5527 /* Set ErrorCode corresponding to a Non-Acknowledge */
5528 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5529
5530 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
5531 tmpstate = hi2c->State;
5532
5533 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5534 {
5535 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
5536 {
5537 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5538 }
5539 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
5540 {
5541 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5542 }
5543 else
5544 {
5545 /* Do nothing */
5546 }
5547
5548 /* Call the corresponding callback to inform upper layer of End of Transfer */
5549 I2C_ITError(hi2c, hi2c->ErrorCode);
5550 }
5551 }
5552 }
5553 else
5554 {
5555 /* Only Clear NACK Flag, no DMA treatment is pending */
5556 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5557 }
5558 }
5559 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
5560 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5561 {
5562 I2C_ITAddrCplt(hi2c, ITFlags);
5563 }
5564 else
5565 {
5566 /* Nothing to do */
5567 }
5568
5569 /* Process Unlocked */
5570 __HAL_UNLOCK(hi2c);
5571
5572 return HAL_OK;
5573 }
5574
5575 /**
5576 * @brief Master sends target device address followed by internal memory address for write request.
5577 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5578 * the configuration information for the specified I2C.
5579 * @param DevAddress Target device address: The device 7 bits address value
5580 * in datasheet must be shifted to the left before calling the interface
5581 * @param MemAddress Internal memory address
5582 * @param MemAddSize Size of internal memory address
5583 * @param Timeout Timeout duration
5584 * @param Tickstart Tick start value
5585 * @retval HAL status
5586 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5587 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5588 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5589 uint32_t Tickstart)
5590 {
5591 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
5592
5593 /* Wait until TXIS flag is set */
5594 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5595 {
5596 return HAL_ERROR;
5597 }
5598
5599 /* If Memory address size is 8Bit */
5600 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5601 {
5602 /* Send Memory Address */
5603 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5604 }
5605 /* If Memory address size is 16Bit */
5606 else
5607 {
5608 /* Send MSB of Memory Address */
5609 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5610
5611 /* Wait until TXIS flag is set */
5612 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5613 {
5614 return HAL_ERROR;
5615 }
5616
5617 /* Send LSB of Memory Address */
5618 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5619 }
5620
5621 /* Wait until TCR flag is set */
5622 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
5623 {
5624 return HAL_ERROR;
5625 }
5626
5627 return HAL_OK;
5628 }
5629
5630 /**
5631 * @brief Master sends target device address followed by internal memory address for read request.
5632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5633 * the configuration information for the specified I2C.
5634 * @param DevAddress Target device address: The device 7 bits address value
5635 * in datasheet must be shifted to the left before calling the interface
5636 * @param MemAddress Internal memory address
5637 * @param MemAddSize Size of internal memory address
5638 * @param Timeout Timeout duration
5639 * @param Tickstart Tick start value
5640 * @retval HAL status
5641 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)5642 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
5643 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
5644 uint32_t Tickstart)
5645 {
5646 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
5647
5648 /* Wait until TXIS flag is set */
5649 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5650 {
5651 return HAL_ERROR;
5652 }
5653
5654 /* If Memory address size is 8Bit */
5655 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
5656 {
5657 /* Send Memory Address */
5658 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5659 }
5660 /* If Memory address size is 16Bit */
5661 else
5662 {
5663 /* Send MSB of Memory Address */
5664 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
5665
5666 /* Wait until TXIS flag is set */
5667 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
5668 {
5669 return HAL_ERROR;
5670 }
5671
5672 /* Send LSB of Memory Address */
5673 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
5674 }
5675
5676 /* Wait until TC flag is set */
5677 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
5678 {
5679 return HAL_ERROR;
5680 }
5681
5682 return HAL_OK;
5683 }
5684
5685 /**
5686 * @brief I2C Address complete process callback.
5687 * @param hi2c I2C handle.
5688 * @param ITFlags Interrupt flags to handle.
5689 * @retval None
5690 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5691 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5692 {
5693 uint8_t transferdirection;
5694 uint16_t slaveaddrcode;
5695 uint16_t ownadd1code;
5696 uint16_t ownadd2code;
5697
5698 /* Prevent unused argument(s) compilation warning */
5699 UNUSED(ITFlags);
5700
5701 /* In case of Listen state, need to inform upper layer of address match code event */
5702 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
5703 {
5704 transferdirection = I2C_GET_DIR(hi2c);
5705 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
5706 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
5707 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
5708
5709 /* If 10bits addressing mode is selected */
5710 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
5711 {
5712 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
5713 {
5714 slaveaddrcode = ownadd1code;
5715 hi2c->AddrEventCount++;
5716 if (hi2c->AddrEventCount == 2U)
5717 {
5718 /* Reset Address Event counter */
5719 hi2c->AddrEventCount = 0U;
5720
5721 /* Clear ADDR flag */
5722 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5723
5724 /* Process Unlocked */
5725 __HAL_UNLOCK(hi2c);
5726
5727 /* Call Slave Addr callback */
5728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5729 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5730 #else
5731 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5732 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5733 }
5734 }
5735 else
5736 {
5737 slaveaddrcode = ownadd2code;
5738
5739 /* Disable ADDR Interrupts */
5740 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5741
5742 /* Process Unlocked */
5743 __HAL_UNLOCK(hi2c);
5744
5745 /* Call Slave Addr callback */
5746 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5747 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5748 #else
5749 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5750 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5751 }
5752 }
5753 /* else 7 bits addressing mode is selected */
5754 else
5755 {
5756 /* Disable ADDR Interrupts */
5757 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
5758
5759 /* Process Unlocked */
5760 __HAL_UNLOCK(hi2c);
5761
5762 /* Call Slave Addr callback */
5763 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5764 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
5765 #else
5766 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
5767 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5768 }
5769 }
5770 /* Else clear address flag only */
5771 else
5772 {
5773 /* Clear ADDR flag */
5774 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
5775
5776 /* Process Unlocked */
5777 __HAL_UNLOCK(hi2c);
5778 }
5779 }
5780
5781 /**
5782 * @brief I2C Master sequential complete process.
5783 * @param hi2c I2C handle.
5784 * @retval None
5785 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)5786 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
5787 {
5788 /* Reset I2C handle mode */
5789 hi2c->Mode = HAL_I2C_MODE_NONE;
5790
5791 /* No Generate Stop, to permit restart mode */
5792 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
5793 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5794 {
5795 hi2c->State = HAL_I2C_STATE_READY;
5796 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5797 hi2c->XferISR = NULL;
5798
5799 /* Disable Interrupts */
5800 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5801
5802 /* Process Unlocked */
5803 __HAL_UNLOCK(hi2c);
5804
5805 /* Call the corresponding callback to inform upper layer of End of Transfer */
5806 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5807 hi2c->MasterTxCpltCallback(hi2c);
5808 #else
5809 HAL_I2C_MasterTxCpltCallback(hi2c);
5810 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5811 }
5812 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
5813 else
5814 {
5815 hi2c->State = HAL_I2C_STATE_READY;
5816 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5817 hi2c->XferISR = NULL;
5818
5819 /* Disable Interrupts */
5820 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5821
5822 /* Process Unlocked */
5823 __HAL_UNLOCK(hi2c);
5824
5825 /* Call the corresponding callback to inform upper layer of End of Transfer */
5826 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5827 hi2c->MasterRxCpltCallback(hi2c);
5828 #else
5829 HAL_I2C_MasterRxCpltCallback(hi2c);
5830 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5831 }
5832 }
5833
5834 /**
5835 * @brief I2C Slave sequential complete process.
5836 * @param hi2c I2C handle.
5837 * @retval None
5838 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)5839 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
5840 {
5841 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
5842
5843 /* Reset I2C handle mode */
5844 hi2c->Mode = HAL_I2C_MODE_NONE;
5845
5846 /* If a DMA is ongoing, Update handle size context */
5847 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
5848 {
5849 /* Disable DMA Request */
5850 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
5851 }
5852 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
5853 {
5854 /* Disable DMA Request */
5855 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
5856 }
5857 else
5858 {
5859 /* Do nothing */
5860 }
5861
5862 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
5863 {
5864 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
5865 hi2c->State = HAL_I2C_STATE_LISTEN;
5866 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5867
5868 /* Disable Interrupts */
5869 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5870
5871 /* Process Unlocked */
5872 __HAL_UNLOCK(hi2c);
5873
5874 /* Call the corresponding callback to inform upper layer of End of Transfer */
5875 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5876 hi2c->SlaveTxCpltCallback(hi2c);
5877 #else
5878 HAL_I2C_SlaveTxCpltCallback(hi2c);
5879 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5880 }
5881
5882 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
5883 {
5884 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
5885 hi2c->State = HAL_I2C_STATE_LISTEN;
5886 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
5887
5888 /* Disable Interrupts */
5889 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5890
5891 /* Process Unlocked */
5892 __HAL_UNLOCK(hi2c);
5893
5894 /* Call the corresponding callback to inform upper layer of End of Transfer */
5895 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5896 hi2c->SlaveRxCpltCallback(hi2c);
5897 #else
5898 HAL_I2C_SlaveRxCpltCallback(hi2c);
5899 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5900 }
5901 else
5902 {
5903 /* Nothing to do */
5904 }
5905 }
5906
5907 /**
5908 * @brief I2C Master complete process.
5909 * @param hi2c I2C handle.
5910 * @param ITFlags Interrupt flags to handle.
5911 * @retval None
5912 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)5913 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
5914 {
5915 uint32_t tmperror;
5916 uint32_t tmpITFlags = ITFlags;
5917 __IO uint32_t tmpreg;
5918
5919 /* Clear STOP Flag */
5920 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
5921
5922 /* Disable Interrupts and Store Previous state */
5923 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5924 {
5925 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5926 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5927 }
5928 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5929 {
5930 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
5931 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5932 }
5933 else
5934 {
5935 /* Do nothing */
5936 }
5937
5938 /* Clear Configuration Register 2 */
5939 I2C_RESET_CR2(hi2c);
5940
5941 /* Reset handle parameters */
5942 hi2c->XferISR = NULL;
5943 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
5944
5945 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
5946 {
5947 /* Clear NACK Flag */
5948 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5949
5950 /* Set acknowledge error code */
5951 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5952 }
5953
5954 /* Fetch Last receive data if any */
5955 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
5956 {
5957 /* Read data from RXDR */
5958 tmpreg = (uint8_t)hi2c->Instance->RXDR;
5959 UNUSED(tmpreg);
5960 }
5961
5962 /* Flush TX register */
5963 I2C_Flush_TXDR(hi2c);
5964
5965 /* Store current volatile hi2c->ErrorCode, misra rule */
5966 tmperror = hi2c->ErrorCode;
5967
5968 /* Call the corresponding callback to inform upper layer of End of Transfer */
5969 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
5970 {
5971 /* Call the corresponding callback to inform upper layer of End of Transfer */
5972 I2C_ITError(hi2c, hi2c->ErrorCode);
5973 }
5974 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
5975 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5976 {
5977 hi2c->State = HAL_I2C_STATE_READY;
5978 hi2c->PreviousState = I2C_STATE_NONE;
5979
5980 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5981 {
5982 hi2c->Mode = HAL_I2C_MODE_NONE;
5983
5984 /* Process Unlocked */
5985 __HAL_UNLOCK(hi2c);
5986
5987 /* Call the corresponding callback to inform upper layer of End of Transfer */
5988 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5989 hi2c->MemTxCpltCallback(hi2c);
5990 #else
5991 HAL_I2C_MemTxCpltCallback(hi2c);
5992 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5993 }
5994 else
5995 {
5996 hi2c->Mode = HAL_I2C_MODE_NONE;
5997
5998 /* Process Unlocked */
5999 __HAL_UNLOCK(hi2c);
6000
6001 /* Call the corresponding callback to inform upper layer of End of Transfer */
6002 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6003 hi2c->MasterTxCpltCallback(hi2c);
6004 #else
6005 HAL_I2C_MasterTxCpltCallback(hi2c);
6006 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6007 }
6008 }
6009 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6010 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6011 {
6012 hi2c->State = HAL_I2C_STATE_READY;
6013 hi2c->PreviousState = I2C_STATE_NONE;
6014
6015 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6016 {
6017 hi2c->Mode = HAL_I2C_MODE_NONE;
6018
6019 /* Process Unlocked */
6020 __HAL_UNLOCK(hi2c);
6021
6022 /* Call the corresponding callback to inform upper layer of End of Transfer */
6023 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6024 hi2c->MemRxCpltCallback(hi2c);
6025 #else
6026 HAL_I2C_MemRxCpltCallback(hi2c);
6027 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6028 }
6029 else
6030 {
6031 hi2c->Mode = HAL_I2C_MODE_NONE;
6032
6033 /* Process Unlocked */
6034 __HAL_UNLOCK(hi2c);
6035
6036 /* Call the corresponding callback to inform upper layer of End of Transfer */
6037 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6038 hi2c->MasterRxCpltCallback(hi2c);
6039 #else
6040 HAL_I2C_MasterRxCpltCallback(hi2c);
6041 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6042 }
6043 }
6044 else
6045 {
6046 /* Nothing to do */
6047 }
6048 }
6049
6050 /**
6051 * @brief I2C Slave complete process.
6052 * @param hi2c I2C handle.
6053 * @param ITFlags Interrupt flags to handle.
6054 * @retval None
6055 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6056 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6057 {
6058 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6059 uint32_t tmpITFlags = ITFlags;
6060 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6061
6062 /* Clear STOP Flag */
6063 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6064
6065 /* Disable Interrupts and Store Previous state */
6066 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6067 {
6068 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6069 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6070 }
6071 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6072 {
6073 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6074 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6075 }
6076 else
6077 {
6078 /* Do nothing */
6079 }
6080
6081 /* Disable Address Acknowledge */
6082 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6083
6084 /* Clear Configuration Register 2 */
6085 I2C_RESET_CR2(hi2c);
6086
6087 /* Flush TX register */
6088 I2C_Flush_TXDR(hi2c);
6089
6090 /* If a DMA is ongoing, Update handle size context */
6091 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6092 {
6093 /* Disable DMA Request */
6094 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6095
6096 if (hi2c->hdmatx != NULL)
6097 {
6098 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6099 }
6100 }
6101 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6102 {
6103 /* Disable DMA Request */
6104 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6105
6106 if (hi2c->hdmarx != NULL)
6107 {
6108 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6109 }
6110 }
6111 else
6112 {
6113 /* Do nothing */
6114 }
6115
6116 /* Store Last receive data if any */
6117 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6118 {
6119 /* Remove RXNE flag on temporary variable as read done */
6120 tmpITFlags &= ~I2C_FLAG_RXNE;
6121
6122 /* Read data from RXDR */
6123 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6124
6125 /* Increment Buffer pointer */
6126 hi2c->pBuffPtr++;
6127
6128 if ((hi2c->XferSize > 0U))
6129 {
6130 hi2c->XferSize--;
6131 hi2c->XferCount--;
6132 }
6133 }
6134
6135 /* All data are not transferred, so set error code accordingly */
6136 if (hi2c->XferCount != 0U)
6137 {
6138 /* Set ErrorCode corresponding to a Non-Acknowledge */
6139 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6140 }
6141
6142 hi2c->Mode = HAL_I2C_MODE_NONE;
6143 hi2c->XferISR = NULL;
6144
6145 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6146 {
6147 /* Call the corresponding callback to inform upper layer of End of Transfer */
6148 I2C_ITError(hi2c, hi2c->ErrorCode);
6149
6150 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6151 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6152 {
6153 /* Call I2C Listen complete process */
6154 I2C_ITListenCplt(hi2c, tmpITFlags);
6155 }
6156 }
6157 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6158 {
6159 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6160 I2C_ITSlaveSeqCplt(hi2c);
6161
6162 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6163 hi2c->State = HAL_I2C_STATE_READY;
6164 hi2c->PreviousState = I2C_STATE_NONE;
6165
6166 /* Process Unlocked */
6167 __HAL_UNLOCK(hi2c);
6168
6169 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6170 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6171 hi2c->ListenCpltCallback(hi2c);
6172 #else
6173 HAL_I2C_ListenCpltCallback(hi2c);
6174 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6175 }
6176 /* Call the corresponding callback to inform upper layer of End of Transfer */
6177 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6178 {
6179 hi2c->State = HAL_I2C_STATE_READY;
6180 hi2c->PreviousState = I2C_STATE_NONE;
6181
6182 /* Process Unlocked */
6183 __HAL_UNLOCK(hi2c);
6184
6185 /* Call the corresponding callback to inform upper layer of End of Transfer */
6186 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6187 hi2c->SlaveRxCpltCallback(hi2c);
6188 #else
6189 HAL_I2C_SlaveRxCpltCallback(hi2c);
6190 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6191 }
6192 else
6193 {
6194 hi2c->State = HAL_I2C_STATE_READY;
6195 hi2c->PreviousState = I2C_STATE_NONE;
6196
6197 /* Process Unlocked */
6198 __HAL_UNLOCK(hi2c);
6199
6200 /* Call the corresponding callback to inform upper layer of End of Transfer */
6201 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6202 hi2c->SlaveTxCpltCallback(hi2c);
6203 #else
6204 HAL_I2C_SlaveTxCpltCallback(hi2c);
6205 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6206 }
6207 }
6208
6209 /**
6210 * @brief I2C Listen complete process.
6211 * @param hi2c I2C handle.
6212 * @param ITFlags Interrupt flags to handle.
6213 * @retval None
6214 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6215 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6216 {
6217 /* Reset handle parameters */
6218 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6219 hi2c->PreviousState = I2C_STATE_NONE;
6220 hi2c->State = HAL_I2C_STATE_READY;
6221 hi2c->Mode = HAL_I2C_MODE_NONE;
6222 hi2c->XferISR = NULL;
6223
6224 /* Store Last receive data if any */
6225 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6226 {
6227 /* Read data from RXDR */
6228 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6229
6230 /* Increment Buffer pointer */
6231 hi2c->pBuffPtr++;
6232
6233 if ((hi2c->XferSize > 0U))
6234 {
6235 hi2c->XferSize--;
6236 hi2c->XferCount--;
6237
6238 /* Set ErrorCode corresponding to a Non-Acknowledge */
6239 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6240 }
6241 }
6242
6243 /* Disable all Interrupts*/
6244 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6245
6246 /* Clear NACK Flag */
6247 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6248
6249 /* Process Unlocked */
6250 __HAL_UNLOCK(hi2c);
6251
6252 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6253 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6254 hi2c->ListenCpltCallback(hi2c);
6255 #else
6256 HAL_I2C_ListenCpltCallback(hi2c);
6257 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6258 }
6259
6260 /**
6261 * @brief I2C interrupts error process.
6262 * @param hi2c I2C handle.
6263 * @param ErrorCode Error code to handle.
6264 * @retval None
6265 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6266 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6267 {
6268 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6269 uint32_t tmppreviousstate;
6270
6271 /* Reset handle parameters */
6272 hi2c->Mode = HAL_I2C_MODE_NONE;
6273 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6274 hi2c->XferCount = 0U;
6275
6276 /* Set new error code */
6277 hi2c->ErrorCode |= ErrorCode;
6278
6279 /* Disable Interrupts */
6280 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6281 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6282 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6283 {
6284 /* Disable all interrupts, except interrupts related to LISTEN state */
6285 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6286
6287 /* keep HAL_I2C_STATE_LISTEN if set */
6288 hi2c->State = HAL_I2C_STATE_LISTEN;
6289 hi2c->XferISR = I2C_Slave_ISR_IT;
6290 }
6291 else
6292 {
6293 /* Disable all interrupts */
6294 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6295
6296 /* If state is an abort treatment on going, don't change state */
6297 /* This change will be do later */
6298 if (hi2c->State != HAL_I2C_STATE_ABORT)
6299 {
6300 /* Set HAL_I2C_STATE_READY */
6301 hi2c->State = HAL_I2C_STATE_READY;
6302 }
6303 hi2c->XferISR = NULL;
6304 }
6305
6306 /* Abort DMA TX transfer if any */
6307 tmppreviousstate = hi2c->PreviousState;
6308 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6309 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6310 {
6311 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6312 {
6313 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6314 }
6315
6316 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6317 {
6318 /* Set the I2C DMA Abort callback :
6319 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6320 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6321
6322 /* Process Unlocked */
6323 __HAL_UNLOCK(hi2c);
6324
6325 /* Abort DMA TX */
6326 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6327 {
6328 /* Call Directly XferAbortCallback function in case of error */
6329 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6330 }
6331 }
6332 else
6333 {
6334 I2C_TreatErrorCallback(hi2c);
6335 }
6336 }
6337 /* Abort DMA RX transfer if any */
6338 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6339 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6340 {
6341 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6342 {
6343 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6344 }
6345
6346 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6347 {
6348 /* Set the I2C DMA Abort callback :
6349 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6350 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6351
6352 /* Process Unlocked */
6353 __HAL_UNLOCK(hi2c);
6354
6355 /* Abort DMA RX */
6356 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6357 {
6358 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6359 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6360 }
6361 }
6362 else
6363 {
6364 I2C_TreatErrorCallback(hi2c);
6365 }
6366 }
6367 else
6368 {
6369 I2C_TreatErrorCallback(hi2c);
6370 }
6371 }
6372
6373 /**
6374 * @brief I2C Error callback treatment.
6375 * @param hi2c I2C handle.
6376 * @retval None
6377 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6378 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6379 {
6380 if (hi2c->State == HAL_I2C_STATE_ABORT)
6381 {
6382 hi2c->State = HAL_I2C_STATE_READY;
6383 hi2c->PreviousState = I2C_STATE_NONE;
6384
6385 /* Process Unlocked */
6386 __HAL_UNLOCK(hi2c);
6387
6388 /* Call the corresponding callback to inform upper layer of End of Transfer */
6389 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6390 hi2c->AbortCpltCallback(hi2c);
6391 #else
6392 HAL_I2C_AbortCpltCallback(hi2c);
6393 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6394 }
6395 else
6396 {
6397 hi2c->PreviousState = I2C_STATE_NONE;
6398
6399 /* Process Unlocked */
6400 __HAL_UNLOCK(hi2c);
6401
6402 /* Call the corresponding callback to inform upper layer of End of Transfer */
6403 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6404 hi2c->ErrorCallback(hi2c);
6405 #else
6406 HAL_I2C_ErrorCallback(hi2c);
6407 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6408 }
6409 }
6410
6411 /**
6412 * @brief I2C Tx data register flush process.
6413 * @param hi2c I2C handle.
6414 * @retval None
6415 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6416 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6417 {
6418 /* If a pending TXIS flag is set */
6419 /* Write a dummy data in TXDR to clear it */
6420 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6421 {
6422 hi2c->Instance->TXDR = 0x00U;
6423 }
6424
6425 /* Flush TX register if not empty */
6426 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6427 {
6428 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6429 }
6430 }
6431
6432 /**
6433 * @brief DMA I2C master transmit process complete callback.
6434 * @param hdma DMA handle
6435 * @retval None
6436 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6437 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6438 {
6439 /* Derogation MISRAC2012-Rule-11.5 */
6440 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6441
6442 /* Disable DMA Request */
6443 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6444
6445 /* If last transfer, enable STOP interrupt */
6446 if (hi2c->XferCount == 0U)
6447 {
6448 /* Enable STOP interrupt */
6449 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6450 }
6451 /* else prepare a new DMA transfer and enable TCReload interrupt */
6452 else
6453 {
6454 /* Update Buffer pointer */
6455 hi2c->pBuffPtr += hi2c->XferSize;
6456
6457 /* Set the XferSize to transfer */
6458 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6459 {
6460 hi2c->XferSize = MAX_NBYTE_SIZE;
6461 }
6462 else
6463 {
6464 hi2c->XferSize = hi2c->XferCount;
6465 }
6466
6467 /* Enable the DMA channel */
6468 if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
6469 hi2c->XferSize) != HAL_OK)
6470 {
6471 /* Call the corresponding callback to inform upper layer of End of Transfer */
6472 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6473 }
6474 else
6475 {
6476 /* Enable TC interrupts */
6477 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6478 }
6479 }
6480 }
6481
6482 /**
6483 * @brief DMA I2C slave transmit process complete callback.
6484 * @param hdma DMA handle
6485 * @retval None
6486 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)6487 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
6488 {
6489 /* Derogation MISRAC2012-Rule-11.5 */
6490 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6491 uint32_t tmpoptions = hi2c->XferOptions;
6492
6493 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
6494 {
6495 /* Disable DMA Request */
6496 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6497
6498 /* Last Byte is Transmitted */
6499 /* Call I2C Slave Sequential complete process */
6500 I2C_ITSlaveSeqCplt(hi2c);
6501 }
6502 else
6503 {
6504 /* No specific action, Master fully manage the generation of STOP condition */
6505 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6506 /* So STOP condition should be manage through Interrupt treatment */
6507 }
6508 }
6509
6510 /**
6511 * @brief DMA I2C master receive process complete callback.
6512 * @param hdma DMA handle
6513 * @retval None
6514 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)6515 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
6516 {
6517 /* Derogation MISRAC2012-Rule-11.5 */
6518 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6519
6520 /* Disable DMA Request */
6521 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6522
6523 /* If last transfer, enable STOP interrupt */
6524 if (hi2c->XferCount == 0U)
6525 {
6526 /* Enable STOP interrupt */
6527 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6528 }
6529 /* else prepare a new DMA transfer and enable TCReload interrupt */
6530 else
6531 {
6532 /* Update Buffer pointer */
6533 hi2c->pBuffPtr += hi2c->XferSize;
6534
6535 /* Set the XferSize to transfer */
6536 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6537 {
6538 hi2c->XferSize = MAX_NBYTE_SIZE;
6539 }
6540 else
6541 {
6542 hi2c->XferSize = hi2c->XferCount;
6543 }
6544
6545 /* Enable the DMA channel */
6546 if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
6547 hi2c->XferSize) != HAL_OK)
6548 {
6549 /* Call the corresponding callback to inform upper layer of End of Transfer */
6550 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6551 }
6552 else
6553 {
6554 /* Enable TC interrupts */
6555 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
6556 }
6557 }
6558 }
6559
6560 /**
6561 * @brief DMA I2C slave receive process complete callback.
6562 * @param hdma DMA handle
6563 * @retval None
6564 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)6565 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
6566 {
6567 /* Derogation MISRAC2012-Rule-11.5 */
6568 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6569 uint32_t tmpoptions = hi2c->XferOptions;
6570
6571 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
6572 (tmpoptions != I2C_NO_OPTION_FRAME))
6573 {
6574 /* Disable DMA Request */
6575 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6576
6577 /* Call I2C Slave Sequential complete process */
6578 I2C_ITSlaveSeqCplt(hi2c);
6579 }
6580 else
6581 {
6582 /* No specific action, Master fully manage the generation of STOP condition */
6583 /* Mean that this generation can arrive at any time, at the end or during DMA process */
6584 /* So STOP condition should be manage through Interrupt treatment */
6585 }
6586 }
6587
6588 /**
6589 * @brief DMA I2C communication error callback.
6590 * @param hdma DMA handle
6591 * @retval None
6592 */
I2C_DMAError(DMA_HandleTypeDef * hdma)6593 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
6594 {
6595 /* Derogation MISRAC2012-Rule-11.5 */
6596 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6597
6598 /* Disable Acknowledge */
6599 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6600
6601 /* Call the corresponding callback to inform upper layer of End of Transfer */
6602 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
6603 }
6604
6605 /**
6606 * @brief DMA I2C communication abort callback
6607 * (To be called at end of DMA Abort procedure).
6608 * @param hdma DMA handle.
6609 * @retval None
6610 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)6611 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
6612 {
6613 /* Derogation MISRAC2012-Rule-11.5 */
6614 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6615
6616 /* Reset AbortCpltCallback */
6617 if (hi2c->hdmatx != NULL)
6618 {
6619 hi2c->hdmatx->XferAbortCallback = NULL;
6620 }
6621 if (hi2c->hdmarx != NULL)
6622 {
6623 hi2c->hdmarx->XferAbortCallback = NULL;
6624 }
6625
6626 I2C_TreatErrorCallback(hi2c);
6627 }
6628
6629 /**
6630 * @brief This function handles I2C Communication Timeout. It waits
6631 * until a flag is no longer in the specified status.
6632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6633 * the configuration information for the specified I2C.
6634 * @param Flag Specifies the I2C flag to check.
6635 * @param Status The actual Flag status (SET or RESET).
6636 * @param Timeout Timeout duration
6637 * @param Tickstart Tick start value
6638 * @retval HAL status
6639 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)6640 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
6641 uint32_t Timeout, uint32_t Tickstart)
6642 {
6643 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
6644 {
6645 /* Check for the Timeout */
6646 if (Timeout != HAL_MAX_DELAY)
6647 {
6648 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6649 {
6650 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6651 hi2c->State = HAL_I2C_STATE_READY;
6652 hi2c->Mode = HAL_I2C_MODE_NONE;
6653
6654 /* Process Unlocked */
6655 __HAL_UNLOCK(hi2c);
6656 return HAL_ERROR;
6657 }
6658 }
6659 }
6660 return HAL_OK;
6661 }
6662
6663 /**
6664 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
6665 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6666 * the configuration information for the specified I2C.
6667 * @param Timeout Timeout duration
6668 * @param Tickstart Tick start value
6669 * @retval HAL status
6670 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6671 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6672 uint32_t Tickstart)
6673 {
6674 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
6675 {
6676 /* Check if an error is detected */
6677 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6678 {
6679 return HAL_ERROR;
6680 }
6681
6682 /* Check for the Timeout */
6683 if (Timeout != HAL_MAX_DELAY)
6684 {
6685 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6686 {
6687 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6688 hi2c->State = HAL_I2C_STATE_READY;
6689 hi2c->Mode = HAL_I2C_MODE_NONE;
6690
6691 /* Process Unlocked */
6692 __HAL_UNLOCK(hi2c);
6693
6694 return HAL_ERROR;
6695 }
6696 }
6697 }
6698 return HAL_OK;
6699 }
6700
6701 /**
6702 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
6703 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6704 * the configuration information for the specified I2C.
6705 * @param Timeout Timeout duration
6706 * @param Tickstart Tick start value
6707 * @retval HAL status
6708 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6709 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6710 uint32_t Tickstart)
6711 {
6712 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6713 {
6714 /* Check if an error is detected */
6715 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6716 {
6717 return HAL_ERROR;
6718 }
6719
6720 /* Check for the Timeout */
6721 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6722 {
6723 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6724 hi2c->State = HAL_I2C_STATE_READY;
6725 hi2c->Mode = HAL_I2C_MODE_NONE;
6726
6727 /* Process Unlocked */
6728 __HAL_UNLOCK(hi2c);
6729
6730 return HAL_ERROR;
6731 }
6732 }
6733 return HAL_OK;
6734 }
6735
6736 /**
6737 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
6738 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6739 * the configuration information for the specified I2C.
6740 * @param Timeout Timeout duration
6741 * @param Tickstart Tick start value
6742 * @retval HAL status
6743 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6744 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
6745 uint32_t Tickstart)
6746 {
6747 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
6748 {
6749 /* Check if an error is detected */
6750 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
6751 {
6752 return HAL_ERROR;
6753 }
6754
6755 /* Check if a STOPF is detected */
6756 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6757 {
6758 /* Check if an RXNE is pending */
6759 /* Store Last receive data if any */
6760 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
6761 {
6762 /* Return HAL_OK */
6763 /* The Reading of data from RXDR will be done in caller function */
6764 return HAL_OK;
6765 }
6766 else
6767 {
6768 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6769 {
6770 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6771 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
6772 }
6773 else
6774 {
6775 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6776 }
6777
6778 /* Clear STOP Flag */
6779 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6780
6781 /* Clear Configuration Register 2 */
6782 I2C_RESET_CR2(hi2c);
6783
6784 hi2c->State = HAL_I2C_STATE_READY;
6785 hi2c->Mode = HAL_I2C_MODE_NONE;
6786
6787 /* Process Unlocked */
6788 __HAL_UNLOCK(hi2c);
6789
6790 return HAL_ERROR;
6791 }
6792 }
6793
6794 /* Check for the Timeout */
6795 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
6796 {
6797 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6798 hi2c->State = HAL_I2C_STATE_READY;
6799
6800 /* Process Unlocked */
6801 __HAL_UNLOCK(hi2c);
6802
6803 return HAL_ERROR;
6804 }
6805 }
6806 return HAL_OK;
6807 }
6808
6809 /**
6810 * @brief This function handles errors detection during an I2C Communication.
6811 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6812 * the configuration information for the specified I2C.
6813 * @param Timeout Timeout duration
6814 * @param Tickstart Tick start value
6815 * @retval HAL status
6816 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)6817 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
6818 {
6819 HAL_StatusTypeDef status = HAL_OK;
6820 uint32_t itflag = hi2c->Instance->ISR;
6821 uint32_t error_code = 0;
6822 uint32_t tickstart = Tickstart;
6823 uint32_t tmp1;
6824 HAL_I2C_ModeTypeDef tmp2;
6825
6826 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
6827 {
6828 /* Clear NACKF Flag */
6829 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6830
6831 /* Wait until STOP Flag is set or timeout occurred */
6832 /* AutoEnd should be initiate after AF */
6833 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
6834 {
6835 /* Check for the Timeout */
6836 if (Timeout != HAL_MAX_DELAY)
6837 {
6838 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
6839 {
6840 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
6841 tmp2 = hi2c->Mode;
6842
6843 /* In case of I2C still busy, try to regenerate a STOP manually */
6844 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
6845 (tmp1 != I2C_CR2_STOP) && \
6846 (tmp2 != HAL_I2C_MODE_SLAVE))
6847 {
6848 /* Generate Stop */
6849 hi2c->Instance->CR2 |= I2C_CR2_STOP;
6850
6851 /* Update Tick with new reference */
6852 tickstart = HAL_GetTick();
6853 }
6854
6855 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
6856 {
6857 /* Check for the Timeout */
6858 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
6859 {
6860 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
6861 hi2c->State = HAL_I2C_STATE_READY;
6862 hi2c->Mode = HAL_I2C_MODE_NONE;
6863
6864 /* Process Unlocked */
6865 __HAL_UNLOCK(hi2c);
6866
6867 status = HAL_ERROR;
6868 }
6869 }
6870 }
6871 }
6872 }
6873
6874 /* In case STOP Flag is detected, clear it */
6875 if (status == HAL_OK)
6876 {
6877 /* Clear STOP Flag */
6878 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6879 }
6880
6881 error_code |= HAL_I2C_ERROR_AF;
6882
6883 status = HAL_ERROR;
6884 }
6885
6886 /* Refresh Content of Status register */
6887 itflag = hi2c->Instance->ISR;
6888
6889 /* Then verify if an additional errors occurs */
6890 /* Check if a Bus error occurred */
6891 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
6892 {
6893 error_code |= HAL_I2C_ERROR_BERR;
6894
6895 /* Clear BERR flag */
6896 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
6897
6898 status = HAL_ERROR;
6899 }
6900
6901 /* Check if an Over-Run/Under-Run error occurred */
6902 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
6903 {
6904 error_code |= HAL_I2C_ERROR_OVR;
6905
6906 /* Clear OVR flag */
6907 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
6908
6909 status = HAL_ERROR;
6910 }
6911
6912 /* Check if an Arbitration Loss error occurred */
6913 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
6914 {
6915 error_code |= HAL_I2C_ERROR_ARLO;
6916
6917 /* Clear ARLO flag */
6918 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
6919
6920 status = HAL_ERROR;
6921 }
6922
6923 if (status != HAL_OK)
6924 {
6925 /* Flush TX register */
6926 I2C_Flush_TXDR(hi2c);
6927
6928 /* Clear Configuration Register 2 */
6929 I2C_RESET_CR2(hi2c);
6930
6931 hi2c->ErrorCode |= error_code;
6932 hi2c->State = HAL_I2C_STATE_READY;
6933 hi2c->Mode = HAL_I2C_MODE_NONE;
6934
6935 /* Process Unlocked */
6936 __HAL_UNLOCK(hi2c);
6937 }
6938
6939 return status;
6940 }
6941
6942 /**
6943 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
6944 * @param hi2c I2C handle.
6945 * @param DevAddress Specifies the slave address to be programmed.
6946 * @param Size Specifies the number of bytes to be programmed.
6947 * This parameter must be a value between 0 and 255.
6948 * @param Mode New state of the I2C START condition generation.
6949 * This parameter can be one of the following values:
6950 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
6951 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
6952 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
6953 * @param Request New state of the I2C START condition generation.
6954 * This parameter can be one of the following values:
6955 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
6956 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
6957 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
6958 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
6959 * @retval None
6960 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)6961 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
6962 uint32_t Request)
6963 {
6964 /* Check the parameters */
6965 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
6966 assert_param(IS_TRANSFER_MODE(Mode));
6967 assert_param(IS_TRANSFER_REQUEST(Request));
6968
6969 /* Declaration of tmp to prevent undefined behavior of volatile usage */
6970 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
6971 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
6972 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
6973
6974 /* update CR2 register */
6975 MODIFY_REG(hi2c->Instance->CR2, \
6976 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
6977 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
6978 I2C_CR2_START | I2C_CR2_STOP)), tmp);
6979 }
6980
6981 /**
6982 * @brief Manage the enabling of Interrupts.
6983 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6984 * the configuration information for the specified I2C.
6985 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
6986 * @retval None
6987 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)6988 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
6989 {
6990 uint32_t tmpisr = 0U;
6991
6992 if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
6993 (hi2c->XferISR == I2C_Slave_ISR_DMA))
6994 {
6995 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
6996 {
6997 /* Enable ERR, STOP, NACK and ADDR interrupts */
6998 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
6999 }
7000
7001 if (InterruptRequest == I2C_XFER_ERROR_IT)
7002 {
7003 /* Enable ERR and NACK interrupts */
7004 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7005 }
7006
7007 if (InterruptRequest == I2C_XFER_CPLT_IT)
7008 {
7009 /* Enable STOP interrupts */
7010 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7011 }
7012
7013 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7014 {
7015 /* Enable TC interrupts */
7016 tmpisr |= I2C_IT_TCI;
7017 }
7018 }
7019 else
7020 {
7021 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7022 {
7023 /* Enable ERR, STOP, NACK, and ADDR interrupts */
7024 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7025 }
7026
7027 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7028 {
7029 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7030 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7031 }
7032
7033 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7034 {
7035 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7036 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7037 }
7038
7039 if (InterruptRequest == I2C_XFER_ERROR_IT)
7040 {
7041 /* Enable ERR and NACK interrupts */
7042 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7043 }
7044
7045 if (InterruptRequest == I2C_XFER_CPLT_IT)
7046 {
7047 /* Enable STOP interrupts */
7048 tmpisr |= I2C_IT_STOPI;
7049 }
7050 }
7051
7052 /* Enable interrupts only at the end */
7053 /* to avoid the risk of I2C interrupt handle execution before */
7054 /* all interrupts requested done */
7055 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7056 }
7057
7058 /**
7059 * @brief Manage the disabling of Interrupts.
7060 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7061 * the configuration information for the specified I2C.
7062 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7063 * @retval None
7064 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7065 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7066 {
7067 uint32_t tmpisr = 0U;
7068
7069 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7070 {
7071 /* Disable TC and TXI interrupts */
7072 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7073
7074 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7075 {
7076 /* Disable NACK and STOP interrupts */
7077 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7078 }
7079 }
7080
7081 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7082 {
7083 /* Disable TC and RXI interrupts */
7084 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7085
7086 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7087 {
7088 /* Disable NACK and STOP interrupts */
7089 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7090 }
7091 }
7092
7093 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7094 {
7095 /* Disable ADDR, NACK and STOP interrupts */
7096 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7097 }
7098
7099 if (InterruptRequest == I2C_XFER_ERROR_IT)
7100 {
7101 /* Enable ERR and NACK interrupts */
7102 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7103 }
7104
7105 if (InterruptRequest == I2C_XFER_CPLT_IT)
7106 {
7107 /* Enable STOP interrupts */
7108 tmpisr |= I2C_IT_STOPI;
7109 }
7110
7111 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7112 {
7113 /* Enable TC interrupts */
7114 tmpisr |= I2C_IT_TCI;
7115 }
7116
7117 /* Disable interrupts only at the end */
7118 /* to avoid a breaking situation like at "t" time */
7119 /* all disable interrupts request are not done */
7120 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7121 }
7122
7123 /**
7124 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7125 * @param hi2c I2C handle.
7126 * @retval None
7127 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7128 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7129 {
7130 /* if user set XferOptions to I2C_OTHER_FRAME */
7131 /* it request implicitly to generate a restart condition */
7132 /* set XferOptions to I2C_FIRST_FRAME */
7133 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7134 {
7135 hi2c->XferOptions = I2C_FIRST_FRAME;
7136 }
7137 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7138 /* it request implicitly to generate a restart condition */
7139 /* then generate a stop condition at the end of transfer */
7140 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7141 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7142 {
7143 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7144 }
7145 else
7146 {
7147 /* Nothing to do */
7148 }
7149 }
7150
7151 /**
7152 * @}
7153 */
7154
7155 #endif /* HAL_I2C_MODULE_ENABLED */
7156 /**
7157 * @}
7158 */
7159
7160 /**
7161 * @}
7162 */
7163
