1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_DFSDM_H 38 #define STM32L4xx_HAL_DFSDM_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 45 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ 46 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 47 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 48 49 /* Includes ------------------------------------------------------------------*/ 50 #include "stm32l4xx_hal_def.h" 51 52 /** @addtogroup STM32L4xx_HAL_Driver 53 * @{ 54 */ 55 56 /** @addtogroup DFSDM 57 * @{ 58 */ 59 60 /* Exported types ------------------------------------------------------------*/ 61 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 62 * @{ 63 */ 64 65 /** 66 * @brief HAL DFSDM Channel states definition 67 */ 68 typedef enum 69 { 70 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 71 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 72 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 73 } HAL_DFSDM_Channel_StateTypeDef; 74 75 /** 76 * @brief DFSDM channel output clock structure definition 77 */ 78 typedef struct 79 { 80 FunctionalState Activation; /*!< Output clock enable/disable */ 81 uint32_t Selection; /*!< Output clock is system clock or audio clock. 82 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 83 uint32_t Divider; /*!< Output clock divider. 84 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 85 } DFSDM_Channel_OutputClockTypeDef; 86 87 /** 88 * @brief DFSDM channel input structure definition 89 */ 90 typedef struct 91 { 92 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 93 ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, 94 STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, 95 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products. 96 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 97 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 98 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 99 uint32_t Pins; /*!< Input pins are taken from same or following channel. 100 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 101 } DFSDM_Channel_InputTypeDef; 102 103 /** 104 * @brief DFSDM channel serial interface structure definition 105 */ 106 typedef struct 107 { 108 uint32_t Type; /*!< SPI or Manchester modes. 109 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 110 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 111 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 112 } DFSDM_Channel_SerialInterfaceTypeDef; 113 114 /** 115 * @brief DFSDM channel analog watchdog structure definition 116 */ 117 typedef struct 118 { 119 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 120 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 121 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 122 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 123 } DFSDM_Channel_AwdTypeDef; 124 125 /** 126 * @brief DFSDM channel init structure definition 127 */ 128 typedef struct 129 { 130 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 131 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 132 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 133 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 134 int32_t Offset; /*!< DFSDM channel offset. 135 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 136 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 137 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 138 } DFSDM_Channel_InitTypeDef; 139 140 /** 141 * @brief DFSDM channel handle structure definition 142 */ 143 typedef struct __DFSDM_Channel_HandleTypeDef 144 { 145 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 146 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 147 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 148 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 149 void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 150 void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 151 void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 152 void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 153 #endif 154 } DFSDM_Channel_HandleTypeDef; 155 156 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 157 /** 158 * @brief DFSDM channel callback ID enumeration definition 159 */ 160 typedef enum 161 { 162 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 163 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 164 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 165 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 166 } HAL_DFSDM_Channel_CallbackIDTypeDef; 167 168 /** 169 * @brief DFSDM channel callback pointer definition 170 */ 171 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 172 #endif 173 174 /** 175 * @brief HAL DFSDM Filter states definition 176 */ 177 typedef enum 178 { 179 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 180 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 181 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 182 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 183 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 184 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 185 } HAL_DFSDM_Filter_StateTypeDef; 186 187 /** 188 * @brief DFSDM filter regular conversion parameters structure definition 189 */ 190 typedef struct 191 { 192 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 193 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 194 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 195 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 196 } DFSDM_Filter_RegularParamTypeDef; 197 198 /** 199 * @brief DFSDM filter injected conversion parameters structure definition 200 */ 201 typedef struct 202 { 203 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 204 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 205 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 206 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 207 uint32_t ExtTrigger; /*!< External trigger. 208 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 209 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 210 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 211 } DFSDM_Filter_InjectedParamTypeDef; 212 213 /** 214 * @brief DFSDM filter parameters structure definition 215 */ 216 typedef struct 217 { 218 uint32_t SincOrder; /*!< Sinc filter order. 219 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 220 uint32_t Oversampling; /*!< Filter oversampling ratio. 221 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 222 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 223 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 224 } DFSDM_Filter_FilterParamTypeDef; 225 226 /** 227 * @brief DFSDM filter init structure definition 228 */ 229 typedef struct 230 { 231 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 232 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 233 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 234 } DFSDM_Filter_InitTypeDef; 235 236 /** 237 * @brief DFSDM filter handle structure definition 238 */ 239 typedef struct __DFSDM_Filter_HandleTypeDef 240 { 241 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 242 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 243 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 244 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 245 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 246 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 247 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 248 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 249 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 250 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 251 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 252 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 253 uint32_t ErrorCode; /*!< DFSDM filter error code */ 254 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 255 void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 256 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 257 void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 258 void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 259 void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 260 void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 261 void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 262 void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 263 void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 264 #endif 265 } DFSDM_Filter_HandleTypeDef; 266 267 /** 268 * @brief DFSDM filter analog watchdog parameters structure definition 269 */ 270 typedef struct 271 { 272 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 273 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 274 uint32_t Channel; /*!< Analog watchdog channel selection. 275 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 276 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 277 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 278 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 279 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 280 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 281 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 282 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 283 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 284 } DFSDM_Filter_AwdParamTypeDef; 285 286 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 287 /** 288 * @brief DFSDM filter callback ID enumeration definition 289 */ 290 typedef enum 291 { 292 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 293 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 294 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 295 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 296 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 297 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 298 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 299 } HAL_DFSDM_Filter_CallbackIDTypeDef; 300 301 /** 302 * @brief DFSDM filter callback pointer definition 303 */ 304 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 305 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 306 #endif 307 308 /** 309 * @} 310 */ 311 /* End of exported types -----------------------------------------------------*/ 312 313 /* Exported constants --------------------------------------------------------*/ 314 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 315 * @{ 316 */ 317 318 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 319 * @{ 320 */ 321 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 322 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 323 /** 324 * @} 325 */ 326 327 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 328 * @{ 329 */ 330 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 331 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 332 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 333 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 334 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 335 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 336 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 337 /** 338 * @} 339 */ 340 341 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 342 * @{ 343 */ 344 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 345 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 346 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 352 * @{ 353 */ 354 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 355 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 356 /** 357 * @} 358 */ 359 360 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 361 * @{ 362 */ 363 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 364 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 365 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 366 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 367 /** 368 * @} 369 */ 370 371 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 372 * @{ 373 */ 374 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 375 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 376 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 377 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 378 /** 379 * @} 380 */ 381 382 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 383 * @{ 384 */ 385 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 386 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 387 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 388 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 394 * @{ 395 */ 396 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 397 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 398 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 399 /** 400 * @} 401 */ 402 403 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 404 * @{ 405 */ 406 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 407 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 408 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 409 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 410 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 411 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 412 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 413 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 414 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 415 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 416 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 417 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 418 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 419 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 420 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 421 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 422 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 423 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 424 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 425 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 426 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 427 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 428 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 429 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 430 #else 431 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 432 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 433 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 434 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 435 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ 436 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ 437 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ 438 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 439 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ 440 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 441 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 442 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 448 * @{ 449 */ 450 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 451 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 452 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 453 /** 454 * @} 455 */ 456 457 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 458 * @{ 459 */ 460 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 461 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 462 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 463 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 464 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 465 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 466 /** 467 * @} 468 */ 469 470 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 471 * @{ 472 */ 473 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 474 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 475 /** 476 * @} 477 */ 478 479 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 480 * @{ 481 */ 482 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 483 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 484 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 485 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 486 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 487 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 488 #endif 489 /** 490 * @} 491 */ 492 493 /** @defgroup DFSDM_BreakSignals DFSDM break signals 494 * @{ 495 */ 496 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 497 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 498 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 499 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 500 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 506 * @{ 507 */ 508 /* DFSDM Channels ------------------------------------------------------------*/ 509 /* The DFSDM channels are defined as follows: 510 - in 16-bit LSB the channel mask is set 511 - in 16-bit MSB the channel number is set 512 e.g. for channel 5 definition: 513 - the channel mask is 0x00000020 (bit 5 is set) 514 - the channel number 5 is 0x00050000 515 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 516 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 517 #define DFSDM_CHANNEL_0 0x00000001U 518 #define DFSDM_CHANNEL_1 0x00010002U 519 #define DFSDM_CHANNEL_2 0x00020004U 520 #define DFSDM_CHANNEL_3 0x00030008U 521 #else 522 #define DFSDM_CHANNEL_0 0x00000001U 523 #define DFSDM_CHANNEL_1 0x00010002U 524 #define DFSDM_CHANNEL_2 0x00020004U 525 #define DFSDM_CHANNEL_3 0x00030008U 526 #define DFSDM_CHANNEL_4 0x00040010U 527 #define DFSDM_CHANNEL_5 0x00050020U 528 #define DFSDM_CHANNEL_6 0x00060040U 529 #define DFSDM_CHANNEL_7 0x00070080U 530 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 531 /** 532 * @} 533 */ 534 535 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 536 * @{ 537 */ 538 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 539 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 540 /** 541 * @} 542 */ 543 544 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 545 * @{ 546 */ 547 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 548 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 549 /** 550 * @} 551 */ 552 553 /** 554 * @} 555 */ 556 /* End of exported constants -------------------------------------------------*/ 557 558 /* Exported macros -----------------------------------------------------------*/ 559 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 560 * @{ 561 */ 562 563 /** @brief Reset DFSDM channel handle state. 564 * @param __HANDLE__ DFSDM channel handle. 565 * @retval None 566 */ 567 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 568 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 569 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 570 (__HANDLE__)->MspInitCallback = NULL; \ 571 (__HANDLE__)->MspDeInitCallback = NULL; \ 572 } while(0) 573 #else 574 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 575 #endif 576 577 /** @brief Reset DFSDM filter handle state. 578 * @param __HANDLE__ DFSDM filter handle. 579 * @retval None 580 */ 581 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 582 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 583 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 584 (__HANDLE__)->MspInitCallback = NULL; \ 585 (__HANDLE__)->MspDeInitCallback = NULL; \ 586 } while(0) 587 #else 588 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 589 #endif 590 591 /** 592 * @} 593 */ 594 /* End of exported macros ----------------------------------------------------*/ 595 596 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 597 /* Include DFSDM HAL Extension module */ 598 #include "stm32l4xx_hal_dfsdm_ex.h" 599 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 600 601 /* Exported functions --------------------------------------------------------*/ 602 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 603 * @{ 604 */ 605 606 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 607 * @{ 608 */ 609 /* Channel initialization and de-initialization functions *********************/ 610 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 611 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 612 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 613 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 614 615 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 616 /* Channel callbacks register/unregister functions ****************************/ 617 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 618 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 619 pDFSDM_Channel_CallbackTypeDef pCallback); 620 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 621 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 622 #endif 623 /** 624 * @} 625 */ 626 627 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 628 * @{ 629 */ 630 /* Channel operation functions ************************************************/ 631 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 632 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 633 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 634 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 635 636 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 637 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 638 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 639 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 640 641 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 642 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 643 644 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 645 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 646 647 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 648 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 649 /** 650 * @} 651 */ 652 653 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 654 * @{ 655 */ 656 /* Channel state function *****************************************************/ 657 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 658 /** 659 * @} 660 */ 661 662 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 663 * @{ 664 */ 665 /* Filter initialization and de-initialization functions *********************/ 666 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 667 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 668 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 669 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 670 671 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 672 /* Filter callbacks register/unregister functions ****************************/ 673 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 674 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 675 pDFSDM_Filter_CallbackTypeDef pCallback); 676 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 677 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 678 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 679 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 680 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 681 #endif 682 /** 683 * @} 684 */ 685 686 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 687 * @{ 688 */ 689 /* Filter control functions *********************/ 690 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 691 uint32_t Channel, 692 uint32_t ContinuousMode); 693 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 694 uint32_t Channel); 695 /** 696 * @} 697 */ 698 699 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 700 * @{ 701 */ 702 /* Filter operation functions *********************/ 703 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 704 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 705 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 706 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 707 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 708 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 709 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 710 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 711 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 712 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 713 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 714 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 715 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 716 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 717 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 718 DFSDM_Filter_AwdParamTypeDef *awdParam); 719 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 720 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 721 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 722 723 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 724 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 725 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 726 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 727 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 728 729 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 730 731 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 732 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 733 734 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 735 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 736 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 737 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 738 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 739 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 740 /** 741 * @} 742 */ 743 744 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 745 * @{ 746 */ 747 /* Filter state functions *****************************************************/ 748 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 749 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 750 /** 751 * @} 752 */ 753 754 /** 755 * @} 756 */ 757 /* End of exported functions -------------------------------------------------*/ 758 759 /* Private macros ------------------------------------------------------------*/ 760 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 761 * @{ 762 */ 763 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 764 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 765 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 766 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 767 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 768 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 769 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 770 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 771 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 772 #else 773 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 774 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 775 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 776 /* STM32L496xx || STM32L4A6xx || */ 777 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 778 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 779 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 780 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 781 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 782 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 783 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 784 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 785 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 786 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 787 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 788 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 789 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 790 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 791 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 792 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 793 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 794 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 795 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 796 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 797 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 798 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 799 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 800 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 801 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 802 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 803 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 804 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 805 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 806 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 807 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 808 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 809 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 810 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 811 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 812 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 813 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 814 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 815 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 816 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 817 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 818 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 819 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 820 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 821 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 822 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 823 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 824 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 825 #else 826 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 827 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 828 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 829 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 830 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 831 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 832 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 833 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 834 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 835 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 836 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 837 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 838 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 839 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 840 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 841 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 842 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 843 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 844 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 845 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 846 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 847 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 848 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 849 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 850 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 851 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 852 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 853 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 854 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 855 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 856 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 857 ((CHANNEL) == DFSDM_CHANNEL_3)) 858 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 859 #else 860 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 861 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 862 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 863 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 864 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 865 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 866 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 867 ((CHANNEL) == DFSDM_CHANNEL_7)) 868 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 869 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 870 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 871 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 872 /** 873 * @} 874 */ 875 /* End of private macros -----------------------------------------------------*/ 876 877 /** 878 * @} 879 */ 880 881 /** 882 * @} 883 */ 884 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 885 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 886 /* STM32L496xx || STM32L4A6xx || */ 887 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 888 889 #ifdef __cplusplus 890 } 891 #endif 892 893 #endif /* STM32L4xx_HAL_DFSDM_H */ 894 895 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 896
