1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_CORTEX_H 38 #define __STM32L4xx_HAL_CORTEX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @defgroup CORTEX CORTEX 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 57 * @{ 58 */ 59 60 #if (__MPU_PRESENT == 1) 61 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 62 * @{ 63 */ 64 typedef struct 65 { 66 uint8_t Enable; /*!< Specifies the status of the region. 67 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 68 uint8_t Number; /*!< Specifies the number of the region to protect. 69 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 70 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 71 uint8_t Size; /*!< Specifies the size of the region to protect. 72 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 73 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 74 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 75 uint8_t TypeExtField; /*!< Specifies the TEX field level. 76 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 77 uint8_t AccessPermission; /*!< Specifies the region access permission type. 78 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 79 uint8_t DisableExec; /*!< Specifies the instruction access status. 80 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 81 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 82 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 83 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 84 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 85 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 86 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 87 }MPU_Region_InitTypeDef; 88 /** 89 * @} 90 */ 91 #endif /* __MPU_PRESENT */ 92 93 /** 94 * @} 95 */ 96 97 /* Exported constants --------------------------------------------------------*/ 98 99 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 100 * @{ 101 */ 102 103 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 104 * @{ 105 */ 106 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 107 4 bits for subpriority */ 108 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 109 3 bits for subpriority */ 110 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 111 2 bits for subpriority */ 112 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 113 1 bit for subpriority */ 114 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 115 0 bit for subpriority */ 116 /** 117 * @} 118 */ 119 120 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 121 * @{ 122 */ 123 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 124 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 125 /** 126 * @} 127 */ 128 129 #if (__MPU_PRESENT == 1) 130 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 131 * @{ 132 */ 133 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 134 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 135 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 136 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 137 /** 138 * @} 139 */ 140 141 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 142 * @{ 143 */ 144 #define MPU_REGION_ENABLE ((uint8_t)0x01) 145 #define MPU_REGION_DISABLE ((uint8_t)0x00) 146 /** 147 * @} 148 */ 149 150 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 151 * @{ 152 */ 153 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 154 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 155 /** 156 * @} 157 */ 158 159 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 160 * @{ 161 */ 162 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 163 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 164 /** 165 * @} 166 */ 167 168 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 169 * @{ 170 */ 171 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 172 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 173 /** 174 * @} 175 */ 176 177 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 178 * @{ 179 */ 180 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 181 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 182 /** 183 * @} 184 */ 185 186 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 187 * @{ 188 */ 189 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 190 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 191 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 192 /** 193 * @} 194 */ 195 196 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 197 * @{ 198 */ 199 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 200 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 201 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 202 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 203 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 204 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 205 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 206 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 207 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 208 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 209 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 210 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 211 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 212 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 213 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 214 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 215 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 216 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 217 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 218 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 219 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 220 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 221 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 222 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 223 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 224 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 225 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 226 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 227 /** 228 * @} 229 */ 230 231 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 232 * @{ 233 */ 234 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 235 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 236 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 237 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 238 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 239 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 240 /** 241 * @} 242 */ 243 244 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 245 * @{ 246 */ 247 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 248 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 249 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 250 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 251 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 252 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 253 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 254 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 255 /** 256 * @} 257 */ 258 #endif /* __MPU_PRESENT */ 259 260 /** 261 * @} 262 */ 263 264 /* Exported macros -----------------------------------------------------------*/ 265 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 266 * @{ 267 */ 268 269 /** 270 * @} 271 */ 272 273 /* Exported functions --------------------------------------------------------*/ 274 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 275 * @{ 276 */ 277 278 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 279 * @brief Initialization and Configuration functions 280 * @{ 281 */ 282 /* Initialization and Configuration functions *****************************/ 283 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 284 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 285 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 286 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 287 void HAL_NVIC_SystemReset(void); 288 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 289 290 /** 291 * @} 292 */ 293 294 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 295 * @brief Cortex control functions 296 * @{ 297 */ 298 /* Peripheral Control functions ***********************************************/ 299 uint32_t HAL_NVIC_GetPriorityGrouping(void); 300 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 301 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 302 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 303 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 304 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 305 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 306 void HAL_SYSTICK_IRQHandler(void); 307 void HAL_SYSTICK_Callback(void); 308 309 #if (__MPU_PRESENT == 1) 310 void HAL_MPU_Enable(uint32_t MPU_Control); 311 void HAL_MPU_Disable(void); 312 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 313 #endif /* __MPU_PRESENT */ 314 /** 315 * @} 316 */ 317 318 /** 319 * @} 320 */ 321 322 /* Private types -------------------------------------------------------------*/ 323 /* Private variables ---------------------------------------------------------*/ 324 /* Private constants ---------------------------------------------------------*/ 325 /* Private macros ------------------------------------------------------------*/ 326 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 327 * @{ 328 */ 329 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 330 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 331 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 332 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 333 ((GROUP) == NVIC_PRIORITYGROUP_4)) 334 335 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 336 337 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 338 339 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 340 341 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 342 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 343 344 #if (__MPU_PRESENT == 1) 345 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 346 ((STATE) == MPU_REGION_DISABLE)) 347 348 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 349 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 350 351 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 352 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 353 354 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 355 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 356 357 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 358 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 359 360 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 361 ((TYPE) == MPU_TEX_LEVEL1) || \ 362 ((TYPE) == MPU_TEX_LEVEL2)) 363 364 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 365 ((TYPE) == MPU_REGION_PRIV_RW) || \ 366 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 367 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 368 ((TYPE) == MPU_REGION_PRIV_RO) || \ 369 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 370 371 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 372 ((NUMBER) == MPU_REGION_NUMBER1) || \ 373 ((NUMBER) == MPU_REGION_NUMBER2) || \ 374 ((NUMBER) == MPU_REGION_NUMBER3) || \ 375 ((NUMBER) == MPU_REGION_NUMBER4) || \ 376 ((NUMBER) == MPU_REGION_NUMBER5) || \ 377 ((NUMBER) == MPU_REGION_NUMBER6) || \ 378 ((NUMBER) == MPU_REGION_NUMBER7)) 379 380 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 381 ((SIZE) == MPU_REGION_SIZE_64B) || \ 382 ((SIZE) == MPU_REGION_SIZE_128B) || \ 383 ((SIZE) == MPU_REGION_SIZE_256B) || \ 384 ((SIZE) == MPU_REGION_SIZE_512B) || \ 385 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 386 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 387 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 388 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 389 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 390 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 391 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 392 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 393 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 394 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 395 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 396 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 397 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 398 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 399 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 400 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 401 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 402 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 403 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 404 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 405 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 406 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 407 ((SIZE) == MPU_REGION_SIZE_4GB)) 408 409 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 410 #endif /* __MPU_PRESENT */ 411 412 /** 413 * @} 414 */ 415 416 /* Private functions ---------------------------------------------------------*/ 417 418 /** 419 * @} 420 */ 421 422 /** 423 * @} 424 */ 425 426 #ifdef __cplusplus 427 } 428 #endif 429 430 #endif /* __STM32L4xx_HAL_CORTEX_H */ 431 432 433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 434
