1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L4xx_HAL_ADC_EX_H 38 #define __STM32L4xx_HAL_ADC_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 /** @addtogroup STM32L4xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup ADCEx 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief ADC Injected Conversion Oversampling structure definition 62 */ 63 typedef struct 64 { 65 uint32_t Ratio; /*!< Configures the oversampling ratio. 66 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 67 68 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 69 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 70 }ADC_InjOversamplingTypeDef; 71 72 /** 73 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 74 * @note Parameters of this structure are shared within 2 scopes: 75 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 76 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 77 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 78 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 79 * ADC state can be either: 80 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 81 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 82 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 83 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 84 * on ADC groups regular and injected. 85 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 86 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 87 */ 88 typedef struct 89 { 90 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 91 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 92 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 93 94 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 95 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 96 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 97 the new channel setting (or parameter number of conversions adjusted) */ 98 99 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 100 Unit: ADC clock cycles. 101 Conversion time is the addition of sampling time and processing time 102 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 103 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 104 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 105 It overwrites the last setting. 106 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 107 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 108 Refer to device datasheet for timings values. */ 109 110 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 111 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 112 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 113 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 114 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 115 It overwrites the last setting. 116 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 117 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 118 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 119 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 120 of another parameter update on the fly) */ 121 122 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 123 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 124 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 125 126 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 127 Offset value must be a positive number. 128 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 129 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 130 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 131 without continuous mode or external trigger that could launch a conversion). */ 132 133 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 134 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 135 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 136 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 137 configure a channel on injected group can impact the configuration of other channels previously set. */ 138 139 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 140 (main sequence subdivided in successive parts). 141 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 142 Discontinuous mode can be enabled only if continuous mode is disabled. 143 This parameter can be set to ENABLE or DISABLE. 144 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 145 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 146 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 147 configure a channel on injected group can impact the configuration of other channels previously set. */ 148 149 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 150 This parameter can be set to ENABLE or DISABLE. 151 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 152 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 153 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 154 To maintain JAUTO always enabled, DMA must be configured in circular mode. 155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 156 configure a channel on injected group can impact the configuration of other channels previously set. */ 157 158 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 159 This parameter can be set to ENABLE or DISABLE. 160 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 161 new injected context is set when queue is full, error is triggered by interruption and through function 162 'HAL_ADCEx_InjectedQueueOverflowCallback'. 163 Caution: This feature request that the sequence is fully configured before injected conversion start. 164 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 165 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 166 configure a channel on injected group can impact the configuration of other channels previously set. 167 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 168 169 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 170 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 171 This parameter can be a value of @ref ADC_injected_external_trigger_source. 172 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 173 configure a channel on injected group can impact the configuration of other channels previously set. */ 174 175 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 176 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 177 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 178 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 179 configure a channel on injected group can impact the configuration of other channels previously set. */ 180 181 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 182 This parameter can be set to ENABLE or DISABLE. 183 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 184 185 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 186 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 187 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 188 }ADC_InjectionConfTypeDef; 189 190 #if defined(ADC_MULTIMODE_SUPPORT) 191 /** 192 * @brief Structure definition of ADC multimode 193 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 194 * Both Master and Slave ADCs must be disabled. 195 */ 196 typedef struct 197 { 198 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 199 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 200 201 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 202 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 203 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 204 205 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 206 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 207 Delay range depends on selected resolution: 208 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 209 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 210 }ADC_MultiModeTypeDef; 211 #endif /* ADC_MULTIMODE_SUPPORT */ 212 213 /** 214 * @} 215 */ 216 217 /* Exported constants --------------------------------------------------------*/ 218 219 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 220 * @{ 221 */ 222 223 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 224 * @{ 225 */ 226 /* ADC group regular trigger sources for all ADC instances */ 227 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 228 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 229 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 230 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 231 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 232 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 233 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 234 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 235 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 236 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 237 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 238 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 239 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 240 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 241 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 242 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 243 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 244 /** 245 * @} 246 */ 247 248 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 249 * @{ 250 */ 251 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 252 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 253 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 254 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 255 /** 256 * @} 257 */ 258 259 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 260 * @{ 261 */ 262 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 263 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 264 /** 265 * @} 266 */ 267 268 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 269 * @{ 270 */ 271 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 272 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 273 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 274 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 275 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 281 * @{ 282 */ 283 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 284 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 285 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 286 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 287 /** 288 * @} 289 */ 290 291 #if defined(ADC_MULTIMODE_SUPPORT) 292 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 293 * @{ 294 */ 295 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 296 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 297 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 298 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 299 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 300 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 301 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 302 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 303 304 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 305 * @{ 306 */ 307 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 308 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 309 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 310 /** 311 * @} 312 */ 313 314 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 315 * @{ 316 */ 317 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 318 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 319 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 320 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 321 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 322 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 323 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 324 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 325 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 326 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 327 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 328 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 329 /** 330 * @} 331 */ 332 333 /** 334 * @} 335 */ 336 #endif /* ADC_MULTIMODE_SUPPORT */ 337 338 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 339 * @{ 340 */ 341 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 342 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 343 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 349 * @{ 350 */ 351 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 352 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 353 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 354 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 355 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 356 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 357 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 358 #else 359 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 360 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 361 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 362 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 363 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 364 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 365 #endif 366 /** 367 * @} 368 */ 369 370 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 371 * @{ 372 */ 373 #if defined(ADC_SMPR1_SMPPLUS) 374 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 375 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 376 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 377 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 378 #else 379 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 380 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 381 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 382 ADC_SMPR1_SMP0) 383 #endif 384 /** 385 * @} 386 */ 387 388 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 389 * @{ 390 */ 391 /* ADC_CFGR fields of parameters that can be updated when no conversion 392 (neither regular nor injected) is on-going */ 393 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 394 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 395 #else 396 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 397 #endif 398 /** 399 * @} 400 */ 401 402 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 403 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 404 * @{ 405 */ 406 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 407 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 408 /** 409 * @} 410 */ 411 #endif 412 413 /** 414 * @} 415 */ 416 417 /* Exported macros -----------------------------------------------------------*/ 418 419 #if defined(ADC_MULTIMODE_SUPPORT) 420 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 421 * @{ 422 */ 423 424 /** @brief Force ADC instance in multimode mode independent (multimode disable). 425 * @note This macro must be used only in case of transition from multimode 426 * to mode independent and in case of unknown previous state, 427 * to ensure ADC configuration is in mode independent. 428 * @note Standard way of multimode configuration change is done from 429 * HAL ADC handle of ADC master using function 430 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 431 * Usage of this macro is not the Standard way of multimode 432 * configuration and can lead to have HAL ADC handles status 433 * misaligned. Usage of this macro must be limited to cases 434 * mentionned above. 435 * @param __HANDLE__ ADC handle. 436 * @retval None 437 */ 438 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 439 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 440 441 /** 442 * @} 443 */ 444 #endif /* ADC_MULTIMODE_SUPPORT */ 445 446 /* Private macros ------------------------------------------------------------*/ 447 448 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 449 * @{ 450 */ 451 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 452 /* code of final user. */ 453 454 /** 455 * @brief Test if conversion trigger of injected group is software start 456 * or external trigger. 457 * @param __HANDLE__ ADC handle. 458 * @retval SET (software start) or RESET (external trigger). 459 */ 460 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 461 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 462 463 /** 464 * @brief Check if conversion is on going on regular or injected groups. 465 * @param __HANDLE__ ADC handle. 466 * @retval SET (conversion is on going) or RESET (no conversion is on going). 467 */ 468 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 469 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 470 ) ? RESET : SET) 471 472 /** 473 * @brief Check if conversion is on going on injected group. 474 * @param __HANDLE__ ADC handle. 475 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 476 */ 477 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 478 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 479 480 /** 481 * @brief Check whether or not ADC is independent. 482 * @param __HANDLE__ ADC handle. 483 * @note When multimode feature is not available, the macro always returns SET. 484 * @retval SET (ADC is independent) or RESET (ADC is not). 485 */ 486 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 487 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 488 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 489 )? \ 490 SET \ 491 : \ 492 RESET \ 493 ) 494 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 495 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 496 #elif defined (STM32L412xx) || defined (STM32L422xx) 497 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 498 #endif 499 500 /** 501 * @brief Set the selected injected Channel rank. 502 * @param __CHANNELNB__ Channel number. 503 * @param __RANKNB__ Rank number. 504 * @retval None 505 */ 506 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 507 508 /** 509 * @brief Configure ADC injected context queue 510 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 511 * @retval None 512 */ 513 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 514 515 /** 516 * @brief Configure ADC discontinuous conversion mode for injected group 517 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 518 * @retval None 519 */ 520 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 521 522 /** 523 * @brief Configure ADC discontinuous conversion mode for regular group 524 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 525 * @retval None 526 */ 527 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 528 529 /** 530 * @brief Configure the number of discontinuous conversions for regular group. 531 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 532 * @retval None 533 */ 534 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 535 536 /** 537 * @brief Configure the ADC auto delay mode. 538 * @param __AUTOWAIT__ Auto delay bit enable or disable. 539 * @retval None 540 */ 541 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 542 543 /** 544 * @brief Configure ADC continuous conversion mode. 545 * @param __CONTINUOUS_MODE__ Continuous mode. 546 * @retval None 547 */ 548 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 549 550 /** 551 * @brief Configure the ADC DMA continuous request. 552 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 553 * @retval None 554 */ 555 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 556 557 /** 558 * @brief Configure the channel number into offset OFRx register. 559 * @param __CHANNEL__ ADC Channel. 560 * @retval None 561 */ 562 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 563 564 /** 565 * @brief Configure the channel number into differential mode selection register. 566 * @param __CHANNEL__ ADC Channel. 567 * @retval None 568 */ 569 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 570 571 /** 572 * @brief Configure calibration factor in differential mode to be set into calibration register. 573 * @param __CALIBRATION_FACTOR__ Calibration factor value. 574 * @retval None 575 */ 576 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 577 578 /** 579 * @brief Calibration factor in differential mode to be retrieved from calibration register. 580 * @param __CALIBRATION_FACTOR__ Calibration factor value. 581 * @retval None 582 */ 583 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 584 585 /** 586 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 587 * @param __THRESHOLD__ Threshold value. 588 * @retval None 589 */ 590 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 591 592 #if defined(ADC_MULTIMODE_SUPPORT) 593 /** 594 * @brief Configure the ADC DMA continuous request for ADC multimode. 595 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 596 * @retval None 597 */ 598 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 599 #endif /* ADC_MULTIMODE_SUPPORT */ 600 601 /** 602 * @brief Shift the offset with respect to the selected ADC resolution. 603 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 604 * If resolution 12 bits, no shift. 605 * If resolution 10 bits, shift of 2 ranks on the left. 606 * If resolution 8 bits, shift of 4 ranks on the left. 607 * If resolution 6 bits, shift of 6 ranks on the left. 608 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 609 * @param __HANDLE__ ADC handle 610 * @param __OFFSET__ Value to be shifted 611 * @retval None 612 */ 613 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 614 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 615 616 /** 617 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 618 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 619 * If resolution 12 bits, no shift. 620 * If resolution 10 bits, shift of 2 ranks on the left. 621 * If resolution 8 bits, shift of 4 ranks on the left. 622 * If resolution 6 bits, shift of 6 ranks on the left. 623 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 624 * @param __HANDLE__ ADC handle 625 * @param __THRESHOLD__ Value to be shifted 626 * @retval None 627 */ 628 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 629 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 630 631 /** 632 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 633 * @note Thresholds have to be left-aligned on bit 7. 634 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 635 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 636 * If resolution 8 bits, no shift. 637 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 638 * @param __HANDLE__ ADC handle 639 * @param __THRESHOLD__ Value to be shifted 640 * @retval None 641 */ 642 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 643 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 644 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 645 ((__THRESHOLD__) << 2UL) \ 646 ) 647 648 /** 649 * @brief Clear Common Control Register. 650 * @param __HANDLE__ ADC handle. 651 * @retval None 652 */ 653 #if defined(ADC_MULTIMODE_SUPPORT) 654 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 655 ADC_CCR_PRESC | \ 656 ADC_CCR_VBATEN | \ 657 ADC_CCR_TSEN | \ 658 ADC_CCR_VREFEN | \ 659 ADC_CCR_MDMA | \ 660 ADC_CCR_DMACFG | \ 661 ADC_CCR_DELAY | \ 662 ADC_CCR_DUAL ) 663 #else 664 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 665 ADC_CCR_PRESC | \ 666 ADC_CCR_VBATEN | \ 667 ADC_CCR_TSEN | \ 668 ADC_CCR_VREFEN ) 669 670 #endif /* ADC_MULTIMODE_SUPPORT */ 671 672 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 673 /** 674 * @brief Set handle instance of the ADC slave associated to the ADC master. 675 * @param __HANDLE_MASTER__ ADC master handle. 676 * @param __HANDLE_SLAVE__ ADC slave handle. 677 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 678 * @retval None 679 */ 680 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 681 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 682 #endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 683 684 685 /** 686 * @brief Verify the ADC instance connected to the temperature sensor. 687 * @param __HANDLE__ ADC handle. 688 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 689 */ 690 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 691 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 692 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 693 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 694 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 695 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 696 #endif 697 698 /** 699 * @brief Verify the ADC instance connected to the battery voltage VBAT. 700 * @param __HANDLE__ ADC handle. 701 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 702 */ 703 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 704 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 705 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 706 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 707 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 708 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 709 #endif 710 711 /** 712 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 713 * @param __HANDLE__ ADC handle. 714 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 715 */ 716 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 717 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 718 719 /** 720 * @brief Verify the length of scheduled injected conversions group. 721 * @param __LENGTH__ number of programmed conversions. 722 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 723 */ 724 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 725 726 /** 727 * @brief Calibration factor size verification (7 bits maximum). 728 * @param __CALIBRATION_FACTOR__ Calibration factor value. 729 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 730 */ 731 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 732 733 734 /** 735 * @brief Verify the ADC channel setting. 736 * @param __HANDLE__ ADC handle. 737 * @param __CHANNEL__ programmed ADC channel. 738 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 739 */ 740 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 741 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 742 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 743 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 744 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 745 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 746 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 747 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 748 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 749 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 750 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 751 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 752 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 753 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 754 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 755 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 756 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 757 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 758 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 759 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 760 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 761 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 762 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 763 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ 764 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) 765 #elif defined (STM32L412xx) || defined (STM32L422xx) 766 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 767 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 768 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 769 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 770 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 771 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 772 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 773 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 774 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 775 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 776 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 777 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 778 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 779 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 780 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 781 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 782 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 783 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 784 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 785 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 786 ((((__HANDLE__)->Instance) == ADC2) && \ 787 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 788 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 789 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 790 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 791 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 792 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 793 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 794 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 795 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 796 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 797 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 798 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 799 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 800 ((__CHANNEL__) == ADC_CHANNEL_16) ))) 801 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 802 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 803 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 804 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 805 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 806 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 807 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 808 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 809 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 810 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 811 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 812 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 813 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 814 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 815 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 816 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 817 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 818 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 819 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 820 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 821 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 822 ((((__HANDLE__)->Instance) == ADC2) && \ 823 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 824 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 825 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 826 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 827 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 828 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 829 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 830 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 831 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 832 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 833 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 834 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 835 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 836 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 837 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 838 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 839 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 840 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 841 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 842 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ 843 ((((__HANDLE__)->Instance) == ADC3) && \ 844 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 845 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 846 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 847 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 848 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 849 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 850 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 851 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 852 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 853 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 854 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 855 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 856 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 857 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 858 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 859 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 860 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ 861 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) 862 #endif 863 864 /** 865 * @brief Verify the ADC channel setting in differential mode. 866 * @param __HANDLE__ ADC handle. 867 * @param __CHANNEL__ programmed ADC channel. 868 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 869 */ 870 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 871 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 872 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 873 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 874 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 875 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 876 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 877 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 878 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 879 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 880 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 881 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 882 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 883 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 884 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 885 ((__CHANNEL__) == ADC_CHANNEL_15) ) 886 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 887 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 888 channels 0, 16 to 18 can be only used in single-ended mode. 889 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 890 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 891 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 892 (((__HANDLE__)->Instance) == ADC2)) && \ 893 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 894 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 895 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 896 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 897 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 898 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 899 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 900 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 901 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 902 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 903 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 904 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 905 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 906 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 907 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 908 ((((__HANDLE__)->Instance) == ADC3) && \ 909 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 910 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 911 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 912 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 913 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 914 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 915 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 916 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 917 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 918 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 919 #endif 920 921 /** 922 * @brief Verify the ADC single-ended input or differential mode setting. 923 * @param __SING_DIFF__ programmed channel setting. 924 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 925 */ 926 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 927 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 928 929 /** 930 * @brief Verify the ADC offset management setting. 931 * @param __OFFSET_NUMBER__ ADC offset management. 932 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 933 */ 934 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 935 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 936 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 937 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 938 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 939 940 /** 941 * @brief Verify the ADC injected channel setting. 942 * @param __CHANNEL__ programmed ADC injected channel. 943 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 944 */ 945 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 946 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 947 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 948 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 949 950 /** 951 * @brief Verify the ADC injected conversions external trigger. 952 * @param __HANDLE__ ADC handle. 953 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 954 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 955 */ 956 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 957 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 958 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 959 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 960 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 961 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 962 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 963 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 964 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 965 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 966 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 967 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 968 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 969 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 970 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 971 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 972 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 973 974 /** 975 * @brief Verify the ADC edge trigger setting for injected group. 976 * @param __EDGE__ programmed ADC edge trigger setting. 977 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 978 */ 979 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 980 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 981 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 982 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 983 984 #if defined(ADC_MULTIMODE_SUPPORT) 985 /** 986 * @brief Verify the ADC multimode setting. 987 * @param __MODE__ programmed ADC multimode setting. 988 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 989 */ 990 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 991 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 992 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 993 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 994 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 995 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 996 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 997 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 998 999 /** 1000 * @brief Verify the ADC multimode DMA access setting. 1001 * @param __MODE__ programmed ADC multimode DMA access setting. 1002 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1003 */ 1004 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 1005 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 1006 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 1007 1008 /** 1009 * @brief Verify the ADC multimode delay setting. 1010 * @param __DELAY__ programmed ADC multimode delay setting. 1011 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1012 */ 1013 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1014 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1015 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1016 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1017 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1018 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1019 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1020 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1021 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 1022 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 1023 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 1024 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 1025 #endif /* ADC_MULTIMODE_SUPPORT */ 1026 1027 /** 1028 * @brief Verify the ADC analog watchdog setting. 1029 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1030 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1031 */ 1032 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1033 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1034 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1035 1036 /** 1037 * @brief Verify the ADC analog watchdog mode setting. 1038 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1039 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1040 */ 1041 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1042 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1043 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1044 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1045 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1046 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1047 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1048 1049 /** 1050 * @brief Verify the ADC conversion (regular or injected or both). 1051 * @param __CONVERSION__ ADC conversion group. 1052 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1053 */ 1054 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1055 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1056 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1057 1058 /** 1059 * @brief Verify the ADC event type. 1060 * @param __EVENT__ ADC event. 1061 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1062 */ 1063 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1064 ((__EVENT__) == ADC_AWD_EVENT) || \ 1065 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1066 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1067 ((__EVENT__) == ADC_OVR_EVENT) || \ 1068 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1069 1070 /** 1071 * @brief Verify the ADC oversampling ratio. 1072 * @param __RATIO__ programmed ADC oversampling ratio. 1073 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1074 */ 1075 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 1076 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 1077 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 1078 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 1079 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 1080 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 1081 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 1082 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 1083 1084 /** 1085 * @brief Verify the ADC oversampling shift. 1086 * @param __SHIFT__ programmed ADC oversampling shift. 1087 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1088 */ 1089 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1090 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1091 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1092 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1093 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1094 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1095 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1096 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1097 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 1098 1099 /** 1100 * @brief Verify the ADC oversampling triggered mode. 1101 * @param __MODE__ programmed ADC oversampling triggered mode. 1102 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1103 */ 1104 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1105 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1106 1107 /** 1108 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1109 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1110 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1111 */ 1112 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1113 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1114 1115 /** 1116 * @brief Verify the DFSDM mode configuration. 1117 * @param __HANDLE__ ADC handle. 1118 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1119 * this reason, the input parameter is the ADC handle and not the configuration parameter 1120 * directly. 1121 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1122 */ 1123 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1124 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1125 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1126 #else 1127 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1128 #endif 1129 1130 /** 1131 * @brief Return the DFSDM configuration mode. 1132 * @param __HANDLE__ ADC handle. 1133 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1134 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1135 * directly. 1136 * @retval DFSDM configuration mode 1137 */ 1138 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 1139 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1140 #else 1141 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1142 #endif 1143 1144 /** 1145 * @} 1146 */ 1147 1148 1149 /* Exported functions --------------------------------------------------------*/ 1150 /** @addtogroup ADCEx_Exported_Functions 1151 * @{ 1152 */ 1153 1154 /** @addtogroup ADCEx_Exported_Functions_Group1 1155 * @{ 1156 */ 1157 /* IO operation functions *****************************************************/ 1158 1159 /* ADC calibration */ 1160 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); 1161 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1162 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 1163 1164 /* Blocking mode: Polling */ 1165 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 1166 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 1167 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1168 1169 /* Non-blocking mode: Interruption */ 1170 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 1171 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 1172 1173 #if defined(ADC_MULTIMODE_SUPPORT) 1174 /* ADC multimode */ 1175 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1176 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1177 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1178 #endif /* ADC_MULTIMODE_SUPPORT */ 1179 1180 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1181 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 1182 1183 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1184 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 1185 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); 1186 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); 1187 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); 1188 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); 1189 1190 /* ADC group regular conversions stop */ 1191 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); 1192 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); 1193 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); 1194 #if defined(ADC_MULTIMODE_SUPPORT) 1195 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); 1196 #endif /* ADC_MULTIMODE_SUPPORT */ 1197 1198 /** 1199 * @} 1200 */ 1201 1202 /** @addtogroup ADCEx_Exported_Functions_Group2 1203 * @{ 1204 */ 1205 /* Peripheral Control functions ***********************************************/ 1206 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 1207 #if defined(ADC_MULTIMODE_SUPPORT) 1208 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1209 #endif /* ADC_MULTIMODE_SUPPORT */ 1210 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); 1211 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); 1212 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); 1213 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); 1214 1215 /** 1216 * @} 1217 */ 1218 1219 /** 1220 * @} 1221 */ 1222 1223 /** 1224 * @} 1225 */ 1226 1227 /** 1228 * @} 1229 */ 1230 1231 #ifdef __cplusplus 1232 } 1233 #endif 1234 1235 #endif /* __STM32L4xx_HAL_ADC_EX_H */ 1236 1237 1238 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1239
