1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2017 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_H 22 #define STM32L4xx_HAL_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_conf.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HAL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup HAL_Exported_Types HAL Exported Types 41 * @{ 42 */ 43 44 /** @defgroup HAL_TICK_FREQ Tick Frequency 45 * @{ 46 */ 47 typedef enum 48 { 49 HAL_TICK_FREQ_10HZ = 100U, 50 HAL_TICK_FREQ_100HZ = 10U, 51 HAL_TICK_FREQ_1KHZ = 1U, 52 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 53 } HAL_TickFreqTypeDef; 54 /** 55 * @} 56 */ 57 58 /** 59 * @} 60 */ 61 62 /* Exported constants --------------------------------------------------------*/ 63 64 /** @defgroup HAL_Exported_Constants HAL Exported Constants 65 * @{ 66 */ 67 68 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 69 * @{ 70 */ 71 72 /** @defgroup SYSCFG_BootMode Boot Mode 73 * @{ 74 */ 75 #define SYSCFG_BOOT_MAINFLASH 0U 76 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 77 78 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 79 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 80 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 81 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 82 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 83 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 84 /* STM32L496xx || STM32L4A6xx || */ 85 /* STM32L4P5xx || STM32L4Q5xx || */ 86 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 87 88 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 89 90 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 91 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 92 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 93 #else 94 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 95 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 96 97 /** 98 * @} 99 */ 100 101 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 102 * @{ 103 */ 104 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 105 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 106 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 107 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 108 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 109 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 110 111 /** 112 * @} 113 */ 114 115 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 116 * @{ 117 */ 118 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 119 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 120 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 121 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 122 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 123 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 124 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 125 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 126 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 127 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 128 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 129 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 130 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 131 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 132 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 133 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 134 #if defined(SYSCFG_SWPR_PAGE31) 135 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 136 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 137 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 138 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 139 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 140 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 141 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 142 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 143 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 144 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 145 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 146 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 147 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 148 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 149 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 150 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 151 #endif /* SYSCFG_SWPR_PAGE31 */ 152 153 /** 154 * @} 155 */ 156 157 #if defined(SYSCFG_SWPR2_PAGE63) 158 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 159 * @{ 160 */ 161 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 162 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 163 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 164 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 165 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 166 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 167 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 168 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 169 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 170 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 171 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 172 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 173 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 174 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 175 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 176 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 177 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 178 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 179 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 180 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 181 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 182 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 183 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 184 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 185 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 186 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 187 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 188 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 189 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 190 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 191 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 192 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 193 194 /** 195 * @} 196 */ 197 #endif /* SYSCFG_SWPR2_PAGE63 */ 198 199 #if defined(VREFBUF) 200 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 201 * @{ 202 */ 203 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 204 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 205 206 /** 207 * @} 208 */ 209 210 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 211 * @{ 212 */ 213 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 214 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 215 216 /** 217 * @} 218 */ 219 #endif /* VREFBUF */ 220 221 /** @defgroup SYSCFG_flags_definition Flags 222 * @{ 223 */ 224 225 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 226 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 227 228 /** 229 * @} 230 */ 231 232 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 233 * @{ 234 */ 235 236 /** @brief Fast-mode Plus driving capability on a specific GPIO 237 */ 238 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 239 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 240 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 241 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 242 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 243 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 244 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 245 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 246 247 /** 248 * @} 249 */ 250 251 /** 252 * @} 253 */ 254 255 /** 256 * @} 257 */ 258 259 /* Exported macros -----------------------------------------------------------*/ 260 /** @defgroup HAL_Exported_Macros HAL Exported Macros 261 * @{ 262 */ 263 264 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 265 * @{ 266 */ 267 268 /** @brief Freeze/Unfreeze Peripherals in Debug mode 269 */ 270 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 271 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 272 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 273 #endif 274 275 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 276 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 277 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 278 #endif 279 280 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 281 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 282 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 283 #endif 284 285 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 286 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 287 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 288 #endif 289 290 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 291 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 292 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 293 #endif 294 295 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 296 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 297 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 298 #endif 299 300 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 301 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 302 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 303 #endif 304 305 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 306 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 307 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 308 #endif 309 310 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 311 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 312 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 313 #endif 314 315 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 316 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 317 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 318 #endif 319 320 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 321 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 322 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 323 #endif 324 325 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 326 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 327 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 328 #endif 329 330 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 331 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 332 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 333 #endif 334 335 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 336 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 337 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 338 #endif 339 340 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 341 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 342 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 343 #endif 344 345 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 346 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 347 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 348 #endif 349 350 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 351 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 352 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 353 #endif 354 355 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 356 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 357 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 358 #endif 359 360 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 361 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 362 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 363 #endif 364 365 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 366 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 367 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 368 #endif 369 370 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 371 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 372 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 373 #endif 374 375 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 376 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 377 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 378 #endif 379 380 /** 381 * @} 382 */ 383 384 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 385 * @{ 386 */ 387 388 /** @brief Main Flash memory mapped at 0x00000000. 389 */ 390 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 391 392 /** @brief System Flash memory mapped at 0x00000000. 393 */ 394 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 395 396 /** @brief Embedded SRAM mapped at 0x00000000. 397 */ 398 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 399 400 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 401 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 402 defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \ 403 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 404 405 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 406 */ 407 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 408 409 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 410 /* STM32L496xx || STM32L4A6xx || */ 411 /* STM32L4P5xx || STM32L4Q5xx || */ 412 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 413 414 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 415 416 /** @brief OCTOSPI mapped at 0x00000000. 417 */ 418 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 419 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 420 421 #else 422 423 /** @brief QUADSPI mapped at 0x00000000. 424 */ 425 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 426 427 #endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 428 429 /** 430 * @brief Return the boot mode as configured by user. 431 * @retval The boot mode as configured by user. The returned value can be one 432 * of the following values: 433 * @arg @ref SYSCFG_BOOT_MAINFLASH 434 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 435 @if STM32L486xx 436 * @arg @ref SYSCFG_BOOT_FMC 437 @endif 438 * @arg @ref SYSCFG_BOOT_SRAM 439 @if STM32L422xx 440 * @arg @ref SYSCFG_BOOT_QUADSPI 441 @endif 442 @if STM32L443xx 443 * @arg @ref SYSCFG_BOOT_QUADSPI 444 @endif 445 @if STM32L462xx 446 * @arg @ref SYSCFG_BOOT_QUADSPI 447 @endif 448 @if STM32L486xx 449 * @arg @ref SYSCFG_BOOT_QUADSPI 450 @endif 451 */ 452 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 453 454 /** @brief SRAM2 page 0 to 31 write protection enable macro 455 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 456 * @note Write protection can only be disabled by a system reset 457 */ 458 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 459 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 460 }while(0) 461 462 #if defined(SYSCFG_SWPR2_PAGE63) 463 /** @brief SRAM2 page 32 to 63 write protection enable macro 464 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 465 * @note Write protection can only be disabled by a system reset 466 */ 467 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 468 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 469 }while(0) 470 #endif /* SYSCFG_SWPR2_PAGE63 */ 471 472 /** @brief SRAM2 page write protection unlock prior to erase 473 * @note Writing a wrong key reactivates the write protection 474 */ 475 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 476 SYSCFG->SKR = 0x53;\ 477 }while(0) 478 479 /** @brief SRAM2 erase 480 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 481 */ 482 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 483 484 /** @brief Floating Point Unit interrupt enable/disable macros 485 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 486 */ 487 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 488 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 489 }while(0) 490 491 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 492 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 493 }while(0) 494 495 /** @brief SYSCFG Break ECC lock. 496 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 497 * @note The selected configuration is locked and can be unlocked only by system reset. 498 */ 499 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 500 501 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 502 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 503 * @note The selected configuration is locked and can be unlocked only by system reset. 504 */ 505 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 506 507 /** @brief SYSCFG Break PVD lock. 508 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 509 * @note The selected configuration is locked and can be unlocked only by system reset. 510 */ 511 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 512 513 /** @brief SYSCFG Break SRAM2 parity lock. 514 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 515 * @note The selected configuration is locked and can be unlocked by system reset. 516 */ 517 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 518 519 /** @brief Check SYSCFG flag is set or not. 520 * @param __FLAG__ specifies the flag to check. 521 * This parameter can be one of the following values: 522 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 523 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 524 * @retval The new state of __FLAG__ (TRUE or FALSE). 525 */ 526 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 527 528 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 529 */ 530 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 531 532 /** @brief Fast-mode Plus driving capability enable/disable macros 533 * @param __FASTMODEPLUS__ This parameter can be a value of : 534 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 535 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 536 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 537 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 538 */ 539 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 540 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 541 }while(0) 542 543 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 544 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 545 }while(0) 546 547 /** 548 * @} 549 */ 550 551 /** 552 * @} 553 */ 554 555 /* Private macros ------------------------------------------------------------*/ 556 /** @defgroup HAL_Private_Macros HAL Private Macros 557 * @{ 558 */ 559 560 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 561 * @{ 562 */ 563 564 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 565 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 566 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 567 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 568 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 569 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 570 571 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 572 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 573 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 574 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 575 576 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 577 578 #if defined(VREFBUF) 579 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 580 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 581 582 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 583 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 584 585 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 586 #endif /* VREFBUF */ 587 588 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 589 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 590 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 591 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 592 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 593 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 594 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 595 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 596 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 597 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 598 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 599 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 600 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 601 #else 602 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 603 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 604 #endif 605 /** 606 * @} 607 */ 608 609 /** 610 * @} 611 */ 612 613 /* Exported variables --------------------------------------------------------*/ 614 615 /** @addtogroup HAL_Exported_Variables 616 * @{ 617 */ 618 extern __IO uint32_t uwTick; 619 extern uint32_t uwTickPrio; 620 extern HAL_TickFreqTypeDef uwTickFreq; 621 /** 622 * @} 623 */ 624 625 /* Exported functions --------------------------------------------------------*/ 626 627 /** @addtogroup HAL_Exported_Functions 628 * @{ 629 */ 630 631 /** @addtogroup HAL_Exported_Functions_Group1 632 * @{ 633 */ 634 635 /* Initialization and de-initialization functions ******************************/ 636 HAL_StatusTypeDef HAL_Init(void); 637 HAL_StatusTypeDef HAL_DeInit(void); 638 void HAL_MspInit(void); 639 void HAL_MspDeInit(void); 640 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 641 642 /** 643 * @} 644 */ 645 646 /** @addtogroup HAL_Exported_Functions_Group2 647 * @{ 648 */ 649 650 /* Peripheral Control functions ************************************************/ 651 void HAL_IncTick(void); 652 void HAL_Delay(uint32_t Delay); 653 uint32_t HAL_GetTick(void); 654 uint32_t HAL_GetTickPrio(void); 655 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 656 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 657 void HAL_SuspendTick(void); 658 void HAL_ResumeTick(void); 659 uint32_t HAL_GetHalVersion(void); 660 uint32_t HAL_GetREVID(void); 661 uint32_t HAL_GetDEVID(void); 662 uint32_t HAL_GetUIDw0(void); 663 uint32_t HAL_GetUIDw1(void); 664 uint32_t HAL_GetUIDw2(void); 665 666 /** 667 * @} 668 */ 669 670 /** @addtogroup HAL_Exported_Functions_Group3 671 * @{ 672 */ 673 674 /* DBGMCU Peripheral Control functions *****************************************/ 675 void HAL_DBGMCU_EnableDBGSleepMode(void); 676 void HAL_DBGMCU_DisableDBGSleepMode(void); 677 void HAL_DBGMCU_EnableDBGStopMode(void); 678 void HAL_DBGMCU_DisableDBGStopMode(void); 679 void HAL_DBGMCU_EnableDBGStandbyMode(void); 680 void HAL_DBGMCU_DisableDBGStandbyMode(void); 681 682 /** 683 * @} 684 */ 685 686 /** @addtogroup HAL_Exported_Functions_Group4 687 * @{ 688 */ 689 690 /* SYSCFG Control functions ****************************************************/ 691 void HAL_SYSCFG_SRAM2Erase(void); 692 void HAL_SYSCFG_EnableMemorySwappingBank(void); 693 void HAL_SYSCFG_DisableMemorySwappingBank(void); 694 695 #if defined(VREFBUF) 696 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 697 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 698 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 699 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 700 void HAL_SYSCFG_DisableVREFBUF(void); 701 #endif /* VREFBUF */ 702 703 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 704 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 705 706 /** 707 * @} 708 */ 709 710 /** 711 * @} 712 */ 713 714 /** 715 * @} 716 */ 717 718 /** 719 * @} 720 */ 721 722 #ifdef __cplusplus 723 } 724 #endif 725 726 #endif /* STM32L4xx_HAL_H */ 727
