1 /**
2   ******************************************************************************
3   * @file    stm32l431xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32L431xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral�s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under Apache License, Version 2.0,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/Apache-2.0
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32l431xx
31   * @{
32   */
33 
34 #ifndef __STM32L431xx_H
35 #define __STM32L431xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47    */
48 #define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
49 #define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
50 #define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
52 #define __FPU_PRESENT             1       /*!< FPU present                                   */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32L4XX Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 typedef enum
67 {
68 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
70   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
71   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
72   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
73   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
74   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
75   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
76   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
77   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
78 /******  STM32 specific Interrupt Numbers **********************************************************************/
79   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
80   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM3/PVM4 through EXTI Line detection Interrupts              */
81   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
82   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
83   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
84   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
85   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
86   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
87   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
88   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
89   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
90   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
91   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
92   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
93   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
94   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
95   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
96   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
97   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                             */
98   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
99   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
100   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
101   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
102   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
103   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
104   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
105   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
106   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
107   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
108   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
109   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
110   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
111   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
112   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
113   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
114   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
115   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
116   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
117   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
118   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
119   SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
120   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
121   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
122   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
123   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
124   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
125   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
126   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
127   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
128   COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
129   LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
130   LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
131   DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
132   DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
133   LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
134   QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
135   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
136   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
137   SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
138   SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
139   TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
140   RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
141   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
142   CRS_IRQn                    = 82      /*!< CRS global interrupt                                              */
143 } IRQn_Type;
144 
145 /**
146   * @}
147   */
148 
149 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
150 #include "system_stm32l4xx.h"
151 #include <stdint.h>
152 
153 /** @addtogroup Peripheral_registers_structures
154   * @{
155   */
156 
157 /**
158   * @brief Analog to Digital Converter
159   */
160 
161 typedef struct
162 {
163   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
164   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
165   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
166   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
167   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
168   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
169   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
170        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
171   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
172   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
173   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
174        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
175   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
176   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
177   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
178   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
179   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
180        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
181        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
182   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
183        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
184   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
185   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
186   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
187   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
188        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
189   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
190   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
191   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
192   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
193        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
194   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
195   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
196        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
197        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
198   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
199   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
200 
201 } ADC_TypeDef;
202 
203 typedef struct
204 {
205   uint32_t      RESERVED1;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x300 */
206   uint32_t      RESERVED2;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
207   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
208   uint32_t      RESERVED3;    /*!< Reserved,                                      Address offset: ADC1 base address + 0x30C */
209 } ADC_Common_TypeDef;
210 
211 
212 /**
213   * @brief Controller Area Network TxMailBox
214   */
215 
216 typedef struct
217 {
218   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
219   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
220   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
221   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
222 } CAN_TxMailBox_TypeDef;
223 
224 /**
225   * @brief Controller Area Network FIFOMailBox
226   */
227 
228 typedef struct
229 {
230   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
231   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
232   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
233   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
234 } CAN_FIFOMailBox_TypeDef;
235 
236 /**
237   * @brief Controller Area Network FilterRegister
238   */
239 
240 typedef struct
241 {
242   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
243   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
244 } CAN_FilterRegister_TypeDef;
245 
246 /**
247   * @brief Controller Area Network
248   */
249 
250 typedef struct
251 {
252   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
253   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
254   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
255   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
256   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
257   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
258   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
259   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
260   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
261   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
262   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
263   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
264   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
265   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
266   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
267   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
268   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
269   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
270   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
271   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
272   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
273   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
274 } CAN_TypeDef;
275 
276 
277 /**
278   * @brief Comparator
279   */
280 
281 typedef struct
282 {
283   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
284 } COMP_TypeDef;
285 
286 typedef struct
287 {
288   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
289 } COMP_Common_TypeDef;
290 
291 /**
292   * @brief CRC calculation unit
293   */
294 
295 typedef struct
296 {
297   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
298   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
299   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
300   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
301   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
302   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
303   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
304   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
305 } CRC_TypeDef;
306 
307 /**
308   * @brief Clock Recovery System
309   */
310 typedef struct
311 {
312 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
313 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
314 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
315 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
316 } CRS_TypeDef;
317 
318 /**
319   * @brief Digital to Analog Converter
320   */
321 
322 typedef struct
323 {
324   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
325   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
326   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
327   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
328   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
329   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
330   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
331   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
332   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
333   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
334   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
335   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
336   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
337   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
338   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
339   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
340   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
341   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
342   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
343   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
344 } DAC_TypeDef;
345 
346 
347 /**
348   * @brief Debug MCU
349   */
350 
351 typedef struct
352 {
353   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
354   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
355   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
356   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
357   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
358 } DBGMCU_TypeDef;
359 
360 
361 /**
362   * @brief DMA Controller
363   */
364 
365 typedef struct
366 {
367   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
368   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
369   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
370   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
371 } DMA_Channel_TypeDef;
372 
373 typedef struct
374 {
375   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
376   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
377 } DMA_TypeDef;
378 
379 typedef struct
380 {
381   __IO uint32_t CSELR;       /*!< DMA channel selection register              */
382 } DMA_Request_TypeDef;
383 
384 /* Legacy define */
385 #define DMA_request_TypeDef  DMA_Request_TypeDef
386 
387 
388 /**
389   * @brief External Interrupt/Event Controller
390   */
391 
392 typedef struct
393 {
394   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
395   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
396   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
397   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
398   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
399   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
400   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
401   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
402   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
403   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
404   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
405   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
406   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
407   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
408 } EXTI_TypeDef;
409 
410 
411 /**
412   * @brief Firewall
413   */
414 
415 typedef struct
416 {
417   __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
418   __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
419   __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
420   __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
421   __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
422   __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
423   uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
424   uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
425   __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
426 } FIREWALL_TypeDef;
427 
428 
429 /**
430   * @brief FLASH Registers
431   */
432 
433 typedef struct
434 {
435   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
436   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
437   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
438   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
439   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
440   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
441   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
442   __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
443   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
444   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
445   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
446   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
447   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
448 } FLASH_TypeDef;
449 
450 
451 
452 /**
453   * @brief General Purpose I/O
454   */
455 
456 typedef struct
457 {
458   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
459   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
460   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
461   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
462   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
463   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
464   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
465   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
466   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
467   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
468 
469 } GPIO_TypeDef;
470 
471 
472 /**
473   * @brief Inter-integrated Circuit Interface
474   */
475 
476 typedef struct
477 {
478   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
479   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
480   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
481   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
482   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
483   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
484   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
485   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
486   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
487   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
488   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
489 } I2C_TypeDef;
490 
491 /**
492   * @brief Independent WATCHDOG
493   */
494 
495 typedef struct
496 {
497   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
498   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
499   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
500   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
501   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
502 } IWDG_TypeDef;
503 
504 /**
505   * @brief LPTIMER
506   */
507 typedef struct
508 {
509   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
510   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
511   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
512   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
513   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
514   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
515   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
516   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
517   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
518 } LPTIM_TypeDef;
519 
520 /**
521   * @brief Operational Amplifier (OPAMP)
522   */
523 
524 typedef struct
525 {
526   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
527   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
528   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
529 } OPAMP_TypeDef;
530 
531 typedef struct
532 {
533   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
534 } OPAMP_Common_TypeDef;
535 
536 /**
537   * @brief Power Control
538   */
539 
540 typedef struct
541 {
542   __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
543   __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
544   __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
545   __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
546   __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
547   __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
548   __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
549   uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
550   __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
551   __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
552   __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
553   __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
554   __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
555   __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
556   __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
557   __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
558   __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
559   __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
560   uint32_t RESERVED1;  /*!< Reserved,                            Address offset: 0x48 */
561   uint32_t RESERVED2;  /*!< Reserved,                            Address offset: 0x4C */
562   uint32_t RESERVED3;  /*!< Reserved,                            Address offset: 0x50 */
563   uint32_t RESERVED4;  /*!< Reserved,                            Address offset: 0x54 */
564   __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
565   __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
566 } PWR_TypeDef;
567 
568 
569 /**
570   * @brief QUAD Serial Peripheral Interface
571   */
572 
573 typedef struct
574 {
575   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
576   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
577   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
578   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
579   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
580   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
581   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
582   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
583   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
584   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
585   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
586   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
587   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
588 } QUADSPI_TypeDef;
589 
590 
591 /**
592   * @brief Reset and Clock Control
593   */
594 
595 typedef struct
596 {
597   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
598   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
599   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
600   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
601   __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
602   uint32_t      RESERVED;    /*!< Reserved,                                                                Address offset: 0x14 */
603   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
604   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
605   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
606   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
607   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
608   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
609   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
610   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
611   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
612   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
613   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
614   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
615   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
616   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
617   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
618   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
619   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
620   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
621   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
622   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
623   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
624   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
625   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
626   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
627   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
628   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
629   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
630   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
631   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
632   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
633   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
634   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
635   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
636 } RCC_TypeDef;
637 
638 /**
639   * @brief Real-Time Clock
640   */
641 
642 typedef struct
643 {
644   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
645   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
646   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
647   __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
648   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
649   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
650        uint32_t reserved;    /*!< Reserved  */
651   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
652   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
653   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
654   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
655   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
656   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
657   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
658   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
659   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
660   __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
661   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
662   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
663   __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
664   __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
665   __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
666   __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
667   __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
668   __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
669   __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
670   __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
671   __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
672   __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
673   __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
674   __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
675   __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
676   __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
677   __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
678   __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
679   __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
680   __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
681   __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
682   __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
683   __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
684   __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
685   __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
686   __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
687   __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
688   __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
689   __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
690   __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
691   __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
692   __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
693   __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
694   __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
695   __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
696 } RTC_TypeDef;
697 
698 /**
699   * @brief Serial Audio Interface
700   */
701 
702 typedef struct
703 {
704   __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
705 } SAI_TypeDef;
706 
707 typedef struct
708 {
709   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
710   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
711   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
712   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
713   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
714   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
715   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
716   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
717 } SAI_Block_TypeDef;
718 
719 
720 /**
721   * @brief Secure digital input/output Interface
722   */
723 
724 typedef struct
725 {
726   __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
727   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
728   __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
729   __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
730   __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
731   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
732   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
733   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
734   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
735   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
736   __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
737   __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
738   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
739   __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
740   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
741   __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
742   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
743   __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
744   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
745   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
746 } SDMMC_TypeDef;
747 
748 
749 /**
750   * @brief Serial Peripheral Interface
751   */
752 
753 typedef struct
754 {
755   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
756   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
757   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
758   __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
759   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
760   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
761   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
762 } SPI_TypeDef;
763 
764 
765 /**
766   * @brief Single Wire Protocol Master Interface SPWMI
767   */
768 
769 typedef struct
770 {
771   __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
772   __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
773     uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
774   __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
775   __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
776   __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
777   __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
778   __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
779   __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
780   __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
781 } SWPMI_TypeDef;
782 
783 
784 /**
785   * @brief System configuration controller
786   */
787 
788 typedef struct
789 {
790   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
791   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
792   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
793   __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
794   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
795   __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
796   __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
797 } SYSCFG_TypeDef;
798 
799 
800 /**
801   * @brief TIM
802   */
803 
804 typedef struct
805 {
806   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
807   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
808   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
809   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
810   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
811   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
812   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
813   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
814   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
815   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
816   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
817   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
818   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
819   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
820   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
821   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
822   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
823   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
824   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
825   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
826   __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
827   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
828   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
829   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
830   __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
831   __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
832 } TIM_TypeDef;
833 
834 
835 /**
836   * @brief Touch Sensing Controller (TSC)
837   */
838 
839 typedef struct
840 {
841   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
842   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
843   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
844   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
845   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
846   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
847   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
848   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
849   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
850   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
851   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
852   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
853   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
854   __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-4C */
855 } TSC_TypeDef;
856 
857 /**
858   * @brief Universal Synchronous Asynchronous Receiver Transmitter
859   */
860 
861 typedef struct
862 {
863   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
864   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
865   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
866   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
867   __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
868   uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
869   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
870   __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
871   uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
872   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
873   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
874   __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
875   uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
876   __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
877   uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
878 } USART_TypeDef;
879 
880 /**
881   * @brief VREFBUF
882   */
883 
884 typedef struct
885 {
886   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
887   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
888 } VREFBUF_TypeDef;
889 
890 /**
891   * @brief Window WATCHDOG
892   */
893 
894 typedef struct
895 {
896   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
897   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
898   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
899 } WWDG_TypeDef;
900 
901 /**
902   * @brief RNG
903   */
904 
905 typedef struct
906 {
907   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
908   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
909   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
910 } RNG_TypeDef;
911 
912 /**
913   * @}
914   */
915 
916 /** @addtogroup Peripheral_memory_map
917   * @{
918   */
919 #define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
920 #define FLASH_END             (0x0803FFFFUL) /*!< FLASH END address                */
921 #define FLASH_BANK1_END       (0x0803FFFFUL) /*!< FLASH END address of bank1       */
922 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 48 KB) base address  */
923 #define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(16 KB) base address */
924 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
925 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
926 
927 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
928 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */
929 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
930 
931 /* Legacy defines */
932 #define SRAM_BASE             SRAM1_BASE
933 #define SRAM_BB_BASE          SRAM1_BB_BASE
934 
935 #define SRAM1_SIZE_MAX        (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
936 #define SRAM2_SIZE            (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
937 
938 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
939 
940 #define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \
941                                   (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
942 
943 /*!< Peripheral memory map */
944 #define APB1PERIPH_BASE        PERIPH_BASE
945 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
946 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
947 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
948 
949 
950 /*!< APB1 peripherals */
951 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
952 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
953 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
954 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
955 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
956 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
957 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
958 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
959 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
960 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
961 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
962 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
963 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
964 #define CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
965 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
966 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
967 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
968 #define DAC1_BASE             (APB1PERIPH_BASE + 0x7400UL)
969 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
970 #define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
971 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
972 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
973 #define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800UL)
974 #define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
975 
976 
977 /*!< APB2 peripherals */
978 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
979 #define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030UL)
980 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
981 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204UL)
982 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
983 #define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
984 #define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800UL)
985 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
986 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
987 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
988 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
989 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
990 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5400UL)
991 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x0004UL)
992 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x0024UL)
993 
994 /*!< AHB1 peripherals */
995 #define DMA1_BASE             (AHB1PERIPH_BASE)
996 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
997 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
998 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
999 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1000 #define TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
1001 
1002 
1003 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
1004 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
1005 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
1006 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
1007 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
1008 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
1009 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
1010 #define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
1011 
1012 
1013 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
1014 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
1015 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
1016 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
1017 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
1018 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
1019 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
1020 #define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
1021 
1022 
1023 /*!< AHB2 peripherals */
1024 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
1025 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
1026 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
1027 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
1028 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000UL)
1029 #define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
1030 
1031 
1032 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
1033 #define ADC1_COMMON_BASE      (AHB2PERIPH_BASE + 0x08040300UL)
1034 
1035 
1036 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
1037 
1038 
1039 
1040 /* Debug MCU registers base address */
1041 #define DBGMCU_BASE           (0xE0042000UL)
1042 
1043 
1044 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
1045 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
1046 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
1047 /**
1048   * @}
1049   */
1050 
1051 /** @addtogroup Peripheral_declaration
1052   * @{
1053   */
1054 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1055 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1056 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1057 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1058 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1059 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1060 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1061 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1062 #define USART2              ((USART_TypeDef *) USART2_BASE)
1063 #define USART3              ((USART_TypeDef *) USART3_BASE)
1064 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1065 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1066 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1067 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1068 #define CAN                 ((CAN_TypeDef *) CAN1_BASE)
1069 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1070 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1071 #define DAC                 ((DAC_TypeDef *) DAC1_BASE)
1072 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1073 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
1074 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1075 #define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1076 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1077 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1078 #define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
1079 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
1080 
1081 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1082 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1083 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1084 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1085 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
1086 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1087 #define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
1088 #define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
1089 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1090 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1091 #define USART1              ((USART_TypeDef *) USART1_BASE)
1092 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1093 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1094 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1095 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1096 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1097 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1098 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1099 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1100 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1101 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1102 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
1103 
1104 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1105 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1106 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1107 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1108 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1109 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1110 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1111 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1112 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1113 
1114 
1115 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1116 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1117 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1118 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1119 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1120 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1121 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1122 #define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1123 
1124 
1125 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1126 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1127 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1128 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1129 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1130 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1131 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1132 #define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1133 
1134 
1135 
1136 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1137 
1138 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1139 
1140 /**
1141   * @}
1142   */
1143 
1144 /** @addtogroup Exported_constants
1145   * @{
1146   */
1147 
1148 /** @addtogroup Peripheral_Registers_Bits_Definition
1149   * @{
1150   */
1151 
1152 /******************************************************************************/
1153 /*                         Peripheral Registers_Bits_Definition               */
1154 /******************************************************************************/
1155 
1156 /******************************************************************************/
1157 /*                                                                            */
1158 /*                        Analog to Digital Converter                         */
1159 /*                                                                            */
1160 /******************************************************************************/
1161 
1162 /*
1163  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1164  */
1165 /* Note: No specific macro feature on this device */
1166 
1167 /********************  Bit definition for ADC_ISR register  *******************/
1168 #define ADC_ISR_ADRDY_Pos              (0U)
1169 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1170 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1171 #define ADC_ISR_EOSMP_Pos              (1U)
1172 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1173 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1174 #define ADC_ISR_EOC_Pos                (2U)
1175 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1176 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1177 #define ADC_ISR_EOS_Pos                (3U)
1178 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1179 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1180 #define ADC_ISR_OVR_Pos                (4U)
1181 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1182 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1183 #define ADC_ISR_JEOC_Pos               (5U)
1184 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1185 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1186 #define ADC_ISR_JEOS_Pos               (6U)
1187 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1188 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1189 #define ADC_ISR_AWD1_Pos               (7U)
1190 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1191 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1192 #define ADC_ISR_AWD2_Pos               (8U)
1193 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1194 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1195 #define ADC_ISR_AWD3_Pos               (9U)
1196 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1197 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1198 #define ADC_ISR_JQOVF_Pos              (10U)
1199 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1200 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1201 
1202 /********************  Bit definition for ADC_IER register  *******************/
1203 #define ADC_IER_ADRDYIE_Pos            (0U)
1204 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1205 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1206 #define ADC_IER_EOSMPIE_Pos            (1U)
1207 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1208 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1209 #define ADC_IER_EOCIE_Pos              (2U)
1210 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1211 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1212 #define ADC_IER_EOSIE_Pos              (3U)
1213 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1214 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1215 #define ADC_IER_OVRIE_Pos              (4U)
1216 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1217 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1218 #define ADC_IER_JEOCIE_Pos             (5U)
1219 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1220 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1221 #define ADC_IER_JEOSIE_Pos             (6U)
1222 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1223 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1224 #define ADC_IER_AWD1IE_Pos             (7U)
1225 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1226 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1227 #define ADC_IER_AWD2IE_Pos             (8U)
1228 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1229 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1230 #define ADC_IER_AWD3IE_Pos             (9U)
1231 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1232 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1233 #define ADC_IER_JQOVFIE_Pos            (10U)
1234 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1235 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1236 
1237 /* Legacy defines */
1238 #define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
1239 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
1240 #define ADC_IER_EOC             (ADC_IER_EOCIE)
1241 #define ADC_IER_EOS             (ADC_IER_EOSIE)
1242 #define ADC_IER_OVR             (ADC_IER_OVRIE)
1243 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
1244 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
1245 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
1246 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
1247 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
1248 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
1249 
1250 /********************  Bit definition for ADC_CR register  ********************/
1251 #define ADC_CR_ADEN_Pos                (0U)
1252 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1253 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1254 #define ADC_CR_ADDIS_Pos               (1U)
1255 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1256 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1257 #define ADC_CR_ADSTART_Pos             (2U)
1258 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1259 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1260 #define ADC_CR_JADSTART_Pos            (3U)
1261 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1262 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1263 #define ADC_CR_ADSTP_Pos               (4U)
1264 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1265 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1266 #define ADC_CR_JADSTP_Pos              (5U)
1267 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1268 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1269 #define ADC_CR_ADVREGEN_Pos            (28U)
1270 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1271 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1272 #define ADC_CR_DEEPPWD_Pos             (29U)
1273 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1274 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1275 #define ADC_CR_ADCALDIF_Pos            (30U)
1276 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1277 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1278 #define ADC_CR_ADCAL_Pos               (31U)
1279 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1280 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1281 
1282 /********************  Bit definition for ADC_CFGR register  ******************/
1283 #define ADC_CFGR_DMAEN_Pos             (0U)
1284 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1285 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1286 #define ADC_CFGR_DMACFG_Pos            (1U)
1287 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1288 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1289 
1290 #define ADC_CFGR_RES_Pos               (3U)
1291 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1292 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1293 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1294 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1295 
1296 #define ADC_CFGR_ALIGN_Pos             (5U)
1297 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */
1298 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
1299 
1300 #define ADC_CFGR_EXTSEL_Pos            (6U)
1301 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */
1302 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1303 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1304 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1305 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1306 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000200 */
1307 
1308 #define ADC_CFGR_EXTEN_Pos             (10U)
1309 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1310 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1311 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1312 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1313 
1314 #define ADC_CFGR_OVRMOD_Pos            (12U)
1315 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1316 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1317 #define ADC_CFGR_CONT_Pos              (13U)
1318 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1319 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1320 #define ADC_CFGR_AUTDLY_Pos            (14U)
1321 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1322 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1323 
1324 #define ADC_CFGR_DISCEN_Pos            (16U)
1325 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1326 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1327 
1328 #define ADC_CFGR_DISCNUM_Pos           (17U)
1329 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1330 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1331 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1332 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1333 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1334 
1335 #define ADC_CFGR_JDISCEN_Pos           (20U)
1336 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1337 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1338 #define ADC_CFGR_JQM_Pos               (21U)
1339 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1340 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1341 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1342 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1343 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1344 #define ADC_CFGR_AWD1EN_Pos            (23U)
1345 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1346 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1347 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1348 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1349 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1350 #define ADC_CFGR_JAUTO_Pos             (25U)
1351 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1352 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1353 
1354 #define ADC_CFGR_AWD1CH_Pos            (26U)
1355 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1356 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1357 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1358 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1359 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1360 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1361 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1362 
1363 #define ADC_CFGR_JQDIS_Pos             (31U)
1364 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1365 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1366 
1367 /********************  Bit definition for ADC_CFGR2 register  *****************/
1368 #define ADC_CFGR2_ROVSE_Pos            (0U)
1369 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1370 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1371 #define ADC_CFGR2_JOVSE_Pos            (1U)
1372 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1373 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1374 
1375 #define ADC_CFGR2_OVSR_Pos             (2U)
1376 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1377 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1378 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1379 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1380 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1381 
1382 #define ADC_CFGR2_OVSS_Pos             (5U)
1383 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1384 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1385 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1386 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1387 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1388 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1389 
1390 #define ADC_CFGR2_TROVS_Pos            (9U)
1391 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1392 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1393 #define ADC_CFGR2_ROVSM_Pos            (10U)
1394 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1395 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1396 
1397 /********************  Bit definition for ADC_SMPR1 register  *****************/
1398 #define ADC_SMPR1_SMP0_Pos             (0U)
1399 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1400 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1401 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1402 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1403 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1404 
1405 #define ADC_SMPR1_SMP1_Pos             (3U)
1406 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1407 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1408 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1409 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1410 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1411 
1412 #define ADC_SMPR1_SMP2_Pos             (6U)
1413 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1414 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1415 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1416 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1417 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1418 
1419 #define ADC_SMPR1_SMP3_Pos             (9U)
1420 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1421 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1422 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1423 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1424 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1425 
1426 #define ADC_SMPR1_SMP4_Pos             (12U)
1427 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1428 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1429 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1430 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1431 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1432 
1433 #define ADC_SMPR1_SMP5_Pos             (15U)
1434 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1435 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1436 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1437 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1438 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1439 
1440 #define ADC_SMPR1_SMP6_Pos             (18U)
1441 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1442 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1443 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1444 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1445 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1446 
1447 #define ADC_SMPR1_SMP7_Pos             (21U)
1448 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1449 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1450 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1451 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1452 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1453 
1454 #define ADC_SMPR1_SMP8_Pos             (24U)
1455 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1456 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1457 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1458 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1459 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1460 
1461 #define ADC_SMPR1_SMP9_Pos             (27U)
1462 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1463 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1464 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1465 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1466 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1467 
1468 /********************  Bit definition for ADC_SMPR2 register  *****************/
1469 #define ADC_SMPR2_SMP10_Pos            (0U)
1470 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1471 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1472 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1473 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1474 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1475 
1476 #define ADC_SMPR2_SMP11_Pos            (3U)
1477 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1478 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1479 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1480 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1481 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1482 
1483 #define ADC_SMPR2_SMP12_Pos            (6U)
1484 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1485 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1486 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1487 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1488 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1489 
1490 #define ADC_SMPR2_SMP13_Pos            (9U)
1491 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1492 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1493 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1494 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1495 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1496 
1497 #define ADC_SMPR2_SMP14_Pos            (12U)
1498 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1499 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1500 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1501 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1502 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1503 
1504 #define ADC_SMPR2_SMP15_Pos            (15U)
1505 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1506 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1507 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1508 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1509 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1510 
1511 #define ADC_SMPR2_SMP16_Pos            (18U)
1512 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1513 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1514 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1515 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1516 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1517 
1518 #define ADC_SMPR2_SMP17_Pos            (21U)
1519 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1520 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1521 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1522 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1523 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1524 
1525 #define ADC_SMPR2_SMP18_Pos            (24U)
1526 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1527 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1528 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1529 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1530 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1531 
1532 /********************  Bit definition for ADC_TR1 register  *******************/
1533 #define ADC_TR1_LT1_Pos                (0U)
1534 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1535 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1536 #define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
1537 #define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
1538 #define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
1539 #define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
1540 #define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
1541 #define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
1542 #define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
1543 #define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
1544 #define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
1545 #define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
1546 #define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
1547 #define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
1548 
1549 #define ADC_TR1_HT1_Pos                (16U)
1550 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1551 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
1552 #define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
1553 #define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
1554 #define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
1555 #define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
1556 #define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
1557 #define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
1558 #define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
1559 #define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
1560 #define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
1561 #define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
1562 #define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
1563 #define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
1564 
1565 /********************  Bit definition for ADC_TR2 register  *******************/
1566 #define ADC_TR2_LT2_Pos                (0U)
1567 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1568 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1569 #define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)             /*!< 0x00000001 */
1570 #define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)             /*!< 0x00000002 */
1571 #define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)             /*!< 0x00000004 */
1572 #define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)             /*!< 0x00000008 */
1573 #define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)             /*!< 0x00000010 */
1574 #define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)             /*!< 0x00000020 */
1575 #define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)             /*!< 0x00000040 */
1576 #define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)             /*!< 0x00000080 */
1577 
1578 #define ADC_TR2_HT2_Pos                (16U)
1579 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1580 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1581 #define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)             /*!< 0x00010000 */
1582 #define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)             /*!< 0x00020000 */
1583 #define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)             /*!< 0x00040000 */
1584 #define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)             /*!< 0x00080000 */
1585 #define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)             /*!< 0x00100000 */
1586 #define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)             /*!< 0x00200000 */
1587 #define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)             /*!< 0x00400000 */
1588 #define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)             /*!< 0x00800000 */
1589 
1590 /********************  Bit definition for ADC_TR3 register  *******************/
1591 #define ADC_TR3_LT3_Pos                (0U)
1592 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1593 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1594 #define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)             /*!< 0x00000001 */
1595 #define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)             /*!< 0x00000002 */
1596 #define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)             /*!< 0x00000004 */
1597 #define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)             /*!< 0x00000008 */
1598 #define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)             /*!< 0x00000010 */
1599 #define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)             /*!< 0x00000020 */
1600 #define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)             /*!< 0x00000040 */
1601 #define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)             /*!< 0x00000080 */
1602 
1603 #define ADC_TR3_HT3_Pos                (16U)
1604 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1605 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1606 #define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)             /*!< 0x00010000 */
1607 #define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)             /*!< 0x00020000 */
1608 #define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)             /*!< 0x00040000 */
1609 #define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)             /*!< 0x00080000 */
1610 #define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)             /*!< 0x00100000 */
1611 #define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)             /*!< 0x00200000 */
1612 #define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)             /*!< 0x00400000 */
1613 #define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)             /*!< 0x00800000 */
1614 
1615 /********************  Bit definition for ADC_SQR1 register  ******************/
1616 #define ADC_SQR1_L_Pos                 (0U)
1617 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1618 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1619 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1620 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1621 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1622 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1623 
1624 #define ADC_SQR1_SQ1_Pos               (6U)
1625 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1626 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1627 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1628 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1629 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1630 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1631 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1632 
1633 #define ADC_SQR1_SQ2_Pos               (12U)
1634 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1635 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1636 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1637 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1638 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1639 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1640 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1641 
1642 #define ADC_SQR1_SQ3_Pos               (18U)
1643 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1644 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1645 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1646 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1647 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1648 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1649 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
1650 
1651 #define ADC_SQR1_SQ4_Pos               (24U)
1652 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1653 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1654 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1655 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1656 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1657 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1658 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1659 
1660 /********************  Bit definition for ADC_SQR2 register  ******************/
1661 #define ADC_SQR2_SQ5_Pos               (0U)
1662 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1663 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1664 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1665 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1666 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1667 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1668 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1669 
1670 #define ADC_SQR2_SQ6_Pos               (6U)
1671 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1672 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1673 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1674 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1675 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1676 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1677 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1678 
1679 #define ADC_SQR2_SQ7_Pos               (12U)
1680 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1681 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1682 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1683 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1684 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1685 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1686 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1687 
1688 #define ADC_SQR2_SQ8_Pos               (18U)
1689 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1690 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1691 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1692 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1693 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1694 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1695 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1696 
1697 #define ADC_SQR2_SQ9_Pos               (24U)
1698 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1699 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1700 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1701 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1702 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1703 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1704 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1705 
1706 /********************  Bit definition for ADC_SQR3 register  ******************/
1707 #define ADC_SQR3_SQ10_Pos              (0U)
1708 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1709 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1710 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1711 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1712 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1713 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1714 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1715 
1716 #define ADC_SQR3_SQ11_Pos              (6U)
1717 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1718 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1719 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1720 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1721 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1722 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1723 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1724 
1725 #define ADC_SQR3_SQ12_Pos              (12U)
1726 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1727 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1728 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1729 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1730 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1731 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1732 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1733 
1734 #define ADC_SQR3_SQ13_Pos              (18U)
1735 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1736 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1737 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1738 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1739 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1740 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1741 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1742 
1743 #define ADC_SQR3_SQ14_Pos              (24U)
1744 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1745 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1746 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1747 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1748 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1749 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1750 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1751 
1752 /********************  Bit definition for ADC_SQR4 register  ******************/
1753 #define ADC_SQR4_SQ15_Pos              (0U)
1754 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1755 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1756 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1757 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1758 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1759 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1760 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1761 
1762 #define ADC_SQR4_SQ16_Pos              (6U)
1763 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1764 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1765 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1766 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1767 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1768 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1769 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1770 
1771 /********************  Bit definition for ADC_DR register  ********************/
1772 #define ADC_DR_RDATA_Pos               (0U)
1773 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1774 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1775 #define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)          /*!< 0x00000001 */
1776 #define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)          /*!< 0x00000002 */
1777 #define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)          /*!< 0x00000004 */
1778 #define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)          /*!< 0x00000008 */
1779 #define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */
1780 #define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */
1781 #define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */
1782 #define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */
1783 #define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)          /*!< 0x00000100 */
1784 #define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)          /*!< 0x00000200 */
1785 #define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)          /*!< 0x00000400 */
1786 #define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)          /*!< 0x00000800 */
1787 #define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)          /*!< 0x00001000 */
1788 #define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)          /*!< 0x00002000 */
1789 #define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)          /*!< 0x00004000 */
1790 #define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)          /*!< 0x00008000 */
1791 
1792 /********************  Bit definition for ADC_JSQR register  ******************/
1793 #define ADC_JSQR_JL_Pos                (0U)
1794 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1795 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1796 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1797 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1798 
1799 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1800 #define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x0000003C */
1801 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1802 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1803 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1804 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1805 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1806 
1807 #define ADC_JSQR_JEXTEN_Pos            (6U)
1808 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x000000C0 */
1809 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1810 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000040 */
1811 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1812 
1813 #define ADC_JSQR_JSQ1_Pos              (8U)
1814 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001F00 */
1815 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1816 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000100 */
1817 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1818 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1819 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1820 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1821 
1822 #define ADC_JSQR_JSQ2_Pos              (14U)
1823 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1824 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1825 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1826 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1827 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1828 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1829 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1830 
1831 #define ADC_JSQR_JSQ3_Pos              (20U)
1832 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01F00000 */
1833 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1834 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00100000 */
1835 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1836 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1837 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1838 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1839 
1840 #define ADC_JSQR_JSQ4_Pos              (26U)
1841 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0x7C000000 */
1842 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1843 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x04000000 */
1844 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1845 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1846 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1847 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1848 
1849 /********************  Bit definition for ADC_OFR1 register  ******************/
1850 #define ADC_OFR1_OFFSET1_Pos           (0U)
1851 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1852 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1853 #define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000001 */
1854 #define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000002 */
1855 #define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000004 */
1856 #define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000008 */
1857 #define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000010 */
1858 #define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000020 */
1859 #define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000040 */
1860 #define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000080 */
1861 #define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000100 */
1862 #define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000200 */
1863 #define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000400 */
1864 #define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000800 */
1865 
1866 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1867 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1868 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1869 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1870 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1871 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1872 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1873 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1874 
1875 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1876 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1877 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1878 
1879 /********************  Bit definition for ADC_OFR2 register  ******************/
1880 #define ADC_OFR2_OFFSET2_Pos           (0U)
1881 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1882 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1883 #define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000001 */
1884 #define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000002 */
1885 #define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000004 */
1886 #define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000008 */
1887 #define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000010 */
1888 #define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000020 */
1889 #define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000040 */
1890 #define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000080 */
1891 #define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000100 */
1892 #define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000200 */
1893 #define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000400 */
1894 #define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000800 */
1895 
1896 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1897 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1898 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1899 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1900 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1901 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1902 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1903 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1904 
1905 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1906 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1907 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1908 
1909 /********************  Bit definition for ADC_OFR3 register  ******************/
1910 #define ADC_OFR3_OFFSET3_Pos           (0U)
1911 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1912 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1913 #define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000001 */
1914 #define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000002 */
1915 #define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000004 */
1916 #define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000008 */
1917 #define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000010 */
1918 #define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000020 */
1919 #define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000040 */
1920 #define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000080 */
1921 #define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000100 */
1922 #define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000200 */
1923 #define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000400 */
1924 #define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000800 */
1925 
1926 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1927 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1928 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1929 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
1930 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
1931 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
1932 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
1933 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
1934 
1935 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1936 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
1937 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1938 
1939 /********************  Bit definition for ADC_OFR4 register  ******************/
1940 #define ADC_OFR4_OFFSET4_Pos           (0U)
1941 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
1942 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1943 #define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000001 */
1944 #define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000002 */
1945 #define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000004 */
1946 #define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000008 */
1947 #define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000010 */
1948 #define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000020 */
1949 #define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000040 */
1950 #define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000080 */
1951 #define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000100 */
1952 #define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000200 */
1953 #define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000400 */
1954 #define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000800 */
1955 
1956 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1957 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
1958 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1959 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
1960 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
1961 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
1962 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
1963 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
1964 
1965 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1966 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
1967 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1968 
1969 /********************  Bit definition for ADC_JDR1 register  ******************/
1970 #define ADC_JDR1_JDATA_Pos             (0U)
1971 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
1972 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1973 #define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000001 */
1974 #define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000002 */
1975 #define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000004 */
1976 #define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000008 */
1977 #define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000010 */
1978 #define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000020 */
1979 #define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000040 */
1980 #define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000080 */
1981 #define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000100 */
1982 #define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000200 */
1983 #define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000400 */
1984 #define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000800 */
1985 #define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00001000 */
1986 #define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00002000 */
1987 #define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00004000 */
1988 #define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00008000 */
1989 
1990 /********************  Bit definition for ADC_JDR2 register  ******************/
1991 #define ADC_JDR2_JDATA_Pos             (0U)
1992 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
1993 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1994 #define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000001 */
1995 #define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000002 */
1996 #define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000004 */
1997 #define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000008 */
1998 #define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000010 */
1999 #define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000020 */
2000 #define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000040 */
2001 #define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000080 */
2002 #define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000100 */
2003 #define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000200 */
2004 #define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000400 */
2005 #define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000800 */
2006 #define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00001000 */
2007 #define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00002000 */
2008 #define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00004000 */
2009 #define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00008000 */
2010 
2011 /********************  Bit definition for ADC_JDR3 register  ******************/
2012 #define ADC_JDR3_JDATA_Pos             (0U)
2013 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
2014 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2015 #define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000001 */
2016 #define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000002 */
2017 #define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000004 */
2018 #define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000008 */
2019 #define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000010 */
2020 #define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000020 */
2021 #define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000040 */
2022 #define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000080 */
2023 #define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000100 */
2024 #define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000200 */
2025 #define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000400 */
2026 #define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000800 */
2027 #define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00001000 */
2028 #define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00002000 */
2029 #define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00004000 */
2030 #define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00008000 */
2031 
2032 /********************  Bit definition for ADC_JDR4 register  ******************/
2033 #define ADC_JDR4_JDATA_Pos             (0U)
2034 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
2035 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2036 #define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000001 */
2037 #define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000002 */
2038 #define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000004 */
2039 #define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000008 */
2040 #define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000010 */
2041 #define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000020 */
2042 #define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000040 */
2043 #define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000080 */
2044 #define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000100 */
2045 #define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000200 */
2046 #define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000400 */
2047 #define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000800 */
2048 #define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00001000 */
2049 #define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00002000 */
2050 #define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00004000 */
2051 #define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00008000 */
2052 
2053 /********************  Bit definition for ADC_AWD2CR register  ****************/
2054 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2055 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
2056 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2057 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
2058 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
2059 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
2060 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
2061 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
2062 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
2063 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
2064 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
2065 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
2066 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
2067 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
2068 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
2069 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
2070 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
2071 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
2072 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
2073 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
2074 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
2075 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
2076 
2077 /********************  Bit definition for ADC_AWD3CR register  ****************/
2078 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2079 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
2080 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2081 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
2082 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
2083 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
2084 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
2085 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
2086 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
2087 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
2088 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
2089 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
2090 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
2091 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
2092 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
2093 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
2094 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
2095 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
2096 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
2097 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
2098 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
2099 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
2100 
2101 /********************  Bit definition for ADC_DIFSEL register  ****************/
2102 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2103 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
2104 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2105 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
2106 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
2107 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
2108 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
2109 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
2110 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
2111 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
2112 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
2113 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
2114 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
2115 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
2116 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
2117 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
2118 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
2119 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
2120 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
2121 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2122 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2123 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2124 
2125 /********************  Bit definition for ADC_CALFACT register  ***************/
2126 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2127 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2128 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2129 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2130 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2131 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2132 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2133 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2134 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2135 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
2136 
2137 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2138 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2139 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2140 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2141 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2142 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2143 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2144 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2145 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2146 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
2147 
2148 /*************************  ADC Common registers  *****************************/
2149 /********************  Bit definition for ADC_CCR register  *******************/
2150 #define ADC_CCR_CKMODE_Pos             (16U)
2151 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2152 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2153 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2154 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2155 
2156 #define ADC_CCR_PRESC_Pos              (18U)
2157 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2158 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2159 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2160 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2161 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2162 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2163 
2164 #define ADC_CCR_VREFEN_Pos             (22U)
2165 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2166 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2167 #define ADC_CCR_TSEN_Pos               (23U)
2168 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
2169 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2170 #define ADC_CCR_VBATEN_Pos             (24U)
2171 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
2172 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2173 
2174 /******************************************************************************/
2175 /*                                                                            */
2176 /*                         Controller Area Network                            */
2177 /*                                                                            */
2178 /******************************************************************************/
2179 /*!<CAN control and status registers */
2180 /*******************  Bit definition for CAN_MCR register  ********************/
2181 #define CAN_MCR_INRQ_Pos       (0U)
2182 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                     /*!< 0x00000001 */
2183 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
2184 #define CAN_MCR_SLEEP_Pos      (1U)
2185 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                    /*!< 0x00000002 */
2186 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
2187 #define CAN_MCR_TXFP_Pos       (2U)
2188 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                     /*!< 0x00000004 */
2189 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
2190 #define CAN_MCR_RFLM_Pos       (3U)
2191 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                     /*!< 0x00000008 */
2192 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
2193 #define CAN_MCR_NART_Pos       (4U)
2194 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                     /*!< 0x00000010 */
2195 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
2196 #define CAN_MCR_AWUM_Pos       (5U)
2197 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                     /*!< 0x00000020 */
2198 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
2199 #define CAN_MCR_ABOM_Pos       (6U)
2200 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                     /*!< 0x00000040 */
2201 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
2202 #define CAN_MCR_TTCM_Pos       (7U)
2203 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                     /*!< 0x00000080 */
2204 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2205 #define CAN_MCR_RESET_Pos      (15U)
2206 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                    /*!< 0x00008000 */
2207 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
2208 
2209 /*******************  Bit definition for CAN_MSR register  ********************/
2210 #define CAN_MSR_INAK_Pos       (0U)
2211 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                     /*!< 0x00000001 */
2212 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
2213 #define CAN_MSR_SLAK_Pos       (1U)
2214 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                     /*!< 0x00000002 */
2215 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
2216 #define CAN_MSR_ERRI_Pos       (2U)
2217 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                     /*!< 0x00000004 */
2218 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
2219 #define CAN_MSR_WKUI_Pos       (3U)
2220 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                     /*!< 0x00000008 */
2221 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
2222 #define CAN_MSR_SLAKI_Pos      (4U)
2223 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                    /*!< 0x00000010 */
2224 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2225 #define CAN_MSR_TXM_Pos        (8U)
2226 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                      /*!< 0x00000100 */
2227 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
2228 #define CAN_MSR_RXM_Pos        (9U)
2229 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                      /*!< 0x00000200 */
2230 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
2231 #define CAN_MSR_SAMP_Pos       (10U)
2232 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                     /*!< 0x00000400 */
2233 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
2234 #define CAN_MSR_RX_Pos         (11U)
2235 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                       /*!< 0x00000800 */
2236 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
2237 
2238 /*******************  Bit definition for CAN_TSR register  ********************/
2239 #define CAN_TSR_RQCP0_Pos      (0U)
2240 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                    /*!< 0x00000001 */
2241 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
2242 #define CAN_TSR_TXOK0_Pos      (1U)
2243 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                    /*!< 0x00000002 */
2244 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
2245 #define CAN_TSR_ALST0_Pos      (2U)
2246 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                    /*!< 0x00000004 */
2247 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
2248 #define CAN_TSR_TERR0_Pos      (3U)
2249 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                    /*!< 0x00000008 */
2250 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
2251 #define CAN_TSR_ABRQ0_Pos      (7U)
2252 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                    /*!< 0x00000080 */
2253 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
2254 #define CAN_TSR_RQCP1_Pos      (8U)
2255 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                    /*!< 0x00000100 */
2256 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
2257 #define CAN_TSR_TXOK1_Pos      (9U)
2258 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                    /*!< 0x00000200 */
2259 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
2260 #define CAN_TSR_ALST1_Pos      (10U)
2261 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                    /*!< 0x00000400 */
2262 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
2263 #define CAN_TSR_TERR1_Pos      (11U)
2264 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                    /*!< 0x00000800 */
2265 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
2266 #define CAN_TSR_ABRQ1_Pos      (15U)
2267 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                    /*!< 0x00008000 */
2268 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
2269 #define CAN_TSR_RQCP2_Pos      (16U)
2270 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                    /*!< 0x00010000 */
2271 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
2272 #define CAN_TSR_TXOK2_Pos      (17U)
2273 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                    /*!< 0x00020000 */
2274 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
2275 #define CAN_TSR_ALST2_Pos      (18U)
2276 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                    /*!< 0x00040000 */
2277 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
2278 #define CAN_TSR_TERR2_Pos      (19U)
2279 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                    /*!< 0x00080000 */
2280 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2281 #define CAN_TSR_ABRQ2_Pos      (23U)
2282 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                    /*!< 0x00800000 */
2283 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
2284 #define CAN_TSR_CODE_Pos       (24U)
2285 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                     /*!< 0x03000000 */
2286 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
2287 
2288 #define CAN_TSR_TME_Pos        (26U)
2289 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                      /*!< 0x1C000000 */
2290 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2291 #define CAN_TSR_TME0_Pos       (26U)
2292 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                     /*!< 0x04000000 */
2293 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2294 #define CAN_TSR_TME1_Pos       (27U)
2295 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                     /*!< 0x08000000 */
2296 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2297 #define CAN_TSR_TME2_Pos       (28U)
2298 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                     /*!< 0x10000000 */
2299 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2300 
2301 #define CAN_TSR_LOW_Pos        (29U)
2302 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                      /*!< 0xE0000000 */
2303 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2304 #define CAN_TSR_LOW0_Pos       (29U)
2305 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                     /*!< 0x20000000 */
2306 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2307 #define CAN_TSR_LOW1_Pos       (30U)
2308 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                     /*!< 0x40000000 */
2309 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2310 #define CAN_TSR_LOW2_Pos       (31U)
2311 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                     /*!< 0x80000000 */
2312 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2313 
2314 /*******************  Bit definition for CAN_RF0R register  *******************/
2315 #define CAN_RF0R_FMP0_Pos      (0U)
2316 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                    /*!< 0x00000003 */
2317 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
2318 #define CAN_RF0R_FULL0_Pos     (3U)
2319 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                   /*!< 0x00000008 */
2320 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2321 #define CAN_RF0R_FOVR0_Pos     (4U)
2322 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                   /*!< 0x00000010 */
2323 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2324 #define CAN_RF0R_RFOM0_Pos     (5U)
2325 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                   /*!< 0x00000020 */
2326 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2327 
2328 /*******************  Bit definition for CAN_RF1R register  *******************/
2329 #define CAN_RF1R_FMP1_Pos      (0U)
2330 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                    /*!< 0x00000003 */
2331 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2332 #define CAN_RF1R_FULL1_Pos     (3U)
2333 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                   /*!< 0x00000008 */
2334 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2335 #define CAN_RF1R_FOVR1_Pos     (4U)
2336 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                   /*!< 0x00000010 */
2337 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2338 #define CAN_RF1R_RFOM1_Pos     (5U)
2339 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                   /*!< 0x00000020 */
2340 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2341 
2342 /********************  Bit definition for CAN_IER register  *******************/
2343 #define CAN_IER_TMEIE_Pos      (0U)
2344 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                    /*!< 0x00000001 */
2345 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2346 #define CAN_IER_FMPIE0_Pos     (1U)
2347 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                   /*!< 0x00000002 */
2348 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2349 #define CAN_IER_FFIE0_Pos      (2U)
2350 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                    /*!< 0x00000004 */
2351 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2352 #define CAN_IER_FOVIE0_Pos     (3U)
2353 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                   /*!< 0x00000008 */
2354 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2355 #define CAN_IER_FMPIE1_Pos     (4U)
2356 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                   /*!< 0x00000010 */
2357 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2358 #define CAN_IER_FFIE1_Pos      (5U)
2359 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                    /*!< 0x00000020 */
2360 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2361 #define CAN_IER_FOVIE1_Pos     (6U)
2362 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                   /*!< 0x00000040 */
2363 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2364 #define CAN_IER_EWGIE_Pos      (8U)
2365 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                    /*!< 0x00000100 */
2366 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2367 #define CAN_IER_EPVIE_Pos      (9U)
2368 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                    /*!< 0x00000200 */
2369 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2370 #define CAN_IER_BOFIE_Pos      (10U)
2371 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                    /*!< 0x00000400 */
2372 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2373 #define CAN_IER_LECIE_Pos      (11U)
2374 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                    /*!< 0x00000800 */
2375 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2376 #define CAN_IER_ERRIE_Pos      (15U)
2377 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                    /*!< 0x00008000 */
2378 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2379 #define CAN_IER_WKUIE_Pos      (16U)
2380 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                    /*!< 0x00010000 */
2381 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2382 #define CAN_IER_SLKIE_Pos      (17U)
2383 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                    /*!< 0x00020000 */
2384 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2385 
2386 /********************  Bit definition for CAN_ESR register  *******************/
2387 #define CAN_ESR_EWGF_Pos       (0U)
2388 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                     /*!< 0x00000001 */
2389 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2390 #define CAN_ESR_EPVF_Pos       (1U)
2391 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                     /*!< 0x00000002 */
2392 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2393 #define CAN_ESR_BOFF_Pos       (2U)
2394 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                     /*!< 0x00000004 */
2395 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2396 
2397 #define CAN_ESR_LEC_Pos        (4U)
2398 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000070 */
2399 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2400 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000010 */
2401 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000020 */
2402 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                      /*!< 0x00000040 */
2403 
2404 #define CAN_ESR_TEC_Pos        (16U)
2405 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                     /*!< 0x00FF0000 */
2406 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2407 #define CAN_ESR_REC_Pos        (24U)
2408 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                     /*!< 0xFF000000 */
2409 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2410 
2411 /*******************  Bit definition for CAN_BTR register  ********************/
2412 #define CAN_BTR_BRP_Pos        (0U)
2413 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                    /*!< 0x000003FF */
2414 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2415 #define CAN_BTR_TS1_Pos        (16U)
2416 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                      /*!< 0x000F0000 */
2417 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2418 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                      /*!< 0x00010000 */
2419 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                      /*!< 0x00020000 */
2420 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                      /*!< 0x00040000 */
2421 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                      /*!< 0x00080000 */
2422 #define CAN_BTR_TS2_Pos        (20U)
2423 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                      /*!< 0x00700000 */
2424 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2425 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                      /*!< 0x00100000 */
2426 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                      /*!< 0x00200000 */
2427 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                      /*!< 0x00400000 */
2428 #define CAN_BTR_SJW_Pos        (24U)
2429 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                      /*!< 0x03000000 */
2430 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2431 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                      /*!< 0x01000000 */
2432 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                      /*!< 0x02000000 */
2433 #define CAN_BTR_LBKM_Pos       (30U)
2434 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                     /*!< 0x40000000 */
2435 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2436 #define CAN_BTR_SILM_Pos       (31U)
2437 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                     /*!< 0x80000000 */
2438 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2439 
2440 /*!<Mailbox registers */
2441 /******************  Bit definition for CAN_TI0R register  ********************/
2442 #define CAN_TI0R_TXRQ_Pos      (0U)
2443 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                    /*!< 0x00000001 */
2444 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2445 #define CAN_TI0R_RTR_Pos       (1U)
2446 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                     /*!< 0x00000002 */
2447 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2448 #define CAN_TI0R_IDE_Pos       (2U)
2449 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                     /*!< 0x00000004 */
2450 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2451 #define CAN_TI0R_EXID_Pos      (3U)
2452 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                /*!< 0x001FFFF8 */
2453 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2454 #define CAN_TI0R_STID_Pos      (21U)
2455 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                  /*!< 0xFFE00000 */
2456 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2457 
2458 /******************  Bit definition for CAN_TDT0R register  *******************/
2459 #define CAN_TDT0R_DLC_Pos      (0U)
2460 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                    /*!< 0x0000000F */
2461 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2462 #define CAN_TDT0R_TGT_Pos      (8U)
2463 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                    /*!< 0x00000100 */
2464 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2465 #define CAN_TDT0R_TIME_Pos     (16U)
2466 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                /*!< 0xFFFF0000 */
2467 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2468 
2469 /******************  Bit definition for CAN_TDL0R register  *******************/
2470 #define CAN_TDL0R_DATA0_Pos    (0U)
2471 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                 /*!< 0x000000FF */
2472 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2473 #define CAN_TDL0R_DATA1_Pos    (8U)
2474 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */
2475 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2476 #define CAN_TDL0R_DATA2_Pos    (16U)
2477 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */
2478 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2479 #define CAN_TDL0R_DATA3_Pos    (24U)
2480 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                 /*!< 0xFF000000 */
2481 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2482 
2483 /******************  Bit definition for CAN_TDH0R register  *******************/
2484 #define CAN_TDH0R_DATA4_Pos    (0U)
2485 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                 /*!< 0x000000FF */
2486 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2487 #define CAN_TDH0R_DATA5_Pos    (8U)
2488 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */
2489 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2490 #define CAN_TDH0R_DATA6_Pos    (16U)
2491 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */
2492 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2493 #define CAN_TDH0R_DATA7_Pos    (24U)
2494 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                 /*!< 0xFF000000 */
2495 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2496 
2497 /*******************  Bit definition for CAN_TI1R register  *******************/
2498 #define CAN_TI1R_TXRQ_Pos      (0U)
2499 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                    /*!< 0x00000001 */
2500 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2501 #define CAN_TI1R_RTR_Pos       (1U)
2502 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                     /*!< 0x00000002 */
2503 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2504 #define CAN_TI1R_IDE_Pos       (2U)
2505 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                     /*!< 0x00000004 */
2506 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2507 #define CAN_TI1R_EXID_Pos      (3U)
2508 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                /*!< 0x001FFFF8 */
2509 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2510 #define CAN_TI1R_STID_Pos      (21U)
2511 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                  /*!< 0xFFE00000 */
2512 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2513 
2514 /*******************  Bit definition for CAN_TDT1R register  ******************/
2515 #define CAN_TDT1R_DLC_Pos      (0U)
2516 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                    /*!< 0x0000000F */
2517 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2518 #define CAN_TDT1R_TGT_Pos      (8U)
2519 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                    /*!< 0x00000100 */
2520 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2521 #define CAN_TDT1R_TIME_Pos     (16U)
2522 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                /*!< 0xFFFF0000 */
2523 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2524 
2525 /*******************  Bit definition for CAN_TDL1R register  ******************/
2526 #define CAN_TDL1R_DATA0_Pos    (0U)
2527 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                 /*!< 0x000000FF */
2528 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2529 #define CAN_TDL1R_DATA1_Pos    (8U)
2530 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */
2531 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2532 #define CAN_TDL1R_DATA2_Pos    (16U)
2533 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */
2534 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2535 #define CAN_TDL1R_DATA3_Pos    (24U)
2536 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                 /*!< 0xFF000000 */
2537 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2538 
2539 /*******************  Bit definition for CAN_TDH1R register  ******************/
2540 #define CAN_TDH1R_DATA4_Pos    (0U)
2541 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                 /*!< 0x000000FF */
2542 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2543 #define CAN_TDH1R_DATA5_Pos    (8U)
2544 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */
2545 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2546 #define CAN_TDH1R_DATA6_Pos    (16U)
2547 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */
2548 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2549 #define CAN_TDH1R_DATA7_Pos    (24U)
2550 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                 /*!< 0xFF000000 */
2551 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2552 
2553 /*******************  Bit definition for CAN_TI2R register  *******************/
2554 #define CAN_TI2R_TXRQ_Pos      (0U)
2555 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                    /*!< 0x00000001 */
2556 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2557 #define CAN_TI2R_RTR_Pos       (1U)
2558 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                     /*!< 0x00000002 */
2559 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2560 #define CAN_TI2R_IDE_Pos       (2U)
2561 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                     /*!< 0x00000004 */
2562 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2563 #define CAN_TI2R_EXID_Pos      (3U)
2564 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                /*!< 0x001FFFF8 */
2565 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2566 #define CAN_TI2R_STID_Pos      (21U)
2567 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                  /*!< 0xFFE00000 */
2568 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2569 
2570 /*******************  Bit definition for CAN_TDT2R register  ******************/
2571 #define CAN_TDT2R_DLC_Pos      (0U)
2572 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                    /*!< 0x0000000F */
2573 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2574 #define CAN_TDT2R_TGT_Pos      (8U)
2575 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                    /*!< 0x00000100 */
2576 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2577 #define CAN_TDT2R_TIME_Pos     (16U)
2578 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                /*!< 0xFFFF0000 */
2579 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2580 
2581 /*******************  Bit definition for CAN_TDL2R register  ******************/
2582 #define CAN_TDL2R_DATA0_Pos    (0U)
2583 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                 /*!< 0x000000FF */
2584 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2585 #define CAN_TDL2R_DATA1_Pos    (8U)
2586 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                 /*!< 0x0000FF00 */
2587 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2588 #define CAN_TDL2R_DATA2_Pos    (16U)
2589 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                 /*!< 0x00FF0000 */
2590 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2591 #define CAN_TDL2R_DATA3_Pos    (24U)
2592 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                 /*!< 0xFF000000 */
2593 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2594 
2595 /*******************  Bit definition for CAN_TDH2R register  ******************/
2596 #define CAN_TDH2R_DATA4_Pos    (0U)
2597 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                 /*!< 0x000000FF */
2598 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2599 #define CAN_TDH2R_DATA5_Pos    (8U)
2600 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                 /*!< 0x0000FF00 */
2601 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2602 #define CAN_TDH2R_DATA6_Pos    (16U)
2603 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                 /*!< 0x00FF0000 */
2604 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2605 #define CAN_TDH2R_DATA7_Pos    (24U)
2606 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                 /*!< 0xFF000000 */
2607 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2608 
2609 /*******************  Bit definition for CAN_RI0R register  *******************/
2610 #define CAN_RI0R_RTR_Pos       (1U)
2611 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                     /*!< 0x00000002 */
2612 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2613 #define CAN_RI0R_IDE_Pos       (2U)
2614 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                     /*!< 0x00000004 */
2615 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2616 #define CAN_RI0R_EXID_Pos      (3U)
2617 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                /*!< 0x001FFFF8 */
2618 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2619 #define CAN_RI0R_STID_Pos      (21U)
2620 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                  /*!< 0xFFE00000 */
2621 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2622 
2623 /*******************  Bit definition for CAN_RDT0R register  ******************/
2624 #define CAN_RDT0R_DLC_Pos      (0U)
2625 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                    /*!< 0x0000000F */
2626 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2627 #define CAN_RDT0R_FMI_Pos      (8U)
2628 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                   /*!< 0x0000FF00 */
2629 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2630 #define CAN_RDT0R_TIME_Pos     (16U)
2631 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                /*!< 0xFFFF0000 */
2632 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2633 
2634 /*******************  Bit definition for CAN_RDL0R register  ******************/
2635 #define CAN_RDL0R_DATA0_Pos    (0U)
2636 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                 /*!< 0x000000FF */
2637 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2638 #define CAN_RDL0R_DATA1_Pos    (8U)
2639 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                 /*!< 0x0000FF00 */
2640 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2641 #define CAN_RDL0R_DATA2_Pos    (16U)
2642 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                 /*!< 0x00FF0000 */
2643 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2644 #define CAN_RDL0R_DATA3_Pos    (24U)
2645 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                 /*!< 0xFF000000 */
2646 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2647 
2648 /*******************  Bit definition for CAN_RDH0R register  ******************/
2649 #define CAN_RDH0R_DATA4_Pos    (0U)
2650 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                 /*!< 0x000000FF */
2651 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2652 #define CAN_RDH0R_DATA5_Pos    (8U)
2653 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                 /*!< 0x0000FF00 */
2654 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2655 #define CAN_RDH0R_DATA6_Pos    (16U)
2656 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                 /*!< 0x00FF0000 */
2657 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2658 #define CAN_RDH0R_DATA7_Pos    (24U)
2659 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                 /*!< 0xFF000000 */
2660 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2661 
2662 /*******************  Bit definition for CAN_RI1R register  *******************/
2663 #define CAN_RI1R_RTR_Pos       (1U)
2664 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                     /*!< 0x00000002 */
2665 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2666 #define CAN_RI1R_IDE_Pos       (2U)
2667 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                     /*!< 0x00000004 */
2668 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2669 #define CAN_RI1R_EXID_Pos      (3U)
2670 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                /*!< 0x001FFFF8 */
2671 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2672 #define CAN_RI1R_STID_Pos      (21U)
2673 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                  /*!< 0xFFE00000 */
2674 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2675 
2676 /*******************  Bit definition for CAN_RDT1R register  ******************/
2677 #define CAN_RDT1R_DLC_Pos      (0U)
2678 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                    /*!< 0x0000000F */
2679 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2680 #define CAN_RDT1R_FMI_Pos      (8U)
2681 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                   /*!< 0x0000FF00 */
2682 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2683 #define CAN_RDT1R_TIME_Pos     (16U)
2684 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                /*!< 0xFFFF0000 */
2685 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2686 
2687 /*******************  Bit definition for CAN_RDL1R register  ******************/
2688 #define CAN_RDL1R_DATA0_Pos    (0U)
2689 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                 /*!< 0x000000FF */
2690 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2691 #define CAN_RDL1R_DATA1_Pos    (8U)
2692 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                 /*!< 0x0000FF00 */
2693 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2694 #define CAN_RDL1R_DATA2_Pos    (16U)
2695 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                 /*!< 0x00FF0000 */
2696 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2697 #define CAN_RDL1R_DATA3_Pos    (24U)
2698 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                 /*!< 0xFF000000 */
2699 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2700 
2701 /*******************  Bit definition for CAN_RDH1R register  ******************/
2702 #define CAN_RDH1R_DATA4_Pos    (0U)
2703 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                 /*!< 0x000000FF */
2704 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2705 #define CAN_RDH1R_DATA5_Pos    (8U)
2706 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                 /*!< 0x0000FF00 */
2707 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2708 #define CAN_RDH1R_DATA6_Pos    (16U)
2709 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                 /*!< 0x00FF0000 */
2710 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2711 #define CAN_RDH1R_DATA7_Pos    (24U)
2712 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                 /*!< 0xFF000000 */
2713 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2714 
2715 /*!<CAN filter registers */
2716 /*******************  Bit definition for CAN_FMR register  ********************/
2717 #define CAN_FMR_FINIT_Pos      (0U)
2718 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                    /*!< 0x00000001 */
2719 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2720 
2721 /*******************  Bit definition for CAN_FM1R register  *******************/
2722 #define CAN_FM1R_FBM_Pos       (0U)
2723 #define CAN_FM1R_FBM_Msk       (0x3FFFUL << CAN_FM1R_FBM_Pos)                  /*!< 0x00003FFF */
2724 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2725 #define CAN_FM1R_FBM0_Pos      (0U)
2726 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                    /*!< 0x00000001 */
2727 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2728 #define CAN_FM1R_FBM1_Pos      (1U)
2729 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                    /*!< 0x00000002 */
2730 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2731 #define CAN_FM1R_FBM2_Pos      (2U)
2732 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                    /*!< 0x00000004 */
2733 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2734 #define CAN_FM1R_FBM3_Pos      (3U)
2735 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                    /*!< 0x00000008 */
2736 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2737 #define CAN_FM1R_FBM4_Pos      (4U)
2738 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                    /*!< 0x00000010 */
2739 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2740 #define CAN_FM1R_FBM5_Pos      (5U)
2741 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                    /*!< 0x00000020 */
2742 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2743 #define CAN_FM1R_FBM6_Pos      (6U)
2744 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                    /*!< 0x00000040 */
2745 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2746 #define CAN_FM1R_FBM7_Pos      (7U)
2747 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                    /*!< 0x00000080 */
2748 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2749 #define CAN_FM1R_FBM8_Pos      (8U)
2750 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                    /*!< 0x00000100 */
2751 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2752 #define CAN_FM1R_FBM9_Pos      (9U)
2753 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                    /*!< 0x00000200 */
2754 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2755 #define CAN_FM1R_FBM10_Pos     (10U)
2756 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                   /*!< 0x00000400 */
2757 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2758 #define CAN_FM1R_FBM11_Pos     (11U)
2759 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                   /*!< 0x00000800 */
2760 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2761 #define CAN_FM1R_FBM12_Pos     (12U)
2762 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                   /*!< 0x00001000 */
2763 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2764 #define CAN_FM1R_FBM13_Pos     (13U)
2765 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                   /*!< 0x00002000 */
2766 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2767 
2768 /*******************  Bit definition for CAN_FS1R register  *******************/
2769 #define CAN_FS1R_FSC_Pos       (0U)
2770 #define CAN_FS1R_FSC_Msk       (0x3FFFUL << CAN_FS1R_FSC_Pos)                  /*!< 0x00003FFF */
2771 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2772 #define CAN_FS1R_FSC0_Pos      (0U)
2773 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                    /*!< 0x00000001 */
2774 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2775 #define CAN_FS1R_FSC1_Pos      (1U)
2776 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                    /*!< 0x00000002 */
2777 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2778 #define CAN_FS1R_FSC2_Pos      (2U)
2779 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                    /*!< 0x00000004 */
2780 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2781 #define CAN_FS1R_FSC3_Pos      (3U)
2782 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                    /*!< 0x00000008 */
2783 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2784 #define CAN_FS1R_FSC4_Pos      (4U)
2785 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                    /*!< 0x00000010 */
2786 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2787 #define CAN_FS1R_FSC5_Pos      (5U)
2788 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                    /*!< 0x00000020 */
2789 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2790 #define CAN_FS1R_FSC6_Pos      (6U)
2791 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                    /*!< 0x00000040 */
2792 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2793 #define CAN_FS1R_FSC7_Pos      (7U)
2794 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                    /*!< 0x00000080 */
2795 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2796 #define CAN_FS1R_FSC8_Pos      (8U)
2797 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                    /*!< 0x00000100 */
2798 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2799 #define CAN_FS1R_FSC9_Pos      (9U)
2800 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                    /*!< 0x00000200 */
2801 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2802 #define CAN_FS1R_FSC10_Pos     (10U)
2803 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                   /*!< 0x00000400 */
2804 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2805 #define CAN_FS1R_FSC11_Pos     (11U)
2806 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                   /*!< 0x00000800 */
2807 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2808 #define CAN_FS1R_FSC12_Pos     (12U)
2809 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                   /*!< 0x00001000 */
2810 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2811 #define CAN_FS1R_FSC13_Pos     (13U)
2812 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                   /*!< 0x00002000 */
2813 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2814 
2815 /******************  Bit definition for CAN_FFA1R register  *******************/
2816 #define CAN_FFA1R_FFA_Pos      (0U)
2817 #define CAN_FFA1R_FFA_Msk      (0x3FFFUL << CAN_FFA1R_FFA_Pos)                 /*!< 0x00003FFF */
2818 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2819 #define CAN_FFA1R_FFA0_Pos     (0U)
2820 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                   /*!< 0x00000001 */
2821 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
2822 #define CAN_FFA1R_FFA1_Pos     (1U)
2823 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                   /*!< 0x00000002 */
2824 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
2825 #define CAN_FFA1R_FFA2_Pos     (2U)
2826 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                   /*!< 0x00000004 */
2827 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
2828 #define CAN_FFA1R_FFA3_Pos     (3U)
2829 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                   /*!< 0x00000008 */
2830 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
2831 #define CAN_FFA1R_FFA4_Pos     (4U)
2832 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                   /*!< 0x00000010 */
2833 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
2834 #define CAN_FFA1R_FFA5_Pos     (5U)
2835 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                   /*!< 0x00000020 */
2836 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
2837 #define CAN_FFA1R_FFA6_Pos     (6U)
2838 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                   /*!< 0x00000040 */
2839 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
2840 #define CAN_FFA1R_FFA7_Pos     (7U)
2841 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                   /*!< 0x00000080 */
2842 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
2843 #define CAN_FFA1R_FFA8_Pos     (8U)
2844 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                   /*!< 0x00000100 */
2845 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
2846 #define CAN_FFA1R_FFA9_Pos     (9U)
2847 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                   /*!< 0x00000200 */
2848 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
2849 #define CAN_FFA1R_FFA10_Pos    (10U)
2850 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                  /*!< 0x00000400 */
2851 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
2852 #define CAN_FFA1R_FFA11_Pos    (11U)
2853 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                  /*!< 0x00000800 */
2854 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
2855 #define CAN_FFA1R_FFA12_Pos    (12U)
2856 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                  /*!< 0x00001000 */
2857 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
2858 #define CAN_FFA1R_FFA13_Pos    (13U)
2859 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                  /*!< 0x00002000 */
2860 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
2861 
2862 /*******************  Bit definition for CAN_FA1R register  *******************/
2863 #define CAN_FA1R_FACT_Pos      (0U)
2864 #define CAN_FA1R_FACT_Msk      (0x3FFFUL << CAN_FA1R_FACT_Pos)                 /*!< 0x00003FFF */
2865 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2866 #define CAN_FA1R_FACT0_Pos     (0U)
2867 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                   /*!< 0x00000001 */
2868 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
2869 #define CAN_FA1R_FACT1_Pos     (1U)
2870 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                   /*!< 0x00000002 */
2871 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
2872 #define CAN_FA1R_FACT2_Pos     (2U)
2873 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                   /*!< 0x00000004 */
2874 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
2875 #define CAN_FA1R_FACT3_Pos     (3U)
2876 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                   /*!< 0x00000008 */
2877 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
2878 #define CAN_FA1R_FACT4_Pos     (4U)
2879 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                   /*!< 0x00000010 */
2880 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
2881 #define CAN_FA1R_FACT5_Pos     (5U)
2882 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                   /*!< 0x00000020 */
2883 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
2884 #define CAN_FA1R_FACT6_Pos     (6U)
2885 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                   /*!< 0x00000040 */
2886 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
2887 #define CAN_FA1R_FACT7_Pos     (7U)
2888 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                   /*!< 0x00000080 */
2889 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
2890 #define CAN_FA1R_FACT8_Pos     (8U)
2891 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                   /*!< 0x00000100 */
2892 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
2893 #define CAN_FA1R_FACT9_Pos     (9U)
2894 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                   /*!< 0x00000200 */
2895 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
2896 #define CAN_FA1R_FACT10_Pos    (10U)
2897 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                  /*!< 0x00000400 */
2898 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
2899 #define CAN_FA1R_FACT11_Pos    (11U)
2900 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                  /*!< 0x00000800 */
2901 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
2902 #define CAN_FA1R_FACT12_Pos    (12U)
2903 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                  /*!< 0x00001000 */
2904 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
2905 #define CAN_FA1R_FACT13_Pos    (13U)
2906 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                  /*!< 0x00002000 */
2907 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
2908 
2909 /*******************  Bit definition for CAN_F0R1 register  *******************/
2910 #define CAN_F0R1_FB0_Pos       (0U)
2911 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                     /*!< 0x00000001 */
2912 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2913 #define CAN_F0R1_FB1_Pos       (1U)
2914 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                     /*!< 0x00000002 */
2915 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2916 #define CAN_F0R1_FB2_Pos       (2U)
2917 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                     /*!< 0x00000004 */
2918 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2919 #define CAN_F0R1_FB3_Pos       (3U)
2920 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                     /*!< 0x00000008 */
2921 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2922 #define CAN_F0R1_FB4_Pos       (4U)
2923 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                     /*!< 0x00000010 */
2924 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2925 #define CAN_F0R1_FB5_Pos       (5U)
2926 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                     /*!< 0x00000020 */
2927 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2928 #define CAN_F0R1_FB6_Pos       (6U)
2929 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                     /*!< 0x00000040 */
2930 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2931 #define CAN_F0R1_FB7_Pos       (7U)
2932 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                     /*!< 0x00000080 */
2933 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2934 #define CAN_F0R1_FB8_Pos       (8U)
2935 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                     /*!< 0x00000100 */
2936 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2937 #define CAN_F0R1_FB9_Pos       (9U)
2938 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                     /*!< 0x00000200 */
2939 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2940 #define CAN_F0R1_FB10_Pos      (10U)
2941 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                    /*!< 0x00000400 */
2942 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2943 #define CAN_F0R1_FB11_Pos      (11U)
2944 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                    /*!< 0x00000800 */
2945 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2946 #define CAN_F0R1_FB12_Pos      (12U)
2947 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                    /*!< 0x00001000 */
2948 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2949 #define CAN_F0R1_FB13_Pos      (13U)
2950 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                    /*!< 0x00002000 */
2951 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2952 #define CAN_F0R1_FB14_Pos      (14U)
2953 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                    /*!< 0x00004000 */
2954 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2955 #define CAN_F0R1_FB15_Pos      (15U)
2956 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                    /*!< 0x00008000 */
2957 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2958 #define CAN_F0R1_FB16_Pos      (16U)
2959 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                    /*!< 0x00010000 */
2960 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2961 #define CAN_F0R1_FB17_Pos      (17U)
2962 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                    /*!< 0x00020000 */
2963 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2964 #define CAN_F0R1_FB18_Pos      (18U)
2965 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                    /*!< 0x00040000 */
2966 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2967 #define CAN_F0R1_FB19_Pos      (19U)
2968 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                    /*!< 0x00080000 */
2969 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2970 #define CAN_F0R1_FB20_Pos      (20U)
2971 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                    /*!< 0x00100000 */
2972 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2973 #define CAN_F0R1_FB21_Pos      (21U)
2974 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                    /*!< 0x00200000 */
2975 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2976 #define CAN_F0R1_FB22_Pos      (22U)
2977 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                    /*!< 0x00400000 */
2978 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2979 #define CAN_F0R1_FB23_Pos      (23U)
2980 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                    /*!< 0x00800000 */
2981 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2982 #define CAN_F0R1_FB24_Pos      (24U)
2983 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                    /*!< 0x01000000 */
2984 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2985 #define CAN_F0R1_FB25_Pos      (25U)
2986 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                    /*!< 0x02000000 */
2987 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2988 #define CAN_F0R1_FB26_Pos      (26U)
2989 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                    /*!< 0x04000000 */
2990 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2991 #define CAN_F0R1_FB27_Pos      (27U)
2992 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                    /*!< 0x08000000 */
2993 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2994 #define CAN_F0R1_FB28_Pos      (28U)
2995 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                    /*!< 0x10000000 */
2996 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2997 #define CAN_F0R1_FB29_Pos      (29U)
2998 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                    /*!< 0x20000000 */
2999 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
3000 #define CAN_F0R1_FB30_Pos      (30U)
3001 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                    /*!< 0x40000000 */
3002 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
3003 #define CAN_F0R1_FB31_Pos      (31U)
3004 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                    /*!< 0x80000000 */
3005 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
3006 
3007 /*******************  Bit definition for CAN_F1R1 register  *******************/
3008 #define CAN_F1R1_FB0_Pos       (0U)
3009 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                     /*!< 0x00000001 */
3010 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
3011 #define CAN_F1R1_FB1_Pos       (1U)
3012 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                     /*!< 0x00000002 */
3013 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3014 #define CAN_F1R1_FB2_Pos       (2U)
3015 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                     /*!< 0x00000004 */
3016 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3017 #define CAN_F1R1_FB3_Pos       (3U)
3018 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                     /*!< 0x00000008 */
3019 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3020 #define CAN_F1R1_FB4_Pos       (4U)
3021 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                     /*!< 0x00000010 */
3022 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3023 #define CAN_F1R1_FB5_Pos       (5U)
3024 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                     /*!< 0x00000020 */
3025 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3026 #define CAN_F1R1_FB6_Pos       (6U)
3027 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                     /*!< 0x00000040 */
3028 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3029 #define CAN_F1R1_FB7_Pos       (7U)
3030 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                     /*!< 0x00000080 */
3031 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3032 #define CAN_F1R1_FB8_Pos       (8U)
3033 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                     /*!< 0x00000100 */
3034 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3035 #define CAN_F1R1_FB9_Pos       (9U)
3036 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                     /*!< 0x00000200 */
3037 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3038 #define CAN_F1R1_FB10_Pos      (10U)
3039 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                    /*!< 0x00000400 */
3040 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3041 #define CAN_F1R1_FB11_Pos      (11U)
3042 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                    /*!< 0x00000800 */
3043 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3044 #define CAN_F1R1_FB12_Pos      (12U)
3045 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                    /*!< 0x00001000 */
3046 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3047 #define CAN_F1R1_FB13_Pos      (13U)
3048 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                    /*!< 0x00002000 */
3049 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3050 #define CAN_F1R1_FB14_Pos      (14U)
3051 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                    /*!< 0x00004000 */
3052 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3053 #define CAN_F1R1_FB15_Pos      (15U)
3054 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                    /*!< 0x00008000 */
3055 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3056 #define CAN_F1R1_FB16_Pos      (16U)
3057 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                    /*!< 0x00010000 */
3058 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3059 #define CAN_F1R1_FB17_Pos      (17U)
3060 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                    /*!< 0x00020000 */
3061 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3062 #define CAN_F1R1_FB18_Pos      (18U)
3063 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                    /*!< 0x00040000 */
3064 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3065 #define CAN_F1R1_FB19_Pos      (19U)
3066 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                    /*!< 0x00080000 */
3067 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3068 #define CAN_F1R1_FB20_Pos      (20U)
3069 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                    /*!< 0x00100000 */
3070 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3071 #define CAN_F1R1_FB21_Pos      (21U)
3072 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                    /*!< 0x00200000 */
3073 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3074 #define CAN_F1R1_FB22_Pos      (22U)
3075 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                    /*!< 0x00400000 */
3076 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3077 #define CAN_F1R1_FB23_Pos      (23U)
3078 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                    /*!< 0x00800000 */
3079 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3080 #define CAN_F1R1_FB24_Pos      (24U)
3081 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                    /*!< 0x01000000 */
3082 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3083 #define CAN_F1R1_FB25_Pos      (25U)
3084 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                    /*!< 0x02000000 */
3085 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3086 #define CAN_F1R1_FB26_Pos      (26U)
3087 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                    /*!< 0x04000000 */
3088 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3089 #define CAN_F1R1_FB27_Pos      (27U)
3090 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                    /*!< 0x08000000 */
3091 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3092 #define CAN_F1R1_FB28_Pos      (28U)
3093 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                    /*!< 0x10000000 */
3094 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3095 #define CAN_F1R1_FB29_Pos      (29U)
3096 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                    /*!< 0x20000000 */
3097 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3098 #define CAN_F1R1_FB30_Pos      (30U)
3099 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                    /*!< 0x40000000 */
3100 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3101 #define CAN_F1R1_FB31_Pos      (31U)
3102 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                    /*!< 0x80000000 */
3103 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3104 
3105 /*******************  Bit definition for CAN_F2R1 register  *******************/
3106 #define CAN_F2R1_FB0_Pos       (0U)
3107 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                     /*!< 0x00000001 */
3108 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3109 #define CAN_F2R1_FB1_Pos       (1U)
3110 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                     /*!< 0x00000002 */
3111 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3112 #define CAN_F2R1_FB2_Pos       (2U)
3113 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                     /*!< 0x00000004 */
3114 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3115 #define CAN_F2R1_FB3_Pos       (3U)
3116 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                     /*!< 0x00000008 */
3117 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3118 #define CAN_F2R1_FB4_Pos       (4U)
3119 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                     /*!< 0x00000010 */
3120 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3121 #define CAN_F2R1_FB5_Pos       (5U)
3122 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                     /*!< 0x00000020 */
3123 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3124 #define CAN_F2R1_FB6_Pos       (6U)
3125 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                     /*!< 0x00000040 */
3126 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3127 #define CAN_F2R1_FB7_Pos       (7U)
3128 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                     /*!< 0x00000080 */
3129 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3130 #define CAN_F2R1_FB8_Pos       (8U)
3131 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                     /*!< 0x00000100 */
3132 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3133 #define CAN_F2R1_FB9_Pos       (9U)
3134 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                     /*!< 0x00000200 */
3135 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3136 #define CAN_F2R1_FB10_Pos      (10U)
3137 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                    /*!< 0x00000400 */
3138 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3139 #define CAN_F2R1_FB11_Pos      (11U)
3140 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                    /*!< 0x00000800 */
3141 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3142 #define CAN_F2R1_FB12_Pos      (12U)
3143 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                    /*!< 0x00001000 */
3144 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3145 #define CAN_F2R1_FB13_Pos      (13U)
3146 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                    /*!< 0x00002000 */
3147 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3148 #define CAN_F2R1_FB14_Pos      (14U)
3149 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                    /*!< 0x00004000 */
3150 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3151 #define CAN_F2R1_FB15_Pos      (15U)
3152 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                    /*!< 0x00008000 */
3153 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3154 #define CAN_F2R1_FB16_Pos      (16U)
3155 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                    /*!< 0x00010000 */
3156 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3157 #define CAN_F2R1_FB17_Pos      (17U)
3158 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                    /*!< 0x00020000 */
3159 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3160 #define CAN_F2R1_FB18_Pos      (18U)
3161 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                    /*!< 0x00040000 */
3162 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3163 #define CAN_F2R1_FB19_Pos      (19U)
3164 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                    /*!< 0x00080000 */
3165 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3166 #define CAN_F2R1_FB20_Pos      (20U)
3167 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                    /*!< 0x00100000 */
3168 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3169 #define CAN_F2R1_FB21_Pos      (21U)
3170 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                    /*!< 0x00200000 */
3171 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3172 #define CAN_F2R1_FB22_Pos      (22U)
3173 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                    /*!< 0x00400000 */
3174 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3175 #define CAN_F2R1_FB23_Pos      (23U)
3176 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                    /*!< 0x00800000 */
3177 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3178 #define CAN_F2R1_FB24_Pos      (24U)
3179 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                    /*!< 0x01000000 */
3180 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3181 #define CAN_F2R1_FB25_Pos      (25U)
3182 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                    /*!< 0x02000000 */
3183 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3184 #define CAN_F2R1_FB26_Pos      (26U)
3185 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                    /*!< 0x04000000 */
3186 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3187 #define CAN_F2R1_FB27_Pos      (27U)
3188 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                    /*!< 0x08000000 */
3189 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3190 #define CAN_F2R1_FB28_Pos      (28U)
3191 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                    /*!< 0x10000000 */
3192 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3193 #define CAN_F2R1_FB29_Pos      (29U)
3194 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                    /*!< 0x20000000 */
3195 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3196 #define CAN_F2R1_FB30_Pos      (30U)
3197 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                    /*!< 0x40000000 */
3198 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3199 #define CAN_F2R1_FB31_Pos      (31U)
3200 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                    /*!< 0x80000000 */
3201 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3202 
3203 /*******************  Bit definition for CAN_F3R1 register  *******************/
3204 #define CAN_F3R1_FB0_Pos       (0U)
3205 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                     /*!< 0x00000001 */
3206 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3207 #define CAN_F3R1_FB1_Pos       (1U)
3208 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                     /*!< 0x00000002 */
3209 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3210 #define CAN_F3R1_FB2_Pos       (2U)
3211 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                     /*!< 0x00000004 */
3212 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3213 #define CAN_F3R1_FB3_Pos       (3U)
3214 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                     /*!< 0x00000008 */
3215 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3216 #define CAN_F3R1_FB4_Pos       (4U)
3217 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                     /*!< 0x00000010 */
3218 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3219 #define CAN_F3R1_FB5_Pos       (5U)
3220 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                     /*!< 0x00000020 */
3221 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3222 #define CAN_F3R1_FB6_Pos       (6U)
3223 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                     /*!< 0x00000040 */
3224 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3225 #define CAN_F3R1_FB7_Pos       (7U)
3226 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                     /*!< 0x00000080 */
3227 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3228 #define CAN_F3R1_FB8_Pos       (8U)
3229 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                     /*!< 0x00000100 */
3230 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3231 #define CAN_F3R1_FB9_Pos       (9U)
3232 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                     /*!< 0x00000200 */
3233 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3234 #define CAN_F3R1_FB10_Pos      (10U)
3235 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                    /*!< 0x00000400 */
3236 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3237 #define CAN_F3R1_FB11_Pos      (11U)
3238 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                    /*!< 0x00000800 */
3239 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3240 #define CAN_F3R1_FB12_Pos      (12U)
3241 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                    /*!< 0x00001000 */
3242 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3243 #define CAN_F3R1_FB13_Pos      (13U)
3244 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                    /*!< 0x00002000 */
3245 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3246 #define CAN_F3R1_FB14_Pos      (14U)
3247 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                    /*!< 0x00004000 */
3248 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3249 #define CAN_F3R1_FB15_Pos      (15U)
3250 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                    /*!< 0x00008000 */
3251 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3252 #define CAN_F3R1_FB16_Pos      (16U)
3253 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                    /*!< 0x00010000 */
3254 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3255 #define CAN_F3R1_FB17_Pos      (17U)
3256 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                    /*!< 0x00020000 */
3257 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3258 #define CAN_F3R1_FB18_Pos      (18U)
3259 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                    /*!< 0x00040000 */
3260 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3261 #define CAN_F3R1_FB19_Pos      (19U)
3262 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                    /*!< 0x00080000 */
3263 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3264 #define CAN_F3R1_FB20_Pos      (20U)
3265 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                    /*!< 0x00100000 */
3266 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3267 #define CAN_F3R1_FB21_Pos      (21U)
3268 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                    /*!< 0x00200000 */
3269 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3270 #define CAN_F3R1_FB22_Pos      (22U)
3271 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                    /*!< 0x00400000 */
3272 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3273 #define CAN_F3R1_FB23_Pos      (23U)
3274 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                    /*!< 0x00800000 */
3275 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3276 #define CAN_F3R1_FB24_Pos      (24U)
3277 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                    /*!< 0x01000000 */
3278 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3279 #define CAN_F3R1_FB25_Pos      (25U)
3280 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                    /*!< 0x02000000 */
3281 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3282 #define CAN_F3R1_FB26_Pos      (26U)
3283 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                    /*!< 0x04000000 */
3284 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3285 #define CAN_F3R1_FB27_Pos      (27U)
3286 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                    /*!< 0x08000000 */
3287 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3288 #define CAN_F3R1_FB28_Pos      (28U)
3289 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                    /*!< 0x10000000 */
3290 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3291 #define CAN_F3R1_FB29_Pos      (29U)
3292 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                    /*!< 0x20000000 */
3293 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3294 #define CAN_F3R1_FB30_Pos      (30U)
3295 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                    /*!< 0x40000000 */
3296 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3297 #define CAN_F3R1_FB31_Pos      (31U)
3298 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                    /*!< 0x80000000 */
3299 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3300 
3301 /*******************  Bit definition for CAN_F4R1 register  *******************/
3302 #define CAN_F4R1_FB0_Pos       (0U)
3303 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                     /*!< 0x00000001 */
3304 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3305 #define CAN_F4R1_FB1_Pos       (1U)
3306 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                     /*!< 0x00000002 */
3307 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3308 #define CAN_F4R1_FB2_Pos       (2U)
3309 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                     /*!< 0x00000004 */
3310 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3311 #define CAN_F4R1_FB3_Pos       (3U)
3312 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                     /*!< 0x00000008 */
3313 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3314 #define CAN_F4R1_FB4_Pos       (4U)
3315 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                     /*!< 0x00000010 */
3316 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3317 #define CAN_F4R1_FB5_Pos       (5U)
3318 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                     /*!< 0x00000020 */
3319 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3320 #define CAN_F4R1_FB6_Pos       (6U)
3321 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                     /*!< 0x00000040 */
3322 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3323 #define CAN_F4R1_FB7_Pos       (7U)
3324 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                     /*!< 0x00000080 */
3325 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3326 #define CAN_F4R1_FB8_Pos       (8U)
3327 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                     /*!< 0x00000100 */
3328 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3329 #define CAN_F4R1_FB9_Pos       (9U)
3330 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                     /*!< 0x00000200 */
3331 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3332 #define CAN_F4R1_FB10_Pos      (10U)
3333 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                    /*!< 0x00000400 */
3334 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3335 #define CAN_F4R1_FB11_Pos      (11U)
3336 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                    /*!< 0x00000800 */
3337 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3338 #define CAN_F4R1_FB12_Pos      (12U)
3339 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                    /*!< 0x00001000 */
3340 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3341 #define CAN_F4R1_FB13_Pos      (13U)
3342 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                    /*!< 0x00002000 */
3343 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3344 #define CAN_F4R1_FB14_Pos      (14U)
3345 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                    /*!< 0x00004000 */
3346 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3347 #define CAN_F4R1_FB15_Pos      (15U)
3348 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                    /*!< 0x00008000 */
3349 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3350 #define CAN_F4R1_FB16_Pos      (16U)
3351 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                    /*!< 0x00010000 */
3352 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3353 #define CAN_F4R1_FB17_Pos      (17U)
3354 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                    /*!< 0x00020000 */
3355 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3356 #define CAN_F4R1_FB18_Pos      (18U)
3357 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                    /*!< 0x00040000 */
3358 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3359 #define CAN_F4R1_FB19_Pos      (19U)
3360 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                    /*!< 0x00080000 */
3361 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3362 #define CAN_F4R1_FB20_Pos      (20U)
3363 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                    /*!< 0x00100000 */
3364 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3365 #define CAN_F4R1_FB21_Pos      (21U)
3366 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                    /*!< 0x00200000 */
3367 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3368 #define CAN_F4R1_FB22_Pos      (22U)
3369 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                    /*!< 0x00400000 */
3370 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3371 #define CAN_F4R1_FB23_Pos      (23U)
3372 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                    /*!< 0x00800000 */
3373 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3374 #define CAN_F4R1_FB24_Pos      (24U)
3375 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                    /*!< 0x01000000 */
3376 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3377 #define CAN_F4R1_FB25_Pos      (25U)
3378 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                    /*!< 0x02000000 */
3379 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3380 #define CAN_F4R1_FB26_Pos      (26U)
3381 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                    /*!< 0x04000000 */
3382 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3383 #define CAN_F4R1_FB27_Pos      (27U)
3384 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                    /*!< 0x08000000 */
3385 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3386 #define CAN_F4R1_FB28_Pos      (28U)
3387 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                    /*!< 0x10000000 */
3388 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3389 #define CAN_F4R1_FB29_Pos      (29U)
3390 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                    /*!< 0x20000000 */
3391 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3392 #define CAN_F4R1_FB30_Pos      (30U)
3393 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                    /*!< 0x40000000 */
3394 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3395 #define CAN_F4R1_FB31_Pos      (31U)
3396 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                    /*!< 0x80000000 */
3397 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3398 
3399 /*******************  Bit definition for CAN_F5R1 register  *******************/
3400 #define CAN_F5R1_FB0_Pos       (0U)
3401 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                     /*!< 0x00000001 */
3402 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3403 #define CAN_F5R1_FB1_Pos       (1U)
3404 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                     /*!< 0x00000002 */
3405 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3406 #define CAN_F5R1_FB2_Pos       (2U)
3407 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                     /*!< 0x00000004 */
3408 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3409 #define CAN_F5R1_FB3_Pos       (3U)
3410 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                     /*!< 0x00000008 */
3411 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3412 #define CAN_F5R1_FB4_Pos       (4U)
3413 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                     /*!< 0x00000010 */
3414 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3415 #define CAN_F5R1_FB5_Pos       (5U)
3416 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                     /*!< 0x00000020 */
3417 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3418 #define CAN_F5R1_FB6_Pos       (6U)
3419 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                     /*!< 0x00000040 */
3420 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3421 #define CAN_F5R1_FB7_Pos       (7U)
3422 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                     /*!< 0x00000080 */
3423 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3424 #define CAN_F5R1_FB8_Pos       (8U)
3425 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                     /*!< 0x00000100 */
3426 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3427 #define CAN_F5R1_FB9_Pos       (9U)
3428 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                     /*!< 0x00000200 */
3429 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3430 #define CAN_F5R1_FB10_Pos      (10U)
3431 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                    /*!< 0x00000400 */
3432 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3433 #define CAN_F5R1_FB11_Pos      (11U)
3434 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                    /*!< 0x00000800 */
3435 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3436 #define CAN_F5R1_FB12_Pos      (12U)
3437 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                    /*!< 0x00001000 */
3438 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3439 #define CAN_F5R1_FB13_Pos      (13U)
3440 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                    /*!< 0x00002000 */
3441 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3442 #define CAN_F5R1_FB14_Pos      (14U)
3443 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                    /*!< 0x00004000 */
3444 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3445 #define CAN_F5R1_FB15_Pos      (15U)
3446 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                    /*!< 0x00008000 */
3447 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3448 #define CAN_F5R1_FB16_Pos      (16U)
3449 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                    /*!< 0x00010000 */
3450 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3451 #define CAN_F5R1_FB17_Pos      (17U)
3452 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                    /*!< 0x00020000 */
3453 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3454 #define CAN_F5R1_FB18_Pos      (18U)
3455 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                    /*!< 0x00040000 */
3456 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3457 #define CAN_F5R1_FB19_Pos      (19U)
3458 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                    /*!< 0x00080000 */
3459 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3460 #define CAN_F5R1_FB20_Pos      (20U)
3461 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                    /*!< 0x00100000 */
3462 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3463 #define CAN_F5R1_FB21_Pos      (21U)
3464 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                    /*!< 0x00200000 */
3465 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3466 #define CAN_F5R1_FB22_Pos      (22U)
3467 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                    /*!< 0x00400000 */
3468 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3469 #define CAN_F5R1_FB23_Pos      (23U)
3470 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                    /*!< 0x00800000 */
3471 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3472 #define CAN_F5R1_FB24_Pos      (24U)
3473 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                    /*!< 0x01000000 */
3474 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3475 #define CAN_F5R1_FB25_Pos      (25U)
3476 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                    /*!< 0x02000000 */
3477 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3478 #define CAN_F5R1_FB26_Pos      (26U)
3479 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                    /*!< 0x04000000 */
3480 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3481 #define CAN_F5R1_FB27_Pos      (27U)
3482 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                    /*!< 0x08000000 */
3483 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3484 #define CAN_F5R1_FB28_Pos      (28U)
3485 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                    /*!< 0x10000000 */
3486 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3487 #define CAN_F5R1_FB29_Pos      (29U)
3488 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                    /*!< 0x20000000 */
3489 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3490 #define CAN_F5R1_FB30_Pos      (30U)
3491 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                    /*!< 0x40000000 */
3492 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3493 #define CAN_F5R1_FB31_Pos      (31U)
3494 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                    /*!< 0x80000000 */
3495 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3496 
3497 /*******************  Bit definition for CAN_F6R1 register  *******************/
3498 #define CAN_F6R1_FB0_Pos       (0U)
3499 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                     /*!< 0x00000001 */
3500 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3501 #define CAN_F6R1_FB1_Pos       (1U)
3502 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                     /*!< 0x00000002 */
3503 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3504 #define CAN_F6R1_FB2_Pos       (2U)
3505 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                     /*!< 0x00000004 */
3506 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3507 #define CAN_F6R1_FB3_Pos       (3U)
3508 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                     /*!< 0x00000008 */
3509 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3510 #define CAN_F6R1_FB4_Pos       (4U)
3511 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                     /*!< 0x00000010 */
3512 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3513 #define CAN_F6R1_FB5_Pos       (5U)
3514 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                     /*!< 0x00000020 */
3515 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3516 #define CAN_F6R1_FB6_Pos       (6U)
3517 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                     /*!< 0x00000040 */
3518 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3519 #define CAN_F6R1_FB7_Pos       (7U)
3520 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                     /*!< 0x00000080 */
3521 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3522 #define CAN_F6R1_FB8_Pos       (8U)
3523 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                     /*!< 0x00000100 */
3524 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3525 #define CAN_F6R1_FB9_Pos       (9U)
3526 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                     /*!< 0x00000200 */
3527 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3528 #define CAN_F6R1_FB10_Pos      (10U)
3529 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                    /*!< 0x00000400 */
3530 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3531 #define CAN_F6R1_FB11_Pos      (11U)
3532 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                    /*!< 0x00000800 */
3533 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3534 #define CAN_F6R1_FB12_Pos      (12U)
3535 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                    /*!< 0x00001000 */
3536 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3537 #define CAN_F6R1_FB13_Pos      (13U)
3538 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                    /*!< 0x00002000 */
3539 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3540 #define CAN_F6R1_FB14_Pos      (14U)
3541 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                    /*!< 0x00004000 */
3542 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3543 #define CAN_F6R1_FB15_Pos      (15U)
3544 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                    /*!< 0x00008000 */
3545 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3546 #define CAN_F6R1_FB16_Pos      (16U)
3547 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                    /*!< 0x00010000 */
3548 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3549 #define CAN_F6R1_FB17_Pos      (17U)
3550 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                    /*!< 0x00020000 */
3551 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3552 #define CAN_F6R1_FB18_Pos      (18U)
3553 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                    /*!< 0x00040000 */
3554 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3555 #define CAN_F6R1_FB19_Pos      (19U)
3556 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                    /*!< 0x00080000 */
3557 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3558 #define CAN_F6R1_FB20_Pos      (20U)
3559 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                    /*!< 0x00100000 */
3560 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3561 #define CAN_F6R1_FB21_Pos      (21U)
3562 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                    /*!< 0x00200000 */
3563 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3564 #define CAN_F6R1_FB22_Pos      (22U)
3565 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                    /*!< 0x00400000 */
3566 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3567 #define CAN_F6R1_FB23_Pos      (23U)
3568 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                    /*!< 0x00800000 */
3569 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3570 #define CAN_F6R1_FB24_Pos      (24U)
3571 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                    /*!< 0x01000000 */
3572 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3573 #define CAN_F6R1_FB25_Pos      (25U)
3574 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                    /*!< 0x02000000 */
3575 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3576 #define CAN_F6R1_FB26_Pos      (26U)
3577 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                    /*!< 0x04000000 */
3578 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3579 #define CAN_F6R1_FB27_Pos      (27U)
3580 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                    /*!< 0x08000000 */
3581 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3582 #define CAN_F6R1_FB28_Pos      (28U)
3583 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                    /*!< 0x10000000 */
3584 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3585 #define CAN_F6R1_FB29_Pos      (29U)
3586 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                    /*!< 0x20000000 */
3587 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3588 #define CAN_F6R1_FB30_Pos      (30U)
3589 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                    /*!< 0x40000000 */
3590 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3591 #define CAN_F6R1_FB31_Pos      (31U)
3592 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                    /*!< 0x80000000 */
3593 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3594 
3595 /*******************  Bit definition for CAN_F7R1 register  *******************/
3596 #define CAN_F7R1_FB0_Pos       (0U)
3597 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                     /*!< 0x00000001 */
3598 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3599 #define CAN_F7R1_FB1_Pos       (1U)
3600 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                     /*!< 0x00000002 */
3601 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3602 #define CAN_F7R1_FB2_Pos       (2U)
3603 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                     /*!< 0x00000004 */
3604 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3605 #define CAN_F7R1_FB3_Pos       (3U)
3606 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                     /*!< 0x00000008 */
3607 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3608 #define CAN_F7R1_FB4_Pos       (4U)
3609 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                     /*!< 0x00000010 */
3610 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3611 #define CAN_F7R1_FB5_Pos       (5U)
3612 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                     /*!< 0x00000020 */
3613 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3614 #define CAN_F7R1_FB6_Pos       (6U)
3615 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                     /*!< 0x00000040 */
3616 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3617 #define CAN_F7R1_FB7_Pos       (7U)
3618 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                     /*!< 0x00000080 */
3619 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3620 #define CAN_F7R1_FB8_Pos       (8U)
3621 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                     /*!< 0x00000100 */
3622 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3623 #define CAN_F7R1_FB9_Pos       (9U)
3624 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                     /*!< 0x00000200 */
3625 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3626 #define CAN_F7R1_FB10_Pos      (10U)
3627 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                    /*!< 0x00000400 */
3628 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3629 #define CAN_F7R1_FB11_Pos      (11U)
3630 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                    /*!< 0x00000800 */
3631 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3632 #define CAN_F7R1_FB12_Pos      (12U)
3633 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                    /*!< 0x00001000 */
3634 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3635 #define CAN_F7R1_FB13_Pos      (13U)
3636 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                    /*!< 0x00002000 */
3637 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3638 #define CAN_F7R1_FB14_Pos      (14U)
3639 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                    /*!< 0x00004000 */
3640 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3641 #define CAN_F7R1_FB15_Pos      (15U)
3642 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                    /*!< 0x00008000 */
3643 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3644 #define CAN_F7R1_FB16_Pos      (16U)
3645 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                    /*!< 0x00010000 */
3646 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3647 #define CAN_F7R1_FB17_Pos      (17U)
3648 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                    /*!< 0x00020000 */
3649 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3650 #define CAN_F7R1_FB18_Pos      (18U)
3651 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                    /*!< 0x00040000 */
3652 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3653 #define CAN_F7R1_FB19_Pos      (19U)
3654 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                    /*!< 0x00080000 */
3655 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3656 #define CAN_F7R1_FB20_Pos      (20U)
3657 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                    /*!< 0x00100000 */
3658 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3659 #define CAN_F7R1_FB21_Pos      (21U)
3660 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                    /*!< 0x00200000 */
3661 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3662 #define CAN_F7R1_FB22_Pos      (22U)
3663 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                    /*!< 0x00400000 */
3664 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3665 #define CAN_F7R1_FB23_Pos      (23U)
3666 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                    /*!< 0x00800000 */
3667 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3668 #define CAN_F7R1_FB24_Pos      (24U)
3669 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                    /*!< 0x01000000 */
3670 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3671 #define CAN_F7R1_FB25_Pos      (25U)
3672 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                    /*!< 0x02000000 */
3673 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3674 #define CAN_F7R1_FB26_Pos      (26U)
3675 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                    /*!< 0x04000000 */
3676 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3677 #define CAN_F7R1_FB27_Pos      (27U)
3678 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                    /*!< 0x08000000 */
3679 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3680 #define CAN_F7R1_FB28_Pos      (28U)
3681 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                    /*!< 0x10000000 */
3682 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3683 #define CAN_F7R1_FB29_Pos      (29U)
3684 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                    /*!< 0x20000000 */
3685 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3686 #define CAN_F7R1_FB30_Pos      (30U)
3687 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                    /*!< 0x40000000 */
3688 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3689 #define CAN_F7R1_FB31_Pos      (31U)
3690 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                    /*!< 0x80000000 */
3691 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3692 
3693 /*******************  Bit definition for CAN_F8R1 register  *******************/
3694 #define CAN_F8R1_FB0_Pos       (0U)
3695 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                     /*!< 0x00000001 */
3696 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3697 #define CAN_F8R1_FB1_Pos       (1U)
3698 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                     /*!< 0x00000002 */
3699 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3700 #define CAN_F8R1_FB2_Pos       (2U)
3701 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                     /*!< 0x00000004 */
3702 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3703 #define CAN_F8R1_FB3_Pos       (3U)
3704 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                     /*!< 0x00000008 */
3705 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3706 #define CAN_F8R1_FB4_Pos       (4U)
3707 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                     /*!< 0x00000010 */
3708 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3709 #define CAN_F8R1_FB5_Pos       (5U)
3710 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                     /*!< 0x00000020 */
3711 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3712 #define CAN_F8R1_FB6_Pos       (6U)
3713 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                     /*!< 0x00000040 */
3714 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3715 #define CAN_F8R1_FB7_Pos       (7U)
3716 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                     /*!< 0x00000080 */
3717 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3718 #define CAN_F8R1_FB8_Pos       (8U)
3719 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                     /*!< 0x00000100 */
3720 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3721 #define CAN_F8R1_FB9_Pos       (9U)
3722 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                     /*!< 0x00000200 */
3723 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3724 #define CAN_F8R1_FB10_Pos      (10U)
3725 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                    /*!< 0x00000400 */
3726 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3727 #define CAN_F8R1_FB11_Pos      (11U)
3728 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                    /*!< 0x00000800 */
3729 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3730 #define CAN_F8R1_FB12_Pos      (12U)
3731 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                    /*!< 0x00001000 */
3732 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3733 #define CAN_F8R1_FB13_Pos      (13U)
3734 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                    /*!< 0x00002000 */
3735 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3736 #define CAN_F8R1_FB14_Pos      (14U)
3737 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                    /*!< 0x00004000 */
3738 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3739 #define CAN_F8R1_FB15_Pos      (15U)
3740 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                    /*!< 0x00008000 */
3741 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3742 #define CAN_F8R1_FB16_Pos      (16U)
3743 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                    /*!< 0x00010000 */
3744 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3745 #define CAN_F8R1_FB17_Pos      (17U)
3746 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                    /*!< 0x00020000 */
3747 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3748 #define CAN_F8R1_FB18_Pos      (18U)
3749 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                    /*!< 0x00040000 */
3750 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3751 #define CAN_F8R1_FB19_Pos      (19U)
3752 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                    /*!< 0x00080000 */
3753 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3754 #define CAN_F8R1_FB20_Pos      (20U)
3755 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                    /*!< 0x00100000 */
3756 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3757 #define CAN_F8R1_FB21_Pos      (21U)
3758 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                    /*!< 0x00200000 */
3759 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3760 #define CAN_F8R1_FB22_Pos      (22U)
3761 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                    /*!< 0x00400000 */
3762 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3763 #define CAN_F8R1_FB23_Pos      (23U)
3764 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                    /*!< 0x00800000 */
3765 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3766 #define CAN_F8R1_FB24_Pos      (24U)
3767 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                    /*!< 0x01000000 */
3768 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3769 #define CAN_F8R1_FB25_Pos      (25U)
3770 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                    /*!< 0x02000000 */
3771 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3772 #define CAN_F8R1_FB26_Pos      (26U)
3773 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                    /*!< 0x04000000 */
3774 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3775 #define CAN_F8R1_FB27_Pos      (27U)
3776 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                    /*!< 0x08000000 */
3777 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3778 #define CAN_F8R1_FB28_Pos      (28U)
3779 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                    /*!< 0x10000000 */
3780 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3781 #define CAN_F8R1_FB29_Pos      (29U)
3782 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                    /*!< 0x20000000 */
3783 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3784 #define CAN_F8R1_FB30_Pos      (30U)
3785 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                    /*!< 0x40000000 */
3786 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3787 #define CAN_F8R1_FB31_Pos      (31U)
3788 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                    /*!< 0x80000000 */
3789 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3790 
3791 /*******************  Bit definition for CAN_F9R1 register  *******************/
3792 #define CAN_F9R1_FB0_Pos       (0U)
3793 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                     /*!< 0x00000001 */
3794 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3795 #define CAN_F9R1_FB1_Pos       (1U)
3796 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                     /*!< 0x00000002 */
3797 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3798 #define CAN_F9R1_FB2_Pos       (2U)
3799 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                     /*!< 0x00000004 */
3800 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3801 #define CAN_F9R1_FB3_Pos       (3U)
3802 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                     /*!< 0x00000008 */
3803 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3804 #define CAN_F9R1_FB4_Pos       (4U)
3805 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                     /*!< 0x00000010 */
3806 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3807 #define CAN_F9R1_FB5_Pos       (5U)
3808 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                     /*!< 0x00000020 */
3809 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3810 #define CAN_F9R1_FB6_Pos       (6U)
3811 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                     /*!< 0x00000040 */
3812 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3813 #define CAN_F9R1_FB7_Pos       (7U)
3814 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                     /*!< 0x00000080 */
3815 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3816 #define CAN_F9R1_FB8_Pos       (8U)
3817 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                     /*!< 0x00000100 */
3818 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3819 #define CAN_F9R1_FB9_Pos       (9U)
3820 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                     /*!< 0x00000200 */
3821 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3822 #define CAN_F9R1_FB10_Pos      (10U)
3823 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                    /*!< 0x00000400 */
3824 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3825 #define CAN_F9R1_FB11_Pos      (11U)
3826 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                    /*!< 0x00000800 */
3827 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3828 #define CAN_F9R1_FB12_Pos      (12U)
3829 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                    /*!< 0x00001000 */
3830 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3831 #define CAN_F9R1_FB13_Pos      (13U)
3832 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                    /*!< 0x00002000 */
3833 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3834 #define CAN_F9R1_FB14_Pos      (14U)
3835 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                    /*!< 0x00004000 */
3836 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3837 #define CAN_F9R1_FB15_Pos      (15U)
3838 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                    /*!< 0x00008000 */
3839 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3840 #define CAN_F9R1_FB16_Pos      (16U)
3841 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                    /*!< 0x00010000 */
3842 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3843 #define CAN_F9R1_FB17_Pos      (17U)
3844 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                    /*!< 0x00020000 */
3845 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3846 #define CAN_F9R1_FB18_Pos      (18U)
3847 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                    /*!< 0x00040000 */
3848 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3849 #define CAN_F9R1_FB19_Pos      (19U)
3850 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                    /*!< 0x00080000 */
3851 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3852 #define CAN_F9R1_FB20_Pos      (20U)
3853 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                    /*!< 0x00100000 */
3854 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3855 #define CAN_F9R1_FB21_Pos      (21U)
3856 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                    /*!< 0x00200000 */
3857 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3858 #define CAN_F9R1_FB22_Pos      (22U)
3859 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                    /*!< 0x00400000 */
3860 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3861 #define CAN_F9R1_FB23_Pos      (23U)
3862 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                    /*!< 0x00800000 */
3863 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3864 #define CAN_F9R1_FB24_Pos      (24U)
3865 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                    /*!< 0x01000000 */
3866 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3867 #define CAN_F9R1_FB25_Pos      (25U)
3868 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                    /*!< 0x02000000 */
3869 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3870 #define CAN_F9R1_FB26_Pos      (26U)
3871 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                    /*!< 0x04000000 */
3872 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3873 #define CAN_F9R1_FB27_Pos      (27U)
3874 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                    /*!< 0x08000000 */
3875 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3876 #define CAN_F9R1_FB28_Pos      (28U)
3877 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                    /*!< 0x10000000 */
3878 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3879 #define CAN_F9R1_FB29_Pos      (29U)
3880 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                    /*!< 0x20000000 */
3881 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3882 #define CAN_F9R1_FB30_Pos      (30U)
3883 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                    /*!< 0x40000000 */
3884 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3885 #define CAN_F9R1_FB31_Pos      (31U)
3886 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                    /*!< 0x80000000 */
3887 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3888 
3889 /*******************  Bit definition for CAN_F10R1 register  ******************/
3890 #define CAN_F10R1_FB0_Pos      (0U)
3891 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                    /*!< 0x00000001 */
3892 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3893 #define CAN_F10R1_FB1_Pos      (1U)
3894 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                    /*!< 0x00000002 */
3895 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3896 #define CAN_F10R1_FB2_Pos      (2U)
3897 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                    /*!< 0x00000004 */
3898 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3899 #define CAN_F10R1_FB3_Pos      (3U)
3900 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                    /*!< 0x00000008 */
3901 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3902 #define CAN_F10R1_FB4_Pos      (4U)
3903 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                    /*!< 0x00000010 */
3904 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3905 #define CAN_F10R1_FB5_Pos      (5U)
3906 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                    /*!< 0x00000020 */
3907 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3908 #define CAN_F10R1_FB6_Pos      (6U)
3909 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                    /*!< 0x00000040 */
3910 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3911 #define CAN_F10R1_FB7_Pos      (7U)
3912 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                    /*!< 0x00000080 */
3913 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3914 #define CAN_F10R1_FB8_Pos      (8U)
3915 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                    /*!< 0x00000100 */
3916 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3917 #define CAN_F10R1_FB9_Pos      (9U)
3918 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                    /*!< 0x00000200 */
3919 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3920 #define CAN_F10R1_FB10_Pos     (10U)
3921 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                   /*!< 0x00000400 */
3922 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3923 #define CAN_F10R1_FB11_Pos     (11U)
3924 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                   /*!< 0x00000800 */
3925 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3926 #define CAN_F10R1_FB12_Pos     (12U)
3927 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                   /*!< 0x00001000 */
3928 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3929 #define CAN_F10R1_FB13_Pos     (13U)
3930 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                   /*!< 0x00002000 */
3931 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3932 #define CAN_F10R1_FB14_Pos     (14U)
3933 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                   /*!< 0x00004000 */
3934 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3935 #define CAN_F10R1_FB15_Pos     (15U)
3936 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                   /*!< 0x00008000 */
3937 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3938 #define CAN_F10R1_FB16_Pos     (16U)
3939 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                   /*!< 0x00010000 */
3940 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3941 #define CAN_F10R1_FB17_Pos     (17U)
3942 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                   /*!< 0x00020000 */
3943 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3944 #define CAN_F10R1_FB18_Pos     (18U)
3945 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                   /*!< 0x00040000 */
3946 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3947 #define CAN_F10R1_FB19_Pos     (19U)
3948 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                   /*!< 0x00080000 */
3949 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3950 #define CAN_F10R1_FB20_Pos     (20U)
3951 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                   /*!< 0x00100000 */
3952 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3953 #define CAN_F10R1_FB21_Pos     (21U)
3954 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                   /*!< 0x00200000 */
3955 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3956 #define CAN_F10R1_FB22_Pos     (22U)
3957 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                   /*!< 0x00400000 */
3958 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3959 #define CAN_F10R1_FB23_Pos     (23U)
3960 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                   /*!< 0x00800000 */
3961 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3962 #define CAN_F10R1_FB24_Pos     (24U)
3963 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                   /*!< 0x01000000 */
3964 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3965 #define CAN_F10R1_FB25_Pos     (25U)
3966 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                   /*!< 0x02000000 */
3967 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3968 #define CAN_F10R1_FB26_Pos     (26U)
3969 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                   /*!< 0x04000000 */
3970 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3971 #define CAN_F10R1_FB27_Pos     (27U)
3972 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                   /*!< 0x08000000 */
3973 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3974 #define CAN_F10R1_FB28_Pos     (28U)
3975 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                   /*!< 0x10000000 */
3976 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3977 #define CAN_F10R1_FB29_Pos     (29U)
3978 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                   /*!< 0x20000000 */
3979 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3980 #define CAN_F10R1_FB30_Pos     (30U)
3981 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                   /*!< 0x40000000 */
3982 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3983 #define CAN_F10R1_FB31_Pos     (31U)
3984 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                   /*!< 0x80000000 */
3985 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3986 
3987 /*******************  Bit definition for CAN_F11R1 register  ******************/
3988 #define CAN_F11R1_FB0_Pos      (0U)
3989 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                    /*!< 0x00000001 */
3990 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3991 #define CAN_F11R1_FB1_Pos      (1U)
3992 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                    /*!< 0x00000002 */
3993 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3994 #define CAN_F11R1_FB2_Pos      (2U)
3995 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                    /*!< 0x00000004 */
3996 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3997 #define CAN_F11R1_FB3_Pos      (3U)
3998 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                    /*!< 0x00000008 */
3999 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
4000 #define CAN_F11R1_FB4_Pos      (4U)
4001 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                    /*!< 0x00000010 */
4002 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
4003 #define CAN_F11R1_FB5_Pos      (5U)
4004 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                    /*!< 0x00000020 */
4005 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
4006 #define CAN_F11R1_FB6_Pos      (6U)
4007 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                    /*!< 0x00000040 */
4008 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
4009 #define CAN_F11R1_FB7_Pos      (7U)
4010 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                    /*!< 0x00000080 */
4011 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
4012 #define CAN_F11R1_FB8_Pos      (8U)
4013 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                    /*!< 0x00000100 */
4014 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4015 #define CAN_F11R1_FB9_Pos      (9U)
4016 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                    /*!< 0x00000200 */
4017 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4018 #define CAN_F11R1_FB10_Pos     (10U)
4019 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                   /*!< 0x00000400 */
4020 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4021 #define CAN_F11R1_FB11_Pos     (11U)
4022 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                   /*!< 0x00000800 */
4023 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4024 #define CAN_F11R1_FB12_Pos     (12U)
4025 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                   /*!< 0x00001000 */
4026 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4027 #define CAN_F11R1_FB13_Pos     (13U)
4028 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                   /*!< 0x00002000 */
4029 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4030 #define CAN_F11R1_FB14_Pos     (14U)
4031 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                   /*!< 0x00004000 */
4032 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4033 #define CAN_F11R1_FB15_Pos     (15U)
4034 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                   /*!< 0x00008000 */
4035 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4036 #define CAN_F11R1_FB16_Pos     (16U)
4037 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                   /*!< 0x00010000 */
4038 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4039 #define CAN_F11R1_FB17_Pos     (17U)
4040 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                   /*!< 0x00020000 */
4041 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4042 #define CAN_F11R1_FB18_Pos     (18U)
4043 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                   /*!< 0x00040000 */
4044 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4045 #define CAN_F11R1_FB19_Pos     (19U)
4046 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                   /*!< 0x00080000 */
4047 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4048 #define CAN_F11R1_FB20_Pos     (20U)
4049 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                   /*!< 0x00100000 */
4050 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4051 #define CAN_F11R1_FB21_Pos     (21U)
4052 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                   /*!< 0x00200000 */
4053 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4054 #define CAN_F11R1_FB22_Pos     (22U)
4055 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                   /*!< 0x00400000 */
4056 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4057 #define CAN_F11R1_FB23_Pos     (23U)
4058 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                   /*!< 0x00800000 */
4059 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4060 #define CAN_F11R1_FB24_Pos     (24U)
4061 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                   /*!< 0x01000000 */
4062 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4063 #define CAN_F11R1_FB25_Pos     (25U)
4064 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                   /*!< 0x02000000 */
4065 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4066 #define CAN_F11R1_FB26_Pos     (26U)
4067 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                   /*!< 0x04000000 */
4068 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4069 #define CAN_F11R1_FB27_Pos     (27U)
4070 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                   /*!< 0x08000000 */
4071 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4072 #define CAN_F11R1_FB28_Pos     (28U)
4073 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                   /*!< 0x10000000 */
4074 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4075 #define CAN_F11R1_FB29_Pos     (29U)
4076 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                   /*!< 0x20000000 */
4077 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4078 #define CAN_F11R1_FB30_Pos     (30U)
4079 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                   /*!< 0x40000000 */
4080 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4081 #define CAN_F11R1_FB31_Pos     (31U)
4082 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                   /*!< 0x80000000 */
4083 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4084 
4085 /*******************  Bit definition for CAN_F12R1 register  ******************/
4086 #define CAN_F12R1_FB0_Pos      (0U)
4087 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                    /*!< 0x00000001 */
4088 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4089 #define CAN_F12R1_FB1_Pos      (1U)
4090 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                    /*!< 0x00000002 */
4091 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4092 #define CAN_F12R1_FB2_Pos      (2U)
4093 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                    /*!< 0x00000004 */
4094 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4095 #define CAN_F12R1_FB3_Pos      (3U)
4096 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                    /*!< 0x00000008 */
4097 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4098 #define CAN_F12R1_FB4_Pos      (4U)
4099 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                    /*!< 0x00000010 */
4100 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4101 #define CAN_F12R1_FB5_Pos      (5U)
4102 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                    /*!< 0x00000020 */
4103 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4104 #define CAN_F12R1_FB6_Pos      (6U)
4105 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                    /*!< 0x00000040 */
4106 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4107 #define CAN_F12R1_FB7_Pos      (7U)
4108 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                    /*!< 0x00000080 */
4109 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4110 #define CAN_F12R1_FB8_Pos      (8U)
4111 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                    /*!< 0x00000100 */
4112 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4113 #define CAN_F12R1_FB9_Pos      (9U)
4114 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                    /*!< 0x00000200 */
4115 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4116 #define CAN_F12R1_FB10_Pos     (10U)
4117 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                   /*!< 0x00000400 */
4118 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4119 #define CAN_F12R1_FB11_Pos     (11U)
4120 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                   /*!< 0x00000800 */
4121 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4122 #define CAN_F12R1_FB12_Pos     (12U)
4123 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                   /*!< 0x00001000 */
4124 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4125 #define CAN_F12R1_FB13_Pos     (13U)
4126 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                   /*!< 0x00002000 */
4127 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4128 #define CAN_F12R1_FB14_Pos     (14U)
4129 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                   /*!< 0x00004000 */
4130 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4131 #define CAN_F12R1_FB15_Pos     (15U)
4132 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                   /*!< 0x00008000 */
4133 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4134 #define CAN_F12R1_FB16_Pos     (16U)
4135 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                   /*!< 0x00010000 */
4136 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4137 #define CAN_F12R1_FB17_Pos     (17U)
4138 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                   /*!< 0x00020000 */
4139 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4140 #define CAN_F12R1_FB18_Pos     (18U)
4141 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                   /*!< 0x00040000 */
4142 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4143 #define CAN_F12R1_FB19_Pos     (19U)
4144 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                   /*!< 0x00080000 */
4145 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4146 #define CAN_F12R1_FB20_Pos     (20U)
4147 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                   /*!< 0x00100000 */
4148 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4149 #define CAN_F12R1_FB21_Pos     (21U)
4150 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                   /*!< 0x00200000 */
4151 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4152 #define CAN_F12R1_FB22_Pos     (22U)
4153 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                   /*!< 0x00400000 */
4154 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4155 #define CAN_F12R1_FB23_Pos     (23U)
4156 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                   /*!< 0x00800000 */
4157 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4158 #define CAN_F12R1_FB24_Pos     (24U)
4159 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                   /*!< 0x01000000 */
4160 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4161 #define CAN_F12R1_FB25_Pos     (25U)
4162 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                   /*!< 0x02000000 */
4163 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4164 #define CAN_F12R1_FB26_Pos     (26U)
4165 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                   /*!< 0x04000000 */
4166 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4167 #define CAN_F12R1_FB27_Pos     (27U)
4168 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                   /*!< 0x08000000 */
4169 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4170 #define CAN_F12R1_FB28_Pos     (28U)
4171 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                   /*!< 0x10000000 */
4172 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4173 #define CAN_F12R1_FB29_Pos     (29U)
4174 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                   /*!< 0x20000000 */
4175 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4176 #define CAN_F12R1_FB30_Pos     (30U)
4177 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                   /*!< 0x40000000 */
4178 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4179 #define CAN_F12R1_FB31_Pos     (31U)
4180 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                   /*!< 0x80000000 */
4181 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4182 
4183 /*******************  Bit definition for CAN_F13R1 register  ******************/
4184 #define CAN_F13R1_FB0_Pos      (0U)
4185 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                    /*!< 0x00000001 */
4186 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4187 #define CAN_F13R1_FB1_Pos      (1U)
4188 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                    /*!< 0x00000002 */
4189 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4190 #define CAN_F13R1_FB2_Pos      (2U)
4191 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                    /*!< 0x00000004 */
4192 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4193 #define CAN_F13R1_FB3_Pos      (3U)
4194 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                    /*!< 0x00000008 */
4195 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4196 #define CAN_F13R1_FB4_Pos      (4U)
4197 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                    /*!< 0x00000010 */
4198 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4199 #define CAN_F13R1_FB5_Pos      (5U)
4200 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                    /*!< 0x00000020 */
4201 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4202 #define CAN_F13R1_FB6_Pos      (6U)
4203 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                    /*!< 0x00000040 */
4204 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4205 #define CAN_F13R1_FB7_Pos      (7U)
4206 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                    /*!< 0x00000080 */
4207 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4208 #define CAN_F13R1_FB8_Pos      (8U)
4209 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                    /*!< 0x00000100 */
4210 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4211 #define CAN_F13R1_FB9_Pos      (9U)
4212 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                    /*!< 0x00000200 */
4213 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4214 #define CAN_F13R1_FB10_Pos     (10U)
4215 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                   /*!< 0x00000400 */
4216 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4217 #define CAN_F13R1_FB11_Pos     (11U)
4218 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                   /*!< 0x00000800 */
4219 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4220 #define CAN_F13R1_FB12_Pos     (12U)
4221 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                   /*!< 0x00001000 */
4222 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4223 #define CAN_F13R1_FB13_Pos     (13U)
4224 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                   /*!< 0x00002000 */
4225 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4226 #define CAN_F13R1_FB14_Pos     (14U)
4227 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                   /*!< 0x00004000 */
4228 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4229 #define CAN_F13R1_FB15_Pos     (15U)
4230 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                   /*!< 0x00008000 */
4231 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4232 #define CAN_F13R1_FB16_Pos     (16U)
4233 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                   /*!< 0x00010000 */
4234 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4235 #define CAN_F13R1_FB17_Pos     (17U)
4236 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                   /*!< 0x00020000 */
4237 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4238 #define CAN_F13R1_FB18_Pos     (18U)
4239 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                   /*!< 0x00040000 */
4240 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4241 #define CAN_F13R1_FB19_Pos     (19U)
4242 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                   /*!< 0x00080000 */
4243 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4244 #define CAN_F13R1_FB20_Pos     (20U)
4245 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                   /*!< 0x00100000 */
4246 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4247 #define CAN_F13R1_FB21_Pos     (21U)
4248 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                   /*!< 0x00200000 */
4249 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4250 #define CAN_F13R1_FB22_Pos     (22U)
4251 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                   /*!< 0x00400000 */
4252 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4253 #define CAN_F13R1_FB23_Pos     (23U)
4254 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                   /*!< 0x00800000 */
4255 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4256 #define CAN_F13R1_FB24_Pos     (24U)
4257 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                   /*!< 0x01000000 */
4258 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4259 #define CAN_F13R1_FB25_Pos     (25U)
4260 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                   /*!< 0x02000000 */
4261 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4262 #define CAN_F13R1_FB26_Pos     (26U)
4263 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                   /*!< 0x04000000 */
4264 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4265 #define CAN_F13R1_FB27_Pos     (27U)
4266 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                   /*!< 0x08000000 */
4267 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4268 #define CAN_F13R1_FB28_Pos     (28U)
4269 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                   /*!< 0x10000000 */
4270 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4271 #define CAN_F13R1_FB29_Pos     (29U)
4272 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                   /*!< 0x20000000 */
4273 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4274 #define CAN_F13R1_FB30_Pos     (30U)
4275 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                   /*!< 0x40000000 */
4276 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4277 #define CAN_F13R1_FB31_Pos     (31U)
4278 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                   /*!< 0x80000000 */
4279 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4280 
4281 /*******************  Bit definition for CAN_F0R2 register  *******************/
4282 #define CAN_F0R2_FB0_Pos       (0U)
4283 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                     /*!< 0x00000001 */
4284 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4285 #define CAN_F0R2_FB1_Pos       (1U)
4286 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                     /*!< 0x00000002 */
4287 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4288 #define CAN_F0R2_FB2_Pos       (2U)
4289 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                     /*!< 0x00000004 */
4290 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4291 #define CAN_F0R2_FB3_Pos       (3U)
4292 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                     /*!< 0x00000008 */
4293 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4294 #define CAN_F0R2_FB4_Pos       (4U)
4295 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                     /*!< 0x00000010 */
4296 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4297 #define CAN_F0R2_FB5_Pos       (5U)
4298 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                     /*!< 0x00000020 */
4299 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4300 #define CAN_F0R2_FB6_Pos       (6U)
4301 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                     /*!< 0x00000040 */
4302 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4303 #define CAN_F0R2_FB7_Pos       (7U)
4304 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                     /*!< 0x00000080 */
4305 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4306 #define CAN_F0R2_FB8_Pos       (8U)
4307 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                     /*!< 0x00000100 */
4308 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4309 #define CAN_F0R2_FB9_Pos       (9U)
4310 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                     /*!< 0x00000200 */
4311 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4312 #define CAN_F0R2_FB10_Pos      (10U)
4313 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                    /*!< 0x00000400 */
4314 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4315 #define CAN_F0R2_FB11_Pos      (11U)
4316 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                    /*!< 0x00000800 */
4317 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4318 #define CAN_F0R2_FB12_Pos      (12U)
4319 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                    /*!< 0x00001000 */
4320 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4321 #define CAN_F0R2_FB13_Pos      (13U)
4322 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                    /*!< 0x00002000 */
4323 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4324 #define CAN_F0R2_FB14_Pos      (14U)
4325 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                    /*!< 0x00004000 */
4326 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4327 #define CAN_F0R2_FB15_Pos      (15U)
4328 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                    /*!< 0x00008000 */
4329 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4330 #define CAN_F0R2_FB16_Pos      (16U)
4331 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                    /*!< 0x00010000 */
4332 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4333 #define CAN_F0R2_FB17_Pos      (17U)
4334 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                    /*!< 0x00020000 */
4335 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4336 #define CAN_F0R2_FB18_Pos      (18U)
4337 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                    /*!< 0x00040000 */
4338 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4339 #define CAN_F0R2_FB19_Pos      (19U)
4340 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                    /*!< 0x00080000 */
4341 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4342 #define CAN_F0R2_FB20_Pos      (20U)
4343 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                    /*!< 0x00100000 */
4344 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4345 #define CAN_F0R2_FB21_Pos      (21U)
4346 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                    /*!< 0x00200000 */
4347 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4348 #define CAN_F0R2_FB22_Pos      (22U)
4349 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                    /*!< 0x00400000 */
4350 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4351 #define CAN_F0R2_FB23_Pos      (23U)
4352 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                    /*!< 0x00800000 */
4353 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4354 #define CAN_F0R2_FB24_Pos      (24U)
4355 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                    /*!< 0x01000000 */
4356 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4357 #define CAN_F0R2_FB25_Pos      (25U)
4358 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                    /*!< 0x02000000 */
4359 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4360 #define CAN_F0R2_FB26_Pos      (26U)
4361 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                    /*!< 0x04000000 */
4362 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4363 #define CAN_F0R2_FB27_Pos      (27U)
4364 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                    /*!< 0x08000000 */
4365 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4366 #define CAN_F0R2_FB28_Pos      (28U)
4367 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                    /*!< 0x10000000 */
4368 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4369 #define CAN_F0R2_FB29_Pos      (29U)
4370 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                    /*!< 0x20000000 */
4371 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4372 #define CAN_F0R2_FB30_Pos      (30U)
4373 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                    /*!< 0x40000000 */
4374 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4375 #define CAN_F0R2_FB31_Pos      (31U)
4376 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                    /*!< 0x80000000 */
4377 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4378 
4379 /*******************  Bit definition for CAN_F1R2 register  *******************/
4380 #define CAN_F1R2_FB0_Pos       (0U)
4381 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                     /*!< 0x00000001 */
4382 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4383 #define CAN_F1R2_FB1_Pos       (1U)
4384 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                     /*!< 0x00000002 */
4385 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4386 #define CAN_F1R2_FB2_Pos       (2U)
4387 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                     /*!< 0x00000004 */
4388 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4389 #define CAN_F1R2_FB3_Pos       (3U)
4390 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                     /*!< 0x00000008 */
4391 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4392 #define CAN_F1R2_FB4_Pos       (4U)
4393 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                     /*!< 0x00000010 */
4394 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4395 #define CAN_F1R2_FB5_Pos       (5U)
4396 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                     /*!< 0x00000020 */
4397 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4398 #define CAN_F1R2_FB6_Pos       (6U)
4399 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                     /*!< 0x00000040 */
4400 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4401 #define CAN_F1R2_FB7_Pos       (7U)
4402 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                     /*!< 0x00000080 */
4403 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4404 #define CAN_F1R2_FB8_Pos       (8U)
4405 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                     /*!< 0x00000100 */
4406 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4407 #define CAN_F1R2_FB9_Pos       (9U)
4408 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                     /*!< 0x00000200 */
4409 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4410 #define CAN_F1R2_FB10_Pos      (10U)
4411 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                    /*!< 0x00000400 */
4412 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4413 #define CAN_F1R2_FB11_Pos      (11U)
4414 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                    /*!< 0x00000800 */
4415 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4416 #define CAN_F1R2_FB12_Pos      (12U)
4417 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                    /*!< 0x00001000 */
4418 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4419 #define CAN_F1R2_FB13_Pos      (13U)
4420 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                    /*!< 0x00002000 */
4421 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4422 #define CAN_F1R2_FB14_Pos      (14U)
4423 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                    /*!< 0x00004000 */
4424 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4425 #define CAN_F1R2_FB15_Pos      (15U)
4426 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                    /*!< 0x00008000 */
4427 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4428 #define CAN_F1R2_FB16_Pos      (16U)
4429 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                    /*!< 0x00010000 */
4430 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4431 #define CAN_F1R2_FB17_Pos      (17U)
4432 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                    /*!< 0x00020000 */
4433 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4434 #define CAN_F1R2_FB18_Pos      (18U)
4435 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                    /*!< 0x00040000 */
4436 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4437 #define CAN_F1R2_FB19_Pos      (19U)
4438 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                    /*!< 0x00080000 */
4439 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4440 #define CAN_F1R2_FB20_Pos      (20U)
4441 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                    /*!< 0x00100000 */
4442 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4443 #define CAN_F1R2_FB21_Pos      (21U)
4444 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                    /*!< 0x00200000 */
4445 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4446 #define CAN_F1R2_FB22_Pos      (22U)
4447 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                    /*!< 0x00400000 */
4448 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4449 #define CAN_F1R2_FB23_Pos      (23U)
4450 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                    /*!< 0x00800000 */
4451 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4452 #define CAN_F1R2_FB24_Pos      (24U)
4453 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                    /*!< 0x01000000 */
4454 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4455 #define CAN_F1R2_FB25_Pos      (25U)
4456 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                    /*!< 0x02000000 */
4457 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4458 #define CAN_F1R2_FB26_Pos      (26U)
4459 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                    /*!< 0x04000000 */
4460 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4461 #define CAN_F1R2_FB27_Pos      (27U)
4462 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                    /*!< 0x08000000 */
4463 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4464 #define CAN_F1R2_FB28_Pos      (28U)
4465 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                    /*!< 0x10000000 */
4466 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4467 #define CAN_F1R2_FB29_Pos      (29U)
4468 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                    /*!< 0x20000000 */
4469 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4470 #define CAN_F1R2_FB30_Pos      (30U)
4471 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                    /*!< 0x40000000 */
4472 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4473 #define CAN_F1R2_FB31_Pos      (31U)
4474 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                    /*!< 0x80000000 */
4475 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4476 
4477 /*******************  Bit definition for CAN_F2R2 register  *******************/
4478 #define CAN_F2R2_FB0_Pos       (0U)
4479 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                     /*!< 0x00000001 */
4480 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4481 #define CAN_F2R2_FB1_Pos       (1U)
4482 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                     /*!< 0x00000002 */
4483 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4484 #define CAN_F2R2_FB2_Pos       (2U)
4485 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                     /*!< 0x00000004 */
4486 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4487 #define CAN_F2R2_FB3_Pos       (3U)
4488 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                     /*!< 0x00000008 */
4489 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4490 #define CAN_F2R2_FB4_Pos       (4U)
4491 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                     /*!< 0x00000010 */
4492 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4493 #define CAN_F2R2_FB5_Pos       (5U)
4494 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                     /*!< 0x00000020 */
4495 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4496 #define CAN_F2R2_FB6_Pos       (6U)
4497 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                     /*!< 0x00000040 */
4498 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4499 #define CAN_F2R2_FB7_Pos       (7U)
4500 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                     /*!< 0x00000080 */
4501 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4502 #define CAN_F2R2_FB8_Pos       (8U)
4503 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                     /*!< 0x00000100 */
4504 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4505 #define CAN_F2R2_FB9_Pos       (9U)
4506 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                     /*!< 0x00000200 */
4507 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4508 #define CAN_F2R2_FB10_Pos      (10U)
4509 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                    /*!< 0x00000400 */
4510 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4511 #define CAN_F2R2_FB11_Pos      (11U)
4512 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                    /*!< 0x00000800 */
4513 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4514 #define CAN_F2R2_FB12_Pos      (12U)
4515 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                    /*!< 0x00001000 */
4516 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4517 #define CAN_F2R2_FB13_Pos      (13U)
4518 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                    /*!< 0x00002000 */
4519 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4520 #define CAN_F2R2_FB14_Pos      (14U)
4521 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                    /*!< 0x00004000 */
4522 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4523 #define CAN_F2R2_FB15_Pos      (15U)
4524 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                    /*!< 0x00008000 */
4525 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4526 #define CAN_F2R2_FB16_Pos      (16U)
4527 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                    /*!< 0x00010000 */
4528 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4529 #define CAN_F2R2_FB17_Pos      (17U)
4530 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                    /*!< 0x00020000 */
4531 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4532 #define CAN_F2R2_FB18_Pos      (18U)
4533 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                    /*!< 0x00040000 */
4534 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4535 #define CAN_F2R2_FB19_Pos      (19U)
4536 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                    /*!< 0x00080000 */
4537 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4538 #define CAN_F2R2_FB20_Pos      (20U)
4539 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                    /*!< 0x00100000 */
4540 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4541 #define CAN_F2R2_FB21_Pos      (21U)
4542 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                    /*!< 0x00200000 */
4543 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4544 #define CAN_F2R2_FB22_Pos      (22U)
4545 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                    /*!< 0x00400000 */
4546 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4547 #define CAN_F2R2_FB23_Pos      (23U)
4548 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                    /*!< 0x00800000 */
4549 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4550 #define CAN_F2R2_FB24_Pos      (24U)
4551 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                    /*!< 0x01000000 */
4552 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4553 #define CAN_F2R2_FB25_Pos      (25U)
4554 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                    /*!< 0x02000000 */
4555 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4556 #define CAN_F2R2_FB26_Pos      (26U)
4557 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                    /*!< 0x04000000 */
4558 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4559 #define CAN_F2R2_FB27_Pos      (27U)
4560 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                    /*!< 0x08000000 */
4561 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4562 #define CAN_F2R2_FB28_Pos      (28U)
4563 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                    /*!< 0x10000000 */
4564 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4565 #define CAN_F2R2_FB29_Pos      (29U)
4566 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                    /*!< 0x20000000 */
4567 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4568 #define CAN_F2R2_FB30_Pos      (30U)
4569 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                    /*!< 0x40000000 */
4570 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4571 #define CAN_F2R2_FB31_Pos      (31U)
4572 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                    /*!< 0x80000000 */
4573 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4574 
4575 /*******************  Bit definition for CAN_F3R2 register  *******************/
4576 #define CAN_F3R2_FB0_Pos       (0U)
4577 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                     /*!< 0x00000001 */
4578 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4579 #define CAN_F3R2_FB1_Pos       (1U)
4580 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                     /*!< 0x00000002 */
4581 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4582 #define CAN_F3R2_FB2_Pos       (2U)
4583 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                     /*!< 0x00000004 */
4584 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4585 #define CAN_F3R2_FB3_Pos       (3U)
4586 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                     /*!< 0x00000008 */
4587 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4588 #define CAN_F3R2_FB4_Pos       (4U)
4589 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                     /*!< 0x00000010 */
4590 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4591 #define CAN_F3R2_FB5_Pos       (5U)
4592 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                     /*!< 0x00000020 */
4593 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4594 #define CAN_F3R2_FB6_Pos       (6U)
4595 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                     /*!< 0x00000040 */
4596 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4597 #define CAN_F3R2_FB7_Pos       (7U)
4598 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                     /*!< 0x00000080 */
4599 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4600 #define CAN_F3R2_FB8_Pos       (8U)
4601 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                     /*!< 0x00000100 */
4602 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4603 #define CAN_F3R2_FB9_Pos       (9U)
4604 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                     /*!< 0x00000200 */
4605 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4606 #define CAN_F3R2_FB10_Pos      (10U)
4607 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                    /*!< 0x00000400 */
4608 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4609 #define CAN_F3R2_FB11_Pos      (11U)
4610 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                    /*!< 0x00000800 */
4611 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4612 #define CAN_F3R2_FB12_Pos      (12U)
4613 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                    /*!< 0x00001000 */
4614 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4615 #define CAN_F3R2_FB13_Pos      (13U)
4616 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                    /*!< 0x00002000 */
4617 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4618 #define CAN_F3R2_FB14_Pos      (14U)
4619 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                    /*!< 0x00004000 */
4620 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4621 #define CAN_F3R2_FB15_Pos      (15U)
4622 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                    /*!< 0x00008000 */
4623 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4624 #define CAN_F3R2_FB16_Pos      (16U)
4625 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                    /*!< 0x00010000 */
4626 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4627 #define CAN_F3R2_FB17_Pos      (17U)
4628 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                    /*!< 0x00020000 */
4629 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4630 #define CAN_F3R2_FB18_Pos      (18U)
4631 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                    /*!< 0x00040000 */
4632 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4633 #define CAN_F3R2_FB19_Pos      (19U)
4634 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                    /*!< 0x00080000 */
4635 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4636 #define CAN_F3R2_FB20_Pos      (20U)
4637 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                    /*!< 0x00100000 */
4638 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4639 #define CAN_F3R2_FB21_Pos      (21U)
4640 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                    /*!< 0x00200000 */
4641 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4642 #define CAN_F3R2_FB22_Pos      (22U)
4643 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                    /*!< 0x00400000 */
4644 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4645 #define CAN_F3R2_FB23_Pos      (23U)
4646 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                    /*!< 0x00800000 */
4647 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4648 #define CAN_F3R2_FB24_Pos      (24U)
4649 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                    /*!< 0x01000000 */
4650 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4651 #define CAN_F3R2_FB25_Pos      (25U)
4652 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                    /*!< 0x02000000 */
4653 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4654 #define CAN_F3R2_FB26_Pos      (26U)
4655 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                    /*!< 0x04000000 */
4656 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4657 #define CAN_F3R2_FB27_Pos      (27U)
4658 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                    /*!< 0x08000000 */
4659 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4660 #define CAN_F3R2_FB28_Pos      (28U)
4661 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                    /*!< 0x10000000 */
4662 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4663 #define CAN_F3R2_FB29_Pos      (29U)
4664 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                    /*!< 0x20000000 */
4665 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4666 #define CAN_F3R2_FB30_Pos      (30U)
4667 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                    /*!< 0x40000000 */
4668 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4669 #define CAN_F3R2_FB31_Pos      (31U)
4670 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                    /*!< 0x80000000 */
4671 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4672 
4673 /*******************  Bit definition for CAN_F4R2 register  *******************/
4674 #define CAN_F4R2_FB0_Pos       (0U)
4675 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                     /*!< 0x00000001 */
4676 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4677 #define CAN_F4R2_FB1_Pos       (1U)
4678 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                     /*!< 0x00000002 */
4679 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4680 #define CAN_F4R2_FB2_Pos       (2U)
4681 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                     /*!< 0x00000004 */
4682 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4683 #define CAN_F4R2_FB3_Pos       (3U)
4684 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                     /*!< 0x00000008 */
4685 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4686 #define CAN_F4R2_FB4_Pos       (4U)
4687 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                     /*!< 0x00000010 */
4688 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4689 #define CAN_F4R2_FB5_Pos       (5U)
4690 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                     /*!< 0x00000020 */
4691 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4692 #define CAN_F4R2_FB6_Pos       (6U)
4693 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                     /*!< 0x00000040 */
4694 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4695 #define CAN_F4R2_FB7_Pos       (7U)
4696 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                     /*!< 0x00000080 */
4697 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4698 #define CAN_F4R2_FB8_Pos       (8U)
4699 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                     /*!< 0x00000100 */
4700 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4701 #define CAN_F4R2_FB9_Pos       (9U)
4702 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                     /*!< 0x00000200 */
4703 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4704 #define CAN_F4R2_FB10_Pos      (10U)
4705 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                    /*!< 0x00000400 */
4706 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4707 #define CAN_F4R2_FB11_Pos      (11U)
4708 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                    /*!< 0x00000800 */
4709 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4710 #define CAN_F4R2_FB12_Pos      (12U)
4711 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                    /*!< 0x00001000 */
4712 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4713 #define CAN_F4R2_FB13_Pos      (13U)
4714 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                    /*!< 0x00002000 */
4715 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4716 #define CAN_F4R2_FB14_Pos      (14U)
4717 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                    /*!< 0x00004000 */
4718 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4719 #define CAN_F4R2_FB15_Pos      (15U)
4720 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                    /*!< 0x00008000 */
4721 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4722 #define CAN_F4R2_FB16_Pos      (16U)
4723 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                    /*!< 0x00010000 */
4724 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4725 #define CAN_F4R2_FB17_Pos      (17U)
4726 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                    /*!< 0x00020000 */
4727 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4728 #define CAN_F4R2_FB18_Pos      (18U)
4729 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                    /*!< 0x00040000 */
4730 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4731 #define CAN_F4R2_FB19_Pos      (19U)
4732 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                    /*!< 0x00080000 */
4733 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4734 #define CAN_F4R2_FB20_Pos      (20U)
4735 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                    /*!< 0x00100000 */
4736 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4737 #define CAN_F4R2_FB21_Pos      (21U)
4738 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                    /*!< 0x00200000 */
4739 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4740 #define CAN_F4R2_FB22_Pos      (22U)
4741 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                    /*!< 0x00400000 */
4742 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4743 #define CAN_F4R2_FB23_Pos      (23U)
4744 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                    /*!< 0x00800000 */
4745 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4746 #define CAN_F4R2_FB24_Pos      (24U)
4747 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                    /*!< 0x01000000 */
4748 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4749 #define CAN_F4R2_FB25_Pos      (25U)
4750 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                    /*!< 0x02000000 */
4751 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4752 #define CAN_F4R2_FB26_Pos      (26U)
4753 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                    /*!< 0x04000000 */
4754 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4755 #define CAN_F4R2_FB27_Pos      (27U)
4756 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                    /*!< 0x08000000 */
4757 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4758 #define CAN_F4R2_FB28_Pos      (28U)
4759 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                    /*!< 0x10000000 */
4760 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4761 #define CAN_F4R2_FB29_Pos      (29U)
4762 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                    /*!< 0x20000000 */
4763 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4764 #define CAN_F4R2_FB30_Pos      (30U)
4765 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                    /*!< 0x40000000 */
4766 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4767 #define CAN_F4R2_FB31_Pos      (31U)
4768 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                    /*!< 0x80000000 */
4769 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4770 
4771 /*******************  Bit definition for CAN_F5R2 register  *******************/
4772 #define CAN_F5R2_FB0_Pos       (0U)
4773 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                     /*!< 0x00000001 */
4774 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4775 #define CAN_F5R2_FB1_Pos       (1U)
4776 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                     /*!< 0x00000002 */
4777 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4778 #define CAN_F5R2_FB2_Pos       (2U)
4779 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                     /*!< 0x00000004 */
4780 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4781 #define CAN_F5R2_FB3_Pos       (3U)
4782 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                     /*!< 0x00000008 */
4783 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4784 #define CAN_F5R2_FB4_Pos       (4U)
4785 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                     /*!< 0x00000010 */
4786 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4787 #define CAN_F5R2_FB5_Pos       (5U)
4788 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                     /*!< 0x00000020 */
4789 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4790 #define CAN_F5R2_FB6_Pos       (6U)
4791 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                     /*!< 0x00000040 */
4792 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4793 #define CAN_F5R2_FB7_Pos       (7U)
4794 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                     /*!< 0x00000080 */
4795 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4796 #define CAN_F5R2_FB8_Pos       (8U)
4797 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                     /*!< 0x00000100 */
4798 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4799 #define CAN_F5R2_FB9_Pos       (9U)
4800 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                     /*!< 0x00000200 */
4801 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4802 #define CAN_F5R2_FB10_Pos      (10U)
4803 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                    /*!< 0x00000400 */
4804 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4805 #define CAN_F5R2_FB11_Pos      (11U)
4806 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                    /*!< 0x00000800 */
4807 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4808 #define CAN_F5R2_FB12_Pos      (12U)
4809 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                    /*!< 0x00001000 */
4810 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4811 #define CAN_F5R2_FB13_Pos      (13U)
4812 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                    /*!< 0x00002000 */
4813 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4814 #define CAN_F5R2_FB14_Pos      (14U)
4815 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                    /*!< 0x00004000 */
4816 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4817 #define CAN_F5R2_FB15_Pos      (15U)
4818 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                    /*!< 0x00008000 */
4819 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4820 #define CAN_F5R2_FB16_Pos      (16U)
4821 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                    /*!< 0x00010000 */
4822 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4823 #define CAN_F5R2_FB17_Pos      (17U)
4824 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                    /*!< 0x00020000 */
4825 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4826 #define CAN_F5R2_FB18_Pos      (18U)
4827 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                    /*!< 0x00040000 */
4828 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4829 #define CAN_F5R2_FB19_Pos      (19U)
4830 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                    /*!< 0x00080000 */
4831 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4832 #define CAN_F5R2_FB20_Pos      (20U)
4833 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                    /*!< 0x00100000 */
4834 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4835 #define CAN_F5R2_FB21_Pos      (21U)
4836 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                    /*!< 0x00200000 */
4837 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4838 #define CAN_F5R2_FB22_Pos      (22U)
4839 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                    /*!< 0x00400000 */
4840 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4841 #define CAN_F5R2_FB23_Pos      (23U)
4842 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                    /*!< 0x00800000 */
4843 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4844 #define CAN_F5R2_FB24_Pos      (24U)
4845 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                    /*!< 0x01000000 */
4846 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4847 #define CAN_F5R2_FB25_Pos      (25U)
4848 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                    /*!< 0x02000000 */
4849 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4850 #define CAN_F5R2_FB26_Pos      (26U)
4851 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                    /*!< 0x04000000 */
4852 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4853 #define CAN_F5R2_FB27_Pos      (27U)
4854 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                    /*!< 0x08000000 */
4855 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4856 #define CAN_F5R2_FB28_Pos      (28U)
4857 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                    /*!< 0x10000000 */
4858 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4859 #define CAN_F5R2_FB29_Pos      (29U)
4860 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                    /*!< 0x20000000 */
4861 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4862 #define CAN_F5R2_FB30_Pos      (30U)
4863 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                    /*!< 0x40000000 */
4864 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4865 #define CAN_F5R2_FB31_Pos      (31U)
4866 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                    /*!< 0x80000000 */
4867 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4868 
4869 /*******************  Bit definition for CAN_F6R2 register  *******************/
4870 #define CAN_F6R2_FB0_Pos       (0U)
4871 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                     /*!< 0x00000001 */
4872 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4873 #define CAN_F6R2_FB1_Pos       (1U)
4874 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                     /*!< 0x00000002 */
4875 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4876 #define CAN_F6R2_FB2_Pos       (2U)
4877 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                     /*!< 0x00000004 */
4878 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4879 #define CAN_F6R2_FB3_Pos       (3U)
4880 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                     /*!< 0x00000008 */
4881 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4882 #define CAN_F6R2_FB4_Pos       (4U)
4883 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                     /*!< 0x00000010 */
4884 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4885 #define CAN_F6R2_FB5_Pos       (5U)
4886 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                     /*!< 0x00000020 */
4887 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4888 #define CAN_F6R2_FB6_Pos       (6U)
4889 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                     /*!< 0x00000040 */
4890 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4891 #define CAN_F6R2_FB7_Pos       (7U)
4892 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                     /*!< 0x00000080 */
4893 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4894 #define CAN_F6R2_FB8_Pos       (8U)
4895 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                     /*!< 0x00000100 */
4896 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4897 #define CAN_F6R2_FB9_Pos       (9U)
4898 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                     /*!< 0x00000200 */
4899 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4900 #define CAN_F6R2_FB10_Pos      (10U)
4901 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                    /*!< 0x00000400 */
4902 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4903 #define CAN_F6R2_FB11_Pos      (11U)
4904 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                    /*!< 0x00000800 */
4905 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4906 #define CAN_F6R2_FB12_Pos      (12U)
4907 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                    /*!< 0x00001000 */
4908 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4909 #define CAN_F6R2_FB13_Pos      (13U)
4910 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                    /*!< 0x00002000 */
4911 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4912 #define CAN_F6R2_FB14_Pos      (14U)
4913 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                    /*!< 0x00004000 */
4914 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4915 #define CAN_F6R2_FB15_Pos      (15U)
4916 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                    /*!< 0x00008000 */
4917 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4918 #define CAN_F6R2_FB16_Pos      (16U)
4919 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                    /*!< 0x00010000 */
4920 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4921 #define CAN_F6R2_FB17_Pos      (17U)
4922 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                    /*!< 0x00020000 */
4923 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4924 #define CAN_F6R2_FB18_Pos      (18U)
4925 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                    /*!< 0x00040000 */
4926 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4927 #define CAN_F6R2_FB19_Pos      (19U)
4928 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                    /*!< 0x00080000 */
4929 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4930 #define CAN_F6R2_FB20_Pos      (20U)
4931 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                    /*!< 0x00100000 */
4932 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4933 #define CAN_F6R2_FB21_Pos      (21U)
4934 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                    /*!< 0x00200000 */
4935 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4936 #define CAN_F6R2_FB22_Pos      (22U)
4937 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                    /*!< 0x00400000 */
4938 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4939 #define CAN_F6R2_FB23_Pos      (23U)
4940 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                    /*!< 0x00800000 */
4941 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4942 #define CAN_F6R2_FB24_Pos      (24U)
4943 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                    /*!< 0x01000000 */
4944 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4945 #define CAN_F6R2_FB25_Pos      (25U)
4946 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                    /*!< 0x02000000 */
4947 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4948 #define CAN_F6R2_FB26_Pos      (26U)
4949 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                    /*!< 0x04000000 */
4950 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4951 #define CAN_F6R2_FB27_Pos      (27U)
4952 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                    /*!< 0x08000000 */
4953 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4954 #define CAN_F6R2_FB28_Pos      (28U)
4955 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                    /*!< 0x10000000 */
4956 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4957 #define CAN_F6R2_FB29_Pos      (29U)
4958 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                    /*!< 0x20000000 */
4959 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4960 #define CAN_F6R2_FB30_Pos      (30U)
4961 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                    /*!< 0x40000000 */
4962 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4963 #define CAN_F6R2_FB31_Pos      (31U)
4964 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                    /*!< 0x80000000 */
4965 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4966 
4967 /*******************  Bit definition for CAN_F7R2 register  *******************/
4968 #define CAN_F7R2_FB0_Pos       (0U)
4969 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                     /*!< 0x00000001 */
4970 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4971 #define CAN_F7R2_FB1_Pos       (1U)
4972 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                     /*!< 0x00000002 */
4973 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4974 #define CAN_F7R2_FB2_Pos       (2U)
4975 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                     /*!< 0x00000004 */
4976 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4977 #define CAN_F7R2_FB3_Pos       (3U)
4978 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                     /*!< 0x00000008 */
4979 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4980 #define CAN_F7R2_FB4_Pos       (4U)
4981 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                     /*!< 0x00000010 */
4982 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4983 #define CAN_F7R2_FB5_Pos       (5U)
4984 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                     /*!< 0x00000020 */
4985 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4986 #define CAN_F7R2_FB6_Pos       (6U)
4987 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                     /*!< 0x00000040 */
4988 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4989 #define CAN_F7R2_FB7_Pos       (7U)
4990 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                     /*!< 0x00000080 */
4991 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4992 #define CAN_F7R2_FB8_Pos       (8U)
4993 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                     /*!< 0x00000100 */
4994 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4995 #define CAN_F7R2_FB9_Pos       (9U)
4996 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                     /*!< 0x00000200 */
4997 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4998 #define CAN_F7R2_FB10_Pos      (10U)
4999 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                    /*!< 0x00000400 */
5000 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
5001 #define CAN_F7R2_FB11_Pos      (11U)
5002 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                    /*!< 0x00000800 */
5003 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
5004 #define CAN_F7R2_FB12_Pos      (12U)
5005 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                    /*!< 0x00001000 */
5006 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
5007 #define CAN_F7R2_FB13_Pos      (13U)
5008 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                    /*!< 0x00002000 */
5009 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
5010 #define CAN_F7R2_FB14_Pos      (14U)
5011 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                    /*!< 0x00004000 */
5012 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5013 #define CAN_F7R2_FB15_Pos      (15U)
5014 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                    /*!< 0x00008000 */
5015 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5016 #define CAN_F7R2_FB16_Pos      (16U)
5017 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                    /*!< 0x00010000 */
5018 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5019 #define CAN_F7R2_FB17_Pos      (17U)
5020 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                    /*!< 0x00020000 */
5021 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5022 #define CAN_F7R2_FB18_Pos      (18U)
5023 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                    /*!< 0x00040000 */
5024 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5025 #define CAN_F7R2_FB19_Pos      (19U)
5026 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                    /*!< 0x00080000 */
5027 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5028 #define CAN_F7R2_FB20_Pos      (20U)
5029 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                    /*!< 0x00100000 */
5030 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5031 #define CAN_F7R2_FB21_Pos      (21U)
5032 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                    /*!< 0x00200000 */
5033 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5034 #define CAN_F7R2_FB22_Pos      (22U)
5035 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                    /*!< 0x00400000 */
5036 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5037 #define CAN_F7R2_FB23_Pos      (23U)
5038 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                    /*!< 0x00800000 */
5039 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5040 #define CAN_F7R2_FB24_Pos      (24U)
5041 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                    /*!< 0x01000000 */
5042 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5043 #define CAN_F7R2_FB25_Pos      (25U)
5044 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                    /*!< 0x02000000 */
5045 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5046 #define CAN_F7R2_FB26_Pos      (26U)
5047 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                    /*!< 0x04000000 */
5048 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5049 #define CAN_F7R2_FB27_Pos      (27U)
5050 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                    /*!< 0x08000000 */
5051 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5052 #define CAN_F7R2_FB28_Pos      (28U)
5053 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                    /*!< 0x10000000 */
5054 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5055 #define CAN_F7R2_FB29_Pos      (29U)
5056 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                    /*!< 0x20000000 */
5057 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5058 #define CAN_F7R2_FB30_Pos      (30U)
5059 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                    /*!< 0x40000000 */
5060 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5061 #define CAN_F7R2_FB31_Pos      (31U)
5062 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                    /*!< 0x80000000 */
5063 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5064 
5065 /*******************  Bit definition for CAN_F8R2 register  *******************/
5066 #define CAN_F8R2_FB0_Pos       (0U)
5067 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                     /*!< 0x00000001 */
5068 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5069 #define CAN_F8R2_FB1_Pos       (1U)
5070 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                     /*!< 0x00000002 */
5071 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5072 #define CAN_F8R2_FB2_Pos       (2U)
5073 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                     /*!< 0x00000004 */
5074 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5075 #define CAN_F8R2_FB3_Pos       (3U)
5076 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                     /*!< 0x00000008 */
5077 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5078 #define CAN_F8R2_FB4_Pos       (4U)
5079 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                     /*!< 0x00000010 */
5080 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5081 #define CAN_F8R2_FB5_Pos       (5U)
5082 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                     /*!< 0x00000020 */
5083 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5084 #define CAN_F8R2_FB6_Pos       (6U)
5085 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                     /*!< 0x00000040 */
5086 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5087 #define CAN_F8R2_FB7_Pos       (7U)
5088 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                     /*!< 0x00000080 */
5089 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5090 #define CAN_F8R2_FB8_Pos       (8U)
5091 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                     /*!< 0x00000100 */
5092 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5093 #define CAN_F8R2_FB9_Pos       (9U)
5094 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                     /*!< 0x00000200 */
5095 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5096 #define CAN_F8R2_FB10_Pos      (10U)
5097 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                    /*!< 0x00000400 */
5098 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5099 #define CAN_F8R2_FB11_Pos      (11U)
5100 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                    /*!< 0x00000800 */
5101 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5102 #define CAN_F8R2_FB12_Pos      (12U)
5103 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                    /*!< 0x00001000 */
5104 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5105 #define CAN_F8R2_FB13_Pos      (13U)
5106 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                    /*!< 0x00002000 */
5107 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5108 #define CAN_F8R2_FB14_Pos      (14U)
5109 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                    /*!< 0x00004000 */
5110 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5111 #define CAN_F8R2_FB15_Pos      (15U)
5112 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                    /*!< 0x00008000 */
5113 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5114 #define CAN_F8R2_FB16_Pos      (16U)
5115 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                    /*!< 0x00010000 */
5116 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5117 #define CAN_F8R2_FB17_Pos      (17U)
5118 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                    /*!< 0x00020000 */
5119 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5120 #define CAN_F8R2_FB18_Pos      (18U)
5121 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                    /*!< 0x00040000 */
5122 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5123 #define CAN_F8R2_FB19_Pos      (19U)
5124 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                    /*!< 0x00080000 */
5125 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5126 #define CAN_F8R2_FB20_Pos      (20U)
5127 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                    /*!< 0x00100000 */
5128 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5129 #define CAN_F8R2_FB21_Pos      (21U)
5130 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                    /*!< 0x00200000 */
5131 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5132 #define CAN_F8R2_FB22_Pos      (22U)
5133 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                    /*!< 0x00400000 */
5134 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5135 #define CAN_F8R2_FB23_Pos      (23U)
5136 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                    /*!< 0x00800000 */
5137 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5138 #define CAN_F8R2_FB24_Pos      (24U)
5139 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                    /*!< 0x01000000 */
5140 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5141 #define CAN_F8R2_FB25_Pos      (25U)
5142 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                    /*!< 0x02000000 */
5143 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5144 #define CAN_F8R2_FB26_Pos      (26U)
5145 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                    /*!< 0x04000000 */
5146 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5147 #define CAN_F8R2_FB27_Pos      (27U)
5148 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                    /*!< 0x08000000 */
5149 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5150 #define CAN_F8R2_FB28_Pos      (28U)
5151 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                    /*!< 0x10000000 */
5152 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5153 #define CAN_F8R2_FB29_Pos      (29U)
5154 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                    /*!< 0x20000000 */
5155 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5156 #define CAN_F8R2_FB30_Pos      (30U)
5157 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                    /*!< 0x40000000 */
5158 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5159 #define CAN_F8R2_FB31_Pos      (31U)
5160 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                    /*!< 0x80000000 */
5161 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5162 
5163 /*******************  Bit definition for CAN_F9R2 register  *******************/
5164 #define CAN_F9R2_FB0_Pos       (0U)
5165 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                     /*!< 0x00000001 */
5166 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5167 #define CAN_F9R2_FB1_Pos       (1U)
5168 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                     /*!< 0x00000002 */
5169 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5170 #define CAN_F9R2_FB2_Pos       (2U)
5171 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                     /*!< 0x00000004 */
5172 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5173 #define CAN_F9R2_FB3_Pos       (3U)
5174 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                     /*!< 0x00000008 */
5175 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5176 #define CAN_F9R2_FB4_Pos       (4U)
5177 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                     /*!< 0x00000010 */
5178 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5179 #define CAN_F9R2_FB5_Pos       (5U)
5180 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                     /*!< 0x00000020 */
5181 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5182 #define CAN_F9R2_FB6_Pos       (6U)
5183 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                     /*!< 0x00000040 */
5184 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5185 #define CAN_F9R2_FB7_Pos       (7U)
5186 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                     /*!< 0x00000080 */
5187 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5188 #define CAN_F9R2_FB8_Pos       (8U)
5189 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                     /*!< 0x00000100 */
5190 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5191 #define CAN_F9R2_FB9_Pos       (9U)
5192 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                     /*!< 0x00000200 */
5193 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5194 #define CAN_F9R2_FB10_Pos      (10U)
5195 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                    /*!< 0x00000400 */
5196 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5197 #define CAN_F9R2_FB11_Pos      (11U)
5198 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                    /*!< 0x00000800 */
5199 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5200 #define CAN_F9R2_FB12_Pos      (12U)
5201 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                    /*!< 0x00001000 */
5202 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5203 #define CAN_F9R2_FB13_Pos      (13U)
5204 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                    /*!< 0x00002000 */
5205 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5206 #define CAN_F9R2_FB14_Pos      (14U)
5207 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                    /*!< 0x00004000 */
5208 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5209 #define CAN_F9R2_FB15_Pos      (15U)
5210 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                    /*!< 0x00008000 */
5211 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5212 #define CAN_F9R2_FB16_Pos      (16U)
5213 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                    /*!< 0x00010000 */
5214 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5215 #define CAN_F9R2_FB17_Pos      (17U)
5216 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                    /*!< 0x00020000 */
5217 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5218 #define CAN_F9R2_FB18_Pos      (18U)
5219 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                    /*!< 0x00040000 */
5220 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5221 #define CAN_F9R2_FB19_Pos      (19U)
5222 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                    /*!< 0x00080000 */
5223 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5224 #define CAN_F9R2_FB20_Pos      (20U)
5225 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                    /*!< 0x00100000 */
5226 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5227 #define CAN_F9R2_FB21_Pos      (21U)
5228 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                    /*!< 0x00200000 */
5229 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5230 #define CAN_F9R2_FB22_Pos      (22U)
5231 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                    /*!< 0x00400000 */
5232 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5233 #define CAN_F9R2_FB23_Pos      (23U)
5234 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                    /*!< 0x00800000 */
5235 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5236 #define CAN_F9R2_FB24_Pos      (24U)
5237 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                    /*!< 0x01000000 */
5238 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5239 #define CAN_F9R2_FB25_Pos      (25U)
5240 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                    /*!< 0x02000000 */
5241 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5242 #define CAN_F9R2_FB26_Pos      (26U)
5243 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                    /*!< 0x04000000 */
5244 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5245 #define CAN_F9R2_FB27_Pos      (27U)
5246 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                    /*!< 0x08000000 */
5247 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5248 #define CAN_F9R2_FB28_Pos      (28U)
5249 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                    /*!< 0x10000000 */
5250 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5251 #define CAN_F9R2_FB29_Pos      (29U)
5252 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                    /*!< 0x20000000 */
5253 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5254 #define CAN_F9R2_FB30_Pos      (30U)
5255 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                    /*!< 0x40000000 */
5256 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5257 #define CAN_F9R2_FB31_Pos      (31U)
5258 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                    /*!< 0x80000000 */
5259 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5260 
5261 /*******************  Bit definition for CAN_F10R2 register  ******************/
5262 #define CAN_F10R2_FB0_Pos      (0U)
5263 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                    /*!< 0x00000001 */
5264 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5265 #define CAN_F10R2_FB1_Pos      (1U)
5266 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                    /*!< 0x00000002 */
5267 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5268 #define CAN_F10R2_FB2_Pos      (2U)
5269 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                    /*!< 0x00000004 */
5270 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5271 #define CAN_F10R2_FB3_Pos      (3U)
5272 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                    /*!< 0x00000008 */
5273 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5274 #define CAN_F10R2_FB4_Pos      (4U)
5275 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                    /*!< 0x00000010 */
5276 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5277 #define CAN_F10R2_FB5_Pos      (5U)
5278 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                    /*!< 0x00000020 */
5279 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5280 #define CAN_F10R2_FB6_Pos      (6U)
5281 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                    /*!< 0x00000040 */
5282 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5283 #define CAN_F10R2_FB7_Pos      (7U)
5284 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                    /*!< 0x00000080 */
5285 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5286 #define CAN_F10R2_FB8_Pos      (8U)
5287 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                    /*!< 0x00000100 */
5288 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5289 #define CAN_F10R2_FB9_Pos      (9U)
5290 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                    /*!< 0x00000200 */
5291 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5292 #define CAN_F10R2_FB10_Pos     (10U)
5293 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                   /*!< 0x00000400 */
5294 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5295 #define CAN_F10R2_FB11_Pos     (11U)
5296 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                   /*!< 0x00000800 */
5297 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5298 #define CAN_F10R2_FB12_Pos     (12U)
5299 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                   /*!< 0x00001000 */
5300 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5301 #define CAN_F10R2_FB13_Pos     (13U)
5302 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                   /*!< 0x00002000 */
5303 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5304 #define CAN_F10R2_FB14_Pos     (14U)
5305 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                   /*!< 0x00004000 */
5306 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5307 #define CAN_F10R2_FB15_Pos     (15U)
5308 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                   /*!< 0x00008000 */
5309 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5310 #define CAN_F10R2_FB16_Pos     (16U)
5311 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                   /*!< 0x00010000 */
5312 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5313 #define CAN_F10R2_FB17_Pos     (17U)
5314 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                   /*!< 0x00020000 */
5315 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5316 #define CAN_F10R2_FB18_Pos     (18U)
5317 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                   /*!< 0x00040000 */
5318 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5319 #define CAN_F10R2_FB19_Pos     (19U)
5320 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                   /*!< 0x00080000 */
5321 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5322 #define CAN_F10R2_FB20_Pos     (20U)
5323 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                   /*!< 0x00100000 */
5324 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5325 #define CAN_F10R2_FB21_Pos     (21U)
5326 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                   /*!< 0x00200000 */
5327 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5328 #define CAN_F10R2_FB22_Pos     (22U)
5329 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                   /*!< 0x00400000 */
5330 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5331 #define CAN_F10R2_FB23_Pos     (23U)
5332 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                   /*!< 0x00800000 */
5333 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5334 #define CAN_F10R2_FB24_Pos     (24U)
5335 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                   /*!< 0x01000000 */
5336 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5337 #define CAN_F10R2_FB25_Pos     (25U)
5338 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                   /*!< 0x02000000 */
5339 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5340 #define CAN_F10R2_FB26_Pos     (26U)
5341 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                   /*!< 0x04000000 */
5342 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5343 #define CAN_F10R2_FB27_Pos     (27U)
5344 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                   /*!< 0x08000000 */
5345 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5346 #define CAN_F10R2_FB28_Pos     (28U)
5347 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                   /*!< 0x10000000 */
5348 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5349 #define CAN_F10R2_FB29_Pos     (29U)
5350 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                   /*!< 0x20000000 */
5351 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5352 #define CAN_F10R2_FB30_Pos     (30U)
5353 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                   /*!< 0x40000000 */
5354 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5355 #define CAN_F10R2_FB31_Pos     (31U)
5356 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                   /*!< 0x80000000 */
5357 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5358 
5359 /*******************  Bit definition for CAN_F11R2 register  ******************/
5360 #define CAN_F11R2_FB0_Pos      (0U)
5361 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                    /*!< 0x00000001 */
5362 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5363 #define CAN_F11R2_FB1_Pos      (1U)
5364 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                    /*!< 0x00000002 */
5365 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5366 #define CAN_F11R2_FB2_Pos      (2U)
5367 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                    /*!< 0x00000004 */
5368 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5369 #define CAN_F11R2_FB3_Pos      (3U)
5370 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                    /*!< 0x00000008 */
5371 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5372 #define CAN_F11R2_FB4_Pos      (4U)
5373 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                    /*!< 0x00000010 */
5374 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5375 #define CAN_F11R2_FB5_Pos      (5U)
5376 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                    /*!< 0x00000020 */
5377 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5378 #define CAN_F11R2_FB6_Pos      (6U)
5379 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                    /*!< 0x00000040 */
5380 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5381 #define CAN_F11R2_FB7_Pos      (7U)
5382 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                    /*!< 0x00000080 */
5383 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5384 #define CAN_F11R2_FB8_Pos      (8U)
5385 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                    /*!< 0x00000100 */
5386 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5387 #define CAN_F11R2_FB9_Pos      (9U)
5388 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                    /*!< 0x00000200 */
5389 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5390 #define CAN_F11R2_FB10_Pos     (10U)
5391 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                   /*!< 0x00000400 */
5392 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5393 #define CAN_F11R2_FB11_Pos     (11U)
5394 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                   /*!< 0x00000800 */
5395 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5396 #define CAN_F11R2_FB12_Pos     (12U)
5397 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                   /*!< 0x00001000 */
5398 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5399 #define CAN_F11R2_FB13_Pos     (13U)
5400 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                   /*!< 0x00002000 */
5401 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5402 #define CAN_F11R2_FB14_Pos     (14U)
5403 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                   /*!< 0x00004000 */
5404 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5405 #define CAN_F11R2_FB15_Pos     (15U)
5406 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                   /*!< 0x00008000 */
5407 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5408 #define CAN_F11R2_FB16_Pos     (16U)
5409 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                   /*!< 0x00010000 */
5410 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5411 #define CAN_F11R2_FB17_Pos     (17U)
5412 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                   /*!< 0x00020000 */
5413 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5414 #define CAN_F11R2_FB18_Pos     (18U)
5415 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                   /*!< 0x00040000 */
5416 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5417 #define CAN_F11R2_FB19_Pos     (19U)
5418 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                   /*!< 0x00080000 */
5419 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5420 #define CAN_F11R2_FB20_Pos     (20U)
5421 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                   /*!< 0x00100000 */
5422 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5423 #define CAN_F11R2_FB21_Pos     (21U)
5424 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                   /*!< 0x00200000 */
5425 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5426 #define CAN_F11R2_FB22_Pos     (22U)
5427 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                   /*!< 0x00400000 */
5428 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5429 #define CAN_F11R2_FB23_Pos     (23U)
5430 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                   /*!< 0x00800000 */
5431 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5432 #define CAN_F11R2_FB24_Pos     (24U)
5433 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                   /*!< 0x01000000 */
5434 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5435 #define CAN_F11R2_FB25_Pos     (25U)
5436 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                   /*!< 0x02000000 */
5437 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5438 #define CAN_F11R2_FB26_Pos     (26U)
5439 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                   /*!< 0x04000000 */
5440 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5441 #define CAN_F11R2_FB27_Pos     (27U)
5442 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                   /*!< 0x08000000 */
5443 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5444 #define CAN_F11R2_FB28_Pos     (28U)
5445 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                   /*!< 0x10000000 */
5446 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5447 #define CAN_F11R2_FB29_Pos     (29U)
5448 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                   /*!< 0x20000000 */
5449 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5450 #define CAN_F11R2_FB30_Pos     (30U)
5451 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                   /*!< 0x40000000 */
5452 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5453 #define CAN_F11R2_FB31_Pos     (31U)
5454 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                   /*!< 0x80000000 */
5455 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5456 
5457 /*******************  Bit definition for CAN_F12R2 register  ******************/
5458 #define CAN_F12R2_FB0_Pos      (0U)
5459 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                    /*!< 0x00000001 */
5460 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5461 #define CAN_F12R2_FB1_Pos      (1U)
5462 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                    /*!< 0x00000002 */
5463 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5464 #define CAN_F12R2_FB2_Pos      (2U)
5465 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                    /*!< 0x00000004 */
5466 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5467 #define CAN_F12R2_FB3_Pos      (3U)
5468 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                    /*!< 0x00000008 */
5469 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5470 #define CAN_F12R2_FB4_Pos      (4U)
5471 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                    /*!< 0x00000010 */
5472 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5473 #define CAN_F12R2_FB5_Pos      (5U)
5474 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                    /*!< 0x00000020 */
5475 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5476 #define CAN_F12R2_FB6_Pos      (6U)
5477 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                    /*!< 0x00000040 */
5478 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5479 #define CAN_F12R2_FB7_Pos      (7U)
5480 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                    /*!< 0x00000080 */
5481 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5482 #define CAN_F12R2_FB8_Pos      (8U)
5483 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                    /*!< 0x00000100 */
5484 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5485 #define CAN_F12R2_FB9_Pos      (9U)
5486 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                    /*!< 0x00000200 */
5487 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5488 #define CAN_F12R2_FB10_Pos     (10U)
5489 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                   /*!< 0x00000400 */
5490 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5491 #define CAN_F12R2_FB11_Pos     (11U)
5492 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                   /*!< 0x00000800 */
5493 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5494 #define CAN_F12R2_FB12_Pos     (12U)
5495 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                   /*!< 0x00001000 */
5496 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5497 #define CAN_F12R2_FB13_Pos     (13U)
5498 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                   /*!< 0x00002000 */
5499 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5500 #define CAN_F12R2_FB14_Pos     (14U)
5501 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                   /*!< 0x00004000 */
5502 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5503 #define CAN_F12R2_FB15_Pos     (15U)
5504 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                   /*!< 0x00008000 */
5505 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5506 #define CAN_F12R2_FB16_Pos     (16U)
5507 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                   /*!< 0x00010000 */
5508 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5509 #define CAN_F12R2_FB17_Pos     (17U)
5510 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                   /*!< 0x00020000 */
5511 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5512 #define CAN_F12R2_FB18_Pos     (18U)
5513 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                   /*!< 0x00040000 */
5514 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5515 #define CAN_F12R2_FB19_Pos     (19U)
5516 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                   /*!< 0x00080000 */
5517 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5518 #define CAN_F12R2_FB20_Pos     (20U)
5519 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                   /*!< 0x00100000 */
5520 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5521 #define CAN_F12R2_FB21_Pos     (21U)
5522 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                   /*!< 0x00200000 */
5523 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5524 #define CAN_F12R2_FB22_Pos     (22U)
5525 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                   /*!< 0x00400000 */
5526 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5527 #define CAN_F12R2_FB23_Pos     (23U)
5528 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                   /*!< 0x00800000 */
5529 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5530 #define CAN_F12R2_FB24_Pos     (24U)
5531 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                   /*!< 0x01000000 */
5532 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5533 #define CAN_F12R2_FB25_Pos     (25U)
5534 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                   /*!< 0x02000000 */
5535 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5536 #define CAN_F12R2_FB26_Pos     (26U)
5537 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                   /*!< 0x04000000 */
5538 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5539 #define CAN_F12R2_FB27_Pos     (27U)
5540 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                   /*!< 0x08000000 */
5541 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5542 #define CAN_F12R2_FB28_Pos     (28U)
5543 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                   /*!< 0x10000000 */
5544 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5545 #define CAN_F12R2_FB29_Pos     (29U)
5546 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                   /*!< 0x20000000 */
5547 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5548 #define CAN_F12R2_FB30_Pos     (30U)
5549 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                   /*!< 0x40000000 */
5550 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5551 #define CAN_F12R2_FB31_Pos     (31U)
5552 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                   /*!< 0x80000000 */
5553 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5554 
5555 /*******************  Bit definition for CAN_F13R2 register  ******************/
5556 #define CAN_F13R2_FB0_Pos      (0U)
5557 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                    /*!< 0x00000001 */
5558 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5559 #define CAN_F13R2_FB1_Pos      (1U)
5560 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                    /*!< 0x00000002 */
5561 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5562 #define CAN_F13R2_FB2_Pos      (2U)
5563 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                    /*!< 0x00000004 */
5564 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5565 #define CAN_F13R2_FB3_Pos      (3U)
5566 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                    /*!< 0x00000008 */
5567 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5568 #define CAN_F13R2_FB4_Pos      (4U)
5569 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                    /*!< 0x00000010 */
5570 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5571 #define CAN_F13R2_FB5_Pos      (5U)
5572 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                    /*!< 0x00000020 */
5573 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5574 #define CAN_F13R2_FB6_Pos      (6U)
5575 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                    /*!< 0x00000040 */
5576 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5577 #define CAN_F13R2_FB7_Pos      (7U)
5578 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                    /*!< 0x00000080 */
5579 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5580 #define CAN_F13R2_FB8_Pos      (8U)
5581 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                    /*!< 0x00000100 */
5582 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5583 #define CAN_F13R2_FB9_Pos      (9U)
5584 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                    /*!< 0x00000200 */
5585 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5586 #define CAN_F13R2_FB10_Pos     (10U)
5587 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                   /*!< 0x00000400 */
5588 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5589 #define CAN_F13R2_FB11_Pos     (11U)
5590 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                   /*!< 0x00000800 */
5591 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5592 #define CAN_F13R2_FB12_Pos     (12U)
5593 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                   /*!< 0x00001000 */
5594 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5595 #define CAN_F13R2_FB13_Pos     (13U)
5596 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                   /*!< 0x00002000 */
5597 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5598 #define CAN_F13R2_FB14_Pos     (14U)
5599 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                   /*!< 0x00004000 */
5600 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5601 #define CAN_F13R2_FB15_Pos     (15U)
5602 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                   /*!< 0x00008000 */
5603 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5604 #define CAN_F13R2_FB16_Pos     (16U)
5605 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                   /*!< 0x00010000 */
5606 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5607 #define CAN_F13R2_FB17_Pos     (17U)
5608 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                   /*!< 0x00020000 */
5609 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5610 #define CAN_F13R2_FB18_Pos     (18U)
5611 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                   /*!< 0x00040000 */
5612 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5613 #define CAN_F13R2_FB19_Pos     (19U)
5614 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                   /*!< 0x00080000 */
5615 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5616 #define CAN_F13R2_FB20_Pos     (20U)
5617 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                   /*!< 0x00100000 */
5618 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5619 #define CAN_F13R2_FB21_Pos     (21U)
5620 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                   /*!< 0x00200000 */
5621 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5622 #define CAN_F13R2_FB22_Pos     (22U)
5623 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                   /*!< 0x00400000 */
5624 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5625 #define CAN_F13R2_FB23_Pos     (23U)
5626 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                   /*!< 0x00800000 */
5627 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5628 #define CAN_F13R2_FB24_Pos     (24U)
5629 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                   /*!< 0x01000000 */
5630 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5631 #define CAN_F13R2_FB25_Pos     (25U)
5632 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                   /*!< 0x02000000 */
5633 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5634 #define CAN_F13R2_FB26_Pos     (26U)
5635 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                   /*!< 0x04000000 */
5636 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5637 #define CAN_F13R2_FB27_Pos     (27U)
5638 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                   /*!< 0x08000000 */
5639 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5640 #define CAN_F13R2_FB28_Pos     (28U)
5641 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                   /*!< 0x10000000 */
5642 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5643 #define CAN_F13R2_FB29_Pos     (29U)
5644 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                   /*!< 0x20000000 */
5645 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5646 #define CAN_F13R2_FB30_Pos     (30U)
5647 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                   /*!< 0x40000000 */
5648 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5649 #define CAN_F13R2_FB31_Pos     (31U)
5650 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                   /*!< 0x80000000 */
5651 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5652 
5653 /******************************************************************************/
5654 /*                                                                            */
5655 /*                          CRC calculation unit                              */
5656 /*                                                                            */
5657 /******************************************************************************/
5658 /*******************  Bit definition for CRC_DR register  *********************/
5659 #define CRC_DR_DR_Pos            (0U)
5660 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
5661 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
5662 
5663 /*******************  Bit definition for CRC_IDR register  ********************/
5664 #define CRC_IDR_IDR_Pos          (0U)
5665 #define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
5666 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
5667 
5668 /********************  Bit definition for CRC_CR register  ********************/
5669 #define CRC_CR_RESET_Pos         (0U)
5670 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
5671 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
5672 #define CRC_CR_POLYSIZE_Pos      (3U)
5673 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
5674 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
5675 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
5676 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
5677 #define CRC_CR_REV_IN_Pos        (5U)
5678 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
5679 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
5680 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
5681 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
5682 #define CRC_CR_REV_OUT_Pos       (7U)
5683 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
5684 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
5685 
5686 /*******************  Bit definition for CRC_INIT register  *******************/
5687 #define CRC_INIT_INIT_Pos        (0U)
5688 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
5689 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
5690 
5691 /*******************  Bit definition for CRC_POL register  ********************/
5692 #define CRC_POL_POL_Pos          (0U)
5693 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
5694 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
5695 
5696 /******************************************************************************/
5697 /*                                                                            */
5698 /*                          CRS Clock Recovery System                         */
5699 /******************************************************************************/
5700 
5701 /*******************  Bit definition for CRS_CR register  *********************/
5702 #define CRS_CR_SYNCOKIE_Pos       (0U)
5703 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
5704 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
5705 #define CRS_CR_SYNCWARNIE_Pos     (1U)
5706 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
5707 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
5708 #define CRS_CR_ERRIE_Pos          (2U)
5709 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
5710 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
5711 #define CRS_CR_ESYNCIE_Pos        (3U)
5712 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
5713 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
5714 #define CRS_CR_CEN_Pos            (5U)
5715 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
5716 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
5717 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
5718 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
5719 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
5720 #define CRS_CR_SWSYNC_Pos         (7U)
5721 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
5722 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
5723 #define CRS_CR_TRIM_Pos           (8U)
5724 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
5725 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< TRIM[5:0] HSI48 oscillator smooth trimming */
5726 #define CRS_CR_TRIM_0             (0x01UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000100 */
5727 #define CRS_CR_TRIM_1             (0x02UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000200 */
5728 #define CRS_CR_TRIM_2             (0x04UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000400 */
5729 #define CRS_CR_TRIM_3             (0x08UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000800 */
5730 #define CRS_CR_TRIM_4             (0x10UL << CRS_CR_TRIM_Pos)                  /*!< 0x00001000 */
5731 #define CRS_CR_TRIM_5             (0x20UL << CRS_CR_TRIM_Pos)                  /*!< 0x00002000 */
5732 
5733 /*******************  Bit definition for CRS_CFGR register  *********************/
5734 #define CRS_CFGR_RELOAD_Pos       (0U)
5735 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
5736 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
5737 #define CRS_CFGR_FELIM_Pos        (16U)
5738 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
5739 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
5740 
5741 #define CRS_CFGR_SYNCDIV_Pos      (24U)
5742 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
5743 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
5744 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
5745 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
5746 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
5747 
5748 #define CRS_CFGR_SYNCSRC_Pos      (28U)
5749 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
5750 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
5751 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
5752 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
5753 
5754 #define CRS_CFGR_SYNCPOL_Pos      (31U)
5755 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
5756 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
5757 
5758 /*******************  Bit definition for CRS_ISR register  *********************/
5759 #define CRS_ISR_SYNCOKF_Pos       (0U)
5760 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
5761 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
5762 #define CRS_ISR_SYNCWARNF_Pos     (1U)
5763 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
5764 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
5765 #define CRS_ISR_ERRF_Pos          (2U)
5766 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
5767 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
5768 #define CRS_ISR_ESYNCF_Pos        (3U)
5769 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
5770 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
5771 #define CRS_ISR_SYNCERR_Pos       (8U)
5772 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
5773 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
5774 #define CRS_ISR_SYNCMISS_Pos      (9U)
5775 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
5776 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
5777 #define CRS_ISR_TRIMOVF_Pos       (10U)
5778 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
5779 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
5780 #define CRS_ISR_FEDIR_Pos         (15U)
5781 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
5782 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
5783 #define CRS_ISR_FECAP_Pos         (16U)
5784 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
5785 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
5786 
5787 /*******************  Bit definition for CRS_ICR register  *********************/
5788 #define CRS_ICR_SYNCOKC_Pos       (0U)
5789 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
5790 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
5791 #define CRS_ICR_SYNCWARNC_Pos     (1U)
5792 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
5793 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
5794 #define CRS_ICR_ERRC_Pos          (2U)
5795 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
5796 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
5797 #define CRS_ICR_ESYNCC_Pos        (3U)
5798 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
5799 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
5800 
5801 /******************************************************************************/
5802 /*                                                                            */
5803 /*                      Digital to Analog Converter                           */
5804 /*                                                                            */
5805 /******************************************************************************/
5806 /*
5807  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
5808  */
5809 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
5810 
5811 /********************  Bit definition for DAC_CR register  ********************/
5812 #define DAC_CR_EN1_Pos              (0U)
5813 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
5814 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5815 #define DAC_CR_TEN1_Pos             (2U)
5816 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000004 */
5817 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5818 
5819 #define DAC_CR_TSEL1_Pos            (3U)
5820 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000038 */
5821 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5822 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
5823 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
5824 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
5825 
5826 #define DAC_CR_WAVE1_Pos            (6U)
5827 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
5828 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5829 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
5830 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
5831 
5832 #define DAC_CR_MAMP1_Pos            (8U)
5833 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
5834 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5835 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
5836 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
5837 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
5838 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
5839 
5840 #define DAC_CR_DMAEN1_Pos           (12U)
5841 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
5842 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5843 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5844 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
5845 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
5846 #define DAC_CR_CEN1_Pos             (14U)
5847 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
5848 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
5849 
5850 #define DAC_CR_EN2_Pos              (16U)
5851 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
5852 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5853 #define DAC_CR_TEN2_Pos             (18U)
5854 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00040000 */
5855 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5856 
5857 #define DAC_CR_TSEL2_Pos            (19U)
5858 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                /*!< 0x00380000 */
5859 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5860 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
5861 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
5862 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
5863 
5864 #define DAC_CR_WAVE2_Pos            (22U)
5865 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
5866 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5867 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
5868 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
5869 
5870 #define DAC_CR_MAMP2_Pos            (24U)
5871 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
5872 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5873 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
5874 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
5875 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
5876 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
5877 
5878 #define DAC_CR_DMAEN2_Pos           (28U)
5879 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
5880 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5881 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5882 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
5883 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
5884 #define DAC_CR_CEN2_Pos             (30U)
5885 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
5886 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
5887 
5888 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5889 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5890 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
5891 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5892 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5893 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
5894 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5895 
5896 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5897 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5898 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
5899 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5900 
5901 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5902 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5903 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
5904 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5905 
5906 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5907 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5908 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
5909 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5910 
5911 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5912 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5913 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
5914 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5915 
5916 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5917 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5918 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
5919 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5920 
5921 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5922 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5923 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
5924 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5925 
5926 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5927 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5928 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
5929 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5930 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5931 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
5932 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5933 
5934 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5935 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5936 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
5937 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5938 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5939 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
5940 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5941 
5942 /******************  Bit definition for DAC_DHR8RD register  ******************/
5943 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5944 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
5945 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5946 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5947 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
5948 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5949 
5950 /*******************  Bit definition for DAC_DOR1 register  *******************/
5951 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5952 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
5953 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5954 
5955 /*******************  Bit definition for DAC_DOR2 register  *******************/
5956 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5957 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
5958 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5959 
5960 /********************  Bit definition for DAC_SR register  ********************/
5961 #define DAC_SR_DMAUDR1_Pos          (13U)
5962 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
5963 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5964 #define DAC_SR_CAL_FLAG1_Pos        (14U)
5965 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
5966 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
5967 #define DAC_SR_BWST1_Pos            (15U)
5968 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
5969 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
5970 
5971 #define DAC_SR_DMAUDR2_Pos          (29U)
5972 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
5973 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5974 #define DAC_SR_CAL_FLAG2_Pos        (30U)
5975 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
5976 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
5977 #define DAC_SR_BWST2_Pos            (31U)
5978 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
5979 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
5980 
5981 /*******************  Bit definition for DAC_CCR register  ********************/
5982 #define DAC_CCR_OTRIM1_Pos          (0U)
5983 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
5984 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
5985 #define DAC_CCR_OTRIM2_Pos          (16U)
5986 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
5987 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
5988 
5989 /*******************  Bit definition for DAC_MCR register  *******************/
5990 #define DAC_MCR_MODE1_Pos           (0U)
5991 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
5992 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
5993 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
5994 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
5995 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
5996 
5997 #define DAC_MCR_MODE2_Pos           (16U)
5998 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
5999 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
6000 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
6001 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
6002 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
6003 
6004 /******************  Bit definition for DAC_SHSR1 register  ******************/
6005 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
6006 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
6007 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
6008 
6009 /******************  Bit definition for DAC_SHSR2 register  ******************/
6010 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
6011 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
6012 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
6013 
6014 /******************  Bit definition for DAC_SHHR register  ******************/
6015 #define DAC_SHHR_THOLD1_Pos         (0U)
6016 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
6017 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
6018 #define DAC_SHHR_THOLD2_Pos         (16U)
6019 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
6020 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
6021 
6022 /******************  Bit definition for DAC_SHRR register  ******************/
6023 #define DAC_SHRR_TREFRESH1_Pos      (0U)
6024 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
6025 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
6026 #define DAC_SHRR_TREFRESH2_Pos      (16U)
6027 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
6028 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
6029 
6030 /******************************************************************************/
6031 /*                                                                            */
6032 /*                           DMA Controller (DMA)                             */
6033 /*                                                                            */
6034 /******************************************************************************/
6035 
6036 /*******************  Bit definition for DMA_ISR register  ********************/
6037 #define DMA_ISR_GIF1_Pos       (0U)
6038 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
6039 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
6040 #define DMA_ISR_TCIF1_Pos      (1U)
6041 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
6042 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
6043 #define DMA_ISR_HTIF1_Pos      (2U)
6044 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
6045 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
6046 #define DMA_ISR_TEIF1_Pos      (3U)
6047 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
6048 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
6049 #define DMA_ISR_GIF2_Pos       (4U)
6050 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
6051 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
6052 #define DMA_ISR_TCIF2_Pos      (5U)
6053 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
6054 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
6055 #define DMA_ISR_HTIF2_Pos      (6U)
6056 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
6057 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
6058 #define DMA_ISR_TEIF2_Pos      (7U)
6059 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
6060 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
6061 #define DMA_ISR_GIF3_Pos       (8U)
6062 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
6063 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
6064 #define DMA_ISR_TCIF3_Pos      (9U)
6065 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
6066 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
6067 #define DMA_ISR_HTIF3_Pos      (10U)
6068 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
6069 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
6070 #define DMA_ISR_TEIF3_Pos      (11U)
6071 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
6072 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
6073 #define DMA_ISR_GIF4_Pos       (12U)
6074 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
6075 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
6076 #define DMA_ISR_TCIF4_Pos      (13U)
6077 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
6078 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
6079 #define DMA_ISR_HTIF4_Pos      (14U)
6080 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
6081 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
6082 #define DMA_ISR_TEIF4_Pos      (15U)
6083 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
6084 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
6085 #define DMA_ISR_GIF5_Pos       (16U)
6086 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
6087 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
6088 #define DMA_ISR_TCIF5_Pos      (17U)
6089 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
6090 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
6091 #define DMA_ISR_HTIF5_Pos      (18U)
6092 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
6093 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
6094 #define DMA_ISR_TEIF5_Pos      (19U)
6095 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
6096 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
6097 #define DMA_ISR_GIF6_Pos       (20U)
6098 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
6099 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
6100 #define DMA_ISR_TCIF6_Pos      (21U)
6101 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
6102 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
6103 #define DMA_ISR_HTIF6_Pos      (22U)
6104 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
6105 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
6106 #define DMA_ISR_TEIF6_Pos      (23U)
6107 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
6108 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
6109 #define DMA_ISR_GIF7_Pos       (24U)
6110 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
6111 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
6112 #define DMA_ISR_TCIF7_Pos      (25U)
6113 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
6114 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
6115 #define DMA_ISR_HTIF7_Pos      (26U)
6116 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
6117 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
6118 #define DMA_ISR_TEIF7_Pos      (27U)
6119 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
6120 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
6121 
6122 /*******************  Bit definition for DMA_IFCR register  *******************/
6123 #define DMA_IFCR_CGIF1_Pos     (0U)
6124 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
6125 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
6126 #define DMA_IFCR_CTCIF1_Pos    (1U)
6127 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
6128 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
6129 #define DMA_IFCR_CHTIF1_Pos    (2U)
6130 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
6131 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
6132 #define DMA_IFCR_CTEIF1_Pos    (3U)
6133 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
6134 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
6135 #define DMA_IFCR_CGIF2_Pos     (4U)
6136 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
6137 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
6138 #define DMA_IFCR_CTCIF2_Pos    (5U)
6139 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
6140 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
6141 #define DMA_IFCR_CHTIF2_Pos    (6U)
6142 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
6143 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
6144 #define DMA_IFCR_CTEIF2_Pos    (7U)
6145 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
6146 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
6147 #define DMA_IFCR_CGIF3_Pos     (8U)
6148 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
6149 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
6150 #define DMA_IFCR_CTCIF3_Pos    (9U)
6151 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
6152 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
6153 #define DMA_IFCR_CHTIF3_Pos    (10U)
6154 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
6155 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
6156 #define DMA_IFCR_CTEIF3_Pos    (11U)
6157 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
6158 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
6159 #define DMA_IFCR_CGIF4_Pos     (12U)
6160 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
6161 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
6162 #define DMA_IFCR_CTCIF4_Pos    (13U)
6163 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
6164 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
6165 #define DMA_IFCR_CHTIF4_Pos    (14U)
6166 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
6167 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
6168 #define DMA_IFCR_CTEIF4_Pos    (15U)
6169 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
6170 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
6171 #define DMA_IFCR_CGIF5_Pos     (16U)
6172 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
6173 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
6174 #define DMA_IFCR_CTCIF5_Pos    (17U)
6175 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
6176 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
6177 #define DMA_IFCR_CHTIF5_Pos    (18U)
6178 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
6179 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
6180 #define DMA_IFCR_CTEIF5_Pos    (19U)
6181 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
6182 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
6183 #define DMA_IFCR_CGIF6_Pos     (20U)
6184 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
6185 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
6186 #define DMA_IFCR_CTCIF6_Pos    (21U)
6187 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
6188 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
6189 #define DMA_IFCR_CHTIF6_Pos    (22U)
6190 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
6191 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
6192 #define DMA_IFCR_CTEIF6_Pos    (23U)
6193 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
6194 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
6195 #define DMA_IFCR_CGIF7_Pos     (24U)
6196 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
6197 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
6198 #define DMA_IFCR_CTCIF7_Pos    (25U)
6199 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
6200 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
6201 #define DMA_IFCR_CHTIF7_Pos    (26U)
6202 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
6203 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
6204 #define DMA_IFCR_CTEIF7_Pos    (27U)
6205 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
6206 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
6207 
6208 /*******************  Bit definition for DMA_CCR register  ********************/
6209 #define DMA_CCR_EN_Pos         (0U)
6210 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
6211 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
6212 #define DMA_CCR_TCIE_Pos       (1U)
6213 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
6214 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
6215 #define DMA_CCR_HTIE_Pos       (2U)
6216 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
6217 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
6218 #define DMA_CCR_TEIE_Pos       (3U)
6219 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
6220 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
6221 #define DMA_CCR_DIR_Pos        (4U)
6222 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
6223 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
6224 #define DMA_CCR_CIRC_Pos       (5U)
6225 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
6226 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
6227 #define DMA_CCR_PINC_Pos       (6U)
6228 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
6229 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
6230 #define DMA_CCR_MINC_Pos       (7U)
6231 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
6232 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
6233 
6234 #define DMA_CCR_PSIZE_Pos      (8U)
6235 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
6236 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
6237 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
6238 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
6239 
6240 #define DMA_CCR_MSIZE_Pos      (10U)
6241 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
6242 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
6243 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
6244 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
6245 
6246 #define DMA_CCR_PL_Pos         (12U)
6247 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
6248 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
6249 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
6250 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
6251 
6252 #define DMA_CCR_MEM2MEM_Pos    (14U)
6253 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
6254 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
6255 
6256 /******************  Bit definition for DMA_CNDTR register  *******************/
6257 #define DMA_CNDTR_NDT_Pos      (0U)
6258 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
6259 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
6260 
6261 /******************  Bit definition for DMA_CPAR register  ********************/
6262 #define DMA_CPAR_PA_Pos        (0U)
6263 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
6264 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
6265 
6266 /******************  Bit definition for DMA_CMAR register  ********************/
6267 #define DMA_CMAR_MA_Pos        (0U)
6268 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
6269 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
6270 
6271 
6272 /*******************  Bit definition for DMA_CSELR register  *******************/
6273 #define DMA_CSELR_C1S_Pos      (0U)
6274 #define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                    /*!< 0x0000000F */
6275 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
6276 #define DMA_CSELR_C2S_Pos      (4U)
6277 #define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                    /*!< 0x000000F0 */
6278 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
6279 #define DMA_CSELR_C3S_Pos      (8U)
6280 #define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                    /*!< 0x00000F00 */
6281 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
6282 #define DMA_CSELR_C4S_Pos      (12U)
6283 #define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                    /*!< 0x0000F000 */
6284 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
6285 #define DMA_CSELR_C5S_Pos      (16U)
6286 #define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                    /*!< 0x000F0000 */
6287 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
6288 #define DMA_CSELR_C6S_Pos      (20U)
6289 #define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                    /*!< 0x00F00000 */
6290 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
6291 #define DMA_CSELR_C7S_Pos      (24U)
6292 #define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                    /*!< 0x0F000000 */
6293 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
6294 
6295 /******************************************************************************/
6296 /*                                                                            */
6297 /*                    External Interrupt/Event Controller                     */
6298 /*                                                                            */
6299 /******************************************************************************/
6300 /*******************  Bit definition for EXTI_IMR1 register  ******************/
6301 #define EXTI_IMR1_IM0_Pos        (0U)
6302 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
6303 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
6304 #define EXTI_IMR1_IM1_Pos        (1U)
6305 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
6306 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
6307 #define EXTI_IMR1_IM2_Pos        (2U)
6308 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
6309 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
6310 #define EXTI_IMR1_IM3_Pos        (3U)
6311 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
6312 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
6313 #define EXTI_IMR1_IM4_Pos        (4U)
6314 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
6315 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
6316 #define EXTI_IMR1_IM5_Pos        (5U)
6317 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
6318 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
6319 #define EXTI_IMR1_IM6_Pos        (6U)
6320 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
6321 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
6322 #define EXTI_IMR1_IM7_Pos        (7U)
6323 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
6324 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
6325 #define EXTI_IMR1_IM8_Pos        (8U)
6326 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
6327 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
6328 #define EXTI_IMR1_IM9_Pos        (9U)
6329 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
6330 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
6331 #define EXTI_IMR1_IM10_Pos       (10U)
6332 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
6333 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
6334 #define EXTI_IMR1_IM11_Pos       (11U)
6335 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
6336 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
6337 #define EXTI_IMR1_IM12_Pos       (12U)
6338 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
6339 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
6340 #define EXTI_IMR1_IM13_Pos       (13U)
6341 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
6342 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
6343 #define EXTI_IMR1_IM14_Pos       (14U)
6344 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
6345 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
6346 #define EXTI_IMR1_IM15_Pos       (15U)
6347 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
6348 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
6349 #define EXTI_IMR1_IM16_Pos       (16U)
6350 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
6351 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
6352 #define EXTI_IMR1_IM17_Pos       (17U)
6353 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
6354 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
6355 #define EXTI_IMR1_IM18_Pos       (18U)
6356 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
6357 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
6358 #define EXTI_IMR1_IM19_Pos       (19U)
6359 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
6360 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
6361 #define EXTI_IMR1_IM20_Pos       (20U)
6362 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
6363 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
6364 #define EXTI_IMR1_IM21_Pos       (21U)
6365 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
6366 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
6367 #define EXTI_IMR1_IM22_Pos       (22U)
6368 #define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
6369 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
6370 #define EXTI_IMR1_IM23_Pos       (23U)
6371 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
6372 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
6373 #define EXTI_IMR1_IM24_Pos       (24U)
6374 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
6375 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
6376 #define EXTI_IMR1_IM25_Pos       (25U)
6377 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
6378 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
6379 #define EXTI_IMR1_IM26_Pos       (26U)
6380 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
6381 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
6382 #define EXTI_IMR1_IM27_Pos       (27U)
6383 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
6384 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
6385 #define EXTI_IMR1_IM28_Pos       (28U)
6386 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
6387 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
6388 #define EXTI_IMR1_IM31_Pos       (31U)
6389 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
6390 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
6391 #define EXTI_IMR1_IM_Pos         (0U)
6392 #define EXTI_IMR1_IM_Msk         (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0x9FFFFFFF */
6393 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
6394 
6395 /*******************  Bit definition for EXTI_EMR1 register  ******************/
6396 #define EXTI_EMR1_EM0_Pos        (0U)
6397 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
6398 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
6399 #define EXTI_EMR1_EM1_Pos        (1U)
6400 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
6401 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
6402 #define EXTI_EMR1_EM2_Pos        (2U)
6403 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
6404 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
6405 #define EXTI_EMR1_EM3_Pos        (3U)
6406 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
6407 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
6408 #define EXTI_EMR1_EM4_Pos        (4U)
6409 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
6410 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
6411 #define EXTI_EMR1_EM5_Pos        (5U)
6412 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
6413 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
6414 #define EXTI_EMR1_EM6_Pos        (6U)
6415 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
6416 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
6417 #define EXTI_EMR1_EM7_Pos        (7U)
6418 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
6419 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
6420 #define EXTI_EMR1_EM8_Pos        (8U)
6421 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
6422 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
6423 #define EXTI_EMR1_EM9_Pos        (9U)
6424 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
6425 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
6426 #define EXTI_EMR1_EM10_Pos       (10U)
6427 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
6428 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
6429 #define EXTI_EMR1_EM11_Pos       (11U)
6430 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
6431 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
6432 #define EXTI_EMR1_EM12_Pos       (12U)
6433 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
6434 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
6435 #define EXTI_EMR1_EM13_Pos       (13U)
6436 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
6437 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
6438 #define EXTI_EMR1_EM14_Pos       (14U)
6439 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
6440 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
6441 #define EXTI_EMR1_EM15_Pos       (15U)
6442 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
6443 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
6444 #define EXTI_EMR1_EM16_Pos       (16U)
6445 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
6446 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
6447 #define EXTI_EMR1_EM17_Pos       (17U)
6448 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
6449 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
6450 #define EXTI_EMR1_EM18_Pos       (18U)
6451 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
6452 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
6453 #define EXTI_EMR1_EM19_Pos       (19U)
6454 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
6455 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
6456 #define EXTI_EMR1_EM20_Pos       (20U)
6457 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
6458 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
6459 #define EXTI_EMR1_EM21_Pos       (21U)
6460 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
6461 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
6462 #define EXTI_EMR1_EM22_Pos       (22U)
6463 #define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
6464 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
6465 #define EXTI_EMR1_EM23_Pos       (23U)
6466 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
6467 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
6468 #define EXTI_EMR1_EM24_Pos       (24U)
6469 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
6470 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
6471 #define EXTI_EMR1_EM25_Pos       (25U)
6472 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
6473 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
6474 #define EXTI_EMR1_EM26_Pos       (26U)
6475 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
6476 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
6477 #define EXTI_EMR1_EM27_Pos       (27U)
6478 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
6479 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
6480 #define EXTI_EMR1_EM28_Pos       (28U)
6481 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
6482 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
6483 #define EXTI_EMR1_EM31_Pos       (31U)
6484 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
6485 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
6486 
6487 /******************  Bit definition for EXTI_RTSR1 register  ******************/
6488 #define EXTI_RTSR1_RT0_Pos       (0U)
6489 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
6490 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6491 #define EXTI_RTSR1_RT1_Pos       (1U)
6492 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
6493 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6494 #define EXTI_RTSR1_RT2_Pos       (2U)
6495 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
6496 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6497 #define EXTI_RTSR1_RT3_Pos       (3U)
6498 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
6499 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6500 #define EXTI_RTSR1_RT4_Pos       (4U)
6501 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
6502 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6503 #define EXTI_RTSR1_RT5_Pos       (5U)
6504 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
6505 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6506 #define EXTI_RTSR1_RT6_Pos       (6U)
6507 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
6508 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6509 #define EXTI_RTSR1_RT7_Pos       (7U)
6510 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
6511 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6512 #define EXTI_RTSR1_RT8_Pos       (8U)
6513 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
6514 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6515 #define EXTI_RTSR1_RT9_Pos       (9U)
6516 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
6517 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6518 #define EXTI_RTSR1_RT10_Pos      (10U)
6519 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
6520 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6521 #define EXTI_RTSR1_RT11_Pos      (11U)
6522 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
6523 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6524 #define EXTI_RTSR1_RT12_Pos      (12U)
6525 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
6526 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6527 #define EXTI_RTSR1_RT13_Pos      (13U)
6528 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
6529 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6530 #define EXTI_RTSR1_RT14_Pos      (14U)
6531 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
6532 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6533 #define EXTI_RTSR1_RT15_Pos      (15U)
6534 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
6535 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6536 #define EXTI_RTSR1_RT16_Pos      (16U)
6537 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
6538 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6539 #define EXTI_RTSR1_RT18_Pos      (18U)
6540 #define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */
6541 #define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
6542 #define EXTI_RTSR1_RT19_Pos      (19U)
6543 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
6544 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6545 #define EXTI_RTSR1_RT20_Pos      (20U)
6546 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
6547 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6548 #define EXTI_RTSR1_RT21_Pos      (21U)
6549 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
6550 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6551 #define EXTI_RTSR1_RT22_Pos      (22U)
6552 #define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
6553 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6554 
6555 /******************  Bit definition for EXTI_FTSR1 register  ******************/
6556 #define EXTI_FTSR1_FT0_Pos       (0U)
6557 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
6558 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6559 #define EXTI_FTSR1_FT1_Pos       (1U)
6560 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
6561 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6562 #define EXTI_FTSR1_FT2_Pos       (2U)
6563 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
6564 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6565 #define EXTI_FTSR1_FT3_Pos       (3U)
6566 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
6567 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6568 #define EXTI_FTSR1_FT4_Pos       (4U)
6569 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
6570 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6571 #define EXTI_FTSR1_FT5_Pos       (5U)
6572 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
6573 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6574 #define EXTI_FTSR1_FT6_Pos       (6U)
6575 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
6576 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6577 #define EXTI_FTSR1_FT7_Pos       (7U)
6578 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
6579 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6580 #define EXTI_FTSR1_FT8_Pos       (8U)
6581 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
6582 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6583 #define EXTI_FTSR1_FT9_Pos       (9U)
6584 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
6585 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6586 #define EXTI_FTSR1_FT10_Pos      (10U)
6587 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
6588 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6589 #define EXTI_FTSR1_FT11_Pos      (11U)
6590 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
6591 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6592 #define EXTI_FTSR1_FT12_Pos      (12U)
6593 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
6594 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6595 #define EXTI_FTSR1_FT13_Pos      (13U)
6596 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
6597 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6598 #define EXTI_FTSR1_FT14_Pos      (14U)
6599 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
6600 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6601 #define EXTI_FTSR1_FT15_Pos      (15U)
6602 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
6603 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6604 #define EXTI_FTSR1_FT16_Pos      (16U)
6605 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
6606 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6607 #define EXTI_FTSR1_FT18_Pos      (18U)
6608 #define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */
6609 #define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
6610 #define EXTI_FTSR1_FT19_Pos      (19U)
6611 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
6612 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6613 #define EXTI_FTSR1_FT20_Pos      (20U)
6614 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
6615 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6616 #define EXTI_FTSR1_FT21_Pos      (21U)
6617 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
6618 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6619 #define EXTI_FTSR1_FT22_Pos      (22U)
6620 #define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
6621 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6622 
6623 /******************  Bit definition for EXTI_SWIER1 register  *****************/
6624 #define EXTI_SWIER1_SWI0_Pos     (0U)
6625 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
6626 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
6627 #define EXTI_SWIER1_SWI1_Pos     (1U)
6628 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
6629 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
6630 #define EXTI_SWIER1_SWI2_Pos     (2U)
6631 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
6632 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
6633 #define EXTI_SWIER1_SWI3_Pos     (3U)
6634 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
6635 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
6636 #define EXTI_SWIER1_SWI4_Pos     (4U)
6637 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
6638 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
6639 #define EXTI_SWIER1_SWI5_Pos     (5U)
6640 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
6641 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
6642 #define EXTI_SWIER1_SWI6_Pos     (6U)
6643 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
6644 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
6645 #define EXTI_SWIER1_SWI7_Pos     (7U)
6646 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
6647 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
6648 #define EXTI_SWIER1_SWI8_Pos     (8U)
6649 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
6650 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
6651 #define EXTI_SWIER1_SWI9_Pos     (9U)
6652 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
6653 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
6654 #define EXTI_SWIER1_SWI10_Pos    (10U)
6655 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
6656 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
6657 #define EXTI_SWIER1_SWI11_Pos    (11U)
6658 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
6659 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
6660 #define EXTI_SWIER1_SWI12_Pos    (12U)
6661 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
6662 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
6663 #define EXTI_SWIER1_SWI13_Pos    (13U)
6664 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
6665 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
6666 #define EXTI_SWIER1_SWI14_Pos    (14U)
6667 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
6668 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
6669 #define EXTI_SWIER1_SWI15_Pos    (15U)
6670 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
6671 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
6672 #define EXTI_SWIER1_SWI16_Pos    (16U)
6673 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
6674 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
6675 #define EXTI_SWIER1_SWI18_Pos    (18U)
6676 #define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */
6677 #define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
6678 #define EXTI_SWIER1_SWI19_Pos    (19U)
6679 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
6680 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
6681 #define EXTI_SWIER1_SWI20_Pos    (20U)
6682 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
6683 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
6684 #define EXTI_SWIER1_SWI21_Pos    (21U)
6685 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
6686 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
6687 #define EXTI_SWIER1_SWI22_Pos    (22U)
6688 #define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
6689 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
6690 
6691 /*******************  Bit definition for EXTI_PR1 register  *******************/
6692 #define EXTI_PR1_PIF0_Pos        (0U)
6693 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
6694 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
6695 #define EXTI_PR1_PIF1_Pos        (1U)
6696 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
6697 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
6698 #define EXTI_PR1_PIF2_Pos        (2U)
6699 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
6700 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
6701 #define EXTI_PR1_PIF3_Pos        (3U)
6702 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
6703 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
6704 #define EXTI_PR1_PIF4_Pos        (4U)
6705 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
6706 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
6707 #define EXTI_PR1_PIF5_Pos        (5U)
6708 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
6709 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
6710 #define EXTI_PR1_PIF6_Pos        (6U)
6711 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
6712 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
6713 #define EXTI_PR1_PIF7_Pos        (7U)
6714 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
6715 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
6716 #define EXTI_PR1_PIF8_Pos        (8U)
6717 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
6718 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
6719 #define EXTI_PR1_PIF9_Pos        (9U)
6720 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
6721 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
6722 #define EXTI_PR1_PIF10_Pos       (10U)
6723 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
6724 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
6725 #define EXTI_PR1_PIF11_Pos       (11U)
6726 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
6727 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
6728 #define EXTI_PR1_PIF12_Pos       (12U)
6729 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
6730 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
6731 #define EXTI_PR1_PIF13_Pos       (13U)
6732 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
6733 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
6734 #define EXTI_PR1_PIF14_Pos       (14U)
6735 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
6736 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
6737 #define EXTI_PR1_PIF15_Pos       (15U)
6738 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
6739 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
6740 #define EXTI_PR1_PIF16_Pos       (16U)
6741 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
6742 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
6743 #define EXTI_PR1_PIF18_Pos       (18U)
6744 #define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */
6745 #define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
6746 #define EXTI_PR1_PIF19_Pos       (19U)
6747 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
6748 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
6749 #define EXTI_PR1_PIF20_Pos       (20U)
6750 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
6751 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
6752 #define EXTI_PR1_PIF21_Pos       (21U)
6753 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
6754 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
6755 #define EXTI_PR1_PIF22_Pos       (22U)
6756 #define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
6757 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
6758 
6759 /*******************  Bit definition for EXTI_IMR2 register  ******************/
6760 #define EXTI_IMR2_IM32_Pos       (0U)
6761 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
6762 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
6763 #define EXTI_IMR2_IM33_Pos       (1U)
6764 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
6765 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
6766 #define EXTI_IMR2_IM34_Pos       (2U)
6767 #define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
6768 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
6769 #define EXTI_IMR2_IM37_Pos       (5U)
6770 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
6771 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
6772 #define EXTI_IMR2_IM38_Pos       (6U)
6773 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
6774 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
6775 #define EXTI_IMR2_IM_Pos         (0U)
6776 #define EXTI_IMR2_IM_Msk         (0x67UL << EXTI_IMR2_IM_Pos)                  /*!< 0x00000067 */
6777 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
6778 
6779 /*******************  Bit definition for EXTI_EMR2 register  ******************/
6780 #define EXTI_EMR2_EM32_Pos       (0U)
6781 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
6782 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
6783 #define EXTI_EMR2_EM33_Pos       (1U)
6784 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
6785 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
6786 #define EXTI_EMR2_EM34_Pos       (2U)
6787 #define EXTI_EMR2_EM34_Msk       (0x1UL << EXTI_EMR2_EM34_Pos)                 /*!< 0x00000004 */
6788 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
6789 #define EXTI_EMR2_EM37_Pos       (5U)
6790 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
6791 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
6792 #define EXTI_EMR2_EM38_Pos       (6U)
6793 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
6794 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
6795 #define EXTI_EMR2_EM_Pos         (0U)
6796 #define EXTI_EMR2_EM_Msk         (0x67UL << EXTI_EMR2_EM_Pos)                  /*!< 0x00000067 */
6797 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
6798 
6799 /******************  Bit definition for EXTI_RTSR2 register  ******************/
6800 #define EXTI_RTSR2_RT37_Pos      (5U)
6801 #define EXTI_RTSR2_RT37_Msk      (0x1UL << EXTI_RTSR2_RT37_Pos)                /*!< 0x00000020 */
6802 #define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
6803 #define EXTI_RTSR2_RT38_Pos      (6U)
6804 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
6805 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
6806 
6807 /******************  Bit definition for EXTI_FTSR2 register  ******************/
6808 #define EXTI_FTSR2_FT37_Pos      (5U)
6809 #define EXTI_FTSR2_FT37_Msk      (0x1UL << EXTI_FTSR2_FT37_Pos)                /*!< 0x00000020 */
6810 #define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
6811 #define EXTI_FTSR2_FT38_Pos      (6U)
6812 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
6813 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
6814 
6815 /******************  Bit definition for EXTI_SWIER2 register  *****************/
6816 #define EXTI_SWIER2_SWI37_Pos    (5U)
6817 #define EXTI_SWIER2_SWI37_Msk    (0x1UL << EXTI_SWIER2_SWI37_Pos)              /*!< 0x00000020 */
6818 #define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
6819 #define EXTI_SWIER2_SWI38_Pos    (6U)
6820 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
6821 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
6822 
6823 /*******************  Bit definition for EXTI_PR2 register  *******************/
6824 #define EXTI_PR2_PIF37_Pos       (5U)
6825 #define EXTI_PR2_PIF37_Msk       (0x1UL << EXTI_PR2_PIF37_Pos)                 /*!< 0x00000020 */
6826 #define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
6827 #define EXTI_PR2_PIF38_Pos       (6U)
6828 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
6829 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
6830 
6831 
6832 /******************************************************************************/
6833 /*                                                                            */
6834 /*                                    FLASH                                   */
6835 /*                                                                            */
6836 /******************************************************************************/
6837 /*******************  Bits definition for FLASH_ACR register  *****************/
6838 #define FLASH_ACR_LATENCY_Pos             (0U)
6839 #define FLASH_ACR_LATENCY_Msk             (0x7UL << FLASH_ACR_LATENCY_Pos)     /*!< 0x00000007 */
6840 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
6841 #define FLASH_ACR_LATENCY_0WS             (0x00000000UL)
6842 #define FLASH_ACR_LATENCY_1WS             (0x00000001UL)
6843 #define FLASH_ACR_LATENCY_2WS             (0x00000002UL)
6844 #define FLASH_ACR_LATENCY_3WS             (0x00000003UL)
6845 #define FLASH_ACR_LATENCY_4WS             (0x00000004UL)
6846 #define FLASH_ACR_PRFTEN_Pos              (8U)
6847 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
6848 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
6849 #define FLASH_ACR_ICEN_Pos                (9U)
6850 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
6851 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
6852 #define FLASH_ACR_DCEN_Pos                (10U)
6853 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
6854 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
6855 #define FLASH_ACR_ICRST_Pos               (11U)
6856 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
6857 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
6858 #define FLASH_ACR_DCRST_Pos               (12U)
6859 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
6860 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
6861 #define FLASH_ACR_RUN_PD_Pos              (13U)
6862 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
6863 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
6864 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
6865 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
6866 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
6867 
6868 /*******************  Bits definition for FLASH_SR register  ******************/
6869 #define FLASH_SR_EOP_Pos                  (0U)
6870 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
6871 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
6872 #define FLASH_SR_OPERR_Pos                (1U)
6873 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
6874 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
6875 #define FLASH_SR_PROGERR_Pos              (3U)
6876 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
6877 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
6878 #define FLASH_SR_WRPERR_Pos               (4U)
6879 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
6880 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
6881 #define FLASH_SR_PGAERR_Pos               (5U)
6882 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
6883 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
6884 #define FLASH_SR_SIZERR_Pos               (6U)
6885 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
6886 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
6887 #define FLASH_SR_PGSERR_Pos               (7U)
6888 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
6889 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
6890 #define FLASH_SR_MISERR_Pos               (8U)
6891 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
6892 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
6893 #define FLASH_SR_FASTERR_Pos              (9U)
6894 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
6895 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
6896 #define FLASH_SR_RDERR_Pos                (14U)
6897 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
6898 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
6899 #define FLASH_SR_OPTVERR_Pos              (15U)
6900 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
6901 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
6902 #define FLASH_SR_BSY_Pos                  (16U)
6903 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
6904 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
6905 #define FLASH_SR_PEMPTY_Pos               (17U)
6906 #define FLASH_SR_PEMPTY_Msk               (0x1UL << FLASH_SR_PEMPTY_Pos)       /*!< 0x00020000 */
6907 #define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk
6908 
6909 /*******************  Bits definition for FLASH_CR register  ******************/
6910 #define FLASH_CR_PG_Pos                   (0U)
6911 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
6912 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
6913 #define FLASH_CR_PER_Pos                  (1U)
6914 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
6915 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
6916 #define FLASH_CR_MER1_Pos                 (2U)
6917 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
6918 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
6919 #define FLASH_CR_PNB_Pos                  (3U)
6920 #define FLASH_CR_PNB_Msk                  (0x7FUL << FLASH_CR_PNB_Pos)         /*!< 0x000003F8 */
6921 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
6922 #define FLASH_CR_STRT_Pos                 (16U)
6923 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
6924 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
6925 #define FLASH_CR_OPTSTRT_Pos              (17U)
6926 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
6927 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
6928 #define FLASH_CR_FSTPG_Pos                (18U)
6929 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
6930 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
6931 #define FLASH_CR_EOPIE_Pos                (24U)
6932 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
6933 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
6934 #define FLASH_CR_ERRIE_Pos                (25U)
6935 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
6936 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
6937 #define FLASH_CR_RDERRIE_Pos              (26U)
6938 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
6939 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
6940 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
6941 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
6942 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
6943 #define FLASH_CR_OPTLOCK_Pos              (30U)
6944 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
6945 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
6946 #define FLASH_CR_LOCK_Pos                 (31U)
6947 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
6948 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
6949 
6950 /*******************  Bits definition for FLASH_ECCR register  ***************/
6951 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
6952 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
6953 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
6954 #define FLASH_ECCR_SYSF_ECC_Pos           (20U)
6955 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00100000 */
6956 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
6957 #define FLASH_ECCR_ECCIE_Pos              (24U)
6958 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
6959 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
6960 #define FLASH_ECCR_ECCC_Pos               (30U)
6961 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
6962 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
6963 #define FLASH_ECCR_ECCD_Pos               (31U)
6964 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
6965 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
6966 
6967 /*******************  Bits definition for FLASH_OPTR register  ***************/
6968 #define FLASH_OPTR_RDP_Pos                (0U)
6969 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
6970 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
6971 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
6972 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
6973 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
6974 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
6975 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
6976 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
6977 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
6978 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
6979 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
6980 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
6981 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
6982 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
6983 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
6984 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
6985 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
6986 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
6987 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
6988 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
6989 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
6990 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
6991 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
6992 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
6993 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
6994 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
6995 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
6996 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
6997 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
6998 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
6999 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
7000 #define FLASH_OPTR_nBOOT1_Pos             (23U)
7001 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
7002 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
7003 #define FLASH_OPTR_SRAM2_PE_Pos           (24U)
7004 #define FLASH_OPTR_SRAM2_PE_Msk           (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)   /*!< 0x01000000 */
7005 #define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk
7006 #define FLASH_OPTR_SRAM2_RST_Pos          (25U)
7007 #define FLASH_OPTR_SRAM2_RST_Msk          (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)  /*!< 0x02000000 */
7008 #define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk
7009 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
7010 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
7011 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
7012 #define FLASH_OPTR_nBOOT0_Pos             (27U)
7013 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
7014 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
7015 
7016 /******************  Bits definition for FLASH_PCROP1SR register  **********/
7017 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
7018 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00007FFF */
7019 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
7020 
7021 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
7022 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
7023 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00007FFF */
7024 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
7025 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
7026 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
7027 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
7028 
7029 /******************  Bits definition for FLASH_WRP1AR register  ***************/
7030 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
7031 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000007F */
7032 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
7033 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
7034 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)  /*!< 0x007F0000 */
7035 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
7036 
7037 /******************  Bits definition for FLASH_WRPB1R register  ***************/
7038 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
7039 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000007F */
7040 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
7041 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
7042 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)  /*!< 0x007F0000 */
7043 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
7044 
7045 
7046 
7047 
7048 /******************************************************************************/
7049 /*                                                                            */
7050 /*                       General Purpose IOs (GPIO)                           */
7051 /*                                                                            */
7052 /******************************************************************************/
7053 /******************  Bits definition for GPIO_MODER register  *****************/
7054 #define GPIO_MODER_MODE0_Pos           (0U)
7055 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
7056 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
7057 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
7058 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
7059 #define GPIO_MODER_MODE1_Pos           (2U)
7060 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
7061 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
7062 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
7063 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
7064 #define GPIO_MODER_MODE2_Pos           (4U)
7065 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
7066 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
7067 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
7068 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
7069 #define GPIO_MODER_MODE3_Pos           (6U)
7070 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
7071 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
7072 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
7073 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
7074 #define GPIO_MODER_MODE4_Pos           (8U)
7075 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
7076 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
7077 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
7078 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
7079 #define GPIO_MODER_MODE5_Pos           (10U)
7080 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
7081 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
7082 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
7083 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
7084 #define GPIO_MODER_MODE6_Pos           (12U)
7085 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
7086 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
7087 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
7088 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
7089 #define GPIO_MODER_MODE7_Pos           (14U)
7090 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
7091 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
7092 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
7093 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
7094 #define GPIO_MODER_MODE8_Pos           (16U)
7095 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
7096 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
7097 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
7098 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
7099 #define GPIO_MODER_MODE9_Pos           (18U)
7100 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
7101 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
7102 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
7103 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
7104 #define GPIO_MODER_MODE10_Pos          (20U)
7105 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
7106 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
7107 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
7108 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
7109 #define GPIO_MODER_MODE11_Pos          (22U)
7110 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
7111 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
7112 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
7113 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
7114 #define GPIO_MODER_MODE12_Pos          (24U)
7115 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
7116 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
7117 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
7118 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
7119 #define GPIO_MODER_MODE13_Pos          (26U)
7120 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
7121 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
7122 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
7123 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
7124 #define GPIO_MODER_MODE14_Pos          (28U)
7125 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
7126 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
7127 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
7128 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
7129 #define GPIO_MODER_MODE15_Pos          (30U)
7130 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
7131 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
7132 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
7133 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
7134 
7135 /* Legacy defines */
7136 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
7137 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
7138 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
7139 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
7140 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
7141 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
7142 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
7143 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
7144 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
7145 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
7146 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
7147 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
7148 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
7149 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
7150 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
7151 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
7152 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
7153 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
7154 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
7155 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
7156 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
7157 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
7158 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
7159 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
7160 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
7161 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
7162 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
7163 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
7164 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
7165 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
7166 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
7167 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
7168 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
7169 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
7170 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
7171 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
7172 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
7173 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
7174 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
7175 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
7176 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
7177 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
7178 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
7179 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
7180 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
7181 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
7182 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
7183 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
7184 
7185 /******************  Bits definition for GPIO_OTYPER register  ****************/
7186 #define GPIO_OTYPER_OT0_Pos            (0U)
7187 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
7188 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
7189 #define GPIO_OTYPER_OT1_Pos            (1U)
7190 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
7191 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
7192 #define GPIO_OTYPER_OT2_Pos            (2U)
7193 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
7194 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
7195 #define GPIO_OTYPER_OT3_Pos            (3U)
7196 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
7197 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
7198 #define GPIO_OTYPER_OT4_Pos            (4U)
7199 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
7200 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
7201 #define GPIO_OTYPER_OT5_Pos            (5U)
7202 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
7203 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
7204 #define GPIO_OTYPER_OT6_Pos            (6U)
7205 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
7206 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
7207 #define GPIO_OTYPER_OT7_Pos            (7U)
7208 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
7209 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
7210 #define GPIO_OTYPER_OT8_Pos            (8U)
7211 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
7212 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
7213 #define GPIO_OTYPER_OT9_Pos            (9U)
7214 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
7215 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
7216 #define GPIO_OTYPER_OT10_Pos           (10U)
7217 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
7218 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
7219 #define GPIO_OTYPER_OT11_Pos           (11U)
7220 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
7221 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
7222 #define GPIO_OTYPER_OT12_Pos           (12U)
7223 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
7224 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
7225 #define GPIO_OTYPER_OT13_Pos           (13U)
7226 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
7227 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
7228 #define GPIO_OTYPER_OT14_Pos           (14U)
7229 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
7230 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
7231 #define GPIO_OTYPER_OT15_Pos           (15U)
7232 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
7233 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
7234 
7235 /* Legacy defines */
7236 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
7237 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
7238 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
7239 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
7240 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
7241 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
7242 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
7243 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
7244 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
7245 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
7246 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
7247 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
7248 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
7249 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
7250 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
7251 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
7252 
7253 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
7254 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
7255 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
7256 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
7257 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
7258 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
7259 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
7260 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
7261 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
7262 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
7263 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
7264 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
7265 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
7266 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
7267 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
7268 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
7269 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
7270 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
7271 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
7272 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
7273 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
7274 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
7275 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
7276 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
7277 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
7278 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
7279 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
7280 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
7281 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
7282 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
7283 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
7284 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
7285 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
7286 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
7287 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
7288 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
7289 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
7290 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
7291 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
7292 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
7293 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
7294 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
7295 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
7296 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
7297 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
7298 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
7299 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
7300 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
7301 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
7302 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
7303 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
7304 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
7305 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
7306 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
7307 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
7308 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
7309 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
7310 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
7311 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
7312 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
7313 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
7314 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
7315 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
7316 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
7317 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
7318 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
7319 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
7320 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
7321 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
7322 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
7323 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
7324 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
7325 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
7326 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
7327 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
7328 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
7329 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
7330 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
7331 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
7332 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
7333 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
7334 
7335 /* Legacy defines */
7336 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
7337 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
7338 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
7339 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
7340 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
7341 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
7342 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
7343 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
7344 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
7345 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
7346 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
7347 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
7348 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
7349 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
7350 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
7351 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
7352 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
7353 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
7354 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
7355 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
7356 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
7357 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
7358 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
7359 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
7360 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
7361 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
7362 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
7363 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
7364 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
7365 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
7366 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
7367 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
7368 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
7369 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
7370 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
7371 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
7372 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
7373 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
7374 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
7375 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
7376 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
7377 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
7378 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
7379 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
7380 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
7381 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
7382 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
7383 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
7384 
7385 /******************  Bits definition for GPIO_PUPDR register  *****************/
7386 #define GPIO_PUPDR_PUPD0_Pos           (0U)
7387 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
7388 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
7389 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
7390 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
7391 #define GPIO_PUPDR_PUPD1_Pos           (2U)
7392 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
7393 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
7394 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
7395 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
7396 #define GPIO_PUPDR_PUPD2_Pos           (4U)
7397 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
7398 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
7399 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
7400 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
7401 #define GPIO_PUPDR_PUPD3_Pos           (6U)
7402 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
7403 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
7404 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
7405 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
7406 #define GPIO_PUPDR_PUPD4_Pos           (8U)
7407 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
7408 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
7409 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
7410 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
7411 #define GPIO_PUPDR_PUPD5_Pos           (10U)
7412 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
7413 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
7414 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
7415 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
7416 #define GPIO_PUPDR_PUPD6_Pos           (12U)
7417 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
7418 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
7419 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
7420 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
7421 #define GPIO_PUPDR_PUPD7_Pos           (14U)
7422 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
7423 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
7424 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
7425 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
7426 #define GPIO_PUPDR_PUPD8_Pos           (16U)
7427 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
7428 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
7429 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
7430 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
7431 #define GPIO_PUPDR_PUPD9_Pos           (18U)
7432 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
7433 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
7434 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
7435 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
7436 #define GPIO_PUPDR_PUPD10_Pos          (20U)
7437 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
7438 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
7439 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
7440 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
7441 #define GPIO_PUPDR_PUPD11_Pos          (22U)
7442 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
7443 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
7444 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
7445 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
7446 #define GPIO_PUPDR_PUPD12_Pos          (24U)
7447 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
7448 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
7449 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
7450 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
7451 #define GPIO_PUPDR_PUPD13_Pos          (26U)
7452 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
7453 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
7454 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
7455 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
7456 #define GPIO_PUPDR_PUPD14_Pos          (28U)
7457 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
7458 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
7459 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
7460 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
7461 #define GPIO_PUPDR_PUPD15_Pos          (30U)
7462 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
7463 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
7464 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
7465 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
7466 
7467 /* Legacy defines */
7468 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
7469 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
7470 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
7471 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
7472 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
7473 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
7474 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
7475 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
7476 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
7477 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
7478 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
7479 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
7480 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
7481 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
7482 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
7483 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
7484 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
7485 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
7486 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
7487 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
7488 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
7489 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
7490 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
7491 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
7492 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
7493 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
7494 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
7495 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
7496 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
7497 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
7498 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
7499 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
7500 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
7501 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
7502 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
7503 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
7504 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
7505 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
7506 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
7507 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
7508 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
7509 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
7510 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
7511 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
7512 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
7513 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
7514 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
7515 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
7516 
7517 /******************  Bits definition for GPIO_IDR register  *******************/
7518 #define GPIO_IDR_ID0_Pos               (0U)
7519 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
7520 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
7521 #define GPIO_IDR_ID1_Pos               (1U)
7522 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
7523 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
7524 #define GPIO_IDR_ID2_Pos               (2U)
7525 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
7526 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
7527 #define GPIO_IDR_ID3_Pos               (3U)
7528 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
7529 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
7530 #define GPIO_IDR_ID4_Pos               (4U)
7531 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
7532 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
7533 #define GPIO_IDR_ID5_Pos               (5U)
7534 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
7535 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
7536 #define GPIO_IDR_ID6_Pos               (6U)
7537 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
7538 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
7539 #define GPIO_IDR_ID7_Pos               (7U)
7540 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
7541 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
7542 #define GPIO_IDR_ID8_Pos               (8U)
7543 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
7544 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
7545 #define GPIO_IDR_ID9_Pos               (9U)
7546 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
7547 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
7548 #define GPIO_IDR_ID10_Pos              (10U)
7549 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
7550 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
7551 #define GPIO_IDR_ID11_Pos              (11U)
7552 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
7553 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
7554 #define GPIO_IDR_ID12_Pos              (12U)
7555 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
7556 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
7557 #define GPIO_IDR_ID13_Pos              (13U)
7558 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
7559 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
7560 #define GPIO_IDR_ID14_Pos              (14U)
7561 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
7562 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
7563 #define GPIO_IDR_ID15_Pos              (15U)
7564 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
7565 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
7566 
7567 /* Legacy defines */
7568 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
7569 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
7570 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
7571 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
7572 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
7573 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
7574 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
7575 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
7576 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
7577 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
7578 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
7579 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
7580 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
7581 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
7582 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
7583 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
7584 
7585 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
7586 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
7587 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
7588 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
7589 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
7590 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
7591 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
7592 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
7593 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
7594 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
7595 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
7596 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
7597 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
7598 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
7599 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
7600 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
7601 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
7602 
7603 /******************  Bits definition for GPIO_ODR register  *******************/
7604 #define GPIO_ODR_OD0_Pos               (0U)
7605 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
7606 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
7607 #define GPIO_ODR_OD1_Pos               (1U)
7608 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
7609 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
7610 #define GPIO_ODR_OD2_Pos               (2U)
7611 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
7612 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
7613 #define GPIO_ODR_OD3_Pos               (3U)
7614 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
7615 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
7616 #define GPIO_ODR_OD4_Pos               (4U)
7617 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
7618 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
7619 #define GPIO_ODR_OD5_Pos               (5U)
7620 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
7621 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
7622 #define GPIO_ODR_OD6_Pos               (6U)
7623 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
7624 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
7625 #define GPIO_ODR_OD7_Pos               (7U)
7626 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
7627 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
7628 #define GPIO_ODR_OD8_Pos               (8U)
7629 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
7630 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
7631 #define GPIO_ODR_OD9_Pos               (9U)
7632 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
7633 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
7634 #define GPIO_ODR_OD10_Pos              (10U)
7635 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
7636 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
7637 #define GPIO_ODR_OD11_Pos              (11U)
7638 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
7639 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
7640 #define GPIO_ODR_OD12_Pos              (12U)
7641 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
7642 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
7643 #define GPIO_ODR_OD13_Pos              (13U)
7644 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
7645 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
7646 #define GPIO_ODR_OD14_Pos              (14U)
7647 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
7648 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
7649 #define GPIO_ODR_OD15_Pos              (15U)
7650 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
7651 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
7652 
7653 /* Legacy defines */
7654 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
7655 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
7656 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
7657 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
7658 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
7659 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
7660 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
7661 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
7662 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
7663 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
7664 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
7665 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
7666 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
7667 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
7668 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
7669 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
7670 
7671 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
7672 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
7673 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
7674 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
7675 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
7676 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
7677 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
7678 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
7679 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
7680 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
7681 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
7682 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
7683 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
7684 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
7685 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
7686 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
7687 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
7688 
7689 /******************  Bits definition for GPIO_BSRR register  ******************/
7690 #define GPIO_BSRR_BS0_Pos              (0U)
7691 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
7692 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
7693 #define GPIO_BSRR_BS1_Pos              (1U)
7694 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
7695 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
7696 #define GPIO_BSRR_BS2_Pos              (2U)
7697 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
7698 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
7699 #define GPIO_BSRR_BS3_Pos              (3U)
7700 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
7701 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
7702 #define GPIO_BSRR_BS4_Pos              (4U)
7703 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
7704 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
7705 #define GPIO_BSRR_BS5_Pos              (5U)
7706 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
7707 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
7708 #define GPIO_BSRR_BS6_Pos              (6U)
7709 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
7710 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
7711 #define GPIO_BSRR_BS7_Pos              (7U)
7712 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
7713 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
7714 #define GPIO_BSRR_BS8_Pos              (8U)
7715 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
7716 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
7717 #define GPIO_BSRR_BS9_Pos              (9U)
7718 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
7719 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
7720 #define GPIO_BSRR_BS10_Pos             (10U)
7721 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
7722 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
7723 #define GPIO_BSRR_BS11_Pos             (11U)
7724 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
7725 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
7726 #define GPIO_BSRR_BS12_Pos             (12U)
7727 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
7728 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
7729 #define GPIO_BSRR_BS13_Pos             (13U)
7730 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
7731 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
7732 #define GPIO_BSRR_BS14_Pos             (14U)
7733 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
7734 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
7735 #define GPIO_BSRR_BS15_Pos             (15U)
7736 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
7737 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
7738 #define GPIO_BSRR_BR0_Pos              (16U)
7739 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
7740 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
7741 #define GPIO_BSRR_BR1_Pos              (17U)
7742 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
7743 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
7744 #define GPIO_BSRR_BR2_Pos              (18U)
7745 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
7746 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
7747 #define GPIO_BSRR_BR3_Pos              (19U)
7748 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
7749 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
7750 #define GPIO_BSRR_BR4_Pos              (20U)
7751 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
7752 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
7753 #define GPIO_BSRR_BR5_Pos              (21U)
7754 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
7755 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
7756 #define GPIO_BSRR_BR6_Pos              (22U)
7757 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
7758 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
7759 #define GPIO_BSRR_BR7_Pos              (23U)
7760 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
7761 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
7762 #define GPIO_BSRR_BR8_Pos              (24U)
7763 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
7764 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
7765 #define GPIO_BSRR_BR9_Pos              (25U)
7766 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
7767 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
7768 #define GPIO_BSRR_BR10_Pos             (26U)
7769 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
7770 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
7771 #define GPIO_BSRR_BR11_Pos             (27U)
7772 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
7773 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
7774 #define GPIO_BSRR_BR12_Pos             (28U)
7775 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
7776 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
7777 #define GPIO_BSRR_BR13_Pos             (29U)
7778 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
7779 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
7780 #define GPIO_BSRR_BR14_Pos             (30U)
7781 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
7782 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
7783 #define GPIO_BSRR_BR15_Pos             (31U)
7784 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
7785 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
7786 
7787 /* Legacy defines */
7788 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
7789 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
7790 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
7791 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
7792 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
7793 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
7794 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
7795 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
7796 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
7797 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
7798 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
7799 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
7800 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
7801 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
7802 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
7803 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
7804 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
7805 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
7806 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
7807 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
7808 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
7809 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
7810 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
7811 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
7812 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
7813 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
7814 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
7815 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
7816 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
7817 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
7818 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
7819 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
7820 
7821 /****************** Bit definition for GPIO_LCKR register *********************/
7822 #define GPIO_LCKR_LCK0_Pos             (0U)
7823 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
7824 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
7825 #define GPIO_LCKR_LCK1_Pos             (1U)
7826 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
7827 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
7828 #define GPIO_LCKR_LCK2_Pos             (2U)
7829 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
7830 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
7831 #define GPIO_LCKR_LCK3_Pos             (3U)
7832 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
7833 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
7834 #define GPIO_LCKR_LCK4_Pos             (4U)
7835 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
7836 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
7837 #define GPIO_LCKR_LCK5_Pos             (5U)
7838 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
7839 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
7840 #define GPIO_LCKR_LCK6_Pos             (6U)
7841 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
7842 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
7843 #define GPIO_LCKR_LCK7_Pos             (7U)
7844 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
7845 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
7846 #define GPIO_LCKR_LCK8_Pos             (8U)
7847 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
7848 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
7849 #define GPIO_LCKR_LCK9_Pos             (9U)
7850 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
7851 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
7852 #define GPIO_LCKR_LCK10_Pos            (10U)
7853 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
7854 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
7855 #define GPIO_LCKR_LCK11_Pos            (11U)
7856 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
7857 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
7858 #define GPIO_LCKR_LCK12_Pos            (12U)
7859 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
7860 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
7861 #define GPIO_LCKR_LCK13_Pos            (13U)
7862 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
7863 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
7864 #define GPIO_LCKR_LCK14_Pos            (14U)
7865 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
7866 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
7867 #define GPIO_LCKR_LCK15_Pos            (15U)
7868 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
7869 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
7870 #define GPIO_LCKR_LCKK_Pos             (16U)
7871 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
7872 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
7873 
7874 /****************** Bit definition for GPIO_AFRL register *********************/
7875 #define GPIO_AFRL_AFSEL0_Pos           (0U)
7876 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
7877 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
7878 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
7879 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
7880 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
7881 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
7882 #define GPIO_AFRL_AFSEL1_Pos           (4U)
7883 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
7884 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
7885 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
7886 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
7887 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
7888 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
7889 #define GPIO_AFRL_AFSEL2_Pos           (8U)
7890 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
7891 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
7892 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
7893 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
7894 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
7895 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
7896 #define GPIO_AFRL_AFSEL3_Pos           (12U)
7897 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
7898 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
7899 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
7900 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
7901 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
7902 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
7903 #define GPIO_AFRL_AFSEL4_Pos           (16U)
7904 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
7905 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
7906 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
7907 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
7908 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
7909 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
7910 #define GPIO_AFRL_AFSEL5_Pos           (20U)
7911 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
7912 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
7913 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
7914 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
7915 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
7916 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
7917 #define GPIO_AFRL_AFSEL6_Pos           (24U)
7918 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
7919 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
7920 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
7921 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
7922 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
7923 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
7924 #define GPIO_AFRL_AFSEL7_Pos           (28U)
7925 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
7926 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
7927 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
7928 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
7929 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
7930 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
7931 
7932 /* Legacy defines */
7933 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
7934 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
7935 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
7936 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
7937 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
7938 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
7939 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
7940 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
7941 
7942 /****************** Bit definition for GPIO_AFRH register *********************/
7943 #define GPIO_AFRH_AFSEL8_Pos           (0U)
7944 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
7945 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
7946 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
7947 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
7948 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
7949 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
7950 #define GPIO_AFRH_AFSEL9_Pos           (4U)
7951 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
7952 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
7953 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
7954 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
7955 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
7956 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
7957 #define GPIO_AFRH_AFSEL10_Pos          (8U)
7958 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
7959 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
7960 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
7961 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
7962 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
7963 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
7964 #define GPIO_AFRH_AFSEL11_Pos          (12U)
7965 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
7966 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
7967 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
7968 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
7969 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
7970 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
7971 #define GPIO_AFRH_AFSEL12_Pos          (16U)
7972 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
7973 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
7974 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
7975 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
7976 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
7977 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
7978 #define GPIO_AFRH_AFSEL13_Pos          (20U)
7979 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
7980 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
7981 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
7982 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
7983 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
7984 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
7985 #define GPIO_AFRH_AFSEL14_Pos          (24U)
7986 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
7987 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
7988 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
7989 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
7990 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
7991 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
7992 #define GPIO_AFRH_AFSEL15_Pos          (28U)
7993 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
7994 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
7995 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
7996 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
7997 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
7998 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
7999 
8000 /* Legacy defines */
8001 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
8002 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
8003 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
8004 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
8005 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
8006 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
8007 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
8008 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
8009 
8010 /******************  Bits definition for GPIO_BRR register  ******************/
8011 #define GPIO_BRR_BR0_Pos               (0U)
8012 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
8013 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
8014 #define GPIO_BRR_BR1_Pos               (1U)
8015 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
8016 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
8017 #define GPIO_BRR_BR2_Pos               (2U)
8018 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
8019 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
8020 #define GPIO_BRR_BR3_Pos               (3U)
8021 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
8022 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
8023 #define GPIO_BRR_BR4_Pos               (4U)
8024 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
8025 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
8026 #define GPIO_BRR_BR5_Pos               (5U)
8027 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
8028 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
8029 #define GPIO_BRR_BR6_Pos               (6U)
8030 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
8031 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
8032 #define GPIO_BRR_BR7_Pos               (7U)
8033 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
8034 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
8035 #define GPIO_BRR_BR8_Pos               (8U)
8036 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
8037 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
8038 #define GPIO_BRR_BR9_Pos               (9U)
8039 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
8040 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
8041 #define GPIO_BRR_BR10_Pos              (10U)
8042 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
8043 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
8044 #define GPIO_BRR_BR11_Pos              (11U)
8045 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
8046 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
8047 #define GPIO_BRR_BR12_Pos              (12U)
8048 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
8049 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
8050 #define GPIO_BRR_BR13_Pos              (13U)
8051 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
8052 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
8053 #define GPIO_BRR_BR14_Pos              (14U)
8054 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
8055 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
8056 #define GPIO_BRR_BR15_Pos              (15U)
8057 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
8058 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
8059 
8060 /* Legacy defines */
8061 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
8062 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
8063 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
8064 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
8065 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
8066 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
8067 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
8068 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
8069 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
8070 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
8071 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
8072 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
8073 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
8074 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
8075 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
8076 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
8077 
8078 
8079 
8080 /******************************************************************************/
8081 /*                                                                            */
8082 /*                      Inter-integrated Circuit Interface (I2C)              */
8083 /*                                                                            */
8084 /******************************************************************************/
8085 /*******************  Bit definition for I2C_CR1 register  *******************/
8086 #define I2C_CR1_PE_Pos               (0U)
8087 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
8088 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
8089 #define I2C_CR1_TXIE_Pos             (1U)
8090 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
8091 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
8092 #define I2C_CR1_RXIE_Pos             (2U)
8093 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
8094 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
8095 #define I2C_CR1_ADDRIE_Pos           (3U)
8096 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
8097 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
8098 #define I2C_CR1_NACKIE_Pos           (4U)
8099 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
8100 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
8101 #define I2C_CR1_STOPIE_Pos           (5U)
8102 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
8103 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
8104 #define I2C_CR1_TCIE_Pos             (6U)
8105 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
8106 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
8107 #define I2C_CR1_ERRIE_Pos            (7U)
8108 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
8109 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
8110 #define I2C_CR1_DNF_Pos              (8U)
8111 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
8112 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
8113 #define I2C_CR1_ANFOFF_Pos           (12U)
8114 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
8115 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
8116 #define I2C_CR1_SWRST_Pos            (13U)
8117 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
8118 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
8119 #define I2C_CR1_TXDMAEN_Pos          (14U)
8120 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
8121 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
8122 #define I2C_CR1_RXDMAEN_Pos          (15U)
8123 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
8124 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
8125 #define I2C_CR1_SBC_Pos              (16U)
8126 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
8127 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
8128 #define I2C_CR1_NOSTRETCH_Pos        (17U)
8129 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
8130 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
8131 #define I2C_CR1_WUPEN_Pos            (18U)
8132 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
8133 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
8134 #define I2C_CR1_GCEN_Pos             (19U)
8135 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
8136 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
8137 #define I2C_CR1_SMBHEN_Pos           (20U)
8138 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
8139 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
8140 #define I2C_CR1_SMBDEN_Pos           (21U)
8141 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
8142 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
8143 #define I2C_CR1_ALERTEN_Pos          (22U)
8144 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
8145 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
8146 #define I2C_CR1_PECEN_Pos            (23U)
8147 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
8148 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
8149 
8150 /******************  Bit definition for I2C_CR2 register  ********************/
8151 #define I2C_CR2_SADD_Pos             (0U)
8152 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
8153 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
8154 #define I2C_CR2_RD_WRN_Pos           (10U)
8155 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
8156 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
8157 #define I2C_CR2_ADD10_Pos            (11U)
8158 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
8159 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
8160 #define I2C_CR2_HEAD10R_Pos          (12U)
8161 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
8162 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
8163 #define I2C_CR2_START_Pos            (13U)
8164 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
8165 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
8166 #define I2C_CR2_STOP_Pos             (14U)
8167 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
8168 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
8169 #define I2C_CR2_NACK_Pos             (15U)
8170 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
8171 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
8172 #define I2C_CR2_NBYTES_Pos           (16U)
8173 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
8174 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
8175 #define I2C_CR2_RELOAD_Pos           (24U)
8176 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
8177 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
8178 #define I2C_CR2_AUTOEND_Pos          (25U)
8179 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
8180 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
8181 #define I2C_CR2_PECBYTE_Pos          (26U)
8182 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
8183 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
8184 
8185 /*******************  Bit definition for I2C_OAR1 register  ******************/
8186 #define I2C_OAR1_OA1_Pos             (0U)
8187 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
8188 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
8189 #define I2C_OAR1_OA1MODE_Pos         (10U)
8190 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
8191 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
8192 #define I2C_OAR1_OA1EN_Pos           (15U)
8193 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
8194 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
8195 
8196 /*******************  Bit definition for I2C_OAR2 register  ******************/
8197 #define I2C_OAR2_OA2_Pos             (1U)
8198 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
8199 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
8200 #define I2C_OAR2_OA2MSK_Pos          (8U)
8201 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
8202 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
8203 #define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
8204 #define I2C_OAR2_OA2MASK01_Pos       (8U)
8205 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
8206 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
8207 #define I2C_OAR2_OA2MASK02_Pos       (9U)
8208 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
8209 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
8210 #define I2C_OAR2_OA2MASK03_Pos       (8U)
8211 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
8212 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
8213 #define I2C_OAR2_OA2MASK04_Pos       (10U)
8214 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
8215 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
8216 #define I2C_OAR2_OA2MASK05_Pos       (8U)
8217 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
8218 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
8219 #define I2C_OAR2_OA2MASK06_Pos       (9U)
8220 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
8221 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
8222 #define I2C_OAR2_OA2MASK07_Pos       (8U)
8223 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
8224 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
8225 #define I2C_OAR2_OA2EN_Pos           (15U)
8226 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
8227 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
8228 
8229 /*******************  Bit definition for I2C_TIMINGR register *******************/
8230 #define I2C_TIMINGR_SCLL_Pos         (0U)
8231 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
8232 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
8233 #define I2C_TIMINGR_SCLH_Pos         (8U)
8234 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
8235 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
8236 #define I2C_TIMINGR_SDADEL_Pos       (16U)
8237 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
8238 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
8239 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
8240 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
8241 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
8242 #define I2C_TIMINGR_PRESC_Pos        (28U)
8243 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
8244 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
8245 
8246 /******************* Bit definition for I2C_TIMEOUTR register *******************/
8247 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
8248 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
8249 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
8250 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
8251 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
8252 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
8253 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
8254 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
8255 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
8256 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
8257 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
8258 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
8259 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
8260 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
8261 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
8262 
8263 /******************  Bit definition for I2C_ISR register  *********************/
8264 #define I2C_ISR_TXE_Pos              (0U)
8265 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
8266 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
8267 #define I2C_ISR_TXIS_Pos             (1U)
8268 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
8269 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
8270 #define I2C_ISR_RXNE_Pos             (2U)
8271 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
8272 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
8273 #define I2C_ISR_ADDR_Pos             (3U)
8274 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
8275 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
8276 #define I2C_ISR_NACKF_Pos            (4U)
8277 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
8278 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
8279 #define I2C_ISR_STOPF_Pos            (5U)
8280 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
8281 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
8282 #define I2C_ISR_TC_Pos               (6U)
8283 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
8284 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
8285 #define I2C_ISR_TCR_Pos              (7U)
8286 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
8287 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
8288 #define I2C_ISR_BERR_Pos             (8U)
8289 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
8290 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
8291 #define I2C_ISR_ARLO_Pos             (9U)
8292 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
8293 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
8294 #define I2C_ISR_OVR_Pos              (10U)
8295 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
8296 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
8297 #define I2C_ISR_PECERR_Pos           (11U)
8298 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
8299 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
8300 #define I2C_ISR_TIMEOUT_Pos          (12U)
8301 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
8302 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
8303 #define I2C_ISR_ALERT_Pos            (13U)
8304 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
8305 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
8306 #define I2C_ISR_BUSY_Pos             (15U)
8307 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
8308 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
8309 #define I2C_ISR_DIR_Pos              (16U)
8310 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
8311 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
8312 #define I2C_ISR_ADDCODE_Pos          (17U)
8313 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
8314 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
8315 
8316 /******************  Bit definition for I2C_ICR register  *********************/
8317 #define I2C_ICR_ADDRCF_Pos           (3U)
8318 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
8319 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
8320 #define I2C_ICR_NACKCF_Pos           (4U)
8321 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
8322 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
8323 #define I2C_ICR_STOPCF_Pos           (5U)
8324 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
8325 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
8326 #define I2C_ICR_BERRCF_Pos           (8U)
8327 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
8328 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
8329 #define I2C_ICR_ARLOCF_Pos           (9U)
8330 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
8331 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
8332 #define I2C_ICR_OVRCF_Pos            (10U)
8333 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
8334 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
8335 #define I2C_ICR_PECCF_Pos            (11U)
8336 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
8337 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
8338 #define I2C_ICR_TIMOUTCF_Pos         (12U)
8339 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
8340 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
8341 #define I2C_ICR_ALERTCF_Pos          (13U)
8342 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
8343 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
8344 
8345 /******************  Bit definition for I2C_PECR register  *********************/
8346 #define I2C_PECR_PEC_Pos             (0U)
8347 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
8348 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
8349 
8350 /******************  Bit definition for I2C_RXDR register  *********************/
8351 #define I2C_RXDR_RXDATA_Pos          (0U)
8352 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
8353 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
8354 
8355 /******************  Bit definition for I2C_TXDR register  *********************/
8356 #define I2C_TXDR_TXDATA_Pos          (0U)
8357 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
8358 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
8359 
8360 /******************************************************************************/
8361 /*                                                                            */
8362 /*                           Independent WATCHDOG                             */
8363 /*                                                                            */
8364 /******************************************************************************/
8365 /*******************  Bit definition for IWDG_KR register  ********************/
8366 #define IWDG_KR_KEY_Pos      (0U)
8367 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
8368 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
8369 
8370 /*******************  Bit definition for IWDG_PR register  ********************/
8371 #define IWDG_PR_PR_Pos       (0U)
8372 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
8373 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
8374 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
8375 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
8376 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
8377 
8378 /*******************  Bit definition for IWDG_RLR register  *******************/
8379 #define IWDG_RLR_RL_Pos      (0U)
8380 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
8381 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
8382 
8383 /*******************  Bit definition for IWDG_SR register  ********************/
8384 #define IWDG_SR_PVU_Pos      (0U)
8385 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
8386 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
8387 #define IWDG_SR_RVU_Pos      (1U)
8388 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
8389 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
8390 #define IWDG_SR_WVU_Pos      (2U)
8391 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
8392 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
8393 
8394 /*******************  Bit definition for IWDG_KR register  ********************/
8395 #define IWDG_WINR_WIN_Pos    (0U)
8396 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
8397 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
8398 
8399 /******************************************************************************/
8400 /*                                                                            */
8401 /*                                     Firewall                               */
8402 /*                                                                            */
8403 /******************************************************************************/
8404 
8405 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
8406 #define FW_CSSA_ADD_Pos      (8U)
8407 #define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                     /*!< 0x00FFFF00 */
8408 #define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
8409 #define FW_CSL_LENG_Pos      (8U)
8410 #define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                     /*!< 0x003FFF00 */
8411 #define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
8412 #define FW_NVDSSA_ADD_Pos    (8U)
8413 #define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                   /*!< 0x00FFFF00 */
8414 #define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
8415 #define FW_NVDSL_LENG_Pos    (8U)
8416 #define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                   /*!< 0x003FFF00 */
8417 #define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
8418 #define FW_VDSSA_ADD_Pos     (6U)
8419 #define FW_VDSSA_ADD_Msk     (0x7FFUL << FW_VDSSA_ADD_Pos)                     /*!< 0x0001FFC0 */
8420 #define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
8421 #define FW_VDSL_LENG_Pos     (6U)
8422 #define FW_VDSL_LENG_Msk     (0x7FFUL << FW_VDSL_LENG_Pos)                     /*!< 0x0001FFC0 */
8423 #define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
8424 
8425 /**************************Bit definition for CR register *********************/
8426 #define FW_CR_FPA_Pos        (0U)
8427 #define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                          /*!< 0x00000001 */
8428 #define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
8429 #define FW_CR_VDS_Pos        (1U)
8430 #define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                          /*!< 0x00000002 */
8431 #define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
8432 #define FW_CR_VDE_Pos        (2U)
8433 #define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                          /*!< 0x00000004 */
8434 #define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
8435 
8436 /******************************************************************************/
8437 /*                                                                            */
8438 /*                             Power Control                                  */
8439 /*                                                                            */
8440 /******************************************************************************/
8441 
8442 /********************  Bit definition for PWR_CR1 register  ********************/
8443 
8444 #define PWR_CR1_LPR_Pos              (14U)
8445 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
8446 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
8447 #define PWR_CR1_VOS_Pos              (9U)
8448 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
8449 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
8450 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
8451 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
8452 #define PWR_CR1_DBP_Pos              (8U)
8453 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
8454 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
8455 #define PWR_CR1_LPMS_Pos             (0U)
8456 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
8457 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
8458 #define PWR_CR1_LPMS_STOP0           (0x00000000UL)                            /*!< Stop 0 mode */
8459 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
8460 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
8461 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
8462 #define PWR_CR1_LPMS_STOP2_Pos       (1U)
8463 #define PWR_CR1_LPMS_STOP2_Msk       (0x1UL << PWR_CR1_LPMS_STOP2_Pos)         /*!< 0x00000002 */
8464 #define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
8465 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
8466 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
8467 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
8468 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
8469 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
8470 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
8471 
8472 
8473 /********************  Bit definition for PWR_CR2 register  ********************/
8474 /*!< PVME  Peripheral Voltage Monitor Enable */
8475 #define PWR_CR2_PVME_Pos             (6U)
8476 #define PWR_CR2_PVME_Msk             (0x3UL << PWR_CR2_PVME_Pos)               /*!< 0x000000C0 */
8477 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
8478 #define PWR_CR2_PVME4_Pos            (7U)
8479 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
8480 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
8481 #define PWR_CR2_PVME3_Pos            (6U)
8482 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
8483 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
8484 /*!< PVD level configuration */
8485 #define PWR_CR2_PLS_Pos              (1U)
8486 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
8487 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
8488 #define PWR_CR2_PLS_LEV0             (0x00000000UL)                            /*!< PVD level 0 */
8489 #define PWR_CR2_PLS_LEV1_Pos         (1U)
8490 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
8491 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
8492 #define PWR_CR2_PLS_LEV2_Pos         (2U)
8493 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
8494 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
8495 #define PWR_CR2_PLS_LEV3_Pos         (1U)
8496 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
8497 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
8498 #define PWR_CR2_PLS_LEV4_Pos         (3U)
8499 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
8500 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
8501 #define PWR_CR2_PLS_LEV5_Pos         (1U)
8502 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
8503 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
8504 #define PWR_CR2_PLS_LEV6_Pos         (2U)
8505 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
8506 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
8507 #define PWR_CR2_PLS_LEV7_Pos         (1U)
8508 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
8509 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
8510 #define PWR_CR2_PVDE_Pos             (0U)
8511 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
8512 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
8513 
8514 /********************  Bit definition for PWR_CR3 register  ********************/
8515 #define PWR_CR3_EIWUL_Pos            (15U)
8516 #define PWR_CR3_EIWUL_Msk            (0x1UL << PWR_CR3_EIWUL_Pos)              /*!< 0x00008000 */
8517 #define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */
8518 #define PWR_CR3_APC_Pos              (10U)
8519 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
8520 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
8521 #define PWR_CR3_RRS_Pos              (8U)
8522 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
8523 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
8524 #define PWR_CR3_EWUP5_Pos            (4U)
8525 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
8526 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
8527 #define PWR_CR3_EWUP4_Pos            (3U)
8528 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
8529 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
8530 #define PWR_CR3_EWUP3_Pos            (2U)
8531 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
8532 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
8533 #define PWR_CR3_EWUP2_Pos            (1U)
8534 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
8535 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
8536 #define PWR_CR3_EWUP1_Pos            (0U)
8537 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
8538 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
8539 #define PWR_CR3_EWUP_Pos             (0U)
8540 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
8541 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
8542 
8543 /* Legacy defines */
8544 #define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos
8545 #define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk
8546 #define PWR_CR3_EIWF                 PWR_CR3_EIWUL
8547 
8548 
8549 /********************  Bit definition for PWR_CR4 register  ********************/
8550 #define PWR_CR4_VBRS_Pos             (9U)
8551 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
8552 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
8553 #define PWR_CR4_VBE_Pos              (8U)
8554 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
8555 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
8556 #define PWR_CR4_WP5_Pos              (4U)
8557 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
8558 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
8559 #define PWR_CR4_WP4_Pos              (3U)
8560 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
8561 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
8562 #define PWR_CR4_WP3_Pos              (2U)
8563 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
8564 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
8565 #define PWR_CR4_WP2_Pos              (1U)
8566 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
8567 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
8568 #define PWR_CR4_WP1_Pos              (0U)
8569 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
8570 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
8571 
8572 /********************  Bit definition for PWR_SR1 register  ********************/
8573 #define PWR_SR1_WUFI_Pos             (15U)
8574 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
8575 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
8576 #define PWR_SR1_SBF_Pos              (8U)
8577 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
8578 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
8579 #define PWR_SR1_WUF_Pos              (0U)
8580 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
8581 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
8582 #define PWR_SR1_WUF5_Pos             (4U)
8583 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
8584 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
8585 #define PWR_SR1_WUF4_Pos             (3U)
8586 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
8587 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
8588 #define PWR_SR1_WUF3_Pos             (2U)
8589 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
8590 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
8591 #define PWR_SR1_WUF2_Pos             (1U)
8592 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
8593 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
8594 #define PWR_SR1_WUF1_Pos             (0U)
8595 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
8596 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
8597 
8598 /********************  Bit definition for PWR_SR2 register  ********************/
8599 #define PWR_SR2_PVMO4_Pos            (15U)
8600 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
8601 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
8602 #define PWR_SR2_PVMO3_Pos            (14U)
8603 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
8604 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
8605 #define PWR_SR2_PVDO_Pos             (11U)
8606 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
8607 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
8608 #define PWR_SR2_VOSF_Pos             (10U)
8609 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
8610 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
8611 #define PWR_SR2_REGLPF_Pos           (9U)
8612 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
8613 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
8614 #define PWR_SR2_REGLPS_Pos           (8U)
8615 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
8616 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
8617 
8618 /********************  Bit definition for PWR_SCR register  ********************/
8619 #define PWR_SCR_CSBF_Pos             (8U)
8620 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
8621 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
8622 #define PWR_SCR_CWUF_Pos             (0U)
8623 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
8624 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
8625 #define PWR_SCR_CWUF5_Pos            (4U)
8626 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
8627 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
8628 #define PWR_SCR_CWUF4_Pos            (3U)
8629 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
8630 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
8631 #define PWR_SCR_CWUF3_Pos            (2U)
8632 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
8633 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
8634 #define PWR_SCR_CWUF2_Pos            (1U)
8635 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
8636 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
8637 #define PWR_SCR_CWUF1_Pos            (0U)
8638 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
8639 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
8640 
8641 /********************  Bit definition for PWR_PUCRA register  ********************/
8642 #define PWR_PUCRA_PA15_Pos           (15U)
8643 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
8644 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
8645 #define PWR_PUCRA_PA13_Pos           (13U)
8646 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
8647 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
8648 #define PWR_PUCRA_PA12_Pos           (12U)
8649 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
8650 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
8651 #define PWR_PUCRA_PA11_Pos           (11U)
8652 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
8653 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
8654 #define PWR_PUCRA_PA10_Pos           (10U)
8655 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
8656 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
8657 #define PWR_PUCRA_PA9_Pos            (9U)
8658 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
8659 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
8660 #define PWR_PUCRA_PA8_Pos            (8U)
8661 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
8662 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
8663 #define PWR_PUCRA_PA7_Pos            (7U)
8664 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
8665 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
8666 #define PWR_PUCRA_PA6_Pos            (6U)
8667 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
8668 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
8669 #define PWR_PUCRA_PA5_Pos            (5U)
8670 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
8671 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
8672 #define PWR_PUCRA_PA4_Pos            (4U)
8673 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
8674 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
8675 #define PWR_PUCRA_PA3_Pos            (3U)
8676 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
8677 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
8678 #define PWR_PUCRA_PA2_Pos            (2U)
8679 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
8680 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
8681 #define PWR_PUCRA_PA1_Pos            (1U)
8682 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
8683 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
8684 #define PWR_PUCRA_PA0_Pos            (0U)
8685 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
8686 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
8687 
8688 /********************  Bit definition for PWR_PDCRA register  ********************/
8689 #define PWR_PDCRA_PA14_Pos           (14U)
8690 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
8691 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
8692 #define PWR_PDCRA_PA12_Pos           (12U)
8693 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
8694 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
8695 #define PWR_PDCRA_PA11_Pos           (11U)
8696 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
8697 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
8698 #define PWR_PDCRA_PA10_Pos           (10U)
8699 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
8700 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
8701 #define PWR_PDCRA_PA9_Pos            (9U)
8702 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
8703 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
8704 #define PWR_PDCRA_PA8_Pos            (8U)
8705 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
8706 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
8707 #define PWR_PDCRA_PA7_Pos            (7U)
8708 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
8709 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
8710 #define PWR_PDCRA_PA6_Pos            (6U)
8711 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
8712 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
8713 #define PWR_PDCRA_PA5_Pos            (5U)
8714 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
8715 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
8716 #define PWR_PDCRA_PA4_Pos            (4U)
8717 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
8718 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
8719 #define PWR_PDCRA_PA3_Pos            (3U)
8720 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
8721 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
8722 #define PWR_PDCRA_PA2_Pos            (2U)
8723 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
8724 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
8725 #define PWR_PDCRA_PA1_Pos            (1U)
8726 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
8727 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
8728 #define PWR_PDCRA_PA0_Pos            (0U)
8729 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
8730 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
8731 
8732 /********************  Bit definition for PWR_PUCRB register  ********************/
8733 #define PWR_PUCRB_PB15_Pos           (15U)
8734 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
8735 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
8736 #define PWR_PUCRB_PB14_Pos           (14U)
8737 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
8738 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
8739 #define PWR_PUCRB_PB13_Pos           (13U)
8740 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
8741 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
8742 #define PWR_PUCRB_PB12_Pos           (12U)
8743 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
8744 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
8745 #define PWR_PUCRB_PB11_Pos           (11U)
8746 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
8747 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
8748 #define PWR_PUCRB_PB10_Pos           (10U)
8749 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
8750 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
8751 #define PWR_PUCRB_PB9_Pos            (9U)
8752 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
8753 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
8754 #define PWR_PUCRB_PB8_Pos            (8U)
8755 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
8756 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
8757 #define PWR_PUCRB_PB7_Pos            (7U)
8758 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
8759 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
8760 #define PWR_PUCRB_PB6_Pos            (6U)
8761 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
8762 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
8763 #define PWR_PUCRB_PB5_Pos            (5U)
8764 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
8765 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
8766 #define PWR_PUCRB_PB4_Pos            (4U)
8767 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
8768 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
8769 #define PWR_PUCRB_PB3_Pos            (3U)
8770 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
8771 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
8772 #define PWR_PUCRB_PB2_Pos            (2U)
8773 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
8774 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
8775 #define PWR_PUCRB_PB1_Pos            (1U)
8776 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
8777 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
8778 #define PWR_PUCRB_PB0_Pos            (0U)
8779 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
8780 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
8781 
8782 /********************  Bit definition for PWR_PDCRB register  ********************/
8783 #define PWR_PDCRB_PB15_Pos           (15U)
8784 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
8785 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
8786 #define PWR_PDCRB_PB14_Pos           (14U)
8787 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
8788 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
8789 #define PWR_PDCRB_PB13_Pos           (13U)
8790 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
8791 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
8792 #define PWR_PDCRB_PB12_Pos           (12U)
8793 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
8794 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
8795 #define PWR_PDCRB_PB11_Pos           (11U)
8796 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
8797 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
8798 #define PWR_PDCRB_PB10_Pos           (10U)
8799 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
8800 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
8801 #define PWR_PDCRB_PB9_Pos            (9U)
8802 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
8803 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
8804 #define PWR_PDCRB_PB8_Pos            (8U)
8805 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
8806 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
8807 #define PWR_PDCRB_PB7_Pos            (7U)
8808 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
8809 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
8810 #define PWR_PDCRB_PB6_Pos            (6U)
8811 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
8812 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
8813 #define PWR_PDCRB_PB5_Pos            (5U)
8814 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
8815 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
8816 #define PWR_PDCRB_PB3_Pos            (3U)
8817 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
8818 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
8819 #define PWR_PDCRB_PB2_Pos            (2U)
8820 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
8821 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
8822 #define PWR_PDCRB_PB1_Pos            (1U)
8823 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
8824 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
8825 #define PWR_PDCRB_PB0_Pos            (0U)
8826 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
8827 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
8828 
8829 /********************  Bit definition for PWR_PUCRC register  ********************/
8830 #define PWR_PUCRC_PC15_Pos           (15U)
8831 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
8832 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
8833 #define PWR_PUCRC_PC14_Pos           (14U)
8834 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
8835 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
8836 #define PWR_PUCRC_PC13_Pos           (13U)
8837 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
8838 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
8839 #define PWR_PUCRC_PC12_Pos           (12U)
8840 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
8841 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
8842 #define PWR_PUCRC_PC11_Pos           (11U)
8843 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
8844 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
8845 #define PWR_PUCRC_PC10_Pos           (10U)
8846 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
8847 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
8848 #define PWR_PUCRC_PC9_Pos            (9U)
8849 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
8850 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
8851 #define PWR_PUCRC_PC8_Pos            (8U)
8852 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
8853 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
8854 #define PWR_PUCRC_PC7_Pos            (7U)
8855 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
8856 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
8857 #define PWR_PUCRC_PC6_Pos            (6U)
8858 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
8859 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
8860 #define PWR_PUCRC_PC5_Pos            (5U)
8861 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
8862 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
8863 #define PWR_PUCRC_PC4_Pos            (4U)
8864 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
8865 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
8866 #define PWR_PUCRC_PC3_Pos            (3U)
8867 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
8868 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
8869 #define PWR_PUCRC_PC2_Pos            (2U)
8870 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
8871 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
8872 #define PWR_PUCRC_PC1_Pos            (1U)
8873 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
8874 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
8875 #define PWR_PUCRC_PC0_Pos            (0U)
8876 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
8877 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
8878 
8879 /********************  Bit definition for PWR_PDCRC register  ********************/
8880 #define PWR_PDCRC_PC15_Pos           (15U)
8881 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
8882 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
8883 #define PWR_PDCRC_PC14_Pos           (14U)
8884 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
8885 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
8886 #define PWR_PDCRC_PC13_Pos           (13U)
8887 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
8888 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
8889 #define PWR_PDCRC_PC12_Pos           (12U)
8890 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
8891 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
8892 #define PWR_PDCRC_PC11_Pos           (11U)
8893 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
8894 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
8895 #define PWR_PDCRC_PC10_Pos           (10U)
8896 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
8897 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
8898 #define PWR_PDCRC_PC9_Pos            (9U)
8899 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
8900 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
8901 #define PWR_PDCRC_PC8_Pos            (8U)
8902 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
8903 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
8904 #define PWR_PDCRC_PC7_Pos            (7U)
8905 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
8906 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
8907 #define PWR_PDCRC_PC6_Pos            (6U)
8908 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
8909 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
8910 #define PWR_PDCRC_PC5_Pos            (5U)
8911 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
8912 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
8913 #define PWR_PDCRC_PC4_Pos            (4U)
8914 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
8915 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
8916 #define PWR_PDCRC_PC3_Pos            (3U)
8917 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
8918 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
8919 #define PWR_PDCRC_PC2_Pos            (2U)
8920 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
8921 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
8922 #define PWR_PDCRC_PC1_Pos            (1U)
8923 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
8924 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
8925 #define PWR_PDCRC_PC0_Pos            (0U)
8926 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
8927 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
8928 
8929 /********************  Bit definition for PWR_PUCRD register  ********************/
8930 #define PWR_PUCRD_PD15_Pos           (15U)
8931 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
8932 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
8933 #define PWR_PUCRD_PD14_Pos           (14U)
8934 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
8935 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
8936 #define PWR_PUCRD_PD13_Pos           (13U)
8937 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
8938 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
8939 #define PWR_PUCRD_PD12_Pos           (12U)
8940 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
8941 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
8942 #define PWR_PUCRD_PD11_Pos           (11U)
8943 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
8944 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
8945 #define PWR_PUCRD_PD10_Pos           (10U)
8946 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
8947 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
8948 #define PWR_PUCRD_PD9_Pos            (9U)
8949 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
8950 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
8951 #define PWR_PUCRD_PD8_Pos            (8U)
8952 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
8953 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
8954 #define PWR_PUCRD_PD7_Pos            (7U)
8955 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
8956 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
8957 #define PWR_PUCRD_PD6_Pos            (6U)
8958 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
8959 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
8960 #define PWR_PUCRD_PD5_Pos            (5U)
8961 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
8962 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
8963 #define PWR_PUCRD_PD4_Pos            (4U)
8964 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
8965 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
8966 #define PWR_PUCRD_PD3_Pos            (3U)
8967 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
8968 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
8969 #define PWR_PUCRD_PD2_Pos            (2U)
8970 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
8971 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
8972 #define PWR_PUCRD_PD1_Pos            (1U)
8973 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
8974 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
8975 #define PWR_PUCRD_PD0_Pos            (0U)
8976 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
8977 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
8978 
8979 /********************  Bit definition for PWR_PDCRD register  ********************/
8980 #define PWR_PDCRD_PD15_Pos           (15U)
8981 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
8982 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
8983 #define PWR_PDCRD_PD14_Pos           (14U)
8984 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
8985 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
8986 #define PWR_PDCRD_PD13_Pos           (13U)
8987 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
8988 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
8989 #define PWR_PDCRD_PD12_Pos           (12U)
8990 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
8991 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
8992 #define PWR_PDCRD_PD11_Pos           (11U)
8993 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
8994 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
8995 #define PWR_PDCRD_PD10_Pos           (10U)
8996 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
8997 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
8998 #define PWR_PDCRD_PD9_Pos            (9U)
8999 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
9000 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
9001 #define PWR_PDCRD_PD8_Pos            (8U)
9002 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
9003 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
9004 #define PWR_PDCRD_PD7_Pos            (7U)
9005 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
9006 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
9007 #define PWR_PDCRD_PD6_Pos            (6U)
9008 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
9009 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
9010 #define PWR_PDCRD_PD5_Pos            (5U)
9011 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
9012 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
9013 #define PWR_PDCRD_PD4_Pos            (4U)
9014 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
9015 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
9016 #define PWR_PDCRD_PD3_Pos            (3U)
9017 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
9018 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
9019 #define PWR_PDCRD_PD2_Pos            (2U)
9020 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
9021 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
9022 #define PWR_PDCRD_PD1_Pos            (1U)
9023 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
9024 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
9025 #define PWR_PDCRD_PD0_Pos            (0U)
9026 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
9027 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
9028 
9029 /********************  Bit definition for PWR_PUCRE register  ********************/
9030 #define PWR_PUCRE_PE15_Pos           (15U)
9031 #define PWR_PUCRE_PE15_Msk           (0x1UL << PWR_PUCRE_PE15_Pos)             /*!< 0x00008000 */
9032 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
9033 #define PWR_PUCRE_PE14_Pos           (14U)
9034 #define PWR_PUCRE_PE14_Msk           (0x1UL << PWR_PUCRE_PE14_Pos)             /*!< 0x00004000 */
9035 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
9036 #define PWR_PUCRE_PE13_Pos           (13U)
9037 #define PWR_PUCRE_PE13_Msk           (0x1UL << PWR_PUCRE_PE13_Pos)             /*!< 0x00002000 */
9038 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
9039 #define PWR_PUCRE_PE12_Pos           (12U)
9040 #define PWR_PUCRE_PE12_Msk           (0x1UL << PWR_PUCRE_PE12_Pos)             /*!< 0x00001000 */
9041 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
9042 #define PWR_PUCRE_PE11_Pos           (11U)
9043 #define PWR_PUCRE_PE11_Msk           (0x1UL << PWR_PUCRE_PE11_Pos)             /*!< 0x00000800 */
9044 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
9045 #define PWR_PUCRE_PE10_Pos           (10U)
9046 #define PWR_PUCRE_PE10_Msk           (0x1UL << PWR_PUCRE_PE10_Pos)             /*!< 0x00000400 */
9047 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
9048 #define PWR_PUCRE_PE9_Pos            (9U)
9049 #define PWR_PUCRE_PE9_Msk            (0x1UL << PWR_PUCRE_PE9_Pos)              /*!< 0x00000200 */
9050 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
9051 #define PWR_PUCRE_PE8_Pos            (8U)
9052 #define PWR_PUCRE_PE8_Msk            (0x1UL << PWR_PUCRE_PE8_Pos)              /*!< 0x00000100 */
9053 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
9054 #define PWR_PUCRE_PE7_Pos            (7U)
9055 #define PWR_PUCRE_PE7_Msk            (0x1UL << PWR_PUCRE_PE7_Pos)              /*!< 0x00000080 */
9056 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
9057 #define PWR_PUCRE_PE6_Pos            (6U)
9058 #define PWR_PUCRE_PE6_Msk            (0x1UL << PWR_PUCRE_PE6_Pos)              /*!< 0x00000040 */
9059 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
9060 #define PWR_PUCRE_PE5_Pos            (5U)
9061 #define PWR_PUCRE_PE5_Msk            (0x1UL << PWR_PUCRE_PE5_Pos)              /*!< 0x00000020 */
9062 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
9063 #define PWR_PUCRE_PE4_Pos            (4U)
9064 #define PWR_PUCRE_PE4_Msk            (0x1UL << PWR_PUCRE_PE4_Pos)              /*!< 0x00000010 */
9065 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
9066 #define PWR_PUCRE_PE3_Pos            (3U)
9067 #define PWR_PUCRE_PE3_Msk            (0x1UL << PWR_PUCRE_PE3_Pos)              /*!< 0x00000008 */
9068 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
9069 #define PWR_PUCRE_PE2_Pos            (2U)
9070 #define PWR_PUCRE_PE2_Msk            (0x1UL << PWR_PUCRE_PE2_Pos)              /*!< 0x00000004 */
9071 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
9072 #define PWR_PUCRE_PE1_Pos            (1U)
9073 #define PWR_PUCRE_PE1_Msk            (0x1UL << PWR_PUCRE_PE1_Pos)              /*!< 0x00000002 */
9074 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
9075 #define PWR_PUCRE_PE0_Pos            (0U)
9076 #define PWR_PUCRE_PE0_Msk            (0x1UL << PWR_PUCRE_PE0_Pos)              /*!< 0x00000001 */
9077 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
9078 
9079 /********************  Bit definition for PWR_PDCRE register  ********************/
9080 #define PWR_PDCRE_PE15_Pos           (15U)
9081 #define PWR_PDCRE_PE15_Msk           (0x1UL << PWR_PDCRE_PE15_Pos)             /*!< 0x00008000 */
9082 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
9083 #define PWR_PDCRE_PE14_Pos           (14U)
9084 #define PWR_PDCRE_PE14_Msk           (0x1UL << PWR_PDCRE_PE14_Pos)             /*!< 0x00004000 */
9085 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
9086 #define PWR_PDCRE_PE13_Pos           (13U)
9087 #define PWR_PDCRE_PE13_Msk           (0x1UL << PWR_PDCRE_PE13_Pos)             /*!< 0x00002000 */
9088 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
9089 #define PWR_PDCRE_PE12_Pos           (12U)
9090 #define PWR_PDCRE_PE12_Msk           (0x1UL << PWR_PDCRE_PE12_Pos)             /*!< 0x00001000 */
9091 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
9092 #define PWR_PDCRE_PE11_Pos           (11U)
9093 #define PWR_PDCRE_PE11_Msk           (0x1UL << PWR_PDCRE_PE11_Pos)             /*!< 0x00000800 */
9094 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
9095 #define PWR_PDCRE_PE10_Pos           (10U)
9096 #define PWR_PDCRE_PE10_Msk           (0x1UL << PWR_PDCRE_PE10_Pos)             /*!< 0x00000400 */
9097 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
9098 #define PWR_PDCRE_PE9_Pos            (9U)
9099 #define PWR_PDCRE_PE9_Msk            (0x1UL << PWR_PDCRE_PE9_Pos)              /*!< 0x00000200 */
9100 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
9101 #define PWR_PDCRE_PE8_Pos            (8U)
9102 #define PWR_PDCRE_PE8_Msk            (0x1UL << PWR_PDCRE_PE8_Pos)              /*!< 0x00000100 */
9103 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
9104 #define PWR_PDCRE_PE7_Pos            (7U)
9105 #define PWR_PDCRE_PE7_Msk            (0x1UL << PWR_PDCRE_PE7_Pos)              /*!< 0x00000080 */
9106 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
9107 #define PWR_PDCRE_PE6_Pos            (6U)
9108 #define PWR_PDCRE_PE6_Msk            (0x1UL << PWR_PDCRE_PE6_Pos)              /*!< 0x00000040 */
9109 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
9110 #define PWR_PDCRE_PE5_Pos            (5U)
9111 #define PWR_PDCRE_PE5_Msk            (0x1UL << PWR_PDCRE_PE5_Pos)              /*!< 0x00000020 */
9112 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
9113 #define PWR_PDCRE_PE4_Pos            (4U)
9114 #define PWR_PDCRE_PE4_Msk            (0x1UL << PWR_PDCRE_PE4_Pos)              /*!< 0x00000010 */
9115 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
9116 #define PWR_PDCRE_PE3_Pos            (3U)
9117 #define PWR_PDCRE_PE3_Msk            (0x1UL << PWR_PDCRE_PE3_Pos)              /*!< 0x00000008 */
9118 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
9119 #define PWR_PDCRE_PE2_Pos            (2U)
9120 #define PWR_PDCRE_PE2_Msk            (0x1UL << PWR_PDCRE_PE2_Pos)              /*!< 0x00000004 */
9121 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
9122 #define PWR_PDCRE_PE1_Pos            (1U)
9123 #define PWR_PDCRE_PE1_Msk            (0x1UL << PWR_PDCRE_PE1_Pos)              /*!< 0x00000002 */
9124 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
9125 #define PWR_PDCRE_PE0_Pos            (0U)
9126 #define PWR_PDCRE_PE0_Msk            (0x1UL << PWR_PDCRE_PE0_Pos)              /*!< 0x00000001 */
9127 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
9128 
9129 
9130 /********************  Bit definition for PWR_PUCRH register  ********************/
9131 #define PWR_PUCRH_PH3_Pos            (3U)
9132 #define PWR_PUCRH_PH3_Msk            (0x1UL << PWR_PUCRH_PH3_Pos)              /*!< 0x00000008 */
9133 #define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
9134 #define PWR_PUCRH_PH1_Pos            (1U)
9135 #define PWR_PUCRH_PH1_Msk            (0x1UL << PWR_PUCRH_PH1_Pos)              /*!< 0x00000002 */
9136 #define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
9137 #define PWR_PUCRH_PH0_Pos            (0U)
9138 #define PWR_PUCRH_PH0_Msk            (0x1UL << PWR_PUCRH_PH0_Pos)              /*!< 0x00000001 */
9139 #define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
9140 
9141 /********************  Bit definition for PWR_PDCRH register  ********************/
9142 #define PWR_PDCRH_PH3_Pos            (3U)
9143 #define PWR_PDCRH_PH3_Msk            (0x1UL << PWR_PDCRH_PH3_Pos)              /*!< 0x00000008 */
9144 #define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
9145 #define PWR_PDCRH_PH1_Pos            (1U)
9146 #define PWR_PDCRH_PH1_Msk            (0x1UL << PWR_PDCRH_PH1_Pos)              /*!< 0x00000002 */
9147 #define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
9148 #define PWR_PDCRH_PH0_Pos            (0U)
9149 #define PWR_PDCRH_PH0_Msk            (0x1UL << PWR_PDCRH_PH0_Pos)              /*!< 0x00000001 */
9150 #define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
9151 
9152 
9153 /******************************************************************************/
9154 /*                                                                            */
9155 /*                         Reset and Clock Control                            */
9156 /*                                                                            */
9157 /******************************************************************************/
9158 /*
9159 * @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
9160 */
9161 #define RCC_PLLSAI1_SUPPORT
9162 #define RCC_PLLP_SUPPORT
9163 #define RCC_HSI48_SUPPORT
9164 #define RCC_PLLP_DIV_2_31_SUPPORT
9165 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
9166 
9167 /********************  Bit definition for RCC_CR register  ********************/
9168 #define RCC_CR_MSION_Pos                     (0U)
9169 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
9170 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
9171 #define RCC_CR_MSIRDY_Pos                    (1U)
9172 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
9173 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
9174 #define RCC_CR_MSIPLLEN_Pos                  (2U)
9175 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
9176 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
9177 #define RCC_CR_MSIRGSEL_Pos                  (3U)
9178 #define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
9179 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
9180 
9181 /*!< MSIRANGE configuration : 12 frequency ranges available */
9182 #define RCC_CR_MSIRANGE_Pos                  (4U)
9183 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
9184 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
9185 #define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
9186 #define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
9187 #define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
9188 #define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
9189 #define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
9190 #define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
9191 #define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
9192 #define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
9193 #define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
9194 #define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
9195 #define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
9196 #define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
9197 
9198 #define RCC_CR_HSION_Pos                     (8U)
9199 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
9200 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
9201 #define RCC_CR_HSIKERON_Pos                  (9U)
9202 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
9203 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
9204 #define RCC_CR_HSIRDY_Pos                    (10U)
9205 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
9206 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
9207 #define RCC_CR_HSIASFS_Pos                   (11U)
9208 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
9209 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
9210 
9211 #define RCC_CR_HSEON_Pos                     (16U)
9212 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
9213 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
9214 #define RCC_CR_HSERDY_Pos                    (17U)
9215 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
9216 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
9217 #define RCC_CR_HSEBYP_Pos                    (18U)
9218 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
9219 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
9220 #define RCC_CR_CSSON_Pos                     (19U)
9221 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
9222 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
9223 
9224 #define RCC_CR_PLLON_Pos                     (24U)
9225 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
9226 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
9227 #define RCC_CR_PLLRDY_Pos                    (25U)
9228 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
9229 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
9230 #define RCC_CR_PLLSAI1ON_Pos                 (26U)
9231 #define RCC_CR_PLLSAI1ON_Msk                 (0x1UL << RCC_CR_PLLSAI1ON_Pos)   /*!< 0x04000000 */
9232 #define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
9233 #define RCC_CR_PLLSAI1RDY_Pos                (27U)
9234 #define RCC_CR_PLLSAI1RDY_Msk                (0x1UL << RCC_CR_PLLSAI1RDY_Pos)  /*!< 0x08000000 */
9235 #define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
9236 
9237 /********************  Bit definition for RCC_ICSCR register  ***************/
9238 /*!< MSICAL configuration */
9239 #define RCC_ICSCR_MSICAL_Pos                 (0U)
9240 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
9241 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
9242 #define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */
9243 #define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */
9244 #define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */
9245 #define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */
9246 #define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */
9247 #define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */
9248 #define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */
9249 #define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */
9250 
9251 /*!< MSITRIM configuration */
9252 #define RCC_ICSCR_MSITRIM_Pos                (8U)
9253 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
9254 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
9255 #define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
9256 #define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
9257 #define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
9258 #define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
9259 #define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
9260 #define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
9261 #define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
9262 #define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
9263 
9264 /*!< HSICAL configuration */
9265 #define RCC_ICSCR_HSICAL_Pos                 (16U)
9266 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
9267 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
9268 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
9269 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
9270 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
9271 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
9272 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
9273 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
9274 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
9275 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
9276 
9277 /*!< HSITRIM configuration */
9278 #define RCC_ICSCR_HSITRIM_Pos                (24U)
9279 #define RCC_ICSCR_HSITRIM_Msk                (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x1F000000 */
9280 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[4:0] bits */
9281 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
9282 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
9283 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
9284 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
9285 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
9286 
9287 /********************  Bit definition for RCC_CFGR register  ******************/
9288 /*!< SW configuration */
9289 #define RCC_CFGR_SW_Pos                      (0U)
9290 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
9291 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
9292 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
9293 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
9294 
9295 #define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */
9296 #define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */
9297 #define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */
9298 #define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */
9299 
9300 /*!< SWS configuration */
9301 #define RCC_CFGR_SWS_Pos                     (2U)
9302 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
9303 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
9304 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
9305 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
9306 
9307 #define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */
9308 #define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */
9309 #define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */
9310 #define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */
9311 
9312 /*!< HPRE configuration */
9313 #define RCC_CFGR_HPRE_Pos                    (4U)
9314 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
9315 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
9316 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
9317 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
9318 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
9319 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
9320 
9321 #define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */
9322 #define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */
9323 #define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */
9324 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */
9325 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */
9326 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */
9327 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */
9328 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */
9329 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */
9330 
9331 /*!< PPRE1 configuration */
9332 #define RCC_CFGR_PPRE1_Pos                   (8U)
9333 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
9334 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
9335 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
9336 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
9337 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
9338 
9339 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
9340 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */
9341 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */
9342 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */
9343 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */
9344 
9345 /*!< PPRE2 configuration */
9346 #define RCC_CFGR_PPRE2_Pos                   (11U)
9347 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
9348 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
9349 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
9350 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
9351 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
9352 
9353 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
9354 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */
9355 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */
9356 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */
9357 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */
9358 
9359 #define RCC_CFGR_STOPWUCK_Pos                (15U)
9360 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
9361 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
9362 
9363 /*!< MCOSEL configuration */
9364 #define RCC_CFGR_MCOSEL_Pos                  (24U)
9365 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
9366 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
9367 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
9368 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
9369 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
9370 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
9371 
9372 #define RCC_CFGR_MCOPRE_Pos                  (28U)
9373 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
9374 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
9375 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
9376 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
9377 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
9378 
9379 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */
9380 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */
9381 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */
9382 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */
9383 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */
9384 
9385 /* Legacy aliases */
9386 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
9387 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
9388 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
9389 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
9390 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
9391 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
9392 
9393 /********************  Bit definition for RCC_PLLCFGR register  ***************/
9394 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
9395 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
9396 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
9397 
9398 #define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
9399 #define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
9400 #define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
9401 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
9402 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
9403 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
9404 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
9405 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
9406 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
9407 
9408 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
9409 #define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000070 */
9410 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
9411 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
9412 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
9413 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
9414 
9415 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
9416 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
9417 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
9418 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
9419 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
9420 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
9421 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
9422 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
9423 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
9424 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
9425 
9426 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
9427 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
9428 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
9429 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
9430 #define RCC_PLLCFGR_PLLP_Msk                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)   /*!< 0x00020000 */
9431 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
9432 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
9433 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
9434 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
9435 
9436 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
9437 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
9438 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
9439 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
9440 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
9441 
9442 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
9443 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
9444 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
9445 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
9446 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
9447 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
9448 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
9449 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
9450 
9451 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
9452 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
9453 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
9454 #define RCC_PLLCFGR_PLLPDIV_0                (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
9455 #define RCC_PLLCFGR_PLLPDIV_1                (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
9456 #define RCC_PLLCFGR_PLLPDIV_2                (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
9457 #define RCC_PLLCFGR_PLLPDIV_3                (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
9458 #define RCC_PLLCFGR_PLLPDIV_4                (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
9459 
9460 /********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
9461 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)
9462 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
9463 #define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk
9464 #define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
9465 #define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
9466 #define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
9467 #define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
9468 #define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
9469 #define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
9470 #define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
9471 
9472 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)
9473 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
9474 #define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
9475 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)
9476 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
9477 #define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk
9478 
9479 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)
9480 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
9481 #define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
9482 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)
9483 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
9484 #define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
9485 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
9486 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
9487 
9488 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)
9489 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
9490 #define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
9491 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)
9492 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
9493 #define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk
9494 #define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
9495 #define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
9496 
9497 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)
9498 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FUL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
9499 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
9500 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
9501 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
9502 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
9503 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
9504 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
9505 
9506 /********************  Bit definition for RCC_CIER register  ******************/
9507 #define RCC_CIER_LSIRDYIE_Pos                (0U)
9508 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
9509 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
9510 #define RCC_CIER_LSERDYIE_Pos                (1U)
9511 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
9512 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
9513 #define RCC_CIER_MSIRDYIE_Pos                (2U)
9514 #define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)  /*!< 0x00000004 */
9515 #define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
9516 #define RCC_CIER_HSIRDYIE_Pos                (3U)
9517 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
9518 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
9519 #define RCC_CIER_HSERDYIE_Pos                (4U)
9520 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
9521 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
9522 #define RCC_CIER_PLLRDYIE_Pos                (5U)
9523 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
9524 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
9525 #define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)
9526 #define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
9527 #define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk
9528 #define RCC_CIER_LSECSSIE_Pos                (9U)
9529 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
9530 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
9531 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
9532 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
9533 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
9534 
9535 /********************  Bit definition for RCC_CIFR register  ******************/
9536 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
9537 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
9538 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
9539 #define RCC_CIFR_LSERDYF_Pos                 (1U)
9540 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
9541 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
9542 #define RCC_CIFR_MSIRDYF_Pos                 (2U)
9543 #define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
9544 #define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
9545 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
9546 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
9547 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
9548 #define RCC_CIFR_HSERDYF_Pos                 (4U)
9549 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
9550 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
9551 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
9552 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
9553 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
9554 #define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)
9555 #define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
9556 #define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk
9557 #define RCC_CIFR_CSSF_Pos                    (8U)
9558 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
9559 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
9560 #define RCC_CIFR_LSECSSF_Pos                 (9U)
9561 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
9562 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
9563 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
9564 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
9565 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
9566 
9567 /********************  Bit definition for RCC_CICR register  ******************/
9568 #define RCC_CICR_LSIRDYC_Pos                 (0U)
9569 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
9570 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
9571 #define RCC_CICR_LSERDYC_Pos                 (1U)
9572 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
9573 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
9574 #define RCC_CICR_MSIRDYC_Pos                 (2U)
9575 #define RCC_CICR_MSIRDYC_Msk                 (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
9576 #define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk
9577 #define RCC_CICR_HSIRDYC_Pos                 (3U)
9578 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
9579 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
9580 #define RCC_CICR_HSERDYC_Pos                 (4U)
9581 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
9582 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
9583 #define RCC_CICR_PLLRDYC_Pos                 (5U)
9584 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
9585 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
9586 #define RCC_CICR_PLLSAI1RDYC_Pos             (6U)
9587 #define RCC_CICR_PLLSAI1RDYC_Msk             (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
9588 #define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk
9589 #define RCC_CICR_CSSC_Pos                    (8U)
9590 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
9591 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
9592 #define RCC_CICR_LSECSSC_Pos                 (9U)
9593 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
9594 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
9595 #define RCC_CICR_HSI48RDYC_Pos               (10U)
9596 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
9597 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
9598 
9599 /********************  Bit definition for RCC_AHB1RSTR register  **************/
9600 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
9601 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
9602 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
9603 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
9604 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
9605 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
9606 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
9607 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
9608 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
9609 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
9610 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
9611 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
9612 #define RCC_AHB1RSTR_TSCRST_Pos              (16U)
9613 #define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
9614 #define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk
9615 
9616 /********************  Bit definition for RCC_AHB2RSTR register  **************/
9617 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
9618 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9619 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
9620 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
9621 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9622 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
9623 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
9624 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9625 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
9626 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
9627 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9628 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
9629 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
9630 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9631 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
9632 #define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)
9633 #define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9634 #define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk
9635 #define RCC_AHB2RSTR_ADCRST_Pos              (13U)
9636 #define RCC_AHB2RSTR_ADCRST_Msk              (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
9637 #define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk
9638 #define RCC_AHB2RSTR_RNGRST_Pos              (18U)
9639 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
9640 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
9641 
9642 /********************  Bit definition for RCC_AHB3RSTR register  **************/
9643 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
9644 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
9645 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
9646 
9647 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
9648 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
9649 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
9650 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
9651 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
9652 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
9653 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
9654 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
9655 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
9656 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
9657 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
9658 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
9659 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
9660 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
9661 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
9662 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
9663 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
9664 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
9665 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
9666 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
9667 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
9668 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
9669 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
9670 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
9671 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
9672 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
9673 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
9674 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
9675 #define RCC_APB1RSTR1_I2C3RST_Pos            (23U)
9676 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
9677 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
9678 #define RCC_APB1RSTR1_CRSRST_Pos             (24U)
9679 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
9680 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
9681 #define RCC_APB1RSTR1_CAN1RST_Pos            (25U)
9682 #define RCC_APB1RSTR1_CAN1RST_Msk            (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
9683 #define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk
9684 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
9685 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
9686 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
9687 #define RCC_APB1RSTR1_DAC1RST_Pos            (29U)
9688 #define RCC_APB1RSTR1_DAC1RST_Msk            (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
9689 #define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk
9690 #define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)
9691 #define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
9692 #define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk
9693 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
9694 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
9695 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
9696 
9697 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
9698 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
9699 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
9700 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
9701 #define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)
9702 #define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
9703 #define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk
9704 #define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)
9705 #define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
9706 #define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk
9707 
9708 /********************  Bit definition for RCC_APB2RSTR register  **************/
9709 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
9710 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
9711 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
9712 #define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)
9713 #define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
9714 #define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk
9715 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
9716 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
9717 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
9718 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
9719 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
9720 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
9721 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
9722 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
9723 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
9724 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
9725 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
9726 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
9727 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
9728 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
9729 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
9730 #define RCC_APB2RSTR_SAI1RST_Pos             (21U)
9731 #define RCC_APB2RSTR_SAI1RST_Msk             (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
9732 #define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
9733 
9734 /********************  Bit definition for RCC_AHB1ENR register  ***************/
9735 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
9736 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
9737 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
9738 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
9739 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
9740 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
9741 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
9742 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
9743 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
9744 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
9745 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
9746 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
9747 #define RCC_AHB1ENR_TSCEN_Pos                (16U)
9748 #define RCC_AHB1ENR_TSCEN_Msk                (0x1UL << RCC_AHB1ENR_TSCEN_Pos)  /*!< 0x00010000 */
9749 #define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk
9750 
9751 /********************  Bit definition for RCC_AHB2ENR register  ***************/
9752 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
9753 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
9754 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
9755 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
9756 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
9757 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
9758 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
9759 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
9760 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
9761 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
9762 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
9763 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
9764 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
9765 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
9766 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
9767 #define RCC_AHB2ENR_GPIOHEN_Pos              (7U)
9768 #define RCC_AHB2ENR_GPIOHEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
9769 #define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk
9770 #define RCC_AHB2ENR_ADCEN_Pos                (13U)
9771 #define RCC_AHB2ENR_ADCEN_Msk                (0x1UL << RCC_AHB2ENR_ADCEN_Pos)  /*!< 0x00002000 */
9772 #define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk
9773 #define RCC_AHB2ENR_RNGEN_Pos                (18U)
9774 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x00040000 */
9775 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
9776 
9777 /********************  Bit definition for RCC_AHB3ENR register  ***************/
9778 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
9779 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
9780 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
9781 
9782 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
9783 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
9784 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
9785 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
9786 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
9787 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
9788 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
9789 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
9790 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
9791 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
9792 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
9793 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
9794 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
9795 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
9796 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
9797 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
9798 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
9799 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
9800 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
9801 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
9802 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
9803 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
9804 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
9805 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
9806 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
9807 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
9808 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
9809 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
9810 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
9811 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
9812 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
9813 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
9814 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
9815 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
9816 #define RCC_APB1ENR1_I2C3EN_Pos              (23U)
9817 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
9818 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
9819 #define RCC_APB1ENR1_CRSEN_Pos               (24U)
9820 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
9821 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
9822 #define RCC_APB1ENR1_CAN1EN_Pos              (25U)
9823 #define RCC_APB1ENR1_CAN1EN_Msk              (0x1UL << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
9824 #define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk
9825 #define RCC_APB1ENR1_PWREN_Pos               (28U)
9826 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
9827 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
9828 #define RCC_APB1ENR1_DAC1EN_Pos              (29U)
9829 #define RCC_APB1ENR1_DAC1EN_Msk              (0x1UL << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
9830 #define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk
9831 #define RCC_APB1ENR1_OPAMPEN_Pos             (30U)
9832 #define RCC_APB1ENR1_OPAMPEN_Msk             (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
9833 #define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk
9834 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
9835 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
9836 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
9837 
9838 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
9839 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
9840 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
9841 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
9842 #define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)
9843 #define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
9844 #define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk
9845 #define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)
9846 #define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
9847 #define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk
9848 
9849 /********************  Bit definition for RCC_APB2ENR register  ***************/
9850 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
9851 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
9852 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
9853 #define RCC_APB2ENR_FWEN_Pos                 (7U)
9854 #define RCC_APB2ENR_FWEN_Msk                 (0x1UL << RCC_APB2ENR_FWEN_Pos)   /*!< 0x00000080 */
9855 #define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk
9856 #define RCC_APB2ENR_SDMMC1EN_Pos             (10U)
9857 #define RCC_APB2ENR_SDMMC1EN_Msk             (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
9858 #define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk
9859 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
9860 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
9861 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
9862 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
9863 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
9864 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
9865 #define RCC_APB2ENR_USART1EN_Pos             (14U)
9866 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
9867 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
9868 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
9869 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
9870 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
9871 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
9872 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
9873 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
9874 #define RCC_APB2ENR_SAI1EN_Pos               (21U)
9875 #define RCC_APB2ENR_SAI1EN_Msk               (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
9876 #define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
9877 
9878 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
9879 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
9880 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
9881 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
9882 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
9883 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
9884 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
9885 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
9886 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
9887 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
9888 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
9889 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
9890 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
9891 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
9892 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
9893 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
9894 #define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)
9895 #define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
9896 #define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk
9897 
9898 /********************  Bit definition for RCC_AHB2SMENR register  *************/
9899 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
9900 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
9901 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
9902 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
9903 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
9904 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
9905 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
9906 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
9907 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
9908 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
9909 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
9910 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
9911 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
9912 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
9913 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
9914 #define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)
9915 #define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
9916 #define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk
9917 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)
9918 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
9919 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
9920 #define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)
9921 #define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
9922 #define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk
9923 #define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)
9924 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
9925 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
9926 
9927 /********************  Bit definition for RCC_AHB3SMENR register  *************/
9928 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
9929 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
9930 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
9931 
9932 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
9933 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
9934 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
9935 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
9936 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
9937 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
9938 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
9939 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
9940 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
9941 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
9942 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
9943 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
9944 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
9945 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
9946 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
9947 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
9948 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
9949 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
9950 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
9951 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
9952 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
9953 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
9954 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
9955 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
9956 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
9957 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
9958 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
9959 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
9960 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
9961 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
9962 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
9963 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
9964 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
9965 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
9966 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)
9967 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
9968 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
9969 #define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)
9970 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
9971 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
9972 #define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)
9973 #define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
9974 #define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk
9975 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
9976 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
9977 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
9978 #define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)
9979 #define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
9980 #define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk
9981 #define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)
9982 #define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
9983 #define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk
9984 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
9985 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
9986 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
9987 
9988 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
9989 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
9990 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
9991 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
9992 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)
9993 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
9994 #define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk
9995 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)
9996 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
9997 #define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk
9998 
9999 /********************  Bit definition for RCC_APB2SMENR register  *************/
10000 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
10001 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
10002 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
10003 #define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)
10004 #define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
10005 #define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk
10006 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
10007 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
10008 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
10009 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
10010 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
10011 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
10012 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
10013 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
10014 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
10015 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
10016 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
10017 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
10018 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
10019 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
10020 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
10021 #define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
10022 #define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
10023 #define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
10024 
10025 /********************  Bit definition for RCC_CCIPR register  ******************/
10026 #define RCC_CCIPR_USART1SEL_Pos              (0U)
10027 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
10028 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
10029 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
10030 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
10031 
10032 #define RCC_CCIPR_USART2SEL_Pos              (2U)
10033 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
10034 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
10035 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
10036 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
10037 
10038 #define RCC_CCIPR_USART3SEL_Pos              (4U)
10039 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
10040 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
10041 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
10042 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
10043 
10044 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
10045 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
10046 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
10047 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
10048 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
10049 
10050 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
10051 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
10052 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
10053 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
10054 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
10055 
10056 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
10057 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
10058 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
10059 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
10060 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
10061 
10062 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
10063 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
10064 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
10065 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
10066 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
10067 
10068 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
10069 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
10070 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
10071 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
10072 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
10073 
10074 #define RCC_CCIPR_LPTIM2SEL_Pos              (20U)
10075 #define RCC_CCIPR_LPTIM2SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
10076 #define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk
10077 #define RCC_CCIPR_LPTIM2SEL_0                (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
10078 #define RCC_CCIPR_LPTIM2SEL_1                (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
10079 
10080 #define RCC_CCIPR_SAI1SEL_Pos                (22U)
10081 #define RCC_CCIPR_SAI1SEL_Msk                (0x3UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00C00000 */
10082 #define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
10083 #define RCC_CCIPR_SAI1SEL_0                  (0x1UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00400000 */
10084 #define RCC_CCIPR_SAI1SEL_1                  (0x2UL << RCC_CCIPR_SAI1SEL_Pos)  /*!< 0x00800000 */
10085 
10086 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
10087 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
10088 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
10089 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
10090 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
10091 
10092 #define RCC_CCIPR_ADCSEL_Pos                 (28U)
10093 #define RCC_CCIPR_ADCSEL_Msk                 (0x3UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x30000000 */
10094 #define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk
10095 #define RCC_CCIPR_ADCSEL_0                   (0x1UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x10000000 */
10096 #define RCC_CCIPR_ADCSEL_1                   (0x2UL << RCC_CCIPR_ADCSEL_Pos)   /*!< 0x20000000 */
10097 
10098 #define RCC_CCIPR_SWPMI1SEL_Pos              (30U)
10099 #define RCC_CCIPR_SWPMI1SEL_Msk              (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
10100 #define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk
10101 
10102 /********************  Bit definition for RCC_BDCR register  ******************/
10103 #define RCC_BDCR_LSEON_Pos                   (0U)
10104 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
10105 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
10106 #define RCC_BDCR_LSERDY_Pos                  (1U)
10107 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
10108 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
10109 #define RCC_BDCR_LSEBYP_Pos                  (2U)
10110 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
10111 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
10112 
10113 #define RCC_BDCR_LSEDRV_Pos                  (3U)
10114 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
10115 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
10116 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
10117 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
10118 
10119 #define RCC_BDCR_LSECSSON_Pos                (5U)
10120 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
10121 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
10122 #define RCC_BDCR_LSECSSD_Pos                 (6U)
10123 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
10124 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
10125 
10126 #define RCC_BDCR_RTCSEL_Pos                  (8U)
10127 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
10128 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
10129 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
10130 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
10131 
10132 #define RCC_BDCR_RTCEN_Pos                   (15U)
10133 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
10134 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
10135 #define RCC_BDCR_BDRST_Pos                   (16U)
10136 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
10137 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
10138 #define RCC_BDCR_LSCOEN_Pos                  (24U)
10139 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
10140 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
10141 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
10142 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
10143 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
10144 
10145 /********************  Bit definition for RCC_CSR register  *******************/
10146 #define RCC_CSR_LSION_Pos                    (0U)
10147 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
10148 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
10149 #define RCC_CSR_LSIRDY_Pos                   (1U)
10150 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
10151 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
10152 
10153 #define RCC_CSR_MSISRANGE_Pos                (8U)
10154 #define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
10155 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
10156 #define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
10157 #define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
10158 #define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
10159 #define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
10160 
10161 #define RCC_CSR_RMVF_Pos                     (23U)
10162 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
10163 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
10164 #define RCC_CSR_FWRSTF_Pos                   (24U)
10165 #define RCC_CSR_FWRSTF_Msk                   (0x1UL << RCC_CSR_FWRSTF_Pos)     /*!< 0x01000000 */
10166 #define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk
10167 #define RCC_CSR_OBLRSTF_Pos                  (25U)
10168 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
10169 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
10170 #define RCC_CSR_PINRSTF_Pos                  (26U)
10171 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
10172 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
10173 #define RCC_CSR_BORRSTF_Pos                  (27U)
10174 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
10175 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
10176 #define RCC_CSR_SFTRSTF_Pos                  (28U)
10177 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
10178 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
10179 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
10180 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
10181 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
10182 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
10183 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
10184 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
10185 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
10186 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
10187 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
10188 
10189 /********************  Bit definition for RCC_CRRCR register  *****************/
10190 #define RCC_CRRCR_HSI48ON_Pos                (0U)
10191 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
10192 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
10193 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
10194 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
10195 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
10196 
10197 /*!< HSI48CAL configuration */
10198 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
10199 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
10200 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
10201 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
10202 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
10203 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
10204 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
10205 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
10206 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
10207 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
10208 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
10209 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
10210 
10211 /******************************************************************************/
10212 /*                                                                            */
10213 /*                                    RNG                                     */
10214 /*                                                                            */
10215 /******************************************************************************/
10216 /********************  Bits definition for RNG_CR register  *******************/
10217 #define RNG_CR_RNGEN_Pos    (2U)
10218 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
10219 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
10220 #define RNG_CR_IE_Pos       (3U)
10221 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
10222 #define RNG_CR_IE           RNG_CR_IE_Msk
10223 
10224 /********************  Bits definition for RNG_SR register  *******************/
10225 #define RNG_SR_DRDY_Pos     (0U)
10226 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
10227 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
10228 #define RNG_SR_CECS_Pos     (1U)
10229 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
10230 #define RNG_SR_CECS         RNG_SR_CECS_Msk
10231 #define RNG_SR_SECS_Pos     (2U)
10232 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
10233 #define RNG_SR_SECS         RNG_SR_SECS_Msk
10234 #define RNG_SR_CEIS_Pos     (5U)
10235 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
10236 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
10237 #define RNG_SR_SEIS_Pos     (6U)
10238 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
10239 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
10240 
10241 /******************************************************************************/
10242 /*                                                                            */
10243 /*                           Real-Time Clock (RTC)                            */
10244 /*                                                                            */
10245 /******************************************************************************/
10246 /*
10247 * @brief Specific device feature definitions
10248 */
10249 #define RTC_TAMPER1_SUPPORT
10250 #define RTC_TAMPER2_SUPPORT
10251 #define RTC_TAMPER3_SUPPORT
10252 
10253 #define RTC_WAKEUP_SUPPORT
10254 #define RTC_BACKUP_SUPPORT
10255 /******************** Number of backup registers ******************************/
10256 #define RTC_BKP_NUMBER                32U
10257 
10258 
10259 /********************  Bits definition for RTC_TR register  *******************/
10260 #define RTC_TR_PM_Pos                  (22U)
10261 #define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
10262 #define RTC_TR_PM                      RTC_TR_PM_Msk
10263 #define RTC_TR_HT_Pos                  (20U)
10264 #define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
10265 #define RTC_TR_HT                      RTC_TR_HT_Msk
10266 #define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                /*!< 0x00100000 */
10267 #define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                /*!< 0x00200000 */
10268 #define RTC_TR_HU_Pos                  (16U)
10269 #define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
10270 #define RTC_TR_HU                      RTC_TR_HU_Msk
10271 #define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                /*!< 0x00010000 */
10272 #define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                /*!< 0x00020000 */
10273 #define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                /*!< 0x00040000 */
10274 #define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                /*!< 0x00080000 */
10275 #define RTC_TR_MNT_Pos                 (12U)
10276 #define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
10277 #define RTC_TR_MNT                     RTC_TR_MNT_Msk
10278 #define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)               /*!< 0x00001000 */
10279 #define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)               /*!< 0x00002000 */
10280 #define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)               /*!< 0x00004000 */
10281 #define RTC_TR_MNU_Pos                 (8U)
10282 #define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
10283 #define RTC_TR_MNU                     RTC_TR_MNU_Msk
10284 #define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)               /*!< 0x00000100 */
10285 #define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)               /*!< 0x00000200 */
10286 #define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)               /*!< 0x00000400 */
10287 #define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)               /*!< 0x00000800 */
10288 #define RTC_TR_ST_Pos                  (4U)
10289 #define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
10290 #define RTC_TR_ST                      RTC_TR_ST_Msk
10291 #define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                /*!< 0x00000010 */
10292 #define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                /*!< 0x00000020 */
10293 #define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                /*!< 0x00000040 */
10294 #define RTC_TR_SU_Pos                  (0U)
10295 #define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
10296 #define RTC_TR_SU                      RTC_TR_SU_Msk
10297 #define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                /*!< 0x00000001 */
10298 #define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                /*!< 0x00000002 */
10299 #define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                /*!< 0x00000004 */
10300 #define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                /*!< 0x00000008 */
10301 
10302 /********************  Bits definition for RTC_DR register  *******************/
10303 #define RTC_DR_YT_Pos                  (20U)
10304 #define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
10305 #define RTC_DR_YT                      RTC_DR_YT_Msk
10306 #define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                /*!< 0x00100000 */
10307 #define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                /*!< 0x00200000 */
10308 #define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                /*!< 0x00400000 */
10309 #define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                /*!< 0x00800000 */
10310 #define RTC_DR_YU_Pos                  (16U)
10311 #define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
10312 #define RTC_DR_YU                      RTC_DR_YU_Msk
10313 #define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                /*!< 0x00010000 */
10314 #define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                /*!< 0x00020000 */
10315 #define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                /*!< 0x00040000 */
10316 #define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                /*!< 0x00080000 */
10317 #define RTC_DR_WDU_Pos                 (13U)
10318 #define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
10319 #define RTC_DR_WDU                     RTC_DR_WDU_Msk
10320 #define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)               /*!< 0x00002000 */
10321 #define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)               /*!< 0x00004000 */
10322 #define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)               /*!< 0x00008000 */
10323 #define RTC_DR_MT_Pos                  (12U)
10324 #define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
10325 #define RTC_DR_MT                      RTC_DR_MT_Msk
10326 #define RTC_DR_MU_Pos                  (8U)
10327 #define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
10328 #define RTC_DR_MU                      RTC_DR_MU_Msk
10329 #define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                /*!< 0x00000100 */
10330 #define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                /*!< 0x00000200 */
10331 #define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                /*!< 0x00000400 */
10332 #define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                /*!< 0x00000800 */
10333 #define RTC_DR_DT_Pos                  (4U)
10334 #define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
10335 #define RTC_DR_DT                      RTC_DR_DT_Msk
10336 #define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                /*!< 0x00000010 */
10337 #define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                /*!< 0x00000020 */
10338 #define RTC_DR_DU_Pos                  (0U)
10339 #define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
10340 #define RTC_DR_DU                      RTC_DR_DU_Msk
10341 #define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                /*!< 0x00000001 */
10342 #define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                /*!< 0x00000002 */
10343 #define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                /*!< 0x00000004 */
10344 #define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                /*!< 0x00000008 */
10345 
10346 /********************  Bits definition for RTC_CR register  *******************/
10347 #define RTC_CR_ITSE_Pos                (24U)
10348 #define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
10349 #define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
10350 #define RTC_CR_COE_Pos                 (23U)
10351 #define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
10352 #define RTC_CR_COE                     RTC_CR_COE_Msk
10353 #define RTC_CR_OSEL_Pos                (21U)
10354 #define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
10355 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
10356 #define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)              /*!< 0x00200000 */
10357 #define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)              /*!< 0x00400000 */
10358 #define RTC_CR_POL_Pos                 (20U)
10359 #define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
10360 #define RTC_CR_POL                     RTC_CR_POL_Msk
10361 #define RTC_CR_COSEL_Pos               (19U)
10362 #define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
10363 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
10364 #define RTC_CR_BKP_Pos                 (18U)
10365 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
10366 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
10367 #define RTC_CR_SUB1H_Pos               (17U)
10368 #define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
10369 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
10370 #define RTC_CR_ADD1H_Pos               (16U)
10371 #define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
10372 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
10373 #define RTC_CR_TSIE_Pos                (15U)
10374 #define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
10375 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
10376 #define RTC_CR_WUTIE_Pos               (14U)
10377 #define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
10378 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
10379 #define RTC_CR_ALRBIE_Pos              (13U)
10380 #define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
10381 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
10382 #define RTC_CR_ALRAIE_Pos              (12U)
10383 #define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
10384 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
10385 #define RTC_CR_TSE_Pos                 (11U)
10386 #define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
10387 #define RTC_CR_TSE                     RTC_CR_TSE_Msk
10388 #define RTC_CR_WUTE_Pos                (10U)
10389 #define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
10390 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
10391 #define RTC_CR_ALRBE_Pos               (9U)
10392 #define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
10393 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
10394 #define RTC_CR_ALRAE_Pos               (8U)
10395 #define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
10396 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
10397 #define RTC_CR_FMT_Pos                 (6U)
10398 #define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
10399 #define RTC_CR_FMT                     RTC_CR_FMT_Msk
10400 #define RTC_CR_BYPSHAD_Pos             (5U)
10401 #define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
10402 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
10403 #define RTC_CR_REFCKON_Pos             (4U)
10404 #define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
10405 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
10406 #define RTC_CR_TSEDGE_Pos              (3U)
10407 #define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
10408 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
10409 #define RTC_CR_WUCKSEL_Pos             (0U)
10410 #define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
10411 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
10412 #define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000001 */
10413 #define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000002 */
10414 #define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000004 */
10415 
10416 /* Legacy defines */
10417 #define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
10418 #define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
10419 #define RTC_CR_BCK                     RTC_CR_BKP
10420 
10421 /********************  Bits definition for RTC_ISR register  ******************/
10422 #define RTC_ISR_ITSF_Pos               (17U)
10423 #define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
10424 #define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
10425 #define RTC_ISR_RECALPF_Pos            (16U)
10426 #define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
10427 #define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
10428 #define RTC_ISR_TAMP3F_Pos             (15U)
10429 #define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
10430 #define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
10431 #define RTC_ISR_TAMP2F_Pos             (14U)
10432 #define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
10433 #define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
10434 #define RTC_ISR_TAMP1F_Pos             (13U)
10435 #define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
10436 #define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
10437 #define RTC_ISR_TSOVF_Pos              (12U)
10438 #define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
10439 #define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
10440 #define RTC_ISR_TSF_Pos                (11U)
10441 #define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
10442 #define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
10443 #define RTC_ISR_WUTF_Pos               (10U)
10444 #define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
10445 #define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
10446 #define RTC_ISR_ALRBF_Pos              (9U)
10447 #define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
10448 #define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
10449 #define RTC_ISR_ALRAF_Pos              (8U)
10450 #define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
10451 #define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
10452 #define RTC_ISR_INIT_Pos               (7U)
10453 #define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
10454 #define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
10455 #define RTC_ISR_INITF_Pos              (6U)
10456 #define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
10457 #define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
10458 #define RTC_ISR_RSF_Pos                (5U)
10459 #define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
10460 #define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
10461 #define RTC_ISR_INITS_Pos              (4U)
10462 #define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
10463 #define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
10464 #define RTC_ISR_SHPF_Pos               (3U)
10465 #define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
10466 #define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
10467 #define RTC_ISR_WUTWF_Pos              (2U)
10468 #define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
10469 #define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
10470 #define RTC_ISR_ALRBWF_Pos             (1U)
10471 #define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
10472 #define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
10473 #define RTC_ISR_ALRAWF_Pos             (0U)
10474 #define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
10475 #define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
10476 
10477 /********************  Bits definition for RTC_PRER register  *****************/
10478 #define RTC_PRER_PREDIV_A_Pos          (16U)
10479 #define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
10480 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
10481 #define RTC_PRER_PREDIV_S_Pos          (0U)
10482 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
10483 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
10484 
10485 /********************  Bits definition for RTC_WUTR register  *****************/
10486 #define RTC_WUTR_WUT_Pos               (0U)
10487 #define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
10488 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
10489 
10490 /********************  Bits definition for RTC_ALRMAR register  ***************/
10491 #define RTC_ALRMAR_MSK4_Pos            (31U)
10492 #define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
10493 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
10494 #define RTC_ALRMAR_WDSEL_Pos           (30U)
10495 #define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
10496 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
10497 #define RTC_ALRMAR_DT_Pos              (28U)
10498 #define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
10499 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
10500 #define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)            /*!< 0x10000000 */
10501 #define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)            /*!< 0x20000000 */
10502 #define RTC_ALRMAR_DU_Pos              (24U)
10503 #define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
10504 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
10505 #define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)            /*!< 0x01000000 */
10506 #define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)            /*!< 0x02000000 */
10507 #define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)            /*!< 0x04000000 */
10508 #define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)            /*!< 0x08000000 */
10509 #define RTC_ALRMAR_MSK3_Pos            (23U)
10510 #define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
10511 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
10512 #define RTC_ALRMAR_PM_Pos              (22U)
10513 #define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
10514 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
10515 #define RTC_ALRMAR_HT_Pos              (20U)
10516 #define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
10517 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
10518 #define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00100000 */
10519 #define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00200000 */
10520 #define RTC_ALRMAR_HU_Pos              (16U)
10521 #define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
10522 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
10523 #define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00010000 */
10524 #define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00020000 */
10525 #define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00040000 */
10526 #define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)            /*!< 0x00080000 */
10527 #define RTC_ALRMAR_MSK2_Pos            (15U)
10528 #define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
10529 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
10530 #define RTC_ALRMAR_MNT_Pos             (12U)
10531 #define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
10532 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
10533 #define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00001000 */
10534 #define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00002000 */
10535 #define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00004000 */
10536 #define RTC_ALRMAR_MNU_Pos             (8U)
10537 #define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
10538 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
10539 #define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000100 */
10540 #define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000200 */
10541 #define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000400 */
10542 #define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000800 */
10543 #define RTC_ALRMAR_MSK1_Pos            (7U)
10544 #define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
10545 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
10546 #define RTC_ALRMAR_ST_Pos              (4U)
10547 #define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
10548 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
10549 #define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000010 */
10550 #define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000020 */
10551 #define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000040 */
10552 #define RTC_ALRMAR_SU_Pos              (0U)
10553 #define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
10554 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
10555 #define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000001 */
10556 #define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000002 */
10557 #define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000004 */
10558 #define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)            /*!< 0x00000008 */
10559 
10560 /********************  Bits definition for RTC_ALRMBR register  ***************/
10561 #define RTC_ALRMBR_MSK4_Pos            (31U)
10562 #define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
10563 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
10564 #define RTC_ALRMBR_WDSEL_Pos           (30U)
10565 #define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
10566 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
10567 #define RTC_ALRMBR_DT_Pos              (28U)
10568 #define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
10569 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
10570 #define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)            /*!< 0x10000000 */
10571 #define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)            /*!< 0x20000000 */
10572 #define RTC_ALRMBR_DU_Pos              (24U)
10573 #define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
10574 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
10575 #define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)            /*!< 0x01000000 */
10576 #define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)            /*!< 0x02000000 */
10577 #define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)            /*!< 0x04000000 */
10578 #define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)            /*!< 0x08000000 */
10579 #define RTC_ALRMBR_MSK3_Pos            (23U)
10580 #define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
10581 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
10582 #define RTC_ALRMBR_PM_Pos              (22U)
10583 #define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
10584 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
10585 #define RTC_ALRMBR_HT_Pos              (20U)
10586 #define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
10587 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
10588 #define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00100000 */
10589 #define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00200000 */
10590 #define RTC_ALRMBR_HU_Pos              (16U)
10591 #define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
10592 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
10593 #define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00010000 */
10594 #define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00020000 */
10595 #define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00040000 */
10596 #define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)            /*!< 0x00080000 */
10597 #define RTC_ALRMBR_MSK2_Pos            (15U)
10598 #define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
10599 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
10600 #define RTC_ALRMBR_MNT_Pos             (12U)
10601 #define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
10602 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
10603 #define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00001000 */
10604 #define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00002000 */
10605 #define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00004000 */
10606 #define RTC_ALRMBR_MNU_Pos             (8U)
10607 #define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
10608 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
10609 #define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000100 */
10610 #define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000200 */
10611 #define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000400 */
10612 #define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000800 */
10613 #define RTC_ALRMBR_MSK1_Pos            (7U)
10614 #define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
10615 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
10616 #define RTC_ALRMBR_ST_Pos              (4U)
10617 #define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
10618 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
10619 #define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000010 */
10620 #define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000020 */
10621 #define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000040 */
10622 #define RTC_ALRMBR_SU_Pos              (0U)
10623 #define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
10624 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
10625 #define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000001 */
10626 #define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000002 */
10627 #define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000004 */
10628 #define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)            /*!< 0x00000008 */
10629 
10630 /********************  Bits definition for RTC_WPR register  ******************/
10631 #define RTC_WPR_KEY_Pos                (0U)
10632 #define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
10633 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
10634 
10635 /********************  Bits definition for RTC_SSR register  ******************/
10636 #define RTC_SSR_SS_Pos                 (0U)
10637 #define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
10638 #define RTC_SSR_SS                     RTC_SSR_SS_Msk
10639 
10640 /********************  Bits definition for RTC_SHIFTR register  ***************/
10641 #define RTC_SHIFTR_SUBFS_Pos           (0U)
10642 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
10643 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
10644 #define RTC_SHIFTR_ADD1S_Pos           (31U)
10645 #define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
10646 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
10647 
10648 /********************  Bits definition for RTC_TSTR register  *****************/
10649 #define RTC_TSTR_PM_Pos                (22U)
10650 #define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
10651 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
10652 #define RTC_TSTR_HT_Pos                (20U)
10653 #define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
10654 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
10655 #define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)              /*!< 0x00100000 */
10656 #define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)              /*!< 0x00200000 */
10657 #define RTC_TSTR_HU_Pos                (16U)
10658 #define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
10659 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
10660 #define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)              /*!< 0x00010000 */
10661 #define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)              /*!< 0x00020000 */
10662 #define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)              /*!< 0x00040000 */
10663 #define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)              /*!< 0x00080000 */
10664 #define RTC_TSTR_MNT_Pos               (12U)
10665 #define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
10666 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
10667 #define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)             /*!< 0x00001000 */
10668 #define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)             /*!< 0x00002000 */
10669 #define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)             /*!< 0x00004000 */
10670 #define RTC_TSTR_MNU_Pos               (8U)
10671 #define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
10672 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
10673 #define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000100 */
10674 #define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000200 */
10675 #define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000400 */
10676 #define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)             /*!< 0x00000800 */
10677 #define RTC_TSTR_ST_Pos                (4U)
10678 #define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
10679 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
10680 #define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)              /*!< 0x00000010 */
10681 #define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)              /*!< 0x00000020 */
10682 #define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)              /*!< 0x00000040 */
10683 #define RTC_TSTR_SU_Pos                (0U)
10684 #define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
10685 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
10686 #define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)              /*!< 0x00000001 */
10687 #define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)              /*!< 0x00000002 */
10688 #define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)              /*!< 0x00000004 */
10689 #define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)              /*!< 0x00000008 */
10690 
10691 /********************  Bits definition for RTC_TSDR register  *****************/
10692 #define RTC_TSDR_WDU_Pos               (13U)
10693 #define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
10694 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
10695 #define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)             /*!< 0x00002000 */
10696 #define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)             /*!< 0x00004000 */
10697 #define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)             /*!< 0x00008000 */
10698 #define RTC_TSDR_MT_Pos                (12U)
10699 #define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
10700 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
10701 #define RTC_TSDR_MU_Pos                (8U)
10702 #define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
10703 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
10704 #define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)              /*!< 0x00000100 */
10705 #define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)              /*!< 0x00000200 */
10706 #define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)              /*!< 0x00000400 */
10707 #define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)              /*!< 0x00000800 */
10708 #define RTC_TSDR_DT_Pos                (4U)
10709 #define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
10710 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
10711 #define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)              /*!< 0x00000010 */
10712 #define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)              /*!< 0x00000020 */
10713 #define RTC_TSDR_DU_Pos                (0U)
10714 #define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
10715 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
10716 #define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)              /*!< 0x00000001 */
10717 #define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)              /*!< 0x00000002 */
10718 #define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)              /*!< 0x00000004 */
10719 #define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)              /*!< 0x00000008 */
10720 
10721 /********************  Bits definition for RTC_TSSSR register  ****************/
10722 #define RTC_TSSSR_SS_Pos               (0U)
10723 #define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
10724 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
10725 
10726 /********************  Bits definition for RTC_CAL register  *****************/
10727 #define RTC_CALR_CALP_Pos              (15U)
10728 #define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
10729 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
10730 #define RTC_CALR_CALW8_Pos             (14U)
10731 #define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
10732 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
10733 #define RTC_CALR_CALW16_Pos            (13U)
10734 #define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
10735 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
10736 #define RTC_CALR_CALM_Pos              (0U)
10737 #define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
10738 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
10739 #define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)          /*!< 0x00000001 */
10740 #define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)          /*!< 0x00000002 */
10741 #define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)          /*!< 0x00000004 */
10742 #define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)          /*!< 0x00000008 */
10743 #define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)          /*!< 0x00000010 */
10744 #define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)          /*!< 0x00000020 */
10745 #define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)          /*!< 0x00000040 */
10746 #define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)          /*!< 0x00000080 */
10747 #define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)          /*!< 0x00000100 */
10748 
10749 /********************  Bits definition for RTC_TAMPCR register  ***************/
10750 #define RTC_TAMPCR_TAMP3MF_Pos         (24U)
10751 #define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
10752 #define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
10753 #define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
10754 #define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
10755 #define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
10756 #define RTC_TAMPCR_TAMP3IE_Pos         (22U)
10757 #define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
10758 #define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
10759 #define RTC_TAMPCR_TAMP2MF_Pos         (21U)
10760 #define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
10761 #define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
10762 #define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
10763 #define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
10764 #define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
10765 #define RTC_TAMPCR_TAMP2IE_Pos         (19U)
10766 #define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
10767 #define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
10768 #define RTC_TAMPCR_TAMP1MF_Pos         (18U)
10769 #define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
10770 #define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
10771 #define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
10772 #define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
10773 #define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
10774 #define RTC_TAMPCR_TAMP1IE_Pos         (16U)
10775 #define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
10776 #define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
10777 #define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
10778 #define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
10779 #define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
10780 #define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
10781 #define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
10782 #define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
10783 #define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00002000 */
10784 #define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00004000 */
10785 #define RTC_TAMPCR_TAMPFLT_Pos         (11U)
10786 #define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
10787 #define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
10788 #define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00000800 */
10789 #define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001000 */
10790 #define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
10791 #define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
10792 #define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
10793 #define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000100 */
10794 #define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000200 */
10795 #define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000400 */
10796 #define RTC_TAMPCR_TAMPTS_Pos          (7U)
10797 #define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
10798 #define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
10799 #define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
10800 #define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
10801 #define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
10802 #define RTC_TAMPCR_TAMP3E_Pos          (5U)
10803 #define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
10804 #define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
10805 #define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
10806 #define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
10807 #define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
10808 #define RTC_TAMPCR_TAMP2E_Pos          (3U)
10809 #define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
10810 #define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
10811 #define RTC_TAMPCR_TAMPIE_Pos          (2U)
10812 #define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
10813 #define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
10814 #define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
10815 #define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
10816 #define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
10817 #define RTC_TAMPCR_TAMP1E_Pos          (0U)
10818 #define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
10819 #define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
10820 
10821 /********************  Bits definition for RTC_ALRMASSR register  *************/
10822 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
10823 #define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
10824 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
10825 #define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x01000000 */
10826 #define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x02000000 */
10827 #define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x04000000 */
10828 #define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x08000000 */
10829 #define RTC_ALRMASSR_SS_Pos            (0U)
10830 #define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
10831 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
10832 
10833 /********************  Bits definition for RTC_ALRMBSSR register  *************/
10834 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
10835 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
10836 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
10837 #define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x01000000 */
10838 #define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x02000000 */
10839 #define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x04000000 */
10840 #define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x08000000 */
10841 #define RTC_ALRMBSSR_SS_Pos            (0U)
10842 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
10843 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
10844 
10845 /********************  Bits definition for RTC_0R register  *******************/
10846 #define RTC_OR_OUT_RMP_Pos             (1U)
10847 #define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
10848 #define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
10849 #define RTC_OR_ALARMOUTTYPE_Pos        (0U)
10850 #define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
10851 #define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
10852 
10853 
10854 /********************  Bits definition for RTC_BKP0R register  ****************/
10855 #define RTC_BKP0R_Pos                  (0U)
10856 #define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
10857 #define RTC_BKP0R                      RTC_BKP0R_Msk
10858 
10859 /********************  Bits definition for RTC_BKP1R register  ****************/
10860 #define RTC_BKP1R_Pos                  (0U)
10861 #define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
10862 #define RTC_BKP1R                      RTC_BKP1R_Msk
10863 
10864 /********************  Bits definition for RTC_BKP2R register  ****************/
10865 #define RTC_BKP2R_Pos                  (0U)
10866 #define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
10867 #define RTC_BKP2R                      RTC_BKP2R_Msk
10868 
10869 /********************  Bits definition for RTC_BKP3R register  ****************/
10870 #define RTC_BKP3R_Pos                  (0U)
10871 #define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
10872 #define RTC_BKP3R                      RTC_BKP3R_Msk
10873 
10874 /********************  Bits definition for RTC_BKP4R register  ****************/
10875 #define RTC_BKP4R_Pos                  (0U)
10876 #define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
10877 #define RTC_BKP4R                      RTC_BKP4R_Msk
10878 
10879 /********************  Bits definition for RTC_BKP5R register  ****************/
10880 #define RTC_BKP5R_Pos                  (0U)
10881 #define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
10882 #define RTC_BKP5R                      RTC_BKP5R_Msk
10883 
10884 /********************  Bits definition for RTC_BKP6R register  ****************/
10885 #define RTC_BKP6R_Pos                  (0U)
10886 #define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
10887 #define RTC_BKP6R                      RTC_BKP6R_Msk
10888 
10889 /********************  Bits definition for RTC_BKP7R register  ****************/
10890 #define RTC_BKP7R_Pos                  (0U)
10891 #define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
10892 #define RTC_BKP7R                      RTC_BKP7R_Msk
10893 
10894 /********************  Bits definition for RTC_BKP8R register  ****************/
10895 #define RTC_BKP8R_Pos                  (0U)
10896 #define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
10897 #define RTC_BKP8R                      RTC_BKP8R_Msk
10898 
10899 /********************  Bits definition for RTC_BKP9R register  ****************/
10900 #define RTC_BKP9R_Pos                  (0U)
10901 #define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
10902 #define RTC_BKP9R                      RTC_BKP9R_Msk
10903 
10904 /********************  Bits definition for RTC_BKP10R register  ***************/
10905 #define RTC_BKP10R_Pos                 (0U)
10906 #define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
10907 #define RTC_BKP10R                     RTC_BKP10R_Msk
10908 
10909 /********************  Bits definition for RTC_BKP11R register  ***************/
10910 #define RTC_BKP11R_Pos                 (0U)
10911 #define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
10912 #define RTC_BKP11R                     RTC_BKP11R_Msk
10913 
10914 /********************  Bits definition for RTC_BKP12R register  ***************/
10915 #define RTC_BKP12R_Pos                 (0U)
10916 #define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
10917 #define RTC_BKP12R                     RTC_BKP12R_Msk
10918 
10919 /********************  Bits definition for RTC_BKP13R register  ***************/
10920 #define RTC_BKP13R_Pos                 (0U)
10921 #define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
10922 #define RTC_BKP13R                     RTC_BKP13R_Msk
10923 
10924 /********************  Bits definition for RTC_BKP14R register  ***************/
10925 #define RTC_BKP14R_Pos                 (0U)
10926 #define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
10927 #define RTC_BKP14R                     RTC_BKP14R_Msk
10928 
10929 /********************  Bits definition for RTC_BKP15R register  ***************/
10930 #define RTC_BKP15R_Pos                 (0U)
10931 #define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
10932 #define RTC_BKP15R                     RTC_BKP15R_Msk
10933 
10934 /********************  Bits definition for RTC_BKP16R register  ***************/
10935 #define RTC_BKP16R_Pos                 (0U)
10936 #define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
10937 #define RTC_BKP16R                     RTC_BKP16R_Msk
10938 
10939 /********************  Bits definition for RTC_BKP17R register  ***************/
10940 #define RTC_BKP17R_Pos                 (0U)
10941 #define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
10942 #define RTC_BKP17R                     RTC_BKP17R_Msk
10943 
10944 /********************  Bits definition for RTC_BKP18R register  ***************/
10945 #define RTC_BKP18R_Pos                 (0U)
10946 #define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
10947 #define RTC_BKP18R                     RTC_BKP18R_Msk
10948 
10949 /********************  Bits definition for RTC_BKP19R register  ***************/
10950 #define RTC_BKP19R_Pos                 (0U)
10951 #define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
10952 #define RTC_BKP19R                     RTC_BKP19R_Msk
10953 
10954 /********************  Bits definition for RTC_BKP20R register  ***************/
10955 #define RTC_BKP20R_Pos                 (0U)
10956 #define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
10957 #define RTC_BKP20R                     RTC_BKP20R_Msk
10958 
10959 /********************  Bits definition for RTC_BKP21R register  ***************/
10960 #define RTC_BKP21R_Pos                 (0U)
10961 #define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
10962 #define RTC_BKP21R                     RTC_BKP21R_Msk
10963 
10964 /********************  Bits definition for RTC_BKP22R register  ***************/
10965 #define RTC_BKP22R_Pos                 (0U)
10966 #define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
10967 #define RTC_BKP22R                     RTC_BKP22R_Msk
10968 
10969 /********************  Bits definition for RTC_BKP23R register  ***************/
10970 #define RTC_BKP23R_Pos                 (0U)
10971 #define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
10972 #define RTC_BKP23R                     RTC_BKP23R_Msk
10973 
10974 /********************  Bits definition for RTC_BKP24R register  ***************/
10975 #define RTC_BKP24R_Pos                 (0U)
10976 #define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
10977 #define RTC_BKP24R                     RTC_BKP24R_Msk
10978 
10979 /********************  Bits definition for RTC_BKP25R register  ***************/
10980 #define RTC_BKP25R_Pos                 (0U)
10981 #define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
10982 #define RTC_BKP25R                     RTC_BKP25R_Msk
10983 
10984 /********************  Bits definition for RTC_BKP26R register  ***************/
10985 #define RTC_BKP26R_Pos                 (0U)
10986 #define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
10987 #define RTC_BKP26R                     RTC_BKP26R_Msk
10988 
10989 /********************  Bits definition for RTC_BKP27R register  ***************/
10990 #define RTC_BKP27R_Pos                 (0U)
10991 #define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
10992 #define RTC_BKP27R                     RTC_BKP27R_Msk
10993 
10994 /********************  Bits definition for RTC_BKP28R register  ***************/
10995 #define RTC_BKP28R_Pos                 (0U)
10996 #define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
10997 #define RTC_BKP28R                     RTC_BKP28R_Msk
10998 
10999 /********************  Bits definition for RTC_BKP29R register  ***************/
11000 #define RTC_BKP29R_Pos                 (0U)
11001 #define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
11002 #define RTC_BKP29R                     RTC_BKP29R_Msk
11003 
11004 /********************  Bits definition for RTC_BKP30R register  ***************/
11005 #define RTC_BKP30R_Pos                 (0U)
11006 #define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
11007 #define RTC_BKP30R                     RTC_BKP30R_Msk
11008 
11009 /********************  Bits definition for RTC_BKP31R register  ***************/
11010 #define RTC_BKP31R_Pos                 (0U)
11011 #define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
11012 #define RTC_BKP31R                     RTC_BKP31R_Msk
11013 
11014 /******************************************************************************/
11015 /*                                                                            */
11016 /*                          Serial Audio Interface                            */
11017 /*                                                                            */
11018 /******************************************************************************/
11019 /********************  Bit definition for SAI_GCR register  *******************/
11020 #define SAI_GCR_SYNCIN_Pos         (0U)
11021 #define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
11022 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
11023 #define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000001 */
11024 #define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000002 */
11025 
11026 #define SAI_GCR_SYNCOUT_Pos        (4U)
11027 #define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
11028 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
11029 #define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000010 */
11030 #define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000020 */
11031 
11032 /*******************  Bit definition for SAI_xCR1 register  *******************/
11033 #define SAI_xCR1_MODE_Pos          (0U)
11034 #define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
11035 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
11036 #define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000001 */
11037 #define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000002 */
11038 
11039 #define SAI_xCR1_PRTCFG_Pos        (2U)
11040 #define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
11041 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
11042 #define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000004 */
11043 #define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x00000008 */
11044 
11045 #define SAI_xCR1_DS_Pos            (5U)
11046 #define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
11047 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
11048 #define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000020 */
11049 #define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000040 */
11050 #define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                  /*!< 0x00000080 */
11051 
11052 #define SAI_xCR1_LSBFIRST_Pos      (8U)
11053 #define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
11054 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
11055 #define SAI_xCR1_CKSTR_Pos         (9U)
11056 #define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
11057 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
11058 
11059 #define SAI_xCR1_SYNCEN_Pos        (10U)
11060 #define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
11061 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
11062 #define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000400 */
11063 #define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000800 */
11064 
11065 #define SAI_xCR1_MONO_Pos          (12U)
11066 #define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
11067 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
11068 #define SAI_xCR1_OUTDRIV_Pos       (13U)
11069 #define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
11070 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
11071 #define SAI_xCR1_SAIEN_Pos         (16U)
11072 #define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
11073 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
11074 #define SAI_xCR1_DMAEN_Pos         (17U)
11075 #define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
11076 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
11077 #define SAI_xCR1_NODIV_Pos         (19U)
11078 #define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
11079 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
11080 
11081 #define SAI_xCR1_MCKDIV_Pos        (20U)
11082 #define SAI_xCR1_MCKDIV_Msk        (0xFUL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00F00000 */
11083 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
11084 #define SAI_xCR1_MCKDIV_0          (0x1UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
11085 #define SAI_xCR1_MCKDIV_1          (0x2UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
11086 #define SAI_xCR1_MCKDIV_2          (0x4UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
11087 #define SAI_xCR1_MCKDIV_3          (0x8UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
11088 
11089 /*******************  Bit definition for SAI_xCR2 register  *******************/
11090 #define SAI_xCR2_FTH_Pos           (0U)
11091 #define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
11092 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
11093 #define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000001 */
11094 #define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000002 */
11095 #define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000004 */
11096 
11097 #define SAI_xCR2_FFLUSH_Pos        (3U)
11098 #define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
11099 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
11100 #define SAI_xCR2_TRIS_Pos          (4U)
11101 #define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
11102 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
11103 #define SAI_xCR2_MUTE_Pos          (5U)
11104 #define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
11105 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
11106 #define SAI_xCR2_MUTEVAL_Pos       (6U)
11107 #define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
11108 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
11109 
11110 
11111 #define SAI_xCR2_MUTECNT_Pos       (7U)
11112 #define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
11113 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
11114 #define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000080 */
11115 #define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000100 */
11116 #define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000200 */
11117 #define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000400 */
11118 #define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00000800 */
11119 #define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001000 */
11120 
11121 #define SAI_xCR2_CPL_Pos           (13U)
11122 #define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
11123 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
11124 #define SAI_xCR2_COMP_Pos          (14U)
11125 #define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
11126 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
11127 #define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                /*!< 0x00004000 */
11128 #define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                /*!< 0x00008000 */
11129 
11130 
11131 /******************  Bit definition for SAI_xFRCR register  *******************/
11132 #define SAI_xFRCR_FRL_Pos          (0U)
11133 #define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
11134 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
11135 #define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000001 */
11136 #define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000002 */
11137 #define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000004 */
11138 #define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000008 */
11139 #define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000010 */
11140 #define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000020 */
11141 #define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000040 */
11142 #define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)               /*!< 0x00000080 */
11143 
11144 #define SAI_xFRCR_FSALL_Pos        (8U)
11145 #define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
11146 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
11147 #define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000100 */
11148 #define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000200 */
11149 #define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000400 */
11150 #define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00000800 */
11151 #define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00001000 */
11152 #define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00002000 */
11153 #define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00004000 */
11154 
11155 #define SAI_xFRCR_FSDEF_Pos        (16U)
11156 #define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
11157 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
11158 #define SAI_xFRCR_FSPOL_Pos        (17U)
11159 #define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
11160 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
11161 #define SAI_xFRCR_FSOFF_Pos        (18U)
11162 #define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
11163 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
11164 
11165 /******************  Bit definition for SAI_xSLOTR register  *******************/
11166 #define SAI_xSLOTR_FBOFF_Pos       (0U)
11167 #define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
11168 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
11169 #define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000001 */
11170 #define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000002 */
11171 #define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000004 */
11172 #define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000008 */
11173 #define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x00000010 */
11174 
11175 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
11176 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
11177 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
11178 #define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000040 */
11179 #define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x00000080 */
11180 
11181 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
11182 #define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
11183 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
11184 #define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000100 */
11185 #define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000200 */
11186 #define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000400 */
11187 #define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000800 */
11188 
11189 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
11190 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
11191 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
11192 
11193 /*******************  Bit definition for SAI_xIMR register  *******************/
11194 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
11195 #define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
11196 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
11197 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
11198 #define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
11199 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
11200 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
11201 #define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
11202 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
11203 #define SAI_xIMR_FREQIE_Pos        (3U)
11204 #define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
11205 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
11206 #define SAI_xIMR_CNRDYIE_Pos       (4U)
11207 #define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
11208 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
11209 #define SAI_xIMR_AFSDETIE_Pos      (5U)
11210 #define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
11211 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
11212 #define SAI_xIMR_LFSDETIE_Pos      (6U)
11213 #define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
11214 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
11215 
11216 /********************  Bit definition for SAI_xSR register  *******************/
11217 #define SAI_xSR_OVRUDR_Pos         (0U)
11218 #define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
11219 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
11220 #define SAI_xSR_MUTEDET_Pos        (1U)
11221 #define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
11222 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
11223 #define SAI_xSR_WCKCFG_Pos         (2U)
11224 #define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
11225 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
11226 #define SAI_xSR_FREQ_Pos           (3U)
11227 #define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
11228 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
11229 #define SAI_xSR_CNRDY_Pos          (4U)
11230 #define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
11231 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
11232 #define SAI_xSR_AFSDET_Pos         (5U)
11233 #define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
11234 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
11235 #define SAI_xSR_LFSDET_Pos         (6U)
11236 #define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
11237 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
11238 
11239 #define SAI_xSR_FLVL_Pos           (16U)
11240 #define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
11241 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
11242 #define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00010000 */
11243 #define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00020000 */
11244 #define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00040000 */
11245 
11246 /******************  Bit definition for SAI_xCLRFR register  ******************/
11247 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
11248 #define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
11249 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
11250 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
11251 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
11252 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
11253 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
11254 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
11255 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
11256 #define SAI_xCLRFR_CFREQ_Pos       (3U)
11257 #define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
11258 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
11259 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
11260 #define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
11261 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
11262 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
11263 #define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
11264 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
11265 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
11266 #define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
11267 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
11268 
11269 /******************  Bit definition for SAI_xDR register  ******************/
11270 #define SAI_xDR_DATA_Pos           (0U)
11271 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
11272 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
11273 
11274 /******************************************************************************/
11275 /*                                                                            */
11276 /*                           SDMMC Interface                                  */
11277 /*                                                                            */
11278 /******************************************************************************/
11279 /******************  Bit definition for SDMMC_POWER register  ******************/
11280 #define SDMMC_POWER_PWRCTRL_Pos         (0U)
11281 #define SDMMC_POWER_PWRCTRL_Msk         (0x3UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000003 */
11282 #define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
11283 #define SDMMC_POWER_PWRCTRL_0           (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
11284 #define SDMMC_POWER_PWRCTRL_1           (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
11285 
11286 /******************  Bit definition for SDMMC_CLKCR register  ******************/
11287 #define SDMMC_CLKCR_CLKDIV_Pos          (0U)
11288 #define SDMMC_CLKCR_CLKDIV_Msk          (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)     /*!< 0x000000FF */
11289 #define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
11290 #define SDMMC_CLKCR_CLKEN_Pos           (8U)
11291 #define SDMMC_CLKCR_CLKEN_Msk           (0x1UL << SDMMC_CLKCR_CLKEN_Pos)       /*!< 0x00000100 */
11292 #define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
11293 #define SDMMC_CLKCR_PWRSAV_Pos          (9U)
11294 #define SDMMC_CLKCR_PWRSAV_Msk          (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)      /*!< 0x00000200 */
11295 #define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
11296 #define SDMMC_CLKCR_BYPASS_Pos          (10U)
11297 #define SDMMC_CLKCR_BYPASS_Msk          (0x1UL << SDMMC_CLKCR_BYPASS_Pos)      /*!< 0x00000400 */
11298 #define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
11299 
11300 #define SDMMC_CLKCR_WIDBUS_Pos          (11U)
11301 #define SDMMC_CLKCR_WIDBUS_Msk          (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001800 */
11302 #define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
11303 #define SDMMC_CLKCR_WIDBUS_0            (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00000800 */
11304 #define SDMMC_CLKCR_WIDBUS_1            (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00001000 */
11305 
11306 #define SDMMC_CLKCR_NEGEDGE_Pos         (13U)
11307 #define SDMMC_CLKCR_NEGEDGE_Msk         (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)     /*!< 0x00002000 */
11308 #define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
11309 #define SDMMC_CLKCR_HWFC_EN_Pos         (14U)
11310 #define SDMMC_CLKCR_HWFC_EN_Msk         (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)     /*!< 0x00004000 */
11311 #define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
11312 
11313 /*******************  Bit definition for SDMMC_ARG register  *******************/
11314 #define SDMMC_ARG_CMDARG_Pos            (0U)
11315 #define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
11316 #define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
11317 
11318 /*******************  Bit definition for SDMMC_CMD register  *******************/
11319 #define SDMMC_CMD_CMDINDEX_Pos          (0U)
11320 #define SDMMC_CMD_CMDINDEX_Msk          (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)     /*!< 0x0000003F */
11321 #define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
11322 
11323 #define SDMMC_CMD_WAITRESP_Pos          (6U)
11324 #define SDMMC_CMD_WAITRESP_Msk          (0x3UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x000000C0 */
11325 #define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
11326 #define SDMMC_CMD_WAITRESP_0            (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000040 */
11327 #define SDMMC_CMD_WAITRESP_1            (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000080 */
11328 
11329 #define SDMMC_CMD_WAITINT_Pos           (8U)
11330 #define SDMMC_CMD_WAITINT_Msk           (0x1UL << SDMMC_CMD_WAITINT_Pos)       /*!< 0x00000100 */
11331 #define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
11332 #define SDMMC_CMD_WAITPEND_Pos          (9U)
11333 #define SDMMC_CMD_WAITPEND_Msk          (0x1UL << SDMMC_CMD_WAITPEND_Pos)      /*!< 0x00000200 */
11334 #define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
11335 #define SDMMC_CMD_CPSMEN_Pos            (10U)
11336 #define SDMMC_CMD_CPSMEN_Msk            (0x1UL << SDMMC_CMD_CPSMEN_Pos)        /*!< 0x00000400 */
11337 #define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
11338 #define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)
11339 #define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)   /*!< 0x00000800 */
11340 #define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
11341 
11342 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
11343 #define SDMMC_RESPCMD_RESPCMD_Pos       (0U)
11344 #define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)  /*!< 0x0000003F */
11345 #define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
11346 
11347 /******************  Bit definition for SDMMC_RESP1 register  ******************/
11348 #define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)
11349 #define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
11350 #define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
11351 
11352 /******************  Bit definition for SDMMC_RESP2 register  ******************/
11353 #define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)
11354 #define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
11355 #define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
11356 
11357 /******************  Bit definition for SDMMC_RESP3 register  ******************/
11358 #define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)
11359 #define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
11360 #define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
11361 
11362 /******************  Bit definition for SDMMC_RESP4 register  ******************/
11363 #define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)
11364 #define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
11365 #define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
11366 
11367 /******************  Bit definition for SDMMC_DTIMER register  *****************/
11368 #define SDMMC_DTIMER_DATATIME_Pos       (0U)
11369 #define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
11370 #define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
11371 
11372 /******************  Bit definition for SDMMC_DLEN register  *******************/
11373 #define SDMMC_DLEN_DATALENGTH_Pos       (0U)
11374 #define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
11375 #define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
11376 
11377 /******************  Bit definition for SDMMC_DCTRL register  ******************/
11378 #define SDMMC_DCTRL_DTEN_Pos            (0U)
11379 #define SDMMC_DCTRL_DTEN_Msk            (0x1UL << SDMMC_DCTRL_DTEN_Pos)        /*!< 0x00000001 */
11380 #define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
11381 #define SDMMC_DCTRL_DTDIR_Pos           (1U)
11382 #define SDMMC_DCTRL_DTDIR_Msk           (0x1UL << SDMMC_DCTRL_DTDIR_Pos)       /*!< 0x00000002 */
11383 #define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
11384 #define SDMMC_DCTRL_DTMODE_Pos          (2U)
11385 #define SDMMC_DCTRL_DTMODE_Msk          (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
11386 #define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
11387 #define SDMMC_DCTRL_DMAEN_Pos           (3U)
11388 #define SDMMC_DCTRL_DMAEN_Msk           (0x1UL << SDMMC_DCTRL_DMAEN_Pos)       /*!< 0x00000008 */
11389 #define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
11390 
11391 #define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)
11392 #define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x000000F0 */
11393 #define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
11394 #define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
11395 #define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
11396 #define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
11397 #define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
11398 
11399 #define SDMMC_DCTRL_RWSTART_Pos         (8U)
11400 #define SDMMC_DCTRL_RWSTART_Msk         (0x1UL << SDMMC_DCTRL_RWSTART_Pos)     /*!< 0x00000100 */
11401 #define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
11402 #define SDMMC_DCTRL_RWSTOP_Pos          (9U)
11403 #define SDMMC_DCTRL_RWSTOP_Msk          (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)      /*!< 0x00000200 */
11404 #define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
11405 #define SDMMC_DCTRL_RWMOD_Pos           (10U)
11406 #define SDMMC_DCTRL_RWMOD_Msk           (0x1UL << SDMMC_DCTRL_RWMOD_Pos)       /*!< 0x00000400 */
11407 #define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
11408 #define SDMMC_DCTRL_SDIOEN_Pos          (11U)
11409 #define SDMMC_DCTRL_SDIOEN_Msk          (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)      /*!< 0x00000800 */
11410 #define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
11411 
11412 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
11413 #define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)
11414 #define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
11415 #define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
11416 
11417 /******************  Bit definition for SDMMC_STA register  ********************/
11418 #define SDMMC_STA_CCRCFAIL_Pos          (0U)
11419 #define SDMMC_STA_CCRCFAIL_Msk          (0x1UL << SDMMC_STA_CCRCFAIL_Pos)      /*!< 0x00000001 */
11420 #define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
11421 #define SDMMC_STA_DCRCFAIL_Pos          (1U)
11422 #define SDMMC_STA_DCRCFAIL_Msk          (0x1UL << SDMMC_STA_DCRCFAIL_Pos)      /*!< 0x00000002 */
11423 #define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
11424 #define SDMMC_STA_CTIMEOUT_Pos          (2U)
11425 #define SDMMC_STA_CTIMEOUT_Msk          (0x1UL << SDMMC_STA_CTIMEOUT_Pos)      /*!< 0x00000004 */
11426 #define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
11427 #define SDMMC_STA_DTIMEOUT_Pos          (3U)
11428 #define SDMMC_STA_DTIMEOUT_Msk          (0x1UL << SDMMC_STA_DTIMEOUT_Pos)      /*!< 0x00000008 */
11429 #define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
11430 #define SDMMC_STA_TXUNDERR_Pos          (4U)
11431 #define SDMMC_STA_TXUNDERR_Msk          (0x1UL << SDMMC_STA_TXUNDERR_Pos)      /*!< 0x00000010 */
11432 #define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
11433 #define SDMMC_STA_RXOVERR_Pos           (5U)
11434 #define SDMMC_STA_RXOVERR_Msk           (0x1UL << SDMMC_STA_RXOVERR_Pos)       /*!< 0x00000020 */
11435 #define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
11436 #define SDMMC_STA_CMDREND_Pos           (6U)
11437 #define SDMMC_STA_CMDREND_Msk           (0x1UL << SDMMC_STA_CMDREND_Pos)       /*!< 0x00000040 */
11438 #define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
11439 #define SDMMC_STA_CMDSENT_Pos           (7U)
11440 #define SDMMC_STA_CMDSENT_Msk           (0x1UL << SDMMC_STA_CMDSENT_Pos)       /*!< 0x00000080 */
11441 #define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
11442 #define SDMMC_STA_DATAEND_Pos           (8U)
11443 #define SDMMC_STA_DATAEND_Msk           (0x1UL << SDMMC_STA_DATAEND_Pos)       /*!< 0x00000100 */
11444 #define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
11445 #define SDMMC_STA_STBITERR_Pos          (9U)
11446 #define SDMMC_STA_STBITERR_Msk          (0x1UL << SDMMC_STA_STBITERR_Pos)      /*!< 0x00000200 */
11447 #define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
11448 #define SDMMC_STA_DBCKEND_Pos           (10U)
11449 #define SDMMC_STA_DBCKEND_Msk           (0x1UL << SDMMC_STA_DBCKEND_Pos)       /*!< 0x00000400 */
11450 #define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
11451 #define SDMMC_STA_CMDACT_Pos            (11U)
11452 #define SDMMC_STA_CMDACT_Msk            (0x1UL << SDMMC_STA_CMDACT_Pos)        /*!< 0x00000800 */
11453 #define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
11454 #define SDMMC_STA_TXACT_Pos             (12U)
11455 #define SDMMC_STA_TXACT_Msk             (0x1UL << SDMMC_STA_TXACT_Pos)         /*!< 0x00001000 */
11456 #define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
11457 #define SDMMC_STA_RXACT_Pos             (13U)
11458 #define SDMMC_STA_RXACT_Msk             (0x1UL << SDMMC_STA_RXACT_Pos)         /*!< 0x00002000 */
11459 #define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
11460 #define SDMMC_STA_TXFIFOHE_Pos          (14U)
11461 #define SDMMC_STA_TXFIFOHE_Msk          (0x1UL << SDMMC_STA_TXFIFOHE_Pos)      /*!< 0x00004000 */
11462 #define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11463 #define SDMMC_STA_RXFIFOHF_Pos          (15U)
11464 #define SDMMC_STA_RXFIFOHF_Msk          (0x1UL << SDMMC_STA_RXFIFOHF_Pos)      /*!< 0x00008000 */
11465 #define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11466 #define SDMMC_STA_TXFIFOF_Pos           (16U)
11467 #define SDMMC_STA_TXFIFOF_Msk           (0x1UL << SDMMC_STA_TXFIFOF_Pos)       /*!< 0x00010000 */
11468 #define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
11469 #define SDMMC_STA_RXFIFOF_Pos           (17U)
11470 #define SDMMC_STA_RXFIFOF_Msk           (0x1UL << SDMMC_STA_RXFIFOF_Pos)       /*!< 0x00020000 */
11471 #define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
11472 #define SDMMC_STA_TXFIFOE_Pos           (18U)
11473 #define SDMMC_STA_TXFIFOE_Msk           (0x1UL << SDMMC_STA_TXFIFOE_Pos)       /*!< 0x00040000 */
11474 #define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
11475 #define SDMMC_STA_RXFIFOE_Pos           (19U)
11476 #define SDMMC_STA_RXFIFOE_Msk           (0x1UL << SDMMC_STA_RXFIFOE_Pos)       /*!< 0x00080000 */
11477 #define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
11478 #define SDMMC_STA_TXDAVL_Pos            (20U)
11479 #define SDMMC_STA_TXDAVL_Msk            (0x1UL << SDMMC_STA_TXDAVL_Pos)        /*!< 0x00100000 */
11480 #define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
11481 #define SDMMC_STA_RXDAVL_Pos            (21U)
11482 #define SDMMC_STA_RXDAVL_Msk            (0x1UL << SDMMC_STA_RXDAVL_Pos)        /*!< 0x00200000 */
11483 #define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
11484 #define SDMMC_STA_SDIOIT_Pos            (22U)
11485 #define SDMMC_STA_SDIOIT_Msk            (0x1UL << SDMMC_STA_SDIOIT_Pos)        /*!< 0x00400000 */
11486 #define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
11487 
11488 /*******************  Bit definition for SDMMC_ICR register  *******************/
11489 #define SDMMC_ICR_CCRCFAILC_Pos         (0U)
11490 #define SDMMC_ICR_CCRCFAILC_Msk         (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)     /*!< 0x00000001 */
11491 #define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
11492 #define SDMMC_ICR_DCRCFAILC_Pos         (1U)
11493 #define SDMMC_ICR_DCRCFAILC_Msk         (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)     /*!< 0x00000002 */
11494 #define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
11495 #define SDMMC_ICR_CTIMEOUTC_Pos         (2U)
11496 #define SDMMC_ICR_CTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)     /*!< 0x00000004 */
11497 #define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
11498 #define SDMMC_ICR_DTIMEOUTC_Pos         (3U)
11499 #define SDMMC_ICR_DTIMEOUTC_Msk         (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)     /*!< 0x00000008 */
11500 #define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
11501 #define SDMMC_ICR_TXUNDERRC_Pos         (4U)
11502 #define SDMMC_ICR_TXUNDERRC_Msk         (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)     /*!< 0x00000010 */
11503 #define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
11504 #define SDMMC_ICR_RXOVERRC_Pos          (5U)
11505 #define SDMMC_ICR_RXOVERRC_Msk          (0x1UL << SDMMC_ICR_RXOVERRC_Pos)      /*!< 0x00000020 */
11506 #define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
11507 #define SDMMC_ICR_CMDRENDC_Pos          (6U)
11508 #define SDMMC_ICR_CMDRENDC_Msk          (0x1UL << SDMMC_ICR_CMDRENDC_Pos)      /*!< 0x00000040 */
11509 #define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
11510 #define SDMMC_ICR_CMDSENTC_Pos          (7U)
11511 #define SDMMC_ICR_CMDSENTC_Msk          (0x1UL << SDMMC_ICR_CMDSENTC_Pos)      /*!< 0x00000080 */
11512 #define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
11513 #define SDMMC_ICR_DATAENDC_Pos          (8U)
11514 #define SDMMC_ICR_DATAENDC_Msk          (0x1UL << SDMMC_ICR_DATAENDC_Pos)      /*!< 0x00000100 */
11515 #define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
11516 #define SDMMC_ICR_STBITERRC_Pos         (9U)
11517 #define SDMMC_ICR_STBITERRC_Msk         (0x1UL << SDMMC_ICR_STBITERRC_Pos)     /*!< 0x00000200 */
11518 #define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
11519 #define SDMMC_ICR_DBCKENDC_Pos          (10U)
11520 #define SDMMC_ICR_DBCKENDC_Msk          (0x1UL << SDMMC_ICR_DBCKENDC_Pos)      /*!< 0x00000400 */
11521 #define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
11522 #define SDMMC_ICR_SDIOITC_Pos           (22U)
11523 #define SDMMC_ICR_SDIOITC_Msk           (0x1UL << SDMMC_ICR_SDIOITC_Pos)       /*!< 0x00400000 */
11524 #define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
11525 
11526 /******************  Bit definition for SDMMC_MASK register  *******************/
11527 #define SDMMC_MASK_CCRCFAILIE_Pos       (0U)
11528 #define SDMMC_MASK_CCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)   /*!< 0x00000001 */
11529 #define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
11530 #define SDMMC_MASK_DCRCFAILIE_Pos       (1U)
11531 #define SDMMC_MASK_DCRCFAILIE_Msk       (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)   /*!< 0x00000002 */
11532 #define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
11533 #define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)
11534 #define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)   /*!< 0x00000004 */
11535 #define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
11536 #define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)
11537 #define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)   /*!< 0x00000008 */
11538 #define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
11539 #define SDMMC_MASK_TXUNDERRIE_Pos       (4U)
11540 #define SDMMC_MASK_TXUNDERRIE_Msk       (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)   /*!< 0x00000010 */
11541 #define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
11542 #define SDMMC_MASK_RXOVERRIE_Pos        (5U)
11543 #define SDMMC_MASK_RXOVERRIE_Msk        (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)    /*!< 0x00000020 */
11544 #define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
11545 #define SDMMC_MASK_CMDRENDIE_Pos        (6U)
11546 #define SDMMC_MASK_CMDRENDIE_Msk        (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)    /*!< 0x00000040 */
11547 #define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
11548 #define SDMMC_MASK_CMDSENTIE_Pos        (7U)
11549 #define SDMMC_MASK_CMDSENTIE_Msk        (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)    /*!< 0x00000080 */
11550 #define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
11551 #define SDMMC_MASK_DATAENDIE_Pos        (8U)
11552 #define SDMMC_MASK_DATAENDIE_Msk        (0x1UL << SDMMC_MASK_DATAENDIE_Pos)    /*!< 0x00000100 */
11553 #define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
11554 #define SDMMC_MASK_DBCKENDIE_Pos        (10U)
11555 #define SDMMC_MASK_DBCKENDIE_Msk        (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)    /*!< 0x00000400 */
11556 #define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
11557 #define SDMMC_MASK_CMDACTIE_Pos         (11U)
11558 #define SDMMC_MASK_CMDACTIE_Msk         (0x1UL << SDMMC_MASK_CMDACTIE_Pos)     /*!< 0x00000800 */
11559 #define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
11560 #define SDMMC_MASK_TXACTIE_Pos          (12U)
11561 #define SDMMC_MASK_TXACTIE_Msk          (0x1UL << SDMMC_MASK_TXACTIE_Pos)      /*!< 0x00001000 */
11562 #define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
11563 #define SDMMC_MASK_RXACTIE_Pos          (13U)
11564 #define SDMMC_MASK_RXACTIE_Msk          (0x1UL << SDMMC_MASK_RXACTIE_Pos)      /*!< 0x00002000 */
11565 #define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
11566 #define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)
11567 #define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)   /*!< 0x00004000 */
11568 #define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
11569 #define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)
11570 #define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)   /*!< 0x00008000 */
11571 #define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
11572 #define SDMMC_MASK_TXFIFOFIE_Pos        (16U)
11573 #define SDMMC_MASK_TXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)    /*!< 0x00010000 */
11574 #define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
11575 #define SDMMC_MASK_RXFIFOFIE_Pos        (17U)
11576 #define SDMMC_MASK_RXFIFOFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)    /*!< 0x00020000 */
11577 #define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
11578 #define SDMMC_MASK_TXFIFOEIE_Pos        (18U)
11579 #define SDMMC_MASK_TXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)    /*!< 0x00040000 */
11580 #define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
11581 #define SDMMC_MASK_RXFIFOEIE_Pos        (19U)
11582 #define SDMMC_MASK_RXFIFOEIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)    /*!< 0x00080000 */
11583 #define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
11584 #define SDMMC_MASK_TXDAVLIE_Pos         (20U)
11585 #define SDMMC_MASK_TXDAVLIE_Msk         (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)     /*!< 0x00100000 */
11586 #define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
11587 #define SDMMC_MASK_RXDAVLIE_Pos         (21U)
11588 #define SDMMC_MASK_RXDAVLIE_Msk         (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)     /*!< 0x00200000 */
11589 #define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
11590 #define SDMMC_MASK_SDIOITIE_Pos         (22U)
11591 #define SDMMC_MASK_SDIOITIE_Msk         (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
11592 #define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
11593 
11594 /*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
11595 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)
11596 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11597 #define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
11598 
11599 /******************  Bit definition for SDMMC_FIFO register  *******************/
11600 #define SDMMC_FIFO_FIFODATA_Pos         (0U)
11601 #define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11602 #define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
11603 
11604 /******************************************************************************/
11605 /*                                                                            */
11606 /*                        Serial Peripheral Interface (SPI)                   */
11607 /*                                                                            */
11608 /******************************************************************************/
11609 /*******************  Bit definition for SPI_CR1 register  ********************/
11610 #define SPI_CR1_CPHA_Pos         (0U)
11611 #define SPI_CR1_CPHA_Msk         (0x1UL << SPI_CR1_CPHA_Pos)                   /*!< 0x00000001 */
11612 #define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
11613 #define SPI_CR1_CPOL_Pos         (1U)
11614 #define SPI_CR1_CPOL_Msk         (0x1UL << SPI_CR1_CPOL_Pos)                   /*!< 0x00000002 */
11615 #define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
11616 #define SPI_CR1_MSTR_Pos         (2U)
11617 #define SPI_CR1_MSTR_Msk         (0x1UL << SPI_CR1_MSTR_Pos)                   /*!< 0x00000004 */
11618 #define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
11619 
11620 #define SPI_CR1_BR_Pos           (3U)
11621 #define SPI_CR1_BR_Msk           (0x7UL << SPI_CR1_BR_Pos)                     /*!< 0x00000038 */
11622 #define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
11623 #define SPI_CR1_BR_0             (0x1UL << SPI_CR1_BR_Pos)                     /*!< 0x00000008 */
11624 #define SPI_CR1_BR_1             (0x2UL << SPI_CR1_BR_Pos)                     /*!< 0x00000010 */
11625 #define SPI_CR1_BR_2             (0x4UL << SPI_CR1_BR_Pos)                     /*!< 0x00000020 */
11626 
11627 #define SPI_CR1_SPE_Pos          (6U)
11628 #define SPI_CR1_SPE_Msk          (0x1UL << SPI_CR1_SPE_Pos)                    /*!< 0x00000040 */
11629 #define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
11630 #define SPI_CR1_LSBFIRST_Pos     (7U)
11631 #define SPI_CR1_LSBFIRST_Msk     (0x1UL << SPI_CR1_LSBFIRST_Pos)               /*!< 0x00000080 */
11632 #define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
11633 #define SPI_CR1_SSI_Pos          (8U)
11634 #define SPI_CR1_SSI_Msk          (0x1UL << SPI_CR1_SSI_Pos)                    /*!< 0x00000100 */
11635 #define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
11636 #define SPI_CR1_SSM_Pos          (9U)
11637 #define SPI_CR1_SSM_Msk          (0x1UL << SPI_CR1_SSM_Pos)                    /*!< 0x00000200 */
11638 #define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
11639 #define SPI_CR1_RXONLY_Pos       (10U)
11640 #define SPI_CR1_RXONLY_Msk       (0x1UL << SPI_CR1_RXONLY_Pos)                 /*!< 0x00000400 */
11641 #define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
11642 #define SPI_CR1_CRCL_Pos         (11U)
11643 #define SPI_CR1_CRCL_Msk         (0x1UL << SPI_CR1_CRCL_Pos)                   /*!< 0x00000800 */
11644 #define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
11645 #define SPI_CR1_CRCNEXT_Pos      (12U)
11646 #define SPI_CR1_CRCNEXT_Msk      (0x1UL << SPI_CR1_CRCNEXT_Pos)                /*!< 0x00001000 */
11647 #define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
11648 #define SPI_CR1_CRCEN_Pos        (13U)
11649 #define SPI_CR1_CRCEN_Msk        (0x1UL << SPI_CR1_CRCEN_Pos)                  /*!< 0x00002000 */
11650 #define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
11651 #define SPI_CR1_BIDIOE_Pos       (14U)
11652 #define SPI_CR1_BIDIOE_Msk       (0x1UL << SPI_CR1_BIDIOE_Pos)                 /*!< 0x00004000 */
11653 #define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
11654 #define SPI_CR1_BIDIMODE_Pos     (15U)
11655 #define SPI_CR1_BIDIMODE_Msk     (0x1UL << SPI_CR1_BIDIMODE_Pos)               /*!< 0x00008000 */
11656 #define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
11657 
11658 /*******************  Bit definition for SPI_CR2 register  ********************/
11659 #define SPI_CR2_RXDMAEN_Pos      (0U)
11660 #define SPI_CR2_RXDMAEN_Msk      (0x1UL << SPI_CR2_RXDMAEN_Pos)                /*!< 0x00000001 */
11661 #define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
11662 #define SPI_CR2_TXDMAEN_Pos      (1U)
11663 #define SPI_CR2_TXDMAEN_Msk      (0x1UL << SPI_CR2_TXDMAEN_Pos)                /*!< 0x00000002 */
11664 #define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
11665 #define SPI_CR2_SSOE_Pos         (2U)
11666 #define SPI_CR2_SSOE_Msk         (0x1UL << SPI_CR2_SSOE_Pos)                   /*!< 0x00000004 */
11667 #define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
11668 #define SPI_CR2_NSSP_Pos         (3U)
11669 #define SPI_CR2_NSSP_Msk         (0x1UL << SPI_CR2_NSSP_Pos)                   /*!< 0x00000008 */
11670 #define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
11671 #define SPI_CR2_FRF_Pos          (4U)
11672 #define SPI_CR2_FRF_Msk          (0x1UL << SPI_CR2_FRF_Pos)                    /*!< 0x00000010 */
11673 #define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
11674 #define SPI_CR2_ERRIE_Pos        (5U)
11675 #define SPI_CR2_ERRIE_Msk        (0x1UL << SPI_CR2_ERRIE_Pos)                  /*!< 0x00000020 */
11676 #define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
11677 #define SPI_CR2_RXNEIE_Pos       (6U)
11678 #define SPI_CR2_RXNEIE_Msk       (0x1UL << SPI_CR2_RXNEIE_Pos)                 /*!< 0x00000040 */
11679 #define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
11680 #define SPI_CR2_TXEIE_Pos        (7U)
11681 #define SPI_CR2_TXEIE_Msk        (0x1UL << SPI_CR2_TXEIE_Pos)                  /*!< 0x00000080 */
11682 #define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
11683 #define SPI_CR2_DS_Pos           (8U)
11684 #define SPI_CR2_DS_Msk           (0xFUL << SPI_CR2_DS_Pos)                     /*!< 0x00000F00 */
11685 #define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
11686 #define SPI_CR2_DS_0             (0x1UL << SPI_CR2_DS_Pos)                     /*!< 0x00000100 */
11687 #define SPI_CR2_DS_1             (0x2UL << SPI_CR2_DS_Pos)                     /*!< 0x00000200 */
11688 #define SPI_CR2_DS_2             (0x4UL << SPI_CR2_DS_Pos)                     /*!< 0x00000400 */
11689 #define SPI_CR2_DS_3             (0x8UL << SPI_CR2_DS_Pos)                     /*!< 0x00000800 */
11690 #define SPI_CR2_FRXTH_Pos        (12U)
11691 #define SPI_CR2_FRXTH_Msk        (0x1UL << SPI_CR2_FRXTH_Pos)                  /*!< 0x00001000 */
11692 #define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
11693 #define SPI_CR2_LDMARX_Pos       (13U)
11694 #define SPI_CR2_LDMARX_Msk       (0x1UL << SPI_CR2_LDMARX_Pos)                 /*!< 0x00002000 */
11695 #define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
11696 #define SPI_CR2_LDMATX_Pos       (14U)
11697 #define SPI_CR2_LDMATX_Msk       (0x1UL << SPI_CR2_LDMATX_Pos)                 /*!< 0x00004000 */
11698 #define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
11699 
11700 /********************  Bit definition for SPI_SR register  ********************/
11701 #define SPI_SR_RXNE_Pos          (0U)
11702 #define SPI_SR_RXNE_Msk          (0x1UL << SPI_SR_RXNE_Pos)                    /*!< 0x00000001 */
11703 #define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
11704 #define SPI_SR_TXE_Pos           (1U)
11705 #define SPI_SR_TXE_Msk           (0x1UL << SPI_SR_TXE_Pos)                     /*!< 0x00000002 */
11706 #define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
11707 #define SPI_SR_CHSIDE_Pos        (2U)
11708 #define SPI_SR_CHSIDE_Msk        (0x1UL << SPI_SR_CHSIDE_Pos)                  /*!< 0x00000004 */
11709 #define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
11710 #define SPI_SR_UDR_Pos           (3U)
11711 #define SPI_SR_UDR_Msk           (0x1UL << SPI_SR_UDR_Pos)                     /*!< 0x00000008 */
11712 #define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
11713 #define SPI_SR_CRCERR_Pos        (4U)
11714 #define SPI_SR_CRCERR_Msk        (0x1UL << SPI_SR_CRCERR_Pos)                  /*!< 0x00000010 */
11715 #define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
11716 #define SPI_SR_MODF_Pos          (5U)
11717 #define SPI_SR_MODF_Msk          (0x1UL << SPI_SR_MODF_Pos)                    /*!< 0x00000020 */
11718 #define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
11719 #define SPI_SR_OVR_Pos           (6U)
11720 #define SPI_SR_OVR_Msk           (0x1UL << SPI_SR_OVR_Pos)                     /*!< 0x00000040 */
11721 #define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
11722 #define SPI_SR_BSY_Pos           (7U)
11723 #define SPI_SR_BSY_Msk           (0x1UL << SPI_SR_BSY_Pos)                     /*!< 0x00000080 */
11724 #define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
11725 #define SPI_SR_FRE_Pos           (8U)
11726 #define SPI_SR_FRE_Msk           (0x1UL << SPI_SR_FRE_Pos)                     /*!< 0x00000100 */
11727 #define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
11728 #define SPI_SR_FRLVL_Pos         (9U)
11729 #define SPI_SR_FRLVL_Msk         (0x3UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000600 */
11730 #define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
11731 #define SPI_SR_FRLVL_0           (0x1UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000200 */
11732 #define SPI_SR_FRLVL_1           (0x2UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000400 */
11733 #define SPI_SR_FTLVL_Pos         (11U)
11734 #define SPI_SR_FTLVL_Msk         (0x3UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001800 */
11735 #define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
11736 #define SPI_SR_FTLVL_0           (0x1UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00000800 */
11737 #define SPI_SR_FTLVL_1           (0x2UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001000 */
11738 
11739 /********************  Bit definition for SPI_DR register  ********************/
11740 #define SPI_DR_DR_Pos            (0U)
11741 #define SPI_DR_DR_Msk            (0xFFFFUL << SPI_DR_DR_Pos)                   /*!< 0x0000FFFF */
11742 #define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
11743 
11744 /*******************  Bit definition for SPI_CRCPR register  ******************/
11745 #define SPI_CRCPR_CRCPOLY_Pos    (0U)
11746 #define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)           /*!< 0x0000FFFF */
11747 #define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
11748 
11749 /******************  Bit definition for SPI_RXCRCR register  ******************/
11750 #define SPI_RXCRCR_RXCRC_Pos     (0U)
11751 #define SPI_RXCRCR_RXCRC_Msk     (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)            /*!< 0x0000FFFF */
11752 #define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
11753 
11754 /******************  Bit definition for SPI_TXCRCR register  ******************/
11755 #define SPI_TXCRCR_TXCRC_Pos     (0U)
11756 #define SPI_TXCRCR_TXCRC_Msk     (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)            /*!< 0x0000FFFF */
11757 #define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
11758 
11759 /******************************************************************************/
11760 /*                                                                            */
11761 /*                                    QUADSPI                                 */
11762 /*                                                                            */
11763 /******************************************************************************/
11764 /*****************  Bit definition for QUADSPI_CR register  *******************/
11765 #define QUADSPI_CR_EN_Pos              (0U)
11766 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
11767 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
11768 #define QUADSPI_CR_ABORT_Pos           (1U)
11769 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
11770 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
11771 #define QUADSPI_CR_DMAEN_Pos           (2U)
11772 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
11773 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
11774 #define QUADSPI_CR_TCEN_Pos            (3U)
11775 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
11776 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
11777 #define QUADSPI_CR_SSHIFT_Pos          (4U)
11778 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
11779 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
11780 #define QUADSPI_CR_DFM_Pos             (6U)
11781 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
11782 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
11783 #define QUADSPI_CR_FSEL_Pos            (7U)
11784 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
11785 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
11786 #define QUADSPI_CR_FTHRES_Pos          (8U)
11787 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
11788 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
11789 #define QUADSPI_CR_TEIE_Pos            (16U)
11790 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
11791 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
11792 #define QUADSPI_CR_TCIE_Pos            (17U)
11793 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
11794 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
11795 #define QUADSPI_CR_FTIE_Pos            (18U)
11796 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
11797 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
11798 #define QUADSPI_CR_SMIE_Pos            (19U)
11799 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
11800 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
11801 #define QUADSPI_CR_TOIE_Pos            (20U)
11802 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
11803 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
11804 #define QUADSPI_CR_APMS_Pos            (22U)
11805 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
11806 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
11807 #define QUADSPI_CR_PMM_Pos             (23U)
11808 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
11809 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
11810 #define QUADSPI_CR_PRESCALER_Pos       (24U)
11811 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
11812 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
11813 
11814 /*****************  Bit definition for QUADSPI_DCR register  ******************/
11815 #define QUADSPI_DCR_CKMODE_Pos         (0U)
11816 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
11817 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
11818 #define QUADSPI_DCR_CSHT_Pos           (8U)
11819 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
11820 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
11821 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
11822 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
11823 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
11824 #define QUADSPI_DCR_FSIZE_Pos          (16U)
11825 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
11826 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
11827 
11828 /******************  Bit definition for QUADSPI_SR register  *******************/
11829 #define QUADSPI_SR_TEF_Pos             (0U)
11830 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
11831 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
11832 #define QUADSPI_SR_TCF_Pos             (1U)
11833 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
11834 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
11835 #define QUADSPI_SR_FTF_Pos             (2U)
11836 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
11837 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
11838 #define QUADSPI_SR_SMF_Pos             (3U)
11839 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
11840 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
11841 #define QUADSPI_SR_TOF_Pos             (4U)
11842 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
11843 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
11844 #define QUADSPI_SR_BUSY_Pos            (5U)
11845 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
11846 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
11847 #define QUADSPI_SR_FLEVEL_Pos          (8U)
11848 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
11849 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
11850 
11851 /******************  Bit definition for QUADSPI_FCR register  ******************/
11852 #define QUADSPI_FCR_CTEF_Pos           (0U)
11853 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
11854 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
11855 #define QUADSPI_FCR_CTCF_Pos           (1U)
11856 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
11857 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
11858 #define QUADSPI_FCR_CSMF_Pos           (3U)
11859 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
11860 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
11861 #define QUADSPI_FCR_CTOF_Pos           (4U)
11862 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
11863 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
11864 
11865 /******************  Bit definition for QUADSPI_DLR register  ******************/
11866 #define QUADSPI_DLR_DL_Pos             (0U)
11867 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
11868 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
11869 
11870 /******************  Bit definition for QUADSPI_CCR register  ******************/
11871 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
11872 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
11873 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
11874 #define QUADSPI_CCR_IMODE_Pos          (8U)
11875 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
11876 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
11877 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
11878 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
11879 #define QUADSPI_CCR_ADMODE_Pos         (10U)
11880 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
11881 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
11882 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
11883 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
11884 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
11885 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
11886 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
11887 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
11888 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
11889 #define QUADSPI_CCR_ABMODE_Pos         (14U)
11890 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
11891 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
11892 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
11893 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
11894 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
11895 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
11896 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
11897 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
11898 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
11899 #define QUADSPI_CCR_DCYC_Pos           (18U)
11900 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
11901 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
11902 #define QUADSPI_CCR_DMODE_Pos          (24U)
11903 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
11904 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
11905 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
11906 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
11907 #define QUADSPI_CCR_FMODE_Pos          (26U)
11908 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
11909 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
11910 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
11911 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
11912 #define QUADSPI_CCR_SIOO_Pos           (28U)
11913 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
11914 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
11915 #define QUADSPI_CCR_DHHC_Pos           (30U)
11916 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
11917 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
11918 #define QUADSPI_CCR_DDRM_Pos           (31U)
11919 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
11920 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
11921 
11922 /******************  Bit definition for QUADSPI_AR register  *******************/
11923 #define QUADSPI_AR_ADDRESS_Pos         (0U)
11924 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
11925 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
11926 
11927 /******************  Bit definition for QUADSPI_ABR register  ******************/
11928 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
11929 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
11930 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
11931 
11932 /******************  Bit definition for QUADSPI_DR register  *******************/
11933 #define QUADSPI_DR_DATA_Pos            (0U)
11934 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
11935 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
11936 
11937 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
11938 #define QUADSPI_PSMKR_MASK_Pos         (0U)
11939 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
11940 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
11941 
11942 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
11943 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
11944 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
11945 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
11946 
11947 /******************  Bit definition for QUADSPI_PIR register  *****************/
11948 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
11949 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
11950 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
11951 
11952 /******************  Bit definition for QUADSPI_LPTR register  *****************/
11953 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
11954 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
11955 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
11956 
11957 /******************************************************************************/
11958 /*                                                                            */
11959 /*                                 SYSCFG                                     */
11960 /*                                                                            */
11961 /******************************************************************************/
11962 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
11963 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
11964 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
11965 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
11966 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
11967 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
11968 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
11969 
11970 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
11971 #define SYSCFG_CFGR1_FWDIS_Pos          (0U)
11972 #define SYSCFG_CFGR1_FWDIS_Msk          (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)      /*!< 0x00000001 */
11973 #define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
11974 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
11975 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
11976 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
11977 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
11978 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
11979 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
11980 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
11981 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
11982 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
11983 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
11984 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
11985 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
11986 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
11987 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
11988 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
11989 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
11990 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
11991 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
11992 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
11993 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
11994 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
11995 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
11996 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
11997 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
11998 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000UL)                         /*!<  Invalid operation Interrupt enable */
11999 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000UL)                         /*!<  Divide-by-zero Interrupt enable */
12000 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000UL)                         /*!<  Underflow Interrupt enable */
12001 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000UL)                         /*!<  Overflow Interrupt enable */
12002 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000UL)                         /*!<  Input denormal Interrupt enable */
12003 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000UL)                         /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
12004 
12005 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
12006 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
12007 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x00000007 */
12008 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
12009 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
12010 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x00000070 */
12011 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
12012 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
12013 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000700 */
12014 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
12015 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
12016 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x00007000 */
12017 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
12018 
12019 /**
12020   * @brief   EXTI0 configuration
12021   */
12022 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000UL)                     /*!<PA[0] pin */
12023 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001UL)                     /*!<PB[0] pin */
12024 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002UL)                     /*!<PC[0] pin */
12025 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003UL)                     /*!<PD[0] pin */
12026 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004UL)                     /*!<PE[0] pin */
12027 #define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007UL)                     /*!<PH[0] pin */
12028 
12029 /**
12030   * @brief   EXTI1 configuration
12031   */
12032 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000UL)                     /*!<PA[1] pin */
12033 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010UL)                     /*!<PB[1] pin */
12034 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020UL)                     /*!<PC[1] pin */
12035 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030UL)                     /*!<PD[1] pin */
12036 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040UL)                     /*!<PE[1] pin */
12037 #define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070UL)                     /*!<PH[1] pin */
12038 
12039 /**
12040   * @brief   EXTI2 configuration
12041   */
12042 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000UL)                     /*!<PA[2] pin */
12043 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100UL)                     /*!<PB[2] pin */
12044 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200UL)                     /*!<PC[2] pin */
12045 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300UL)                     /*!<PD[2] pin */
12046 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400UL)                     /*!<PE[2] pin */
12047 
12048 /**
12049   * @brief   EXTI3 configuration
12050   */
12051 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000UL)                     /*!<PA[3] pin */
12052 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000UL)                     /*!<PB[3] pin */
12053 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000UL)                     /*!<PC[3] pin */
12054 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000UL)                     /*!<PD[3] pin */
12055 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000UL)                     /*!<PE[3] pin */
12056 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000UL)                     /*!<PG[3] pin */
12057 
12058 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
12059 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
12060 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x00000007 */
12061 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
12062 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
12063 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x00000070 */
12064 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
12065 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
12066 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000700 */
12067 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
12068 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
12069 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x00007000 */
12070 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
12071 /**
12072   * @brief   EXTI4 configuration
12073   */
12074 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000UL)                     /*!<PA[4] pin */
12075 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001UL)                     /*!<PB[4] pin */
12076 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002UL)                     /*!<PC[4] pin */
12077 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003UL)                     /*!<PD[4] pin */
12078 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004UL)                     /*!<PE[4] pin */
12079 
12080 /**
12081   * @brief   EXTI5 configuration
12082   */
12083 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000UL)                     /*!<PA[5] pin */
12084 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010UL)                     /*!<PB[5] pin */
12085 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020UL)                     /*!<PC[5] pin */
12086 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030UL)                     /*!<PD[5] pin */
12087 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040UL)                     /*!<PE[5] pin */
12088 
12089 /**
12090   * @brief   EXTI6 configuration
12091   */
12092 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000UL)                     /*!<PA[6] pin */
12093 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100UL)                     /*!<PB[6] pin */
12094 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200UL)                     /*!<PC[6] pin */
12095 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300UL)                     /*!<PD[6] pin */
12096 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400UL)                     /*!<PE[6] pin */
12097 
12098 /**
12099   * @brief   EXTI7 configuration
12100   */
12101 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000UL)                     /*!<PA[7] pin */
12102 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000UL)                     /*!<PB[7] pin */
12103 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000UL)                     /*!<PC[7] pin */
12104 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000UL)                     /*!<PD[7] pin */
12105 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000UL)                     /*!<PE[7] pin */
12106 
12107 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
12108 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
12109 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x00000007 */
12110 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
12111 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
12112 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x00000070 */
12113 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
12114 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
12115 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000700 */
12116 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
12117 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
12118 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x00007000 */
12119 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
12120 
12121 /**
12122   * @brief   EXTI8 configuration
12123   */
12124 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000UL)                     /*!<PA[8] pin */
12125 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001UL)                     /*!<PB[8] pin */
12126 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002UL)                     /*!<PC[8] pin */
12127 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003UL)                     /*!<PD[8] pin */
12128 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004UL)                     /*!<PE[8] pin */
12129 
12130 /**
12131   * @brief   EXTI9 configuration
12132   */
12133 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000UL)                     /*!<PA[9] pin */
12134 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010UL)                     /*!<PB[9] pin */
12135 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020UL)                     /*!<PC[9] pin */
12136 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030UL)                     /*!<PD[9] pin */
12137 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040UL)                     /*!<PE[9] pin */
12138 
12139 /**
12140   * @brief   EXTI10 configuration
12141   */
12142 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000UL)                     /*!<PA[10] pin */
12143 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100UL)                     /*!<PB[10] pin */
12144 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200UL)                     /*!<PC[10] pin */
12145 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300UL)                     /*!<PD[10] pin */
12146 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400UL)                     /*!<PE[10] pin */
12147 
12148 /**
12149   * @brief   EXTI11 configuration
12150   */
12151 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000UL)                     /*!<PA[11] pin */
12152 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000UL)                     /*!<PB[11] pin */
12153 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000UL)                     /*!<PC[11] pin */
12154 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000UL)                     /*!<PD[11] pin */
12155 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000UL)                     /*!<PE[11] pin */
12156 
12157 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
12158 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
12159 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
12160 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
12161 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
12162 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
12163 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
12164 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
12165 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
12166 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
12167 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
12168 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
12169 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
12170 
12171 /**
12172   * @brief   EXTI12 configuration
12173   */
12174 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000UL)                     /*!<PA[12] pin */
12175 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001UL)                     /*!<PB[12] pin */
12176 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002UL)                     /*!<PC[12] pin */
12177 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003UL)                     /*!<PD[12] pin */
12178 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004UL)                     /*!<PE[12] pin */
12179 
12180 /**
12181   * @brief   EXTI13 configuration
12182   */
12183 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000UL)                     /*!<PA[13] pin */
12184 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010UL)                     /*!<PB[13] pin */
12185 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020UL)                     /*!<PC[13] pin */
12186 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030UL)                     /*!<PD[13] pin */
12187 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040UL)                     /*!<PE[13] pin */
12188 
12189 /**
12190   * @brief   EXTI14 configuration
12191   */
12192 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000UL)                     /*!<PA[14] pin */
12193 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100UL)                     /*!<PB[14] pin */
12194 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200UL)                     /*!<PC[14] pin */
12195 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300UL)                     /*!<PD[14] pin */
12196 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400UL)                     /*!<PE[14] pin */
12197 
12198 /**
12199   * @brief   EXTI15 configuration
12200   */
12201 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000UL)                     /*!<PA[15] pin */
12202 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000UL)                     /*!<PB[15] pin */
12203 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000UL)                     /*!<PC[15] pin */
12204 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000UL)                     /*!<PD[15] pin */
12205 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000UL)                     /*!<PE[15] pin */
12206 
12207 /******************  Bit definition for SYSCFG_SCSR register  ****************/
12208 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
12209 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)     /*!< 0x00000001 */
12210 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
12211 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
12212 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)    /*!< 0x00000002 */
12213 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
12214 
12215 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
12216 #define SYSCFG_CFGR2_CLL_Pos            (0U)
12217 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
12218 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
12219 #define SYSCFG_CFGR2_SPL_Pos            (1U)
12220 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
12221 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
12222 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
12223 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
12224 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
12225 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
12226 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
12227 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
12228 #define SYSCFG_CFGR2_SPF_Pos            (8U)
12229 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
12230 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
12231 
12232 /******************  Bit definition for SYSCFG_SWPR register  ****************/
12233 #define SYSCFG_SWPR_PAGE0_Pos           (0U)
12234 #define SYSCFG_SWPR_PAGE0_Msk           (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
12235 #define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
12236 #define SYSCFG_SWPR_PAGE1_Pos           (1U)
12237 #define SYSCFG_SWPR_PAGE1_Msk           (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
12238 #define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
12239 #define SYSCFG_SWPR_PAGE2_Pos           (2U)
12240 #define SYSCFG_SWPR_PAGE2_Msk           (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
12241 #define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
12242 #define SYSCFG_SWPR_PAGE3_Pos           (3U)
12243 #define SYSCFG_SWPR_PAGE3_Msk           (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
12244 #define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
12245 #define SYSCFG_SWPR_PAGE4_Pos           (4U)
12246 #define SYSCFG_SWPR_PAGE4_Msk           (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
12247 #define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
12248 #define SYSCFG_SWPR_PAGE5_Pos           (5U)
12249 #define SYSCFG_SWPR_PAGE5_Msk           (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
12250 #define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
12251 #define SYSCFG_SWPR_PAGE6_Pos           (6U)
12252 #define SYSCFG_SWPR_PAGE6_Msk           (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
12253 #define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
12254 #define SYSCFG_SWPR_PAGE7_Pos           (7U)
12255 #define SYSCFG_SWPR_PAGE7_Msk           (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
12256 #define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
12257 #define SYSCFG_SWPR_PAGE8_Pos           (8U)
12258 #define SYSCFG_SWPR_PAGE8_Msk           (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
12259 #define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
12260 #define SYSCFG_SWPR_PAGE9_Pos           (9U)
12261 #define SYSCFG_SWPR_PAGE9_Msk           (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
12262 #define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
12263 #define SYSCFG_SWPR_PAGE10_Pos          (10U)
12264 #define SYSCFG_SWPR_PAGE10_Msk          (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
12265 #define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
12266 #define SYSCFG_SWPR_PAGE11_Pos          (11U)
12267 #define SYSCFG_SWPR_PAGE11_Msk          (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
12268 #define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
12269 #define SYSCFG_SWPR_PAGE12_Pos          (12U)
12270 #define SYSCFG_SWPR_PAGE12_Msk          (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
12271 #define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
12272 #define SYSCFG_SWPR_PAGE13_Pos          (13U)
12273 #define SYSCFG_SWPR_PAGE13_Msk          (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
12274 #define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
12275 #define SYSCFG_SWPR_PAGE14_Pos          (14U)
12276 #define SYSCFG_SWPR_PAGE14_Msk          (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
12277 #define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
12278 #define SYSCFG_SWPR_PAGE15_Pos          (15U)
12279 #define SYSCFG_SWPR_PAGE15_Msk          (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
12280 #define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
12281 
12282 /******************  Bit definition for SYSCFG_SKR register  ****************/
12283 #define SYSCFG_SKR_KEY_Pos              (0U)
12284 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
12285 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
12286 
12287 
12288 
12289 
12290 /******************************************************************************/
12291 /*                                                                            */
12292 /*                                    TIM                                     */
12293 /*                                                                            */
12294 /******************************************************************************/
12295 /*******************  Bit definition for TIM_CR1 register  ********************/
12296 #define TIM_CR1_CEN_Pos           (0U)
12297 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
12298 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
12299 #define TIM_CR1_UDIS_Pos          (1U)
12300 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
12301 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
12302 #define TIM_CR1_URS_Pos           (2U)
12303 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
12304 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
12305 #define TIM_CR1_OPM_Pos           (3U)
12306 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
12307 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
12308 #define TIM_CR1_DIR_Pos           (4U)
12309 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
12310 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
12311 
12312 #define TIM_CR1_CMS_Pos           (5U)
12313 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
12314 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
12315 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
12316 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
12317 
12318 #define TIM_CR1_ARPE_Pos          (7U)
12319 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
12320 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
12321 
12322 #define TIM_CR1_CKD_Pos           (8U)
12323 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
12324 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
12325 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
12326 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
12327 
12328 #define TIM_CR1_UIFREMAP_Pos      (11U)
12329 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
12330 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
12331 
12332 /*******************  Bit definition for TIM_CR2 register  ********************/
12333 #define TIM_CR2_CCPC_Pos          (0U)
12334 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
12335 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
12336 #define TIM_CR2_CCUS_Pos          (2U)
12337 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
12338 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
12339 #define TIM_CR2_CCDS_Pos          (3U)
12340 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
12341 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
12342 
12343 #define TIM_CR2_MMS_Pos           (4U)
12344 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
12345 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
12346 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
12347 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
12348 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
12349 
12350 #define TIM_CR2_TI1S_Pos          (7U)
12351 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
12352 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
12353 #define TIM_CR2_OIS1_Pos          (8U)
12354 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
12355 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
12356 #define TIM_CR2_OIS1N_Pos         (9U)
12357 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
12358 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
12359 #define TIM_CR2_OIS2_Pos          (10U)
12360 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
12361 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
12362 #define TIM_CR2_OIS2N_Pos         (11U)
12363 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
12364 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
12365 #define TIM_CR2_OIS3_Pos          (12U)
12366 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
12367 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
12368 #define TIM_CR2_OIS3N_Pos         (13U)
12369 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
12370 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
12371 #define TIM_CR2_OIS4_Pos          (14U)
12372 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
12373 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
12374 #define TIM_CR2_OIS5_Pos          (16U)
12375 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
12376 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
12377 #define TIM_CR2_OIS6_Pos          (18U)
12378 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
12379 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
12380 
12381 #define TIM_CR2_MMS2_Pos          (20U)
12382 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
12383 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
12384 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
12385 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
12386 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
12387 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
12388 
12389 /*******************  Bit definition for TIM_SMCR register  *******************/
12390 #define TIM_SMCR_SMS_Pos          (0U)
12391 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
12392 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
12393 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
12394 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
12395 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
12396 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
12397 
12398 #define TIM_SMCR_OCCS_Pos         (3U)
12399 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
12400 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
12401 
12402 #define TIM_SMCR_TS_Pos           (4U)
12403 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000070 */
12404 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
12405 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000010 */
12406 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000020 */
12407 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000040 */
12408 
12409 #define TIM_SMCR_MSM_Pos          (7U)
12410 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
12411 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
12412 
12413 #define TIM_SMCR_ETF_Pos          (8U)
12414 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
12415 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
12416 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
12417 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
12418 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
12419 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
12420 
12421 #define TIM_SMCR_ETPS_Pos         (12U)
12422 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
12423 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
12424 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
12425 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
12426 
12427 #define TIM_SMCR_ECE_Pos          (14U)
12428 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
12429 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
12430 #define TIM_SMCR_ETP_Pos          (15U)
12431 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
12432 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
12433 
12434 /*******************  Bit definition for TIM_DIER register  *******************/
12435 #define TIM_DIER_UIE_Pos          (0U)
12436 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
12437 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
12438 #define TIM_DIER_CC1IE_Pos        (1U)
12439 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
12440 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
12441 #define TIM_DIER_CC2IE_Pos        (2U)
12442 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
12443 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
12444 #define TIM_DIER_CC3IE_Pos        (3U)
12445 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
12446 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
12447 #define TIM_DIER_CC4IE_Pos        (4U)
12448 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
12449 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
12450 #define TIM_DIER_COMIE_Pos        (5U)
12451 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
12452 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
12453 #define TIM_DIER_TIE_Pos          (6U)
12454 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
12455 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
12456 #define TIM_DIER_BIE_Pos          (7U)
12457 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
12458 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
12459 #define TIM_DIER_UDE_Pos          (8U)
12460 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
12461 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
12462 #define TIM_DIER_CC1DE_Pos        (9U)
12463 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
12464 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
12465 #define TIM_DIER_CC2DE_Pos        (10U)
12466 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
12467 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
12468 #define TIM_DIER_CC3DE_Pos        (11U)
12469 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
12470 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
12471 #define TIM_DIER_CC4DE_Pos        (12U)
12472 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
12473 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
12474 #define TIM_DIER_COMDE_Pos        (13U)
12475 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
12476 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
12477 #define TIM_DIER_TDE_Pos          (14U)
12478 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
12479 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
12480 
12481 /********************  Bit definition for TIM_SR register  ********************/
12482 #define TIM_SR_UIF_Pos            (0U)
12483 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
12484 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
12485 #define TIM_SR_CC1IF_Pos          (1U)
12486 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
12487 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
12488 #define TIM_SR_CC2IF_Pos          (2U)
12489 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
12490 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
12491 #define TIM_SR_CC3IF_Pos          (3U)
12492 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
12493 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
12494 #define TIM_SR_CC4IF_Pos          (4U)
12495 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
12496 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
12497 #define TIM_SR_COMIF_Pos          (5U)
12498 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
12499 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
12500 #define TIM_SR_TIF_Pos            (6U)
12501 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
12502 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
12503 #define TIM_SR_BIF_Pos            (7U)
12504 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
12505 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
12506 #define TIM_SR_B2IF_Pos           (8U)
12507 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
12508 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
12509 #define TIM_SR_CC1OF_Pos          (9U)
12510 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
12511 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
12512 #define TIM_SR_CC2OF_Pos          (10U)
12513 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
12514 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
12515 #define TIM_SR_CC3OF_Pos          (11U)
12516 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
12517 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
12518 #define TIM_SR_CC4OF_Pos          (12U)
12519 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
12520 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
12521 #define TIM_SR_SBIF_Pos           (13U)
12522 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
12523 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
12524 #define TIM_SR_CC5IF_Pos          (16U)
12525 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
12526 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
12527 #define TIM_SR_CC6IF_Pos          (17U)
12528 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
12529 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
12530 
12531 
12532 /*******************  Bit definition for TIM_EGR register  ********************/
12533 #define TIM_EGR_UG_Pos            (0U)
12534 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
12535 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
12536 #define TIM_EGR_CC1G_Pos          (1U)
12537 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
12538 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
12539 #define TIM_EGR_CC2G_Pos          (2U)
12540 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
12541 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
12542 #define TIM_EGR_CC3G_Pos          (3U)
12543 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
12544 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
12545 #define TIM_EGR_CC4G_Pos          (4U)
12546 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
12547 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
12548 #define TIM_EGR_COMG_Pos          (5U)
12549 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
12550 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
12551 #define TIM_EGR_TG_Pos            (6U)
12552 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
12553 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
12554 #define TIM_EGR_BG_Pos            (7U)
12555 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
12556 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
12557 #define TIM_EGR_B2G_Pos           (8U)
12558 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
12559 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
12560 
12561 
12562 /******************  Bit definition for TIM_CCMR1 register  *******************/
12563 #define TIM_CCMR1_CC1S_Pos        (0U)
12564 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
12565 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
12566 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
12567 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
12568 
12569 #define TIM_CCMR1_OC1FE_Pos       (2U)
12570 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
12571 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
12572 #define TIM_CCMR1_OC1PE_Pos       (3U)
12573 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
12574 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
12575 
12576 #define TIM_CCMR1_OC1M_Pos        (4U)
12577 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
12578 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
12579 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
12580 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
12581 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
12582 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
12583 
12584 #define TIM_CCMR1_OC1CE_Pos       (7U)
12585 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
12586 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
12587 
12588 #define TIM_CCMR1_CC2S_Pos        (8U)
12589 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
12590 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
12591 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
12592 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
12593 
12594 #define TIM_CCMR1_OC2FE_Pos       (10U)
12595 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
12596 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
12597 #define TIM_CCMR1_OC2PE_Pos       (11U)
12598 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
12599 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
12600 
12601 #define TIM_CCMR1_OC2M_Pos        (12U)
12602 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
12603 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
12604 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
12605 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
12606 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
12607 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
12608 
12609 #define TIM_CCMR1_OC2CE_Pos       (15U)
12610 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
12611 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
12612 
12613 /*----------------------------------------------------------------------------*/
12614 #define TIM_CCMR1_IC1PSC_Pos      (2U)
12615 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
12616 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
12617 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
12618 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
12619 
12620 #define TIM_CCMR1_IC1F_Pos        (4U)
12621 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
12622 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
12623 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
12624 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
12625 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
12626 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
12627 
12628 #define TIM_CCMR1_IC2PSC_Pos      (10U)
12629 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
12630 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
12631 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
12632 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
12633 
12634 #define TIM_CCMR1_IC2F_Pos        (12U)
12635 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
12636 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
12637 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
12638 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
12639 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
12640 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
12641 
12642 /******************  Bit definition for TIM_CCMR2 register  *******************/
12643 #define TIM_CCMR2_CC3S_Pos        (0U)
12644 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
12645 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
12646 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
12647 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
12648 
12649 #define TIM_CCMR2_OC3FE_Pos       (2U)
12650 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
12651 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
12652 #define TIM_CCMR2_OC3PE_Pos       (3U)
12653 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
12654 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
12655 
12656 #define TIM_CCMR2_OC3M_Pos        (4U)
12657 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
12658 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
12659 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
12660 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
12661 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
12662 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
12663 
12664 #define TIM_CCMR2_OC3CE_Pos       (7U)
12665 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
12666 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
12667 
12668 #define TIM_CCMR2_CC4S_Pos        (8U)
12669 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
12670 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
12671 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
12672 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
12673 
12674 #define TIM_CCMR2_OC4FE_Pos       (10U)
12675 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
12676 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
12677 #define TIM_CCMR2_OC4PE_Pos       (11U)
12678 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
12679 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
12680 
12681 #define TIM_CCMR2_OC4M_Pos        (12U)
12682 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
12683 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
12684 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
12685 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
12686 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
12687 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
12688 
12689 #define TIM_CCMR2_OC4CE_Pos       (15U)
12690 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
12691 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
12692 
12693 /*----------------------------------------------------------------------------*/
12694 #define TIM_CCMR2_IC3PSC_Pos      (2U)
12695 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
12696 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
12697 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
12698 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
12699 
12700 #define TIM_CCMR2_IC3F_Pos        (4U)
12701 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
12702 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
12703 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
12704 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
12705 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
12706 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
12707 
12708 #define TIM_CCMR2_IC4PSC_Pos      (10U)
12709 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
12710 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12711 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
12712 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
12713 
12714 #define TIM_CCMR2_IC4F_Pos        (12U)
12715 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
12716 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12717 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
12718 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
12719 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
12720 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
12721 
12722 /******************  Bit definition for TIM_CCMR3 register  *******************/
12723 #define TIM_CCMR3_OC5FE_Pos       (2U)
12724 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
12725 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
12726 #define TIM_CCMR3_OC5PE_Pos       (3U)
12727 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
12728 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
12729 
12730 #define TIM_CCMR3_OC5M_Pos        (4U)
12731 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
12732 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
12733 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
12734 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
12735 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
12736 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
12737 
12738 #define TIM_CCMR3_OC5CE_Pos       (7U)
12739 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
12740 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
12741 
12742 #define TIM_CCMR3_OC6FE_Pos       (10U)
12743 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
12744 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
12745 #define TIM_CCMR3_OC6PE_Pos       (11U)
12746 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
12747 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
12748 
12749 #define TIM_CCMR3_OC6M_Pos        (12U)
12750 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
12751 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
12752 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
12753 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
12754 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
12755 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
12756 
12757 #define TIM_CCMR3_OC6CE_Pos       (15U)
12758 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
12759 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
12760 
12761 /*******************  Bit definition for TIM_CCER register  *******************/
12762 #define TIM_CCER_CC1E_Pos         (0U)
12763 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
12764 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
12765 #define TIM_CCER_CC1P_Pos         (1U)
12766 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
12767 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
12768 #define TIM_CCER_CC1NE_Pos        (2U)
12769 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
12770 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
12771 #define TIM_CCER_CC1NP_Pos        (3U)
12772 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
12773 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
12774 #define TIM_CCER_CC2E_Pos         (4U)
12775 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
12776 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
12777 #define TIM_CCER_CC2P_Pos         (5U)
12778 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
12779 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
12780 #define TIM_CCER_CC2NE_Pos        (6U)
12781 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
12782 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
12783 #define TIM_CCER_CC2NP_Pos        (7U)
12784 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
12785 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
12786 #define TIM_CCER_CC3E_Pos         (8U)
12787 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
12788 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
12789 #define TIM_CCER_CC3P_Pos         (9U)
12790 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
12791 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
12792 #define TIM_CCER_CC3NE_Pos        (10U)
12793 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
12794 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
12795 #define TIM_CCER_CC3NP_Pos        (11U)
12796 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
12797 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
12798 #define TIM_CCER_CC4E_Pos         (12U)
12799 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
12800 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
12801 #define TIM_CCER_CC4P_Pos         (13U)
12802 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
12803 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
12804 #define TIM_CCER_CC4NP_Pos        (15U)
12805 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
12806 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
12807 #define TIM_CCER_CC5E_Pos         (16U)
12808 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
12809 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
12810 #define TIM_CCER_CC5P_Pos         (17U)
12811 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
12812 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
12813 #define TIM_CCER_CC6E_Pos         (20U)
12814 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
12815 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
12816 #define TIM_CCER_CC6P_Pos         (21U)
12817 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
12818 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
12819 
12820 /*******************  Bit definition for TIM_CNT register  ********************/
12821 #define TIM_CNT_CNT_Pos           (0U)
12822 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
12823 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
12824 #define TIM_CNT_UIFCPY_Pos        (31U)
12825 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
12826 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
12827 
12828 /*******************  Bit definition for TIM_PSC register  ********************/
12829 #define TIM_PSC_PSC_Pos           (0U)
12830 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
12831 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
12832 
12833 /*******************  Bit definition for TIM_ARR register  ********************/
12834 #define TIM_ARR_ARR_Pos           (0U)
12835 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
12836 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
12837 
12838 /*******************  Bit definition for TIM_RCR register  ********************/
12839 #define TIM_RCR_REP_Pos           (0U)
12840 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
12841 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
12842 
12843 /*******************  Bit definition for TIM_CCR1 register  *******************/
12844 #define TIM_CCR1_CCR1_Pos         (0U)
12845 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
12846 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
12847 
12848 /*******************  Bit definition for TIM_CCR2 register  *******************/
12849 #define TIM_CCR2_CCR2_Pos         (0U)
12850 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
12851 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
12852 
12853 /*******************  Bit definition for TIM_CCR3 register  *******************/
12854 #define TIM_CCR3_CCR3_Pos         (0U)
12855 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
12856 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
12857 
12858 /*******************  Bit definition for TIM_CCR4 register  *******************/
12859 #define TIM_CCR4_CCR4_Pos         (0U)
12860 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
12861 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
12862 
12863 /*******************  Bit definition for TIM_CCR5 register  *******************/
12864 #define TIM_CCR5_CCR5_Pos         (0U)
12865 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
12866 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
12867 #define TIM_CCR5_GC5C1_Pos        (29U)
12868 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
12869 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
12870 #define TIM_CCR5_GC5C2_Pos        (30U)
12871 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
12872 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
12873 #define TIM_CCR5_GC5C3_Pos        (31U)
12874 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
12875 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
12876 
12877 /*******************  Bit definition for TIM_CCR6 register  *******************/
12878 #define TIM_CCR6_CCR6_Pos         (0U)
12879 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
12880 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
12881 
12882 /*******************  Bit definition for TIM_BDTR register  *******************/
12883 #define TIM_BDTR_DTG_Pos          (0U)
12884 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
12885 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12886 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
12887 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
12888 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
12889 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
12890 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
12891 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
12892 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
12893 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
12894 
12895 #define TIM_BDTR_LOCK_Pos         (8U)
12896 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
12897 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
12898 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
12899 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
12900 
12901 #define TIM_BDTR_OSSI_Pos         (10U)
12902 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
12903 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
12904 #define TIM_BDTR_OSSR_Pos         (11U)
12905 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
12906 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
12907 #define TIM_BDTR_BKE_Pos          (12U)
12908 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
12909 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
12910 #define TIM_BDTR_BKP_Pos          (13U)
12911 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
12912 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
12913 #define TIM_BDTR_AOE_Pos          (14U)
12914 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
12915 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
12916 #define TIM_BDTR_MOE_Pos          (15U)
12917 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
12918 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
12919 
12920 #define TIM_BDTR_BKF_Pos          (16U)
12921 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
12922 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
12923 #define TIM_BDTR_BK2F_Pos         (20U)
12924 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
12925 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
12926 
12927 #define TIM_BDTR_BK2E_Pos         (24U)
12928 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
12929 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
12930 #define TIM_BDTR_BK2P_Pos         (25U)
12931 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
12932 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
12933 
12934 /*******************  Bit definition for TIM_DCR register  ********************/
12935 #define TIM_DCR_DBA_Pos           (0U)
12936 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
12937 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
12938 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
12939 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
12940 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
12941 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
12942 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
12943 
12944 #define TIM_DCR_DBL_Pos           (8U)
12945 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
12946 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
12947 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
12948 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
12949 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
12950 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
12951 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
12952 
12953 /*******************  Bit definition for TIM_DMAR register  *******************/
12954 #define TIM_DMAR_DMAB_Pos         (0U)
12955 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
12956 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
12957 
12958 /*******************  Bit definition for TIM1_OR1 register  *******************/
12959 #define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)
12960 #define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */
12961 #define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
12962 #define TIM1_OR1_ETR_ADC1_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000001 */
12963 #define TIM1_OR1_ETR_ADC1_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000002 */
12964 
12965 #define TIM1_OR1_TI1_RMP_Pos           (4U)
12966 #define TIM1_OR1_TI1_RMP_Msk           (0x1UL << TIM1_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */
12967 #define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
12968 
12969 /*******************  Bit definition for TIM1_OR2 register  *******************/
12970 #define TIM1_OR2_BKINE_Pos             (0U)
12971 #define TIM1_OR2_BKINE_Msk             (0x1UL << TIM1_OR2_BKINE_Pos)           /*!< 0x00000001 */
12972 #define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
12973 #define TIM1_OR2_BKCMP1E_Pos           (1U)
12974 #define TIM1_OR2_BKCMP1E_Msk           (0x1UL << TIM1_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */
12975 #define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
12976 #define TIM1_OR2_BKCMP2E_Pos           (2U)
12977 #define TIM1_OR2_BKCMP2E_Msk           (0x1UL << TIM1_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */
12978 #define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
12979 #define TIM1_OR2_BKINP_Pos             (9U)
12980 #define TIM1_OR2_BKINP_Msk             (0x1UL << TIM1_OR2_BKINP_Pos)           /*!< 0x00000200 */
12981 #define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
12982 #define TIM1_OR2_BKCMP1P_Pos           (10U)
12983 #define TIM1_OR2_BKCMP1P_Msk           (0x1UL << TIM1_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */
12984 #define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
12985 #define TIM1_OR2_BKCMP2P_Pos           (11U)
12986 #define TIM1_OR2_BKCMP2P_Msk           (0x1UL << TIM1_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */
12987 #define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
12988 
12989 #define TIM1_OR2_ETRSEL_Pos            (14U)
12990 #define TIM1_OR2_ETRSEL_Msk            (0x7UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */
12991 #define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
12992 #define TIM1_OR2_ETRSEL_0              (0x1UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00004000 */
12993 #define TIM1_OR2_ETRSEL_1              (0x2UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00008000 */
12994 #define TIM1_OR2_ETRSEL_2              (0x4UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00010000 */
12995 
12996 /*******************  Bit definition for TIM1_OR3 register  *******************/
12997 #define TIM1_OR3_BK2INE_Pos            (0U)
12998 #define TIM1_OR3_BK2INE_Msk            (0x1UL << TIM1_OR3_BK2INE_Pos)          /*!< 0x00000001 */
12999 #define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
13000 #define TIM1_OR3_BK2CMP1E_Pos          (1U)
13001 #define TIM1_OR3_BK2CMP1E_Msk          (0x1UL << TIM1_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */
13002 #define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
13003 #define TIM1_OR3_BK2CMP2E_Pos          (2U)
13004 #define TIM1_OR3_BK2CMP2E_Msk          (0x1UL << TIM1_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */
13005 #define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
13006 #define TIM1_OR3_BK2INP_Pos            (9U)
13007 #define TIM1_OR3_BK2INP_Msk            (0x1UL << TIM1_OR3_BK2INP_Pos)          /*!< 0x00000200 */
13008 #define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
13009 #define TIM1_OR3_BK2CMP1P_Pos          (10U)
13010 #define TIM1_OR3_BK2CMP1P_Msk          (0x1UL << TIM1_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */
13011 #define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
13012 #define TIM1_OR3_BK2CMP2P_Pos          (11U)
13013 #define TIM1_OR3_BK2CMP2P_Msk          (0x1UL << TIM1_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */
13014 #define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
13015 
13016 
13017 /*******************  Bit definition for TIM2_OR1 register  *******************/
13018 #define TIM2_OR1_ITR1_RMP_Pos     (0U)
13019 #define TIM2_OR1_ITR1_RMP_Msk     (0x1UL << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */
13020 #define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
13021 #define TIM2_OR1_ETR1_RMP_Pos     (1U)
13022 #define TIM2_OR1_ETR1_RMP_Msk     (0x1UL << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */
13023 #define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
13024 
13025 #define TIM2_OR1_TI4_RMP_Pos      (2U)
13026 #define TIM2_OR1_TI4_RMP_Msk      (0x3UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */
13027 #define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
13028 #define TIM2_OR1_TI4_RMP_0        (0x1UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */
13029 #define TIM2_OR1_TI4_RMP_1        (0x2UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */
13030 
13031 /*******************  Bit definition for TIM2_OR2 register  *******************/
13032 #define TIM2_OR2_ETRSEL_Pos       (14U)
13033 #define TIM2_OR2_ETRSEL_Msk       (0x7UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */
13034 #define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
13035 #define TIM2_OR2_ETRSEL_0         (0x1UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */
13036 #define TIM2_OR2_ETRSEL_1         (0x2UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */
13037 #define TIM2_OR2_ETRSEL_2         (0x4UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */
13038 
13039 
13040 /*******************  Bit definition for TIM15_OR1 register  ******************/
13041 #define TIM15_OR1_TI1_RMP_Pos           (0U)
13042 #define TIM15_OR1_TI1_RMP_Msk           (0x1UL << TIM15_OR1_TI1_RMP_Pos)       /*!< 0x00000001 */
13043 #define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
13044 
13045 #define TIM15_OR1_ENCODER_MODE_Pos      (1U)
13046 #define TIM15_OR1_ENCODER_MODE_Msk      (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000006 */
13047 #define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
13048 #define TIM15_OR1_ENCODER_MODE_0        (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000002 */
13049 #define TIM15_OR1_ENCODER_MODE_1        (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000004 */
13050 
13051 /*******************  Bit definition for TIM15_OR2 register  ******************/
13052 #define TIM15_OR2_BKINE_Pos             (0U)
13053 #define TIM15_OR2_BKINE_Msk             (0x1UL << TIM15_OR2_BKINE_Pos)         /*!< 0x00000001 */
13054 #define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
13055 #define TIM15_OR2_BKCMP1E_Pos           (1U)
13056 #define TIM15_OR2_BKCMP1E_Msk           (0x1UL << TIM15_OR2_BKCMP1E_Pos)       /*!< 0x00000002 */
13057 #define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
13058 #define TIM15_OR2_BKCMP2E_Pos           (2U)
13059 #define TIM15_OR2_BKCMP2E_Msk           (0x1UL << TIM15_OR2_BKCMP2E_Pos)       /*!< 0x00000004 */
13060 #define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
13061 #define TIM15_OR2_BKINP_Pos             (9U)
13062 #define TIM15_OR2_BKINP_Msk             (0x1UL << TIM15_OR2_BKINP_Pos)         /*!< 0x00000200 */
13063 #define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
13064 #define TIM15_OR2_BKCMP1P_Pos           (10U)
13065 #define TIM15_OR2_BKCMP1P_Msk           (0x1UL << TIM15_OR2_BKCMP1P_Pos)       /*!< 0x00000400 */
13066 #define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
13067 #define TIM15_OR2_BKCMP2P_Pos           (11U)
13068 #define TIM15_OR2_BKCMP2P_Msk           (0x1UL << TIM15_OR2_BKCMP2P_Pos)       /*!< 0x00000800 */
13069 #define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
13070 
13071 /*******************  Bit definition for TIM16_OR1 register  ******************/
13072 #define TIM16_OR1_TI1_RMP_Pos      (0U)
13073 #define TIM16_OR1_TI1_RMP_Msk      (0x7UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000007 */
13074 #define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
13075 #define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
13076 #define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
13077 #define TIM16_OR1_TI1_RMP_2        (0x4UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000004 */
13078 
13079 /*******************  Bit definition for TIM16_OR2 register  ******************/
13080 #define TIM16_OR2_BKINE_Pos        (0U)
13081 #define TIM16_OR2_BKINE_Msk        (0x1UL << TIM16_OR2_BKINE_Pos)              /*!< 0x00000001 */
13082 #define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
13083 #define TIM16_OR2_BKCMP1E_Pos      (1U)
13084 #define TIM16_OR2_BKCMP1E_Msk      (0x1UL << TIM16_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */
13085 #define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
13086 #define TIM16_OR2_BKCMP2E_Pos      (2U)
13087 #define TIM16_OR2_BKCMP2E_Msk      (0x1UL << TIM16_OR2_BKCMP2E_Pos)            /*!< 0x00000004 */
13088 #define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
13089 #define TIM16_OR2_BKINP_Pos        (9U)
13090 #define TIM16_OR2_BKINP_Msk        (0x1UL << TIM16_OR2_BKINP_Pos)              /*!< 0x00000200 */
13091 #define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
13092 #define TIM16_OR2_BKCMP1P_Pos      (10U)
13093 #define TIM16_OR2_BKCMP1P_Msk      (0x1UL << TIM16_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */
13094 #define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
13095 #define TIM16_OR2_BKCMP2P_Pos      (11U)
13096 #define TIM16_OR2_BKCMP2P_Msk      (0x1UL << TIM16_OR2_BKCMP2P_Pos)            /*!< 0x00000800 */
13097 #define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
13098 
13099 
13100 /******************************************************************************/
13101 /*                                                                            */
13102 /*                         Low Power Timer (LPTIM)                            */
13103 /*                                                                            */
13104 /******************************************************************************/
13105 /******************  Bit definition for LPTIM_ISR register  *******************/
13106 #define LPTIM_ISR_CMPM_Pos          (0U)
13107 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
13108 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
13109 #define LPTIM_ISR_ARRM_Pos          (1U)
13110 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
13111 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
13112 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
13113 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
13114 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
13115 #define LPTIM_ISR_CMPOK_Pos         (3U)
13116 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
13117 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
13118 #define LPTIM_ISR_ARROK_Pos         (4U)
13119 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
13120 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
13121 #define LPTIM_ISR_UP_Pos            (5U)
13122 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
13123 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
13124 #define LPTIM_ISR_DOWN_Pos          (6U)
13125 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
13126 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
13127 
13128 /******************  Bit definition for LPTIM_ICR register  *******************/
13129 #define LPTIM_ICR_CMPMCF_Pos        (0U)
13130 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
13131 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
13132 #define LPTIM_ICR_ARRMCF_Pos        (1U)
13133 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
13134 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
13135 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
13136 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
13137 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
13138 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
13139 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
13140 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
13141 #define LPTIM_ICR_ARROKCF_Pos       (4U)
13142 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
13143 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
13144 #define LPTIM_ICR_UPCF_Pos          (5U)
13145 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
13146 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
13147 #define LPTIM_ICR_DOWNCF_Pos        (6U)
13148 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
13149 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
13150 
13151 /******************  Bit definition for LPTIM_IER register ********************/
13152 #define LPTIM_IER_CMPMIE_Pos        (0U)
13153 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
13154 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
13155 #define LPTIM_IER_ARRMIE_Pos        (1U)
13156 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
13157 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
13158 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
13159 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
13160 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
13161 #define LPTIM_IER_CMPOKIE_Pos       (3U)
13162 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
13163 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
13164 #define LPTIM_IER_ARROKIE_Pos       (4U)
13165 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
13166 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
13167 #define LPTIM_IER_UPIE_Pos          (5U)
13168 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
13169 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
13170 #define LPTIM_IER_DOWNIE_Pos        (6U)
13171 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
13172 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
13173 
13174 /******************  Bit definition for LPTIM_CFGR register *******************/
13175 #define LPTIM_CFGR_CKSEL_Pos        (0U)
13176 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
13177 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
13178 
13179 #define LPTIM_CFGR_CKPOL_Pos        (1U)
13180 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
13181 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
13182 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
13183 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
13184 
13185 #define LPTIM_CFGR_CKFLT_Pos        (3U)
13186 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
13187 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
13188 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
13189 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
13190 
13191 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
13192 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
13193 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
13194 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
13195 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
13196 
13197 #define LPTIM_CFGR_PRESC_Pos        (9U)
13198 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
13199 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
13200 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
13201 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
13202 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
13203 
13204 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
13205 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
13206 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
13207 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
13208 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
13209 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
13210 
13211 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
13212 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
13213 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
13214 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
13215 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
13216 
13217 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
13218 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
13219 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
13220 #define LPTIM_CFGR_WAVE_Pos         (20U)
13221 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
13222 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
13223 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
13224 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
13225 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
13226 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
13227 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
13228 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
13229 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
13230 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
13231 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
13232 #define LPTIM_CFGR_ENC_Pos          (24U)
13233 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
13234 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
13235 
13236 /******************  Bit definition for LPTIM_CR register  ********************/
13237 #define LPTIM_CR_ENABLE_Pos         (0U)
13238 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
13239 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
13240 #define LPTIM_CR_SNGSTRT_Pos        (1U)
13241 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
13242 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
13243 #define LPTIM_CR_CNTSTRT_Pos        (2U)
13244 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
13245 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
13246 
13247 /******************  Bit definition for LPTIM_CMP register  *******************/
13248 #define LPTIM_CMP_CMP_Pos           (0U)
13249 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
13250 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
13251 
13252 /******************  Bit definition for LPTIM_ARR register  *******************/
13253 #define LPTIM_ARR_ARR_Pos           (0U)
13254 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
13255 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
13256 
13257 /******************  Bit definition for LPTIM_CNT register  *******************/
13258 #define LPTIM_CNT_CNT_Pos           (0U)
13259 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
13260 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
13261 
13262 /******************  Bit definition for LPTIM_OR register  ********************/
13263 #define LPTIM_OR_OR_Pos             (0U)
13264 #define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
13265 #define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
13266 #define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
13267 #define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
13268 
13269 /******************************************************************************/
13270 /*                                                                            */
13271 /*                      Analog Comparators (COMP)                             */
13272 /*                                                                            */
13273 /******************************************************************************/
13274 /**********************  Bit definition for COMP_CSR register  ****************/
13275 #define COMP_CSR_EN_Pos            (0U)
13276 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
13277 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
13278 
13279 #define COMP_CSR_PWRMODE_Pos       (2U)
13280 #define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
13281 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
13282 #define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
13283 #define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
13284 
13285 #define COMP_CSR_INMSEL_Pos        (4U)
13286 #define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
13287 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
13288 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
13289 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
13290 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
13291 
13292 #define COMP_CSR_INPSEL_Pos        (7U)
13293 #define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
13294 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
13295 #define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
13296 #define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
13297 
13298 #define COMP_CSR_WINMODE_Pos       (9U)
13299 #define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */
13300 #define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
13301 
13302 #define COMP_CSR_POLARITY_Pos      (15U)
13303 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
13304 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
13305 
13306 #define COMP_CSR_HYST_Pos          (16U)
13307 #define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
13308 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
13309 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
13310 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
13311 
13312 #define COMP_CSR_BLANKING_Pos      (18U)
13313 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
13314 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
13315 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
13316 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
13317 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
13318 
13319 #define COMP_CSR_BRGEN_Pos         (22U)
13320 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
13321 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
13322 #define COMP_CSR_SCALEN_Pos        (23U)
13323 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
13324 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
13325 
13326 #define COMP_CSR_INMESEL_Pos       (25U)
13327 #define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
13328 #define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
13329 #define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
13330 #define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
13331 
13332 #define COMP_CSR_VALUE_Pos         (30U)
13333 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
13334 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
13335 
13336 #define COMP_CSR_LOCK_Pos          (31U)
13337 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
13338 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
13339 
13340 /******************************************************************************/
13341 /*                                                                            */
13342 /*                         Operational Amplifier (OPAMP)                      */
13343 /*                                                                            */
13344 /******************************************************************************/
13345 /*********************  Bit definition for OPAMPx_CSR register  ***************/
13346 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
13347 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
13348 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
13349 #define OPAMP_CSR_OPALPM_Pos             (1U)
13350 #define OPAMP_CSR_OPALPM_Msk             (0x1UL << OPAMP_CSR_OPALPM_Pos)       /*!< 0x00000002 */
13351 #define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
13352 
13353 #define OPAMP_CSR_OPAMODE_Pos            (2U)
13354 #define OPAMP_CSR_OPAMODE_Msk            (0x3UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x0000000C */
13355 #define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
13356 #define OPAMP_CSR_OPAMODE_0              (0x1UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000004 */
13357 #define OPAMP_CSR_OPAMODE_1              (0x2UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000008 */
13358 
13359 #define OPAMP_CSR_PGGAIN_Pos             (4U)
13360 #define OPAMP_CSR_PGGAIN_Msk             (0x3UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000030 */
13361 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
13362 #define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000010 */
13363 #define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000020 */
13364 
13365 #define OPAMP_CSR_VMSEL_Pos              (8U)
13366 #define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000300 */
13367 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
13368 #define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000100 */
13369 #define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000200 */
13370 
13371 #define OPAMP_CSR_VPSEL_Pos              (10U)
13372 #define OPAMP_CSR_VPSEL_Msk              (0x1UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x00000400 */
13373 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
13374 #define OPAMP_CSR_CALON_Pos              (12U)
13375 #define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00001000 */
13376 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
13377 #define OPAMP_CSR_CALSEL_Pos             (13U)
13378 #define OPAMP_CSR_CALSEL_Msk             (0x1UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00002000 */
13379 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
13380 #define OPAMP_CSR_USERTRIM_Pos           (14U)
13381 #define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00004000 */
13382 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
13383 #define OPAMP_CSR_CALOUT_Pos             (15U)
13384 #define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x00008000 */
13385 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
13386 
13387 /*********************  Bit definition for OPAMP1_CSR register  ***************/
13388 #define OPAMP1_CSR_OPAEN_Pos              (0U)
13389 #define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
13390 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
13391 #define OPAMP1_CSR_OPALPM_Pos             (1U)
13392 #define OPAMP1_CSR_OPALPM_Msk             (0x1UL << OPAMP1_CSR_OPALPM_Pos)     /*!< 0x00000002 */
13393 #define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
13394 
13395 #define OPAMP1_CSR_OPAMODE_Pos            (2U)
13396 #define OPAMP1_CSR_OPAMODE_Msk            (0x3UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x0000000C */
13397 #define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
13398 #define OPAMP1_CSR_OPAMODE_0              (0x1UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000004 */
13399 #define OPAMP1_CSR_OPAMODE_1              (0x2UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000008 */
13400 
13401 #define OPAMP1_CSR_PGAGAIN_Pos            (4U)
13402 #define OPAMP1_CSR_PGAGAIN_Msk            (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */
13403 #define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
13404 #define OPAMP1_CSR_PGAGAIN_0              (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */
13405 #define OPAMP1_CSR_PGAGAIN_1              (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */
13406 
13407 #define OPAMP1_CSR_VMSEL_Pos              (8U)
13408 #define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000300 */
13409 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
13410 #define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000100 */
13411 #define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000200 */
13412 
13413 #define OPAMP1_CSR_VPSEL_Pos              (10U)
13414 #define OPAMP1_CSR_VPSEL_Msk              (0x1UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x00000400 */
13415 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
13416 #define OPAMP1_CSR_CALON_Pos              (12U)
13417 #define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00001000 */
13418 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
13419 #define OPAMP1_CSR_CALSEL_Pos             (13U)
13420 #define OPAMP1_CSR_CALSEL_Msk             (0x1UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00002000 */
13421 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
13422 #define OPAMP1_CSR_USERTRIM_Pos           (14U)
13423 #define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00004000 */
13424 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
13425 #define OPAMP1_CSR_CALOUT_Pos             (15U)
13426 #define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x00008000 */
13427 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
13428 
13429 #define OPAMP1_CSR_OPARANGE_Pos           (31U)
13430 #define OPAMP1_CSR_OPARANGE_Msk           (0x1UL << OPAMP1_CSR_OPARANGE_Pos)   /*!< 0x80000000 */
13431 #define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
13432 
13433 /*******************  Bit definition for OPAMP_OTR register  ******************/
13434 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
13435 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13436 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
13437 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
13438 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13439 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
13440 
13441 /*******************  Bit definition for OPAMP1_OTR register  ******************/
13442 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
13443 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13444 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
13445 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
13446 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13447 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
13448 
13449 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
13450 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)
13451 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
13452 #define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
13453 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)
13454 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
13455 #define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
13456 
13457 /*******************  Bit definition for OPAMP1_LPOTR register  ****************/
13458 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)
13459 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
13460 #define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
13461 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)
13462 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
13463 #define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
13464 
13465 /******************************************************************************/
13466 /*                                                                            */
13467 /*                          Touch Sensing Controller (TSC)                    */
13468 /*                                                                            */
13469 /******************************************************************************/
13470 /*******************  Bit definition for TSC_CR register  *********************/
13471 #define TSC_CR_TSCE_Pos          (0U)
13472 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
13473 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
13474 #define TSC_CR_START_Pos         (1U)
13475 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
13476 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
13477 #define TSC_CR_AM_Pos            (2U)
13478 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
13479 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
13480 #define TSC_CR_SYNCPOL_Pos       (3U)
13481 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
13482 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
13483 #define TSC_CR_IODEF_Pos         (4U)
13484 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
13485 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
13486 
13487 #define TSC_CR_MCV_Pos           (5U)
13488 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
13489 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
13490 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
13491 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
13492 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
13493 
13494 #define TSC_CR_PGPSC_Pos         (12U)
13495 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
13496 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
13497 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
13498 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
13499 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
13500 
13501 #define TSC_CR_SSPSC_Pos         (15U)
13502 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
13503 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
13504 #define TSC_CR_SSE_Pos           (16U)
13505 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
13506 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
13507 
13508 #define TSC_CR_SSD_Pos           (17U)
13509 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
13510 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
13511 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
13512 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
13513 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
13514 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
13515 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
13516 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
13517 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
13518 
13519 #define TSC_CR_CTPL_Pos          (24U)
13520 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
13521 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
13522 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
13523 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
13524 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
13525 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
13526 
13527 #define TSC_CR_CTPH_Pos          (28U)
13528 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
13529 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
13530 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
13531 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
13532 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
13533 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
13534 
13535 /*******************  Bit definition for TSC_IER register  ********************/
13536 #define TSC_IER_EOAIE_Pos        (0U)
13537 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
13538 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
13539 #define TSC_IER_MCEIE_Pos        (1U)
13540 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
13541 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
13542 
13543 /*******************  Bit definition for TSC_ICR register  ********************/
13544 #define TSC_ICR_EOAIC_Pos        (0U)
13545 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
13546 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
13547 #define TSC_ICR_MCEIC_Pos        (1U)
13548 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
13549 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
13550 
13551 /*******************  Bit definition for TSC_ISR register  ********************/
13552 #define TSC_ISR_EOAF_Pos         (0U)
13553 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
13554 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
13555 #define TSC_ISR_MCEF_Pos         (1U)
13556 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
13557 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
13558 
13559 /*******************  Bit definition for TSC_IOHCR register  ******************/
13560 #define TSC_IOHCR_G1_IO1_Pos     (0U)
13561 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
13562 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
13563 #define TSC_IOHCR_G1_IO2_Pos     (1U)
13564 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
13565 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
13566 #define TSC_IOHCR_G1_IO3_Pos     (2U)
13567 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
13568 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
13569 #define TSC_IOHCR_G1_IO4_Pos     (3U)
13570 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
13571 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
13572 #define TSC_IOHCR_G2_IO1_Pos     (4U)
13573 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
13574 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
13575 #define TSC_IOHCR_G2_IO2_Pos     (5U)
13576 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
13577 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
13578 #define TSC_IOHCR_G2_IO3_Pos     (6U)
13579 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
13580 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
13581 #define TSC_IOHCR_G2_IO4_Pos     (7U)
13582 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
13583 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
13584 #define TSC_IOHCR_G3_IO1_Pos     (8U)
13585 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
13586 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
13587 #define TSC_IOHCR_G3_IO2_Pos     (9U)
13588 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
13589 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
13590 #define TSC_IOHCR_G3_IO3_Pos     (10U)
13591 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
13592 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
13593 #define TSC_IOHCR_G3_IO4_Pos     (11U)
13594 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
13595 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
13596 #define TSC_IOHCR_G4_IO1_Pos     (12U)
13597 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
13598 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
13599 #define TSC_IOHCR_G4_IO2_Pos     (13U)
13600 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
13601 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
13602 #define TSC_IOHCR_G4_IO3_Pos     (14U)
13603 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
13604 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
13605 #define TSC_IOHCR_G4_IO4_Pos     (15U)
13606 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
13607 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
13608 #define TSC_IOHCR_G5_IO1_Pos     (16U)
13609 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)               /*!< 0x00010000 */
13610 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
13611 #define TSC_IOHCR_G5_IO2_Pos     (17U)
13612 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)               /*!< 0x00020000 */
13613 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
13614 #define TSC_IOHCR_G5_IO3_Pos     (18U)
13615 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)               /*!< 0x00040000 */
13616 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
13617 #define TSC_IOHCR_G5_IO4_Pos     (19U)
13618 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)               /*!< 0x00080000 */
13619 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
13620 #define TSC_IOHCR_G6_IO1_Pos     (20U)
13621 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)               /*!< 0x00100000 */
13622 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
13623 #define TSC_IOHCR_G6_IO2_Pos     (21U)
13624 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)               /*!< 0x00200000 */
13625 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
13626 #define TSC_IOHCR_G6_IO3_Pos     (22U)
13627 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)               /*!< 0x00400000 */
13628 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
13629 #define TSC_IOHCR_G6_IO4_Pos     (23U)
13630 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)               /*!< 0x00800000 */
13631 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
13632 #define TSC_IOHCR_G7_IO1_Pos     (24U)
13633 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)               /*!< 0x01000000 */
13634 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
13635 #define TSC_IOHCR_G7_IO2_Pos     (25U)
13636 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)               /*!< 0x02000000 */
13637 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
13638 #define TSC_IOHCR_G7_IO3_Pos     (26U)
13639 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)               /*!< 0x04000000 */
13640 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
13641 #define TSC_IOHCR_G7_IO4_Pos     (27U)
13642 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)               /*!< 0x08000000 */
13643 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
13644 
13645 /*******************  Bit definition for TSC_IOASCR register  *****************/
13646 #define TSC_IOASCR_G1_IO1_Pos    (0U)
13647 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
13648 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
13649 #define TSC_IOASCR_G1_IO2_Pos    (1U)
13650 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
13651 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
13652 #define TSC_IOASCR_G1_IO3_Pos    (2U)
13653 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
13654 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
13655 #define TSC_IOASCR_G1_IO4_Pos    (3U)
13656 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
13657 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
13658 #define TSC_IOASCR_G2_IO1_Pos    (4U)
13659 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
13660 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
13661 #define TSC_IOASCR_G2_IO2_Pos    (5U)
13662 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
13663 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
13664 #define TSC_IOASCR_G2_IO3_Pos    (6U)
13665 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
13666 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
13667 #define TSC_IOASCR_G2_IO4_Pos    (7U)
13668 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
13669 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
13670 #define TSC_IOASCR_G3_IO1_Pos    (8U)
13671 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
13672 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
13673 #define TSC_IOASCR_G3_IO2_Pos    (9U)
13674 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
13675 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
13676 #define TSC_IOASCR_G3_IO3_Pos    (10U)
13677 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
13678 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
13679 #define TSC_IOASCR_G3_IO4_Pos    (11U)
13680 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
13681 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
13682 #define TSC_IOASCR_G4_IO1_Pos    (12U)
13683 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
13684 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
13685 #define TSC_IOASCR_G4_IO2_Pos    (13U)
13686 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
13687 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
13688 #define TSC_IOASCR_G4_IO3_Pos    (14U)
13689 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
13690 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
13691 #define TSC_IOASCR_G4_IO4_Pos    (15U)
13692 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
13693 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
13694 #define TSC_IOASCR_G5_IO1_Pos    (16U)
13695 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)              /*!< 0x00010000 */
13696 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
13697 #define TSC_IOASCR_G5_IO2_Pos    (17U)
13698 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)              /*!< 0x00020000 */
13699 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
13700 #define TSC_IOASCR_G5_IO3_Pos    (18U)
13701 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)              /*!< 0x00040000 */
13702 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
13703 #define TSC_IOASCR_G5_IO4_Pos    (19U)
13704 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)              /*!< 0x00080000 */
13705 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
13706 #define TSC_IOASCR_G6_IO1_Pos    (20U)
13707 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)              /*!< 0x00100000 */
13708 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
13709 #define TSC_IOASCR_G6_IO2_Pos    (21U)
13710 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)              /*!< 0x00200000 */
13711 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
13712 #define TSC_IOASCR_G6_IO3_Pos    (22U)
13713 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)              /*!< 0x00400000 */
13714 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
13715 #define TSC_IOASCR_G6_IO4_Pos    (23U)
13716 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)              /*!< 0x00800000 */
13717 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
13718 #define TSC_IOASCR_G7_IO1_Pos    (24U)
13719 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)              /*!< 0x01000000 */
13720 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
13721 #define TSC_IOASCR_G7_IO2_Pos    (25U)
13722 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)              /*!< 0x02000000 */
13723 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
13724 #define TSC_IOASCR_G7_IO3_Pos    (26U)
13725 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)              /*!< 0x04000000 */
13726 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
13727 #define TSC_IOASCR_G7_IO4_Pos    (27U)
13728 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)              /*!< 0x08000000 */
13729 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
13730 
13731 /*******************  Bit definition for TSC_IOSCR register  ******************/
13732 #define TSC_IOSCR_G1_IO1_Pos     (0U)
13733 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
13734 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
13735 #define TSC_IOSCR_G1_IO2_Pos     (1U)
13736 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
13737 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
13738 #define TSC_IOSCR_G1_IO3_Pos     (2U)
13739 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
13740 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
13741 #define TSC_IOSCR_G1_IO4_Pos     (3U)
13742 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
13743 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
13744 #define TSC_IOSCR_G2_IO1_Pos     (4U)
13745 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
13746 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
13747 #define TSC_IOSCR_G2_IO2_Pos     (5U)
13748 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
13749 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
13750 #define TSC_IOSCR_G2_IO3_Pos     (6U)
13751 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
13752 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
13753 #define TSC_IOSCR_G2_IO4_Pos     (7U)
13754 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
13755 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
13756 #define TSC_IOSCR_G3_IO1_Pos     (8U)
13757 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
13758 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
13759 #define TSC_IOSCR_G3_IO2_Pos     (9U)
13760 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
13761 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
13762 #define TSC_IOSCR_G3_IO3_Pos     (10U)
13763 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
13764 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
13765 #define TSC_IOSCR_G3_IO4_Pos     (11U)
13766 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
13767 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
13768 #define TSC_IOSCR_G4_IO1_Pos     (12U)
13769 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
13770 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
13771 #define TSC_IOSCR_G4_IO2_Pos     (13U)
13772 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
13773 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
13774 #define TSC_IOSCR_G4_IO3_Pos     (14U)
13775 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
13776 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
13777 #define TSC_IOSCR_G4_IO4_Pos     (15U)
13778 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
13779 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
13780 #define TSC_IOSCR_G5_IO1_Pos     (16U)
13781 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)               /*!< 0x00010000 */
13782 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
13783 #define TSC_IOSCR_G5_IO2_Pos     (17U)
13784 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)               /*!< 0x00020000 */
13785 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
13786 #define TSC_IOSCR_G5_IO3_Pos     (18U)
13787 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)               /*!< 0x00040000 */
13788 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
13789 #define TSC_IOSCR_G5_IO4_Pos     (19U)
13790 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)               /*!< 0x00080000 */
13791 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
13792 #define TSC_IOSCR_G6_IO1_Pos     (20U)
13793 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)               /*!< 0x00100000 */
13794 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
13795 #define TSC_IOSCR_G6_IO2_Pos     (21U)
13796 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)               /*!< 0x00200000 */
13797 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
13798 #define TSC_IOSCR_G6_IO3_Pos     (22U)
13799 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)               /*!< 0x00400000 */
13800 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
13801 #define TSC_IOSCR_G6_IO4_Pos     (23U)
13802 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)               /*!< 0x00800000 */
13803 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
13804 #define TSC_IOSCR_G7_IO1_Pos     (24U)
13805 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)               /*!< 0x01000000 */
13806 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
13807 #define TSC_IOSCR_G7_IO2_Pos     (25U)
13808 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)               /*!< 0x02000000 */
13809 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
13810 #define TSC_IOSCR_G7_IO3_Pos     (26U)
13811 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)               /*!< 0x04000000 */
13812 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
13813 #define TSC_IOSCR_G7_IO4_Pos     (27U)
13814 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)               /*!< 0x08000000 */
13815 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
13816 
13817 /*******************  Bit definition for TSC_IOCCR register  ******************/
13818 #define TSC_IOCCR_G1_IO1_Pos     (0U)
13819 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
13820 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
13821 #define TSC_IOCCR_G1_IO2_Pos     (1U)
13822 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
13823 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
13824 #define TSC_IOCCR_G1_IO3_Pos     (2U)
13825 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
13826 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
13827 #define TSC_IOCCR_G1_IO4_Pos     (3U)
13828 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
13829 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
13830 #define TSC_IOCCR_G2_IO1_Pos     (4U)
13831 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
13832 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
13833 #define TSC_IOCCR_G2_IO2_Pos     (5U)
13834 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
13835 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
13836 #define TSC_IOCCR_G2_IO3_Pos     (6U)
13837 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
13838 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
13839 #define TSC_IOCCR_G2_IO4_Pos     (7U)
13840 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
13841 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
13842 #define TSC_IOCCR_G3_IO1_Pos     (8U)
13843 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
13844 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
13845 #define TSC_IOCCR_G3_IO2_Pos     (9U)
13846 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
13847 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
13848 #define TSC_IOCCR_G3_IO3_Pos     (10U)
13849 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
13850 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
13851 #define TSC_IOCCR_G3_IO4_Pos     (11U)
13852 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
13853 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
13854 #define TSC_IOCCR_G4_IO1_Pos     (12U)
13855 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
13856 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
13857 #define TSC_IOCCR_G4_IO2_Pos     (13U)
13858 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
13859 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
13860 #define TSC_IOCCR_G4_IO3_Pos     (14U)
13861 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
13862 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
13863 #define TSC_IOCCR_G4_IO4_Pos     (15U)
13864 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
13865 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
13866 #define TSC_IOCCR_G5_IO1_Pos     (16U)
13867 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)               /*!< 0x00010000 */
13868 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
13869 #define TSC_IOCCR_G5_IO2_Pos     (17U)
13870 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)               /*!< 0x00020000 */
13871 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
13872 #define TSC_IOCCR_G5_IO3_Pos     (18U)
13873 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)               /*!< 0x00040000 */
13874 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
13875 #define TSC_IOCCR_G5_IO4_Pos     (19U)
13876 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)               /*!< 0x00080000 */
13877 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
13878 #define TSC_IOCCR_G6_IO1_Pos     (20U)
13879 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)               /*!< 0x00100000 */
13880 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
13881 #define TSC_IOCCR_G6_IO2_Pos     (21U)
13882 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)               /*!< 0x00200000 */
13883 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
13884 #define TSC_IOCCR_G6_IO3_Pos     (22U)
13885 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)               /*!< 0x00400000 */
13886 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
13887 #define TSC_IOCCR_G6_IO4_Pos     (23U)
13888 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)               /*!< 0x00800000 */
13889 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
13890 #define TSC_IOCCR_G7_IO1_Pos     (24U)
13891 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)               /*!< 0x01000000 */
13892 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
13893 #define TSC_IOCCR_G7_IO2_Pos     (25U)
13894 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)               /*!< 0x02000000 */
13895 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
13896 #define TSC_IOCCR_G7_IO3_Pos     (26U)
13897 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)               /*!< 0x04000000 */
13898 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
13899 #define TSC_IOCCR_G7_IO4_Pos     (27U)
13900 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)               /*!< 0x08000000 */
13901 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
13902 
13903 /*******************  Bit definition for TSC_IOGCSR register  *****************/
13904 #define TSC_IOGCSR_G1E_Pos       (0U)
13905 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
13906 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
13907 #define TSC_IOGCSR_G2E_Pos       (1U)
13908 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
13909 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
13910 #define TSC_IOGCSR_G3E_Pos       (2U)
13911 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
13912 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
13913 #define TSC_IOGCSR_G4E_Pos       (3U)
13914 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
13915 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
13916 #define TSC_IOGCSR_G5E_Pos       (4U)
13917 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                 /*!< 0x00000010 */
13918 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
13919 #define TSC_IOGCSR_G6E_Pos       (5U)
13920 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                 /*!< 0x00000020 */
13921 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
13922 #define TSC_IOGCSR_G7E_Pos       (6U)
13923 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                 /*!< 0x00000040 */
13924 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
13925 #define TSC_IOGCSR_G1S_Pos       (16U)
13926 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
13927 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
13928 #define TSC_IOGCSR_G2S_Pos       (17U)
13929 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
13930 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
13931 #define TSC_IOGCSR_G3S_Pos       (18U)
13932 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
13933 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
13934 #define TSC_IOGCSR_G4S_Pos       (19U)
13935 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
13936 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
13937 #define TSC_IOGCSR_G5S_Pos       (20U)
13938 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                 /*!< 0x00100000 */
13939 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
13940 #define TSC_IOGCSR_G6S_Pos       (21U)
13941 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                 /*!< 0x00200000 */
13942 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
13943 #define TSC_IOGCSR_G7S_Pos       (22U)
13944 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                 /*!< 0x00400000 */
13945 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
13946 
13947 /*******************  Bit definition for TSC_IOGXCR register  *****************/
13948 #define TSC_IOGXCR_CNT_Pos       (0U)
13949 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
13950 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
13951 
13952 /******************************************************************************/
13953 /*                                                                            */
13954 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
13955 /*                                                                            */
13956 /******************************************************************************/
13957 
13958 /*
13959 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
13960 */
13961 #define USART_TCBGT_SUPPORT
13962 
13963 /******************  Bit definition for USART_CR1 register  *******************/
13964 #define USART_CR1_UE_Pos              (0U)
13965 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)              /*!< 0x00000001 */
13966 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
13967 #define USART_CR1_UESM_Pos            (1U)
13968 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)            /*!< 0x00000002 */
13969 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
13970 #define USART_CR1_RE_Pos              (2U)
13971 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)              /*!< 0x00000004 */
13972 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
13973 #define USART_CR1_TE_Pos              (3U)
13974 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)              /*!< 0x00000008 */
13975 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
13976 #define USART_CR1_IDLEIE_Pos          (4U)
13977 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)          /*!< 0x00000010 */
13978 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
13979 #define USART_CR1_RXNEIE_Pos          (5U)
13980 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)          /*!< 0x00000020 */
13981 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
13982 #define USART_CR1_TCIE_Pos            (6U)
13983 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)            /*!< 0x00000040 */
13984 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
13985 #define USART_CR1_TXEIE_Pos           (7U)
13986 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)           /*!< 0x00000080 */
13987 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
13988 #define USART_CR1_PEIE_Pos            (8U)
13989 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)            /*!< 0x00000100 */
13990 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
13991 #define USART_CR1_PS_Pos              (9U)
13992 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)              /*!< 0x00000200 */
13993 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
13994 #define USART_CR1_PCE_Pos             (10U)
13995 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)             /*!< 0x00000400 */
13996 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
13997 #define USART_CR1_WAKE_Pos            (11U)
13998 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)            /*!< 0x00000800 */
13999 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
14000 #define USART_CR1_M_Pos               (12U)
14001 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)           /*!< 0x10001000 */
14002 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
14003 #define USART_CR1_M0_Pos              (12U)
14004 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)              /*!< 0x00001000 */
14005 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
14006 #define USART_CR1_MME_Pos             (13U)
14007 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)             /*!< 0x00002000 */
14008 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
14009 #define USART_CR1_CMIE_Pos            (14U)
14010 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)            /*!< 0x00004000 */
14011 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
14012 #define USART_CR1_OVER8_Pos           (15U)
14013 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)           /*!< 0x00008000 */
14014 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
14015 #define USART_CR1_DEDT_Pos            (16U)
14016 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)           /*!< 0x001F0000 */
14017 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
14018 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */
14019 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */
14020 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */
14021 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */
14022 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */
14023 #define USART_CR1_DEAT_Pos            (21U)
14024 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)           /*!< 0x03E00000 */
14025 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
14026 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */
14027 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */
14028 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */
14029 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */
14030 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */
14031 #define USART_CR1_RTOIE_Pos           (26U)
14032 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)           /*!< 0x04000000 */
14033 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
14034 #define USART_CR1_EOBIE_Pos           (27U)
14035 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)           /*!< 0x08000000 */
14036 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
14037 #define USART_CR1_M1_Pos              (28U)
14038 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)              /*!< 0x10000000 */
14039 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
14040 
14041 /******************  Bit definition for USART_CR2 register  *******************/
14042 #define USART_CR2_ADDM7_Pos           (4U)
14043 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)           /*!< 0x00000010 */
14044 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
14045 #define USART_CR2_LBDL_Pos            (5U)
14046 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)            /*!< 0x00000020 */
14047 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
14048 #define USART_CR2_LBDIE_Pos           (6U)
14049 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)           /*!< 0x00000040 */
14050 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
14051 #define USART_CR2_LBCL_Pos            (8U)
14052 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)            /*!< 0x00000100 */
14053 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
14054 #define USART_CR2_CPHA_Pos            (9U)
14055 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)            /*!< 0x00000200 */
14056 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
14057 #define USART_CR2_CPOL_Pos            (10U)
14058 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)            /*!< 0x00000400 */
14059 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
14060 #define USART_CR2_CLKEN_Pos           (11U)
14061 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)           /*!< 0x00000800 */
14062 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
14063 #define USART_CR2_STOP_Pos            (12U)
14064 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)            /*!< 0x00003000 */
14065 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
14066 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)            /*!< 0x00001000 */
14067 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)            /*!< 0x00002000 */
14068 #define USART_CR2_LINEN_Pos           (14U)
14069 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)           /*!< 0x00004000 */
14070 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
14071 #define USART_CR2_SWAP_Pos            (15U)
14072 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)            /*!< 0x00008000 */
14073 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
14074 #define USART_CR2_RXINV_Pos           (16U)
14075 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)           /*!< 0x00010000 */
14076 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
14077 #define USART_CR2_TXINV_Pos           (17U)
14078 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)           /*!< 0x00020000 */
14079 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
14080 #define USART_CR2_DATAINV_Pos         (18U)
14081 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)         /*!< 0x00040000 */
14082 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
14083 #define USART_CR2_MSBFIRST_Pos        (19U)
14084 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)        /*!< 0x00080000 */
14085 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
14086 #define USART_CR2_ABREN_Pos           (20U)
14087 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)           /*!< 0x00100000 */
14088 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
14089 #define USART_CR2_ABRMODE_Pos         (21U)
14090 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00600000 */
14091 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
14092 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */
14093 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */
14094 #define USART_CR2_RTOEN_Pos           (23U)
14095 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)           /*!< 0x00800000 */
14096 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
14097 #define USART_CR2_ADD_Pos             (24U)
14098 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)            /*!< 0xFF000000 */
14099 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
14100 
14101 /******************  Bit definition for USART_CR3 register  *******************/
14102 #define USART_CR3_EIE_Pos             (0U)
14103 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)             /*!< 0x00000001 */
14104 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
14105 #define USART_CR3_IREN_Pos            (1U)
14106 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)            /*!< 0x00000002 */
14107 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
14108 #define USART_CR3_IRLP_Pos            (2U)
14109 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)            /*!< 0x00000004 */
14110 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
14111 #define USART_CR3_HDSEL_Pos           (3U)
14112 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)           /*!< 0x00000008 */
14113 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
14114 #define USART_CR3_NACK_Pos            (4U)
14115 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)            /*!< 0x00000010 */
14116 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
14117 #define USART_CR3_SCEN_Pos            (5U)
14118 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)            /*!< 0x00000020 */
14119 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
14120 #define USART_CR3_DMAR_Pos            (6U)
14121 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)            /*!< 0x00000040 */
14122 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
14123 #define USART_CR3_DMAT_Pos            (7U)
14124 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)            /*!< 0x00000080 */
14125 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
14126 #define USART_CR3_RTSE_Pos            (8U)
14127 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)            /*!< 0x00000100 */
14128 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
14129 #define USART_CR3_CTSE_Pos            (9U)
14130 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)            /*!< 0x00000200 */
14131 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
14132 #define USART_CR3_CTSIE_Pos           (10U)
14133 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)           /*!< 0x00000400 */
14134 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
14135 #define USART_CR3_ONEBIT_Pos          (11U)
14136 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)          /*!< 0x00000800 */
14137 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
14138 #define USART_CR3_OVRDIS_Pos          (12U)
14139 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)          /*!< 0x00001000 */
14140 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
14141 #define USART_CR3_DDRE_Pos            (13U)
14142 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)            /*!< 0x00002000 */
14143 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
14144 #define USART_CR3_DEM_Pos             (14U)
14145 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)             /*!< 0x00004000 */
14146 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
14147 #define USART_CR3_DEP_Pos             (15U)
14148 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)             /*!< 0x00008000 */
14149 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
14150 #define USART_CR3_SCARCNT_Pos         (17U)
14151 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)         /*!< 0x000E0000 */
14152 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
14153 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */
14154 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */
14155 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */
14156 #define USART_CR3_WUS_Pos             (20U)
14157 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)             /*!< 0x00300000 */
14158 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
14159 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)             /*!< 0x00100000 */
14160 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)             /*!< 0x00200000 */
14161 #define USART_CR3_WUFIE_Pos           (22U)
14162 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)           /*!< 0x00400000 */
14163 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
14164 #define USART_CR3_UCESM_Pos           (23U)
14165 #define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)           /*!< 0x02000000 */
14166 #define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< USART Clock enable in Stop mode */
14167 #define USART_CR3_TCBGTIE_Pos         (24U)
14168 #define USART_CR3_TCBGTIE_Msk         (0x1UL << USART_CR3_TCBGTIE_Pos)         /*!< 0x01000000 */
14169 #define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
14170 
14171 /******************  Bit definition for USART_BRR register  *******************/
14172 #define USART_BRR_DIV_FRACTION_Pos    (0U)
14173 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)    /*!< 0x0000000F */
14174 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
14175 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
14176 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)  /*!< 0x0000FFF0 */
14177 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
14178 
14179 /******************  Bit definition for USART_GTPR register  ******************/
14180 #define USART_GTPR_PSC_Pos            (0U)
14181 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)           /*!< 0x000000FF */
14182 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
14183 #define USART_GTPR_GT_Pos             (8U)
14184 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)            /*!< 0x0000FF00 */
14185 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
14186 
14187 /*******************  Bit definition for USART_RTOR register  *****************/
14188 #define USART_RTOR_RTO_Pos            (0U)
14189 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)       /*!< 0x00FFFFFF */
14190 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
14191 #define USART_RTOR_BLEN_Pos           (24U)
14192 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)          /*!< 0xFF000000 */
14193 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
14194 
14195 /*******************  Bit definition for USART_RQR register  ******************/
14196 #define USART_RQR_ABRRQ_Pos           (0U)
14197 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)           /*!< 0x00000001 */
14198 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
14199 #define USART_RQR_SBKRQ_Pos           (1U)
14200 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)           /*!< 0x00000002 */
14201 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
14202 #define USART_RQR_MMRQ_Pos            (2U)
14203 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)            /*!< 0x00000004 */
14204 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
14205 #define USART_RQR_RXFRQ_Pos           (3U)
14206 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)           /*!< 0x00000008 */
14207 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
14208 #define USART_RQR_TXFRQ_Pos           (4U)
14209 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)           /*!< 0x00000010 */
14210 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
14211 
14212 /*******************  Bit definition for USART_ISR register  ******************/
14213 #define USART_ISR_PE_Pos              (0U)
14214 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)              /*!< 0x00000001 */
14215 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
14216 #define USART_ISR_FE_Pos              (1U)
14217 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)              /*!< 0x00000002 */
14218 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
14219 #define USART_ISR_NE_Pos              (2U)
14220 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)              /*!< 0x00000004 */
14221 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */
14222 #define USART_ISR_ORE_Pos             (3U)
14223 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)             /*!< 0x00000008 */
14224 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
14225 #define USART_ISR_IDLE_Pos            (4U)
14226 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)            /*!< 0x00000010 */
14227 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
14228 #define USART_ISR_RXNE_Pos            (5U)
14229 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)            /*!< 0x00000020 */
14230 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
14231 #define USART_ISR_TC_Pos              (6U)
14232 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)              /*!< 0x00000040 */
14233 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
14234 #define USART_ISR_TXE_Pos             (7U)
14235 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)             /*!< 0x00000080 */
14236 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
14237 #define USART_ISR_LBDF_Pos            (8U)
14238 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)            /*!< 0x00000100 */
14239 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
14240 #define USART_ISR_CTSIF_Pos           (9U)
14241 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)           /*!< 0x00000200 */
14242 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
14243 #define USART_ISR_CTS_Pos             (10U)
14244 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)             /*!< 0x00000400 */
14245 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
14246 #define USART_ISR_RTOF_Pos            (11U)
14247 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)            /*!< 0x00000800 */
14248 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
14249 #define USART_ISR_EOBF_Pos            (12U)
14250 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)            /*!< 0x00001000 */
14251 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
14252 #define USART_ISR_ABRE_Pos            (14U)
14253 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)            /*!< 0x00004000 */
14254 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
14255 #define USART_ISR_ABRF_Pos            (15U)
14256 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)            /*!< 0x00008000 */
14257 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
14258 #define USART_ISR_BUSY_Pos            (16U)
14259 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)            /*!< 0x00010000 */
14260 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
14261 #define USART_ISR_CMF_Pos             (17U)
14262 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)             /*!< 0x00020000 */
14263 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
14264 #define USART_ISR_SBKF_Pos            (18U)
14265 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)            /*!< 0x00040000 */
14266 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
14267 #define USART_ISR_RWU_Pos             (19U)
14268 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)             /*!< 0x00080000 */
14269 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
14270 #define USART_ISR_WUF_Pos             (20U)
14271 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)             /*!< 0x00100000 */
14272 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
14273 #define USART_ISR_TEACK_Pos           (21U)
14274 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)           /*!< 0x00200000 */
14275 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
14276 #define USART_ISR_REACK_Pos           (22U)
14277 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)           /*!< 0x00400000 */
14278 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
14279 #define USART_ISR_TCBGT_Pos           (25U)
14280 #define USART_ISR_TCBGT_Msk           (0x1UL << USART_ISR_TCBGT_Pos)           /*!< 0x02000000 */
14281 #define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
14282 
14283 /*******************  Bit definition for USART_ICR register  ******************/
14284 #define USART_ICR_PECF_Pos            (0U)
14285 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)            /*!< 0x00000001 */
14286 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
14287 #define USART_ICR_FECF_Pos            (1U)
14288 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)            /*!< 0x00000002 */
14289 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
14290 #define USART_ICR_NECF_Pos            (2U)
14291 #define USART_ICR_NECF_Msk            (0x1UL << USART_ICR_NECF_Pos)            /*!< 0x00000004 */
14292 #define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */
14293 #define USART_ICR_ORECF_Pos           (3U)
14294 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)           /*!< 0x00000008 */
14295 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
14296 #define USART_ICR_IDLECF_Pos          (4U)
14297 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)          /*!< 0x00000010 */
14298 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
14299 #define USART_ICR_TCCF_Pos            (6U)
14300 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)            /*!< 0x00000040 */
14301 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
14302 #define USART_ICR_TCBGTCF_Pos         (7U)
14303 #define USART_ICR_TCBGTCF_Msk         (0x1UL << USART_ICR_TCBGTCF_Pos)         /*!< 0x00000080 */
14304 #define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
14305 #define USART_ICR_LBDCF_Pos           (8U)
14306 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)           /*!< 0x00000100 */
14307 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
14308 #define USART_ICR_CTSCF_Pos           (9U)
14309 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)           /*!< 0x00000200 */
14310 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
14311 #define USART_ICR_RTOCF_Pos           (11U)
14312 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)           /*!< 0x00000800 */
14313 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
14314 #define USART_ICR_EOBCF_Pos           (12U)
14315 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)           /*!< 0x00001000 */
14316 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
14317 #define USART_ICR_CMCF_Pos            (17U)
14318 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)            /*!< 0x00020000 */
14319 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
14320 #define USART_ICR_WUCF_Pos            (20U)
14321 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)            /*!< 0x00100000 */
14322 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
14323 
14324 /* Legacy defines */
14325 #define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos
14326 #define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk
14327 #define USART_ICR_NCF                 USART_ICR_NECF
14328 
14329 /*******************  Bit definition for USART_RDR register  ******************/
14330 #define USART_RDR_RDR_Pos             (0U)
14331 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
14332 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
14333 
14334 /*******************  Bit definition for USART_TDR register  ******************/
14335 #define USART_TDR_TDR_Pos             (0U)
14336 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
14337 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
14338 
14339 /******************************************************************************/
14340 /*                                                                            */
14341 /*           Single Wire Protocol Master Interface (SWPMI)                    */
14342 /*                                                                            */
14343 /******************************************************************************/
14344 
14345 /*******************  Bit definition for SWPMI_CR register   ********************/
14346 #define SWPMI_CR_RXDMA_Pos       (0U)
14347 #define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
14348 #define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
14349 #define SWPMI_CR_TXDMA_Pos       (1U)
14350 #define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
14351 #define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
14352 #define SWPMI_CR_RXMODE_Pos      (2U)
14353 #define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
14354 #define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
14355 #define SWPMI_CR_TXMODE_Pos      (3U)
14356 #define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
14357 #define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
14358 #define SWPMI_CR_LPBK_Pos        (4U)
14359 #define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
14360 #define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
14361 #define SWPMI_CR_SWPACT_Pos      (5U)
14362 #define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
14363 #define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
14364 #define SWPMI_CR_DEACT_Pos       (10U)
14365 #define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
14366 #define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
14367 
14368 /*******************  Bit definition for SWPMI_BRR register  ********************/
14369 #define SWPMI_BRR_BR_Pos         (0U)
14370 #define SWPMI_BRR_BR_Msk         (0x3FUL << SWPMI_BRR_BR_Pos)                  /*!< 0x0000003F */
14371 #define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
14372 
14373 /*******************  Bit definition for SWPMI_ISR register  ********************/
14374 #define SWPMI_ISR_RXBFF_Pos      (0U)
14375 #define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
14376 #define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
14377 #define SWPMI_ISR_TXBEF_Pos      (1U)
14378 #define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
14379 #define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
14380 #define SWPMI_ISR_RXBERF_Pos     (2U)
14381 #define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
14382 #define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
14383 #define SWPMI_ISR_RXOVRF_Pos     (3U)
14384 #define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
14385 #define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
14386 #define SWPMI_ISR_TXUNRF_Pos     (4U)
14387 #define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
14388 #define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
14389 #define SWPMI_ISR_RXNE_Pos       (5U)
14390 #define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
14391 #define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
14392 #define SWPMI_ISR_TXE_Pos        (6U)
14393 #define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
14394 #define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
14395 #define SWPMI_ISR_TCF_Pos        (7U)
14396 #define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
14397 #define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
14398 #define SWPMI_ISR_SRF_Pos        (8U)
14399 #define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
14400 #define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
14401 #define SWPMI_ISR_SUSP_Pos       (9U)
14402 #define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
14403 #define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
14404 #define SWPMI_ISR_DEACTF_Pos     (10U)
14405 #define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
14406 #define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
14407 
14408 /*******************  Bit definition for SWPMI_ICR register  ********************/
14409 #define SWPMI_ICR_CRXBFF_Pos     (0U)
14410 #define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
14411 #define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
14412 #define SWPMI_ICR_CTXBEF_Pos     (1U)
14413 #define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
14414 #define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
14415 #define SWPMI_ICR_CRXBERF_Pos    (2U)
14416 #define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
14417 #define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
14418 #define SWPMI_ICR_CRXOVRF_Pos    (3U)
14419 #define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
14420 #define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
14421 #define SWPMI_ICR_CTXUNRF_Pos    (4U)
14422 #define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
14423 #define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
14424 #define SWPMI_ICR_CTCF_Pos       (7U)
14425 #define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
14426 #define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
14427 #define SWPMI_ICR_CSRF_Pos       (8U)
14428 #define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
14429 #define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
14430 
14431 /*******************  Bit definition for SWPMI_IER register  ********************/
14432 #define SWPMI_IER_SRIE_Pos       (8U)
14433 #define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
14434 #define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
14435 #define SWPMI_IER_TCIE_Pos       (7U)
14436 #define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
14437 #define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
14438 #define SWPMI_IER_TIE_Pos        (6U)
14439 #define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
14440 #define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
14441 #define SWPMI_IER_RIE_Pos        (5U)
14442 #define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
14443 #define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
14444 #define SWPMI_IER_TXUNRIE_Pos    (4U)
14445 #define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
14446 #define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
14447 #define SWPMI_IER_RXOVRIE_Pos    (3U)
14448 #define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
14449 #define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
14450 #define SWPMI_IER_RXBERIE_Pos    (2U)
14451 #define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
14452 #define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
14453 #define SWPMI_IER_TXBEIE_Pos     (1U)
14454 #define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
14455 #define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
14456 #define SWPMI_IER_RXBFIE_Pos     (0U)
14457 #define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
14458 #define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
14459 
14460 /*******************  Bit definition for SWPMI_RFL register  ********************/
14461 #define SWPMI_RFL_RFL_Pos        (0U)
14462 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
14463 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
14464 #define SWPMI_RFL_RFL_0_1_Pos    (0U)
14465 #define SWPMI_RFL_RFL_0_1_Msk    (0x3UL << SWPMI_RFL_RFL_0_1_Pos)              /*!< 0x00000003 */
14466 #define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
14467 
14468 /*******************  Bit definition for SWPMI_TDR register  ********************/
14469 #define SWPMI_TDR_TD_Pos         (0U)
14470 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
14471 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
14472 
14473 /*******************  Bit definition for SWPMI_RDR register  ********************/
14474 #define SWPMI_RDR_RD_Pos         (0U)
14475 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
14476 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
14477 
14478 /*******************  Bit definition for SWPMI_OR register  ********************/
14479 #define SWPMI_OR_TBYP_Pos        (0U)
14480 #define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
14481 #define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
14482 #define SWPMI_OR_CLASS_Pos       (1U)
14483 #define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
14484 #define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
14485 
14486 /******************************************************************************/
14487 /*                                                                            */
14488 /*                                 VREFBUF                                    */
14489 /*                                                                            */
14490 /******************************************************************************/
14491 /*******************  Bit definition for VREFBUF_CSR register  ****************/
14492 #define VREFBUF_CSR_ENVR_Pos    (0U)
14493 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
14494 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
14495 #define VREFBUF_CSR_HIZ_Pos     (1U)
14496 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
14497 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
14498 #define VREFBUF_CSR_VRS_Pos     (2U)
14499 #define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
14500 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
14501 #define VREFBUF_CSR_VRR_Pos     (3U)
14502 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
14503 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
14504 
14505 /*******************  Bit definition for VREFBUF_CCR register  ******************/
14506 #define VREFBUF_CCR_TRIM_Pos    (0U)
14507 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
14508 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
14509 
14510 /******************************************************************************/
14511 /*                                                                            */
14512 /*                            Window WATCHDOG                                 */
14513 /*                                                                            */
14514 /******************************************************************************/
14515 /*******************  Bit definition for WWDG_CR register  ********************/
14516 #define WWDG_CR_T_Pos           (0U)
14517 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
14518 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
14519 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
14520 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
14521 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
14522 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
14523 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
14524 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
14525 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
14526 
14527 #define WWDG_CR_WDGA_Pos        (7U)
14528 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
14529 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
14530 
14531 /*******************  Bit definition for WWDG_CFR register  *******************/
14532 #define WWDG_CFR_W_Pos          (0U)
14533 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
14534 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
14535 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
14536 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
14537 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
14538 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
14539 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
14540 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
14541 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
14542 
14543 #define WWDG_CFR_WDGTB_Pos      (7U)
14544 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000180 */
14545 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
14546 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000080 */
14547 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000100 */
14548 
14549 #define WWDG_CFR_EWI_Pos        (9U)
14550 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
14551 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
14552 
14553 /*******************  Bit definition for WWDG_SR register  ********************/
14554 #define WWDG_SR_EWIF_Pos        (0U)
14555 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
14556 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
14557 
14558 
14559 /******************************************************************************/
14560 /*                                                                            */
14561 /*                                 Debug MCU                                  */
14562 /*                                                                            */
14563 /******************************************************************************/
14564 /********************  Bit definition for DBGMCU_IDCODE register  *************/
14565 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
14566 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
14567 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
14568 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
14569 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
14570 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
14571 
14572 /********************  Bit definition for DBGMCU_CR register  *****************/
14573 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
14574 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
14575 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
14576 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
14577 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
14578 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
14579 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
14580 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
14581 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
14582 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
14583 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
14584 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
14585 
14586 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
14587 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
14588 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
14589 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
14590 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
14591 
14592 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
14593 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
14594 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
14595 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
14596 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
14597 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
14598 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
14599 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
14600 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
14601 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
14602 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
14603 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
14604 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
14605 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
14606 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
14607 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
14608 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
14609 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
14610 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
14611 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
14612 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
14613 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
14614 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
14615 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
14616 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
14617 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)
14618 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
14619 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
14620 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)
14621 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
14622 #define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
14623 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
14624 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
14625 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
14626 
14627 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
14628 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)
14629 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
14630 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
14631 
14632 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
14633 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
14634 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
14635 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
14636 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
14637 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
14638 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
14639 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
14640 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
14641 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
14642 
14643 
14644 /**
14645   * @}
14646   */
14647 
14648 /**
14649   * @}
14650   */
14651 
14652 /** @addtogroup Exported_macros
14653   * @{
14654   */
14655 
14656 /******************************* ADC Instances ********************************/
14657 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14658 
14659 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
14660 
14661 /******************************** CAN Instances ******************************/
14662 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
14663 
14664 /******************************** COMP Instances ******************************/
14665 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
14666                                         ((INSTANCE) == COMP2))
14667 
14668 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
14669 
14670 /******************** COMP Instances with window mode capability **************/
14671 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
14672 
14673 /******************************* CRC Instances ********************************/
14674 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14675 
14676 /******************************* DAC Instances ********************************/
14677 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14678 
14679 /******************************** DMA Instances *******************************/
14680 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
14681                                        ((INSTANCE) == DMA1_Channel2) || \
14682                                        ((INSTANCE) == DMA1_Channel3) || \
14683                                        ((INSTANCE) == DMA1_Channel4) || \
14684                                        ((INSTANCE) == DMA1_Channel5) || \
14685                                        ((INSTANCE) == DMA1_Channel6) || \
14686                                        ((INSTANCE) == DMA1_Channel7) || \
14687                                        ((INSTANCE) == DMA2_Channel1) || \
14688                                        ((INSTANCE) == DMA2_Channel2) || \
14689                                        ((INSTANCE) == DMA2_Channel3) || \
14690                                        ((INSTANCE) == DMA2_Channel4) || \
14691                                        ((INSTANCE) == DMA2_Channel5) || \
14692                                        ((INSTANCE) == DMA2_Channel6) || \
14693                                        ((INSTANCE) == DMA2_Channel7))
14694 
14695 /******************************* GPIO Instances *******************************/
14696 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14697                                         ((INSTANCE) == GPIOB) || \
14698                                         ((INSTANCE) == GPIOC) || \
14699                                         ((INSTANCE) == GPIOD) || \
14700                                         ((INSTANCE) == GPIOE) || \
14701                                         ((INSTANCE) == GPIOH))
14702 
14703 /******************************* GPIO AF Instances ****************************/
14704 /* On L4, all GPIO Bank support AF */
14705 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
14706 
14707 /**************************** GPIO Lock Instances *****************************/
14708 /* On L4, all GPIO Bank support the Lock mechanism */
14709 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
14710 
14711 /******************************** I2C Instances *******************************/
14712 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14713                                        ((INSTANCE) == I2C2) || \
14714                                        ((INSTANCE) == I2C3))
14715 
14716 /****************** I2C Instances : wakeup capability from stop modes *********/
14717 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
14718 
14719 /****************************** OPAMP Instances *******************************/
14720 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
14721 
14722 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
14723 
14724 /******************************* QSPI Instances *******************************/
14725 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
14726 
14727 /******************************* RNG Instances ********************************/
14728 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
14729 
14730 /****************************** RTC Instances *********************************/
14731 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
14732 
14733 /******************************** SAI Instances *******************************/
14734 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
14735                                        ((INSTANCE) == SAI1_Block_B))
14736 
14737 /****************************** SDMMC Instances *******************************/
14738 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
14739 
14740 /****************************** SMBUS Instances *******************************/
14741 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14742                                          ((INSTANCE) == I2C2) || \
14743                                          ((INSTANCE) == I2C3))
14744 
14745 /******************************** SPI Instances *******************************/
14746 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14747                                        ((INSTANCE) == SPI2) || \
14748                                        ((INSTANCE) == SPI3))
14749 
14750 /******************************** SWPMI Instances *****************************/
14751 #define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
14752 
14753 /****************** LPTIM Instances : All supported instances *****************/
14754 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
14755                                          ((INSTANCE) == LPTIM2))
14756 
14757 /****************** LPTIM Instances : supporting the encoder mode *************/
14758 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
14759 
14760 /****************** TIM Instances : All supported instances *******************/
14761 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
14762                                          ((INSTANCE) == TIM2)   || \
14763                                          ((INSTANCE) == TIM6)   || \
14764                                          ((INSTANCE) == TIM7)   || \
14765                                          ((INSTANCE) == TIM15)  || \
14766                                          ((INSTANCE) == TIM16))
14767 
14768 /****************** TIM Instances : supporting 32 bits counter ****************/
14769 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
14770 
14771 /****************** TIM Instances : supporting the break function *************/
14772 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
14773                                             ((INSTANCE) == TIM15)   || \
14774                                             ((INSTANCE) == TIM16))
14775 
14776 /************** TIM Instances : supporting Break source selection *************/
14777 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14778                                                ((INSTANCE) == TIM15)  || \
14779                                                ((INSTANCE) == TIM16))
14780 
14781 /****************** TIM Instances : supporting 2 break inputs *****************/
14782 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
14783 
14784 /************* TIM Instances : at least 1 capture/compare channel *************/
14785 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14786                                          ((INSTANCE) == TIM2)   || \
14787                                          ((INSTANCE) == TIM15)  || \
14788                                          ((INSTANCE) == TIM16))
14789 
14790 /************ TIM Instances : at least 2 capture/compare channels *************/
14791 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14792                                          ((INSTANCE) == TIM2)   || \
14793                                          ((INSTANCE) == TIM15))
14794 
14795 /************ TIM Instances : at least 3 capture/compare channels *************/
14796 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14797                                          ((INSTANCE) == TIM2))
14798 
14799 /************ TIM Instances : at least 4 capture/compare channels *************/
14800 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14801                                          ((INSTANCE) == TIM2))
14802 
14803 /****************** TIM Instances : at least 5 capture/compare channels *******/
14804 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
14805 
14806 /****************** TIM Instances : at least 6 capture/compare channels *******/
14807 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
14808 
14809 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
14810 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
14811                                             ((INSTANCE) == TIM15)  || \
14812                                             ((INSTANCE) == TIM16))
14813 
14814 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
14815 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
14816                                             ((INSTANCE) == TIM2)   || \
14817                                             ((INSTANCE) == TIM6)   || \
14818                                             ((INSTANCE) == TIM7)   || \
14819                                             ((INSTANCE) == TIM15)  || \
14820                                             ((INSTANCE) == TIM16))
14821 
14822 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
14823 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
14824                                             ((INSTANCE) == TIM2)   || \
14825                                             ((INSTANCE) == TIM15)  || \
14826                                             ((INSTANCE) == TIM16))
14827 
14828 /******************** TIM Instances : DMA burst feature ***********************/
14829 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14830                                             ((INSTANCE) == TIM2)   || \
14831                                             ((INSTANCE) == TIM15)  || \
14832                                             ((INSTANCE) == TIM16))
14833 
14834 /******************* TIM Instances : output(s) available **********************/
14835 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
14836     ((((INSTANCE) == TIM1) &&                  \
14837      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14838       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14839       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14840       ((CHANNEL) == TIM_CHANNEL_4) ||          \
14841       ((CHANNEL) == TIM_CHANNEL_5) ||          \
14842       ((CHANNEL) == TIM_CHANNEL_6)))           \
14843      ||                                        \
14844      (((INSTANCE) == TIM2) &&                  \
14845      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14846       ((CHANNEL) == TIM_CHANNEL_2) ||          \
14847       ((CHANNEL) == TIM_CHANNEL_3) ||          \
14848       ((CHANNEL) == TIM_CHANNEL_4)))           \
14849      ||                                        \
14850      (((INSTANCE) == TIM15) &&                 \
14851      (((CHANNEL) == TIM_CHANNEL_1) ||          \
14852       ((CHANNEL) == TIM_CHANNEL_2)))           \
14853      ||                                        \
14854      (((INSTANCE) == TIM16) &&                 \
14855      (((CHANNEL) == TIM_CHANNEL_1))))
14856 
14857 /****************** TIM Instances : supporting complementary output(s) ********/
14858 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
14859    ((((INSTANCE) == TIM1) &&                    \
14860      (((CHANNEL) == TIM_CHANNEL_1) ||           \
14861       ((CHANNEL) == TIM_CHANNEL_2) ||           \
14862       ((CHANNEL) == TIM_CHANNEL_3)))            \
14863     ||                                          \
14864     (((INSTANCE) == TIM15) &&                   \
14865      ((CHANNEL) == TIM_CHANNEL_1))              \
14866     ||                                          \
14867     (((INSTANCE) == TIM16) &&                   \
14868      ((CHANNEL) == TIM_CHANNEL_1)))
14869 
14870 /****************** TIM Instances : supporting clock division *****************/
14871 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
14872                                                     ((INSTANCE) == TIM2)    || \
14873                                                     ((INSTANCE) == TIM15)   || \
14874                                                     ((INSTANCE) == TIM16))
14875 
14876 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
14877 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14878                                                         ((INSTANCE) == TIM2) || \
14879                                                         ((INSTANCE) == TIM15))
14880 
14881 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
14882 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14883                                                         ((INSTANCE) == TIM2))
14884 
14885 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
14886 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
14887                                                         ((INSTANCE) == TIM2) || \
14888                                                         ((INSTANCE) == TIM15))
14889 
14890 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
14891 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
14892                                                         ((INSTANCE) == TIM2) || \
14893                                                         ((INSTANCE) == TIM15))
14894 
14895 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
14896 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
14897 
14898 /****************** TIM Instances : supporting commutation event generation ***/
14899 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14900                                                      ((INSTANCE) == TIM15)  || \
14901                                                      ((INSTANCE) == TIM16))
14902 
14903 /****************** TIM Instances : supporting counting mode selection ********/
14904 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
14905                                                         ((INSTANCE) == TIM2))
14906 
14907 /****************** TIM Instances : supporting encoder interface **************/
14908 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
14909                                                       ((INSTANCE) == TIM2))
14910 
14911 /****************** TIM Instances : supporting Hall sensor interface **********/
14912 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
14913                                                           ((INSTANCE) == TIM2))
14914 
14915 /**************** TIM Instances : external trigger input available ************/
14916 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
14917                                             ((INSTANCE) == TIM2))
14918 
14919 /************* TIM Instances : supporting ETR source selection ***************/
14920 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14921                                              ((INSTANCE) == TIM2))
14922 
14923 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
14924 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
14925                                             ((INSTANCE) == TIM2)  || \
14926                                             ((INSTANCE) == TIM6)  || \
14927                                             ((INSTANCE) == TIM7)  || \
14928                                             ((INSTANCE) == TIM15))
14929 
14930 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14931 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14932                                             ((INSTANCE) == TIM2)  || \
14933                                             ((INSTANCE) == TIM15))
14934 
14935 /****************** TIM Instances : supporting OCxREF clear *******************/
14936 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
14937                                                        ((INSTANCE) == TIM2))
14938 
14939 /****************** TIM Instances : remapping capability **********************/
14940 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
14941                                             ((INSTANCE) == TIM2)  || \
14942                                             ((INSTANCE) == TIM15) || \
14943                                             ((INSTANCE) == TIM16))
14944 
14945 /****************** TIM Instances : supporting repetition counter *************/
14946 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
14947                                                        ((INSTANCE) == TIM15) || \
14948                                                        ((INSTANCE) == TIM16))
14949 
14950 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
14951 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
14952 
14953 /******************* TIM Instances : Timer input XOR function *****************/
14954 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
14955                                             ((INSTANCE) == TIM2)   || \
14956                                             ((INSTANCE) == TIM15))
14957 
14958 /****************** TIM Instances : Advanced timer instances *******************/
14959 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
14960 
14961 /****************************** TSC Instances *********************************/
14962 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
14963 
14964 /******************** USART Instances : Synchronous mode **********************/
14965 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14966                                      ((INSTANCE) == USART2) || \
14967                                      ((INSTANCE) == USART3))
14968 
14969 /******************** UART Instances : Asynchronous mode **********************/
14970 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14971                                     ((INSTANCE) == USART2) || \
14972                                     ((INSTANCE) == USART3))
14973 
14974 /****************** UART Instances : Auto Baud Rate detection ****************/
14975 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14976                                                             ((INSTANCE) == USART2) || \
14977                                                             ((INSTANCE) == USART3))
14978 
14979 /****************** UART Instances : Driver Enable *****************/
14980 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
14981                                                       ((INSTANCE) == USART2) || \
14982                                                       ((INSTANCE) == USART3) || \
14983                                                       ((INSTANCE) == LPUART1))
14984 
14985 /******************** UART Instances : Half-Duplex mode **********************/
14986 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
14987                                                  ((INSTANCE) == USART2) || \
14988                                                  ((INSTANCE) == USART3) || \
14989                                                  ((INSTANCE) == LPUART1))
14990 
14991 /****************** UART Instances : Hardware Flow control ********************/
14992 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
14993                                            ((INSTANCE) == USART2) || \
14994                                            ((INSTANCE) == USART3) || \
14995                                            ((INSTANCE) == LPUART1))
14996 
14997 /******************** UART Instances : LIN mode **********************/
14998 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
14999                                           ((INSTANCE) == USART2) || \
15000                                           ((INSTANCE) == USART3))
15001 
15002 /******************** UART Instances : Wake-up from Stop mode **********************/
15003 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
15004                                                       ((INSTANCE) == USART2) || \
15005                                                       ((INSTANCE) == USART3) || \
15006                                                       ((INSTANCE) == LPUART1))
15007 
15008 /*********************** UART Instances : IRDA mode ***************************/
15009 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15010                                     ((INSTANCE) == USART2) || \
15011                                     ((INSTANCE) == USART3))
15012 
15013 /********************* USART Instances : Smard card mode ***********************/
15014 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15015                                          ((INSTANCE) == USART2) || \
15016                                          ((INSTANCE) == USART3))
15017 
15018 /******************** LPUART Instance *****************************************/
15019 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
15020 
15021 /****************************** IWDG Instances ********************************/
15022 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
15023 
15024 /****************************** WWDG Instances ********************************/
15025 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15026 
15027 /**
15028   * @}
15029   */
15030 
15031 
15032 /******************************************************************************/
15033 /*  For a painless codes migration between the STM32L4xx device product       */
15034 /*  lines, the aliases defined below are put in place to overcome the         */
15035 /*  differences in the interrupt handlers and IRQn definitions.               */
15036 /*  No need to update developed interrupt code when moving across             */
15037 /*  product lines within the same STM32L4 Family                              */
15038 /******************************************************************************/
15039 
15040 /* Aliases for __IRQn */
15041 #define TIM6_IRQn                      TIM6_DAC_IRQn
15042 #define ADC1_2_IRQn                    ADC1_IRQn
15043 #define TIM1_TRG_COM_TIM17_IRQn        TIM1_TRG_COM_IRQn
15044 #define HASH_RNG_IRQn                  RNG_IRQn
15045 #define HASH_CRS_IRQn                  CRS_IRQn
15046 
15047 /* Aliases for __IRQHandler */
15048 #define TIM6_IRQHandler                TIM6_DAC_IRQHandler
15049 #define ADC1_2_IRQHandler              ADC1_IRQHandler
15050 #define TIM1_TRG_COM_TIM17_IRQHandler  TIM1_TRG_COM_IRQHandler
15051 #define HASH_RNG_IRQHandler            RNG_IRQHandler
15052 #define HASH_CRS_IRQHandler            CRS_IRQHandler
15053 
15054 #ifdef __cplusplus
15055 }
15056 #endif /* __cplusplus */
15057 
15058 #endif /* __STM32L431xx_H */
15059 
15060 /**
15061   * @}
15062   */
15063 
15064   /**
15065   * @}
15066   */
15067 
15068 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
15069