1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.
28 *
29 * This software is licensed under terms that can be found in the LICENSE file in
30 * the root directory of this software component.
31 * If no LICENSE file comes with this software, it is provided AS-IS.
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32L1xx_LL_BUS_H
37 #define __STM32L1xx_LL_BUS_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32l1xx.h"
45
46 /** @addtogroup STM32L1xx_LL_Driver
47 * @{
48 */
49
50 #if defined(RCC)
51
52 /** @defgroup BUS_LL BUS
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58
59 /* Private constants ---------------------------------------------------------*/
60
61 /* Private macros ------------------------------------------------------------*/
62
63 /* Exported types ------------------------------------------------------------*/
64 /* Exported constants --------------------------------------------------------*/
65 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
66 * @{
67 */
68
69 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
70 * @{
71 */
72 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
73 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
74 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
75 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
76 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
77 #if defined(GPIOE)
78 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
79 #endif/*GPIOE*/
80 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
81 #if defined(GPIOF)
82 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
83 #endif/*GPIOF*/
84 #if defined(GPIOG)
85 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
86 #endif/*GPIOG*/
87 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
88 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
89 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
90 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
91 #if defined(DMA2)
92 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
93 #endif/*DMA2*/
94 #if defined(AES)
95 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
96 #endif/*AES*/
97 #if defined(FSMC_Bank1)
98 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
99 #endif/*FSMC_Bank1*/
100 /**
101 * @}
102 */
103
104 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
105 * @{
106 */
107 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
108 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
109 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
110 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
111 #if defined(TIM5)
112 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
113 #endif /*TIM5*/
114 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
115 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
116 #if defined(LCD)
117 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
118 #endif /*LCD*/
119 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
120 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
121 #if defined(SPI3)
122 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
123 #endif /*SPI3*/
124 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
125 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
126 #if defined(UART4)
127 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
128 #endif /*UART4*/
129 #if defined(UART5)
130 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
131 #endif /*UART5*/
132 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
133 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
134 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
135 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
136 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
137 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
138 #if defined(OPAMP)
139 /* Note: Peripherals COMP and OPAMP share the same clock domain */
140 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
141 #endif
142 /**
143 * @}
144 */
145
146 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
147 * @{
148 */
149 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
150 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
151 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
152 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
153 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
154 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
155 #if defined(SDIO)
156 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
157 #endif /*SDIO*/
158 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
159 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
160 /**
161 * @}
162 */
163
164 /**
165 * @}
166 */
167
168 /* Exported macro ------------------------------------------------------------*/
169
170 /* Exported functions --------------------------------------------------------*/
171 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
172 * @{
173 */
174
175 /** @defgroup BUS_LL_EF_AHB1 AHB1
176 * @{
177 */
178
179 /**
180 * @brief Enable AHB1 peripherals clock.
181 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
182 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
183 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
184 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
185 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
186 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
187 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
188 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
189 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
190 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
191 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
192 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
193 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
194 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
195 * @param Periphs This parameter can be a combination of the following values:
196 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
197 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
198 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
199 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
200 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
201 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
202 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
203 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
204 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
205 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
206 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
207 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
208 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
209 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
210 *
211 * (*) value not defined in all devices.
212 * @retval None
213 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)214 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
215 {
216 __IO uint32_t tmpreg;
217 SET_BIT(RCC->AHBENR, Periphs);
218 /* Delay after an RCC peripheral clock enabling */
219 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
220 (void)tmpreg;
221 }
222
223 /**
224 * @brief Check if AHB1 peripheral clock is enabled or not
225 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
226 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
227 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
228 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
229 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
230 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
231 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
232 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
233 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
234 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
235 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
236 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
237 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
238 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
239 * @param Periphs This parameter can be a combination of the following values:
240 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
241 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
242 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
243 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
244 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
245 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
246 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
247 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
248 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
249 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
250 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
251 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
252 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
253 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
254 *
255 * (*) value not defined in all devices.
256 * @retval State of Periphs (1 or 0).
257 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)258 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
259 {
260 return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);
261 }
262
263 /**
264 * @brief Disable AHB1 peripherals clock.
265 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
266 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
267 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
268 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
269 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
270 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
271 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
272 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
273 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
274 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
275 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
276 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
277 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
278 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
279 * @param Periphs This parameter can be a combination of the following values:
280 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
281 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
282 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
283 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
284 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
285 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
286 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
287 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
288 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
289 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
290 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
291 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
292 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
293 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
294 *
295 * (*) value not defined in all devices.
296 * @retval None
297 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)298 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
299 {
300 CLEAR_BIT(RCC->AHBENR, Periphs);
301 }
302
303 /**
304 * @brief Force AHB1 peripherals reset.
305 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
306 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
307 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
308 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
309 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
310 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
311 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
312 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
313 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
314 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
315 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
316 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
317 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
318 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
319 * @param Periphs This parameter can be a combination of the following values:
320 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
321 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
322 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
323 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
324 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
325 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
326 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
327 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
328 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
329 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
330 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
331 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
333 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
334 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
335 *
336 * (*) value not defined in all devices.
337 * @retval None
338 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)339 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
340 {
341 SET_BIT(RCC->AHBRSTR, Periphs);
342 }
343
344 /**
345 * @brief Release AHB1 peripherals reset.
346 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
347 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
348 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
349 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
350 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
351 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
352 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
353 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
354 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
355 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
356 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
357 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
358 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
359 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
360 * @param Periphs This parameter can be a combination of the following values:
361 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
362 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
363 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
364 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
368 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
370 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
371 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
372 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
373 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
374 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
375 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
376 *
377 * (*) value not defined in all devices.
378 * @retval None
379 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)380 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
381 {
382 CLEAR_BIT(RCC->AHBRSTR, Periphs);
383 }
384
385 /**
386 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
387 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
388 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
389 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
390 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
391 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
392 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
393 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
394 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
395 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
396 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
397 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
398 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
399 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
400 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
401 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
402 * @param Periphs This parameter can be a combination of the following values:
403 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
410 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
411 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
412 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
413 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
414 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
415 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
416 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
417 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
418 *
419 * (*) value not defined in all devices.
420 * @retval None
421 */
LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)422 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
423 {
424 __IO uint32_t tmpreg;
425 SET_BIT(RCC->AHBLPENR, Periphs);
426 /* Delay after an RCC peripheral clock enabling */
427 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
428 (void)tmpreg;
429 }
430
431 /**
432 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
433 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
434 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
435 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
436 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
437 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
438 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
439 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
440 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
441 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
442 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
443 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
444 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
445 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
446 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
447 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
448 * @param Periphs This parameter can be a combination of the following values:
449 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
450 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
457 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
458 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
459 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
460 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
461 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
462 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
463 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
464 *
465 * (*) value not defined in all devices.
466 * @retval None
467 */
LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)468 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
469 {
470 CLEAR_BIT(RCC->AHBLPENR, Periphs);
471 }
472
473 /**
474 * @}
475 */
476
477 /** @defgroup BUS_LL_EF_APB1 APB1
478 * @{
479 */
480
481 /**
482 * @brief Enable APB1 peripherals clock.
483 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
484 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
485 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
486 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
487 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
488 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
489 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
490 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
491 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
492 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
493 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
494 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
495 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
496 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
497 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
498 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
499 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
500 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
501 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
502 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
503 * @param Periphs This parameter can be a combination of the following values:
504 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
505 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
506 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
507 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
510 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
511 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
512 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
513 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
514 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
515 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
516 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
517 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
518 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
519 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
520 * @arg @ref LL_APB1_GRP1_PERIPH_USB
521 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
522 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
523 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
524 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
525 *
526 * (*) value not defined in all devices.
527 * @retval None
528 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)529 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
530 {
531 __IO uint32_t tmpreg;
532 SET_BIT(RCC->APB1ENR, Periphs);
533 /* Delay after an RCC peripheral clock enabling */
534 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
535 (void)tmpreg;
536 }
537
538 /**
539 * @brief Check if APB1 peripheral clock is enabled or not
540 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
541 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
542 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
543 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
544 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
545 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
546 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
547 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
548 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
549 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
550 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
551 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
552 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
553 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
554 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
555 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
556 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
557 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
558 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
559 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
560 * @param Periphs This parameter can be a combination of the following values:
561 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
562 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
565 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
566 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
567 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
568 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
569 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
570 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
571 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
572 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
573 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
574 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
575 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
576 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
577 * @arg @ref LL_APB1_GRP1_PERIPH_USB
578 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
579 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
580 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
581 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
582 *
583 * (*) value not defined in all devices.
584 * @retval State of Periphs (1 or 0).
585 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)586 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
587 {
588 return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
589 }
590
591 /**
592 * @brief Disable APB1 peripherals clock.
593 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
594 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
595 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
596 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
597 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
598 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
599 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
600 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
601 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
602 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
603 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
604 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
605 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
606 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
607 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
608 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
609 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
610 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
611 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
612 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
613 * @param Periphs This parameter can be a combination of the following values:
614 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
615 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
620 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
621 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
622 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
623 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
624 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
625 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
626 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
627 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
628 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
629 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
630 * @arg @ref LL_APB1_GRP1_PERIPH_USB
631 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
632 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
633 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
634 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
635 *
636 * (*) value not defined in all devices.
637 * @retval None
638 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)639 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
640 {
641 CLEAR_BIT(RCC->APB1ENR, Periphs);
642 }
643
644 /**
645 * @brief Force APB1 peripherals reset.
646 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
647 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
648 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
649 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
650 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
651 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
652 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
653 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
654 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
655 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
656 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
657 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
658 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
659 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
660 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
661 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
662 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
663 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
664 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
665 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
666 * @param Periphs This parameter can be a combination of the following values:
667 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
668 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
669 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
670 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
671 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
672 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
673 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
674 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
675 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
676 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
677 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
678 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
679 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
680 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
681 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
682 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
683 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
684 * @arg @ref LL_APB1_GRP1_PERIPH_USB
685 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
686 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
687 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
688 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
689 *
690 * (*) value not defined in all devices.
691 * @retval None
692 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)693 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
694 {
695 SET_BIT(RCC->APB1RSTR, Periphs);
696 }
697
698 /**
699 * @brief Release APB1 peripherals reset.
700 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
701 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
702 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
703 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
704 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
705 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
706 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
707 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
708 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
709 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
710 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
711 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
712 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
713 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
714 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
715 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
716 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
717 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
718 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
719 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
720 * @param Periphs This parameter can be a combination of the following values:
721 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
722 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
723 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
724 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
725 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
726 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
727 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
728 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
729 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
730 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
731 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
732 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
733 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
734 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
735 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
736 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
737 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
738 * @arg @ref LL_APB1_GRP1_PERIPH_USB
739 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
740 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
741 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
742 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
743 *
744 * (*) value not defined in all devices.
745 * @retval None
746 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)747 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
748 {
749 CLEAR_BIT(RCC->APB1RSTR, Periphs);
750 }
751
752 /**
753 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
754 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
755 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
756 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
757 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
758 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
759 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
760 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
761 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
762 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
763 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
764 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
765 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
766 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
767 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
768 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
769 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
770 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
771 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
772 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
773 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
774 * @param Periphs This parameter can be a combination of the following values:
775 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
776 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
777 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
778 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
779 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
780 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
781 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
782 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
783 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
784 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
785 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
786 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
787 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
788 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
789 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
790 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
791 * @arg @ref LL_APB1_GRP1_PERIPH_USB
792 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
793 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
794 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
795 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
796 *
797 * (*) value not defined in all devices.
798 * @retval None
799 */
LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)800 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
801 {
802 __IO uint32_t tmpreg;
803 SET_BIT(RCC->APB1LPENR, Periphs);
804 /* Delay after an RCC peripheral clock enabling */
805 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
806 (void)tmpreg;
807 }
808
809 /**
810 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
811 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
812 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
813 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
814 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
815 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
816 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
817 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
818 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
819 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
820 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
821 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
822 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
823 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
824 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
825 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
826 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
827 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
828 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
829 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
830 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
831 * @param Periphs This parameter can be a combination of the following values:
832 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
833 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
834 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
835 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
836 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
837 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
838 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
839 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
840 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
841 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
842 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
843 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
844 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
845 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
846 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
847 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
848 * @arg @ref LL_APB1_GRP1_PERIPH_USB
849 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
850 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
851 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
852 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
853 *
854 * (*) value not defined in all devices.
855 * @retval None
856 */
LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)857 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
858 {
859 CLEAR_BIT(RCC->APB1LPENR, Periphs);
860 }
861
862 /**
863 * @}
864 */
865
866 /** @defgroup BUS_LL_EF_APB2 APB2
867 * @{
868 */
869
870 /**
871 * @brief Enable APB2 peripherals clock.
872 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
873 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
874 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
875 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
876 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
877 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
878 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
879 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
880 * @param Periphs This parameter can be a combination of the following values:
881 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
883 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
885 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
886 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
887 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
888 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
889 *
890 * (*) value not defined in all devices.
891 * @retval None
892 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)893 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
894 {
895 __IO uint32_t tmpreg;
896 SET_BIT(RCC->APB2ENR, Periphs);
897 /* Delay after an RCC peripheral clock enabling */
898 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
899 (void)tmpreg;
900 }
901
902 /**
903 * @brief Check if APB2 peripheral clock is enabled or not
904 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
905 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
906 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
907 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
908 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
909 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
910 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
911 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
912 * @param Periphs This parameter can be a combination of the following values:
913 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
914 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
915 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
916 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
917 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
918 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
919 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
920 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
921 *
922 * (*) value not defined in all devices.
923 * @retval State of Periphs (1 or 0).
924 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)925 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
926 {
927 return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);
928 }
929
930 /**
931 * @brief Disable APB2 peripherals clock.
932 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
933 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
934 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
935 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
936 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
937 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
938 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
939 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
940 * @param Periphs This parameter can be a combination of the following values:
941 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
942 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
943 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
944 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
945 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
946 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
947 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
948 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
949 *
950 * (*) value not defined in all devices.
951 * @retval None
952 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)953 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
954 {
955 CLEAR_BIT(RCC->APB2ENR, Periphs);
956 }
957
958 /**
959 * @brief Force APB2 peripherals reset.
960 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
961 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
962 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
963 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
964 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
965 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
966 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
967 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
968 * @param Periphs This parameter can be a combination of the following values:
969 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
970 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
971 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
972 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
974 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
975 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
976 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
977 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
978 *
979 * (*) value not defined in all devices.
980 * @retval None
981 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)982 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
983 {
984 SET_BIT(RCC->APB2RSTR, Periphs);
985 }
986
987 /**
988 * @brief Release APB2 peripherals reset.
989 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
990 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
991 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
992 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
993 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
994 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
995 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
996 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
997 * @param Periphs This parameter can be a combination of the following values:
998 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
999 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1000 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1001 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1002 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1003 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1004 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1005 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1006 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1007 *
1008 * (*) value not defined in all devices.
1009 * @retval None
1010 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1011 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1012 {
1013 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1014 }
1015
1016 /**
1017 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
1018 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
1019 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
1020 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
1021 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
1022 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
1023 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
1024 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
1025 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
1026 * @param Periphs This parameter can be a combination of the following values:
1027 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1028 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1029 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1030 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1031 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1032 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1033 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1034 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1035 *
1036 * (*) value not defined in all devices.
1037 * @retval None
1038 */
LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)1039 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
1040 {
1041 __IO uint32_t tmpreg;
1042 SET_BIT(RCC->APB2LPENR, Periphs);
1043 /* Delay after an RCC peripheral clock enabling */
1044 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1045 (void)tmpreg;
1046 }
1047
1048 /**
1049 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
1050 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
1051 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
1052 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
1053 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
1054 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
1055 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
1056 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
1057 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
1058 * @param Periphs This parameter can be a combination of the following values:
1059 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1060 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1061 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1062 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1063 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1064 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1065 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1066 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1067 *
1068 * (*) value not defined in all devices.
1069 * @retval None
1070 */
LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)1071 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
1072 {
1073 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1074 }
1075
1076 /**
1077 * @}
1078 */
1079
1080
1081 /**
1082 * @}
1083 */
1084
1085 /**
1086 * @}
1087 */
1088
1089 #endif /* defined(RCC) */
1090
1091 /**
1092 * @}
1093 */
1094
1095 #ifdef __cplusplus
1096 }
1097 #endif
1098
1099 #endif /* __STM32L1xx_LL_BUS_H */
1100
1101
