1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_nor.h 4 * @author MCD Application Team 5 * @brief Header file of NOR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L1xx_HAL_NOR_H 38 #define __STM32L1xx_HAL_NOR_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l1xx_ll_fsmc.h" 46 47 /** @addtogroup STM32L1xx_HAL_Driver 48 * @{ 49 */ 50 51 #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) 52 /** @addtogroup NOR 53 * @{ 54 */ 55 56 /** @addtogroup NOR_Private_Constants 57 * @{ 58 */ 59 60 /* NOR device IDs addresses */ 61 #define MC_ADDRESS ((uint16_t)0x0000) 62 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) 63 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) 64 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) 65 66 /* NOR CFI IDs addresses */ 67 #define CFI1_ADDRESS ((uint16_t)0x10) 68 #define CFI2_ADDRESS ((uint16_t)0x11) 69 #define CFI3_ADDRESS ((uint16_t)0x12) 70 #define CFI4_ADDRESS ((uint16_t)0x13) 71 72 /* NOR operation wait timeout */ 73 #define NOR_TMEOUT ((uint16_t)0xFFFF) 74 75 /* NOR memory data width */ 76 #define NOR_MEMORY_8B ((uint8_t)0x0) 77 #define NOR_MEMORY_16B ((uint8_t)0x1) 78 79 /* NOR memory device read/write start address */ 80 #define NOR_MEMORY_ADRESS1 FSMC_BANK1_1 81 #define NOR_MEMORY_ADRESS2 FSMC_BANK1_2 82 #define NOR_MEMORY_ADRESS3 FSMC_BANK1_3 83 #define NOR_MEMORY_ADRESS4 FSMC_BANK1_4 84 85 /** 86 * @} 87 */ 88 89 /** @addtogroup NOR_Private_Macros 90 * @{ 91 */ 92 93 /** 94 * @brief NOR memory address shifting. 95 * @param __NOR_ADDRESS: NOR base address 96 * @param __NOR_MEMORY_WIDTH_: NOR memory width 97 * @param __ADDRESS__: NOR memory address 98 * @retval NOR shifted address value 99 */ 100 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ 101 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ 102 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ 103 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) 104 105 /** 106 * @brief NOR memory write data to specified address. 107 * @param __ADDRESS__: NOR memory address 108 * @param __DATA__: Data to write 109 * @retval None 110 */ 111 #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)) 112 113 /** 114 * @} 115 */ 116 117 /* Exported typedef ----------------------------------------------------------*/ 118 /** @defgroup NOR_Exported_Types NOR Exported Types 119 * @{ 120 */ 121 122 /** 123 * @brief HAL SRAM State structures definition 124 */ 125 typedef enum 126 { 127 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ 128 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ 129 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ 130 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ 131 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ 132 }HAL_NOR_StateTypeDef; 133 134 /** 135 * @brief FSMC NOR Status typedef 136 */ 137 typedef enum 138 { 139 HAL_NOR_STATUS_SUCCESS = 0, 140 HAL_NOR_STATUS_ONGOING, 141 HAL_NOR_STATUS_ERROR, 142 HAL_NOR_STATUS_TIMEOUT 143 }HAL_NOR_StatusTypeDef; 144 145 /** 146 * @brief FSMC NOR ID typedef 147 */ 148 typedef struct 149 { 150 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ 151 152 uint16_t Device_Code1; 153 154 uint16_t Device_Code2; 155 156 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. 157 These codes can be accessed by performing read operations with specific 158 control signals and addresses set.They can also be accessed by issuing 159 an Auto Select command */ 160 }NOR_IDTypeDef; 161 162 /** 163 * @brief FSMC NOR CFI typedef 164 */ 165 typedef struct 166 { 167 /*!< Defines the information stored in the memory's Common flash interface 168 which contains a description of various electrical and timing parameters, 169 density information and functions supported by the memory */ 170 171 uint16_t CFI_1; 172 173 uint16_t CFI_2; 174 175 uint16_t CFI_3; 176 177 uint16_t CFI_4; 178 }NOR_CFITypeDef; 179 180 /** 181 * @brief NOR handle Structure definition 182 */ 183 typedef struct 184 { 185 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 186 187 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 188 189 FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ 190 191 HAL_LockTypeDef Lock; /*!< NOR locking object */ 192 193 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ 194 195 }NOR_HandleTypeDef; 196 197 /** 198 * @} 199 */ 200 201 /* Exported constants --------------------------------------------------------*/ 202 /* Exported macro ------------------------------------------------------------*/ 203 204 /** @defgroup NOR_Exported_macro NOR Exported Macros 205 * @{ 206 */ 207 208 /** @brief Reset NOR handle state 209 * @param __HANDLE__: NOR handle 210 * @retval None 211 */ 212 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) 213 214 /** 215 * @} 216 */ 217 218 /* Exported functions --------------------------------------------------------*/ 219 /** @addtogroup NOR_Exported_Functions NOR Exported Functions 220 * @{ 221 */ 222 223 /** @addtogroup NOR_Exported_Functions_Group1 224 * @{ 225 */ 226 227 /* Initialization/de-initialization functions **********************************/ 228 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming); 229 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); 230 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); 231 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); 232 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); 233 234 /** 235 * @} 236 */ 237 238 /** @addtogroup NOR_Exported_Functions_Group2 239 * @{ 240 */ 241 242 /* I/O operation functions ***************************************************/ 243 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); 244 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); 245 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); 246 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); 247 248 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); 249 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); 250 251 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); 252 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); 253 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); 254 255 /** 256 * @} 257 */ 258 259 /** @addtogroup NOR_Exported_Functions_Group3 260 * @{ 261 */ 262 263 /* NOR Control functions *****************************************************/ 264 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); 265 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); 266 267 /** 268 * @} 269 */ 270 271 /** @addtogroup NOR_Exported_Functions_Group4 272 * @{ 273 */ 274 275 /* NOR State functions ********************************************************/ 276 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); 277 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); 278 279 /** 280 * @} 281 */ 282 283 /** 284 * @} 285 */ 286 287 288 /** 289 * @} 290 */ 291 292 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ 293 294 /** 295 * @} 296 */ 297 298 #ifdef __cplusplus 299 } 300 #endif 301 302 #endif /* __STM32L1xx_HAL_NOR_H */ 303 304 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 305
