1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L1xx_HAL_ADC_EX_H 38 #define __STM32L1xx_HAL_ADC_EX_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l1xx_hal_def.h" 46 47 /** @addtogroup STM32L1xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup ADCEx 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup ADCEx_Exported_Types ADCEx Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief ADC Configuration injected Channel structure definition 62 * @note Parameters of this structure are shared within 2 scopes: 63 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset 64 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 65 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. 66 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 67 * ADC state can be either: 68 * - For all parameters: ADC disabled 69 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. 70 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. 71 */ 72 typedef struct 73 { 74 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure 75 This parameter can be a value of @ref ADC_channels 76 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 77 uint32_t InjectedRank; /*!< Rank in the injected group sequencer 78 This parameter must be a value of @ref ADCEx_injected_rank 79 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 80 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 81 Unit: ADC clock cycles 82 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 83 This parameter can be a value of @ref ADC_sampling_times 84 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 85 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 86 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 87 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 88 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 89 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). 90 Offset value must be a positive number. 91 Depending of ADC resolution selected (12, 10, 8 or 6 bits), 92 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 93 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 94 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 95 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 96 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 97 configure a channel on injected group can impact the configuration of other channels previously set. */ 98 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 99 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 100 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 101 This parameter can be set to ENABLE or DISABLE. 102 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. 103 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 104 configure a channel on injected group can impact the configuration of other channels previously set. */ 105 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 106 This parameter can be set to ENABLE or DISABLE. 107 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 108 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) 109 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 110 To maintain JAUTO always enabled, DMA must be configured in circular mode. 111 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 112 configure a channel on injected group can impact the configuration of other channels previously set. */ 113 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 114 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. 115 If set to external trigger source, triggering is on event rising edge. 116 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected 117 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 118 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) 119 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 120 configure a channel on injected group can impact the configuration of other channels previously set. */ 121 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 122 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. 123 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 124 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 125 configure a channel on injected group can impact the configuration of other channels previously set. */ 126 }ADC_InjectionConfTypeDef; 127 /** 128 * @} 129 */ 130 131 132 /* Exported constants --------------------------------------------------------*/ 133 134 /** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants 135 * @{ 136 */ 137 138 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group 139 * @{ 140 */ 141 #define ADC_INJECTED_RANK_1 (0x00000001U) 142 #define ADC_INJECTED_RANK_2 (0x00000002U) 143 #define ADC_INJECTED_RANK_3 (0x00000003U) 144 #define ADC_INJECTED_RANK_4 (0x00000004U) 145 /** 146 * @} 147 */ 148 149 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group 150 * @{ 151 */ 152 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) 153 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) 154 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) 155 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) 156 /** 157 * @} 158 */ 159 160 /** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected 161 * @{ 162 */ 163 /* External triggers for injected groups of ADC1 */ 164 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1 165 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO 166 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4 167 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO 168 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ADC_EXTERNALTRIGINJEC_T4_CC1 169 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ADC_EXTERNALTRIGINJEC_T4_CC2 170 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC_EXTERNALTRIGINJEC_T4_CC3 171 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC_EXTERNALTRIGINJEC_T7_TRGO 172 #define ADC_EXTERNALTRIGINJECCONV_T9_CC1 ADC_EXTERNALTRIGINJEC_T9_CC1 173 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO 174 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1 175 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15 176 #define ADC_INJECTED_SOFTWARE_START (0x00000010U) 177 /** 178 * @} 179 */ 180 181 /** 182 * @} 183 */ 184 185 186 /* Private constants ---------------------------------------------------------*/ 187 188 /** @addtogroup ADCEx_Private_Constants ADCEx Private Constants 189 * @{ 190 */ 191 192 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected 193 * @{ 194 */ 195 196 /* List of external triggers of injected group for ADC1: */ 197 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 198 #define ADC_EXTERNALTRIGINJEC_T9_CC1 (0x00000000U) 199 #define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0)) 200 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 )) 201 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 202 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_2 )) 203 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) 204 #define ADC_EXTERNALTRIGINJEC_T4_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) 205 #define ADC_EXTERNALTRIGINJEC_T4_CC2 ((uint32_t)( ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 206 #define ADC_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 )) 207 #define ADC_EXTERNALTRIGINJEC_T10_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) 208 #define ADC_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 )) 209 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) 210 /** 211 * @} 212 */ 213 214 /** 215 * @} 216 */ 217 218 219 /* Exported macro ------------------------------------------------------------*/ 220 221 /** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros 222 * @{ 223 */ 224 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 225 /* final user. */ 226 227 /** 228 * @brief Selection of channels bank. 229 * Note: Banks availability depends on devices categories. 230 * This macro is intended to change bank selection quickly on the fly, 231 * without going through ADC init structure update and execution of function 232 * 'HAL_ADC_Init()'. 233 * @param __HANDLE__: ADC handle 234 * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank. 235 * @retval None 236 */ 237 #define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__) \ 238 MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__)) 239 240 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 241 /** 242 * @brief Configures the ADC channels speed. 243 * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5. 244 * - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is 245 * in power down mode. 246 * - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is 247 * in power down mode. 248 * - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in 249 * power down mode. Otherwise, channel 13 is connected to OPAMP3 output and 250 * routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. 251 * (Note: OPAMP3 is available on STM32L1 Cat.4 only). 252 * @param __CHANNEL__: ADC channel 253 * This parameter can be one of the following values: 254 * @arg ADC_CHANNEL_3: Channel 3 is selected. 255 * @arg ADC_CHANNEL_8: Channel 8 is selected. 256 * @arg ADC_CHANNEL_13: Channel 13 is selected. 257 * @retval None 258 */ 259 #define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__) \ 260 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 261 )? \ 262 (SET_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 263 : \ 264 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 265 )? \ 266 (SET_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 267 : \ 268 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 269 )? \ 270 (SET_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 271 : \ 272 (SET_BIT(COMP->CSR, 0x00000000)) \ 273 ) \ 274 ) \ 275 ) 276 277 #define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__) \ 278 ( ( ((__CHANNEL__) == ADC_CHANNEL_3) \ 279 )? \ 280 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3)) \ 281 : \ 282 ( ( ((__CHANNEL__) == ADC_CHANNEL_8) \ 283 )? \ 284 (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8)) \ 285 : \ 286 ( ( ((__CHANNEL__) == ADC_CHANNEL_13) \ 287 )? \ 288 (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13)) \ 289 : \ 290 (SET_BIT(COMP->CSR, 0x00000000)) \ 291 ) \ 292 ) \ 293 ) 294 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 295 296 /** 297 * @} 298 */ 299 300 /* Private macro ------------------------------------------------------------*/ 301 302 /** @defgroup ADCEx_Private_Macro ADCEx Private Macro 303 * @{ 304 */ 305 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 306 /* code of final user. */ 307 308 /** 309 * @brief Set ADC ranks available in register SQR1. 310 * Register SQR1 bits availability depends on device category. 311 * @param _NbrOfConversion_: Regular channel sequence length 312 * @retval None 313 */ 314 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 315 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 316 #else 317 #define __ADC_SQR1_SQXX (ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) 318 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 319 320 /** 321 * @brief Set the ADC's sample time for channel numbers between 30 and 31. 322 * Register SMPR0 availability depends on device category. If register is not 323 * available on the current device, this macro does nothing. 324 * @retval None 325 * @param _SAMPLETIME_: Sample time parameter. 326 * @param _CHANNELNB_: Channel number. 327 * @retval None 328 */ 329 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 330 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 331 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30))) 332 #else 333 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \ 334 (0x00000000U) 335 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 336 337 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 338 /** 339 * @brief Set the ADC's sample time for channel numbers between 20 and 29. 340 * @param _SAMPLETIME_: Sample time parameter. 341 * @param _CHANNELNB_: Channel number. 342 * @retval None 343 */ 344 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 345 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 346 #else 347 /** 348 * @brief Set the ADC's sample time for channel numbers between 20 and 26. 349 * @param _SAMPLETIME_: Sample time parameter. 350 * @param _CHANNELNB_: Channel number. 351 * @retval None 352 */ 353 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ 354 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20))) 355 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 356 357 /** 358 * @brief Defines the highest channel available in register SMPR1. Channels 359 * availability depends on device category: 360 * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3 361 * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5 362 * @param None 363 * @retval None 364 */ 365 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 366 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_29 367 #else 368 #define ADC_SMPR1_CHANNEL_MAX ADC_CHANNEL_26 369 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 370 371 372 /** 373 * @brief Define mask of configuration bits of ADC and regular group in 374 * register CR2 (bits of ADC enable, conversion start and injected group are 375 * excluded of this mask). 376 * @retval None 377 */ 378 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 379 #define ADC_CR2_MASK_ADCINIT() \ 380 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT) 381 #else 382 #define ADC_CR2_MASK_ADCINIT() \ 383 (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT) 384 #endif 385 386 387 /** 388 * @brief Get the maximum ADC conversion cycles on all channels. 389 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles) 390 * Approximation of sampling time within 2 ranges, returns the highest value: 391 * below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles} 392 * between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles} 393 * Unit: ADC clock cycles 394 * @param __HANDLE__: ADC handle 395 * @retval ADC conversion cycles on all channels 396 */ 397 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 398 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 399 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 400 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 401 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) && \ 402 (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ? \ 403 \ 404 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 405 ) 406 #else 407 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \ 408 (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET) && \ 409 (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \ 410 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \ 411 \ 412 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES \ 413 ) 414 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 415 416 /** 417 * @brief Get the ADC clock prescaler from ADC common control register 418 * and convert it to its decimal number setting (refer to reference manual) 419 * @retval None 420 */ 421 #define ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__) \ 422 ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE))) 423 424 /** 425 * @brief Clear register SMPR0. 426 * Register SMPR0 availability depends on device category. If register is not 427 * available on the current device, this macro performs no action. 428 * @param __HANDLE__: ADC handle 429 * @retval None 430 */ 431 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 432 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 433 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | \ 434 ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 435 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 436 ADC_SMPR1_SMP20 )) 437 438 #define ADC_SMPR0_CLEAR(__HANDLE__) \ 439 (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30))) 440 #else 441 #define ADC_SMPR1_CLEAR(__HANDLE__) \ 442 CLEAR_BIT((__HANDLE__)->Instance->SMPR1, (ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | \ 443 ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 | \ 444 ADC_SMPR1_SMP20 )) 445 446 #define ADC_SMPR0_CLEAR(__HANDLE__) __NOP() 447 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 448 449 /** 450 * @brief Clear register CR2. 451 * @param __HANDLE__: ADC handle 452 * @retval None 453 */ 454 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 455 #define ADC_CR2_CLEAR(__HANDLE__) \ 456 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 457 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 458 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 459 ADC_CR2_DMA | ADC_CR2_DELS | ADC_CR2_CFG | \ 460 ADC_CR2_CONT | ADC_CR2_ADON )) \ 461 ) 462 #else 463 #define ADC_CR2_CLEAR(__HANDLE__) \ 464 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | \ 465 ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | \ 466 ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | \ 467 ADC_CR2_DMA | ADC_CR2_DELS | \ 468 ADC_CR2_CONT | ADC_CR2_ADON )) \ 469 ) 470 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 471 472 /** 473 * @brief Set the sampling time of selected channel on register SMPR0 474 * Register SMPR0 availability depends on device category. If register is not 475 * available on the current device, this macro performs no action. 476 * @param __HANDLE__: ADC handle 477 * @param _SAMPLETIME_: Sample time parameter. 478 * @param __CHANNEL__: Channel number. 479 * @retval None 480 */ 481 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 482 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) \ 483 MODIFY_REG((__HANDLE__)->Instance->SMPR0, \ 484 ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)), \ 485 ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__)) ) 486 #else 487 #define ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP() 488 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 489 490 491 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ 492 ((CHANNEL) == ADC_INJECTED_RANK_2) || \ 493 ((CHANNEL) == ADC_INJECTED_RANK_3) || \ 494 ((CHANNEL) == ADC_INJECTED_RANK_4) ) 495 496 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 497 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 498 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 499 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 500 501 #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ 502 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ 503 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ 504 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ 505 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ 506 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ 507 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ 508 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \ 509 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1) || \ 510 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO) || \ 511 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1) || \ 512 ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ 513 ((REGTRIG) == ADC_SOFTWARE_START) ) 514 515 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification 516 * @{ 517 */ 518 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U))) 519 /** 520 * @} 521 */ 522 523 /** 524 * @} 525 */ 526 527 528 /* Exported functions --------------------------------------------------------*/ 529 /** @addtogroup ADCEx_Exported_Functions 530 * @{ 531 */ 532 533 /* IO operation functions *****************************************************/ 534 /** @addtogroup ADCEx_Exported_Functions_Group1 535 * @{ 536 */ 537 538 /* Blocking mode: Polling */ 539 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 540 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 541 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 542 543 /* Non-blocking mode: Interruption */ 544 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 545 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 546 547 /* ADC retrieve conversion value intended to be used with polling or interruption */ 548 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 549 550 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 551 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 552 /** 553 * @} 554 */ 555 556 557 /* Peripheral Control functions ***********************************************/ 558 /** @addtogroup ADCEx_Exported_Functions_Group2 559 * @{ 560 */ 561 562 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 563 /** 564 * @} 565 */ 566 567 568 /** 569 * @} 570 */ 571 572 573 /** 574 * @} 575 */ 576 577 /** 578 * @} 579 */ 580 581 #ifdef __cplusplus 582 } 583 #endif 584 585 #endif /* __STM32L1xx_HAL_ADC_EX_H */ 586 587 588 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 589
