1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32L1xx_HAL_ADC_H 38 #define __STM32L1xx_HAL_ADC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l1xx_hal_def.h" 46 47 /** @addtogroup STM32L1xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup ADC 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup ADC_Exported_Types ADC Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief Structure definition of ADC and regular group initialization 62 * @note Parameters of this structure are shared within 2 scopes: 63 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 64 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 65 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 66 * ADC state can be either: 67 * - For all parameters: ADC disabled 68 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 69 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 70 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 71 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). 72 */ 73 typedef struct 74 { 75 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. 76 This parameter can be a value of @ref ADC_ClockPrescaler 77 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 78 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 79 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ 80 uint32_t Resolution; /*!< Configures the ADC resolution. 81 This parameter can be a value of @ref ADC_Resolution */ 82 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 83 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 84 This parameter can be a value of @ref ADC_Data_align */ 85 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 86 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 87 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 88 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 89 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 90 Scan direction is upward: from rank1 to rank 'n'. 91 This parameter can be a value of @ref ADC_Scan_mode */ 92 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 93 This parameter can be a value of @ref ADC_EOCSelection. 94 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 95 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 96 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 97 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 98 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 99 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 100 conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 101 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 102 This parameter can be a value of @ref ADC_LowPowerAutoWait. 103 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. 104 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed 105 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). 106 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ 107 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 108 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 109 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */ 110 uint32_t ChannelsBank; /*!< Selects the ADC channels bank. 111 This parameter can be a value of @ref ADC_ChannelsBank. 112 Note: Banks availability depends on devices categories. 113 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */ 114 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 115 after the selected trigger occurred (software start or external trigger). 116 This parameter can be set to ENABLE or DISABLE. */ 117 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 118 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 119 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 120 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ 121 #else 122 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 123 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 124 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ 125 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 126 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 127 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 128 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 129 This parameter can be set to ENABLE or DISABLE. */ 130 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 131 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 132 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 133 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 134 If set to ADC_SOFTWARE_START, external triggers are disabled. 135 If set to external trigger source, triggering is on event rising edge by default. 136 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 137 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 138 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 139 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 140 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 141 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 142 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 143 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 144 This parameter can be set to ENABLE or DISABLE. */ 145 }ADC_InitTypeDef; 146 147 /** 148 * @brief Structure definition of ADC channel for regular group 149 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 150 * ADC can be either disabled or enabled without conversion on going on regular group. 151 */ 152 typedef struct 153 { 154 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 155 This parameter can be a value of @ref ADC_channels 156 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. 157 Maximum number of channels by device category (without taking in account each device package constraints): 158 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26. 159 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 160 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 161 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. 162 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ 163 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 164 This parameter can be a value of @ref ADC_regular_rank 165 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 166 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 167 Unit: ADC clock cycles 168 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 169 This parameter can be a value of @ref ADC_sampling_times 170 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 171 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 172 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 173 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 174 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 175 }ADC_ChannelConfTypeDef; 176 177 /** 178 * @brief ADC Configuration analog watchdog definition 179 * @note The setting of these parameters with function is conditioned to ADC state. 180 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 181 */ 182 typedef struct 183 { 184 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 185 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 186 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 187 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 188 This parameter can be a value of @ref ADC_channels. */ 189 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 190 This parameter can be set to ENABLE or DISABLE */ 191 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 192 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 193 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 194 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 195 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 196 }ADC_AnalogWDGConfTypeDef; 197 198 /** 199 * @brief HAL ADC state machine: ADC states definition (bitfields) 200 */ 201 /* States of ADC global scope */ 202 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 203 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 204 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ 205 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 206 207 /* States of ADC errors */ 208 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 209 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 210 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 211 212 /* States of ADC group regular */ 213 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 214 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 215 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 216 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 217 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32L1 device: End Of Sampling flag raised */ 218 219 /* States of ADC group injected */ 220 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 221 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 222 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ 223 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */ 224 225 /* States of ADC analog watchdogs */ 226 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ 227 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */ 228 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */ 229 230 /* States of ADC multi-mode */ 231 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */ 232 233 234 /** 235 * @brief ADC handle Structure definition 236 */ 237 typedef struct 238 { 239 ADC_TypeDef *Instance; /*!< Register base address */ 240 241 ADC_InitTypeDef Init; /*!< ADC required parameters */ 242 243 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ 244 245 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 246 247 HAL_LockTypeDef Lock; /*!< ADC locking object */ 248 249 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 250 251 __IO uint32_t ErrorCode; /*!< ADC Error code */ 252 }ADC_HandleTypeDef; 253 /** 254 * @} 255 */ 256 257 258 259 /* Exported constants --------------------------------------------------------*/ 260 261 /** @defgroup ADC_Exported_Constants ADC Exported Constants 262 * @{ 263 */ 264 265 /** @defgroup ADC_Error_Code ADC Error Code 266 * @{ 267 */ 268 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 269 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, 270 enable/disable, erroneous state */ 271 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 272 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler 278 * @{ 279 */ 280 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ 281 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ 282 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ 283 /** 284 * @} 285 */ 286 287 /** @defgroup ADC_Resolution ADC Resolution 288 * @{ 289 */ 290 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 291 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ 292 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ 293 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ 294 /** 295 * @} 296 */ 297 298 /** @defgroup ADC_Data_align ADC Data_align 299 * @{ 300 */ 301 #define ADC_DATAALIGN_RIGHT (0x00000000U) 302 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 303 /** 304 * @} 305 */ 306 307 /** @defgroup ADC_Scan_mode ADC Scan mode 308 * @{ 309 */ 310 #define ADC_SCAN_DISABLE (0x00000000U) 311 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 312 /** 313 * @} 314 */ 315 316 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group 317 * @{ 318 */ 319 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 320 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 321 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 322 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 323 /** 324 * @} 325 */ 326 327 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular 328 * @{ 329 */ 330 /* List of external triggers with generic trigger name, sorted by trigger */ 331 /* name: */ 332 333 /* External triggers of regular group for ADC1 */ 334 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3 335 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 336 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO 337 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1 338 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3 339 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO 340 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 341 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO 342 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO 343 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 344 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO 345 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 346 #define ADC_SOFTWARE_START (0x00000010U) 347 /** 348 * @} 349 */ 350 351 /** @defgroup ADC_EOCSelection ADC EOCSelection 352 * @{ 353 */ 354 #define ADC_EOC_SEQ_CONV (0x00000000U) 355 #define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) 356 /** 357 * @} 358 */ 359 360 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait 361 * @{ 362 */ 363 /*!< Note : For compatibility with other STM32 devices with ADC autowait */ 364 /* feature limited to enable or disable settings: */ 365 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */ 366 367 #define ADC_AUTOWAIT_DISABLE (0x00000000U) 368 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */ 369 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */ 370 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */ 371 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */ 372 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */ 373 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ 374 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ 375 376 /** 377 * @} 378 */ 379 380 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff 381 * @{ 382 */ 383 #define ADC_AUTOPOWEROFF_DISABLE (0x00000000U) 384 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ 385 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ 386 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ 387 /** 388 * @} 389 */ 390 391 392 /** @defgroup ADC_ChannelsBank ADC ChannelsBank 393 * @{ 394 */ 395 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 396 #define ADC_CHANNELS_BANK_A (0x00000000U) 397 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) 398 399 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 400 ((BANK) == ADC_CHANNELS_BANK_B) ) 401 #else 402 #define ADC_CHANNELS_BANK_A (0x00000000U) 403 404 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 405 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 406 /** 407 * @} 408 */ 409 410 /** @defgroup ADC_channels ADC channels 411 * @{ 412 */ 413 /* Note: Depending on devices, some channels may not be available on package */ 414 /* pins. Refer to device datasheet for channels availability. */ 415 #define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */ 416 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 417 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 418 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 419 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */ 420 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 421 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 422 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 423 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */ 424 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 425 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 426 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 427 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */ 428 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 429 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 430 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 431 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */ 432 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 433 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 434 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 435 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 436 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 437 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */ 438 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 439 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ 440 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 441 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 442 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 443 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 444 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 445 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 446 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 447 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 448 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 449 450 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 451 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 452 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 453 454 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 455 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ 456 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ 457 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) 458 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ 459 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ 460 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup ADC_sampling_times ADC sampling times 466 * @{ 467 */ 468 #define ADC_SAMPLETIME_4CYCLES (0x00000000U) /*!< Sampling time 4 ADC clock cycles */ 469 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ 470 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ 471 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */ 472 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ 473 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ 474 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ 475 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ 476 /** 477 * @} 478 */ 479 480 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels 481 * @{ 482 */ 483 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \ 484 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \ 485 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \ 486 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2) 487 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 488 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \ 489 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \ 490 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2) 491 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 492 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 493 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ 494 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 495 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 496 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 497 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 498 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ 499 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ 500 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 501 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ 502 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) 503 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 504 505 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ 506 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ 507 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \ 508 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1) 509 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 510 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \ 511 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \ 512 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1) 513 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 514 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 515 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ 516 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 517 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 518 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 519 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 520 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ 521 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ 522 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 523 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ 524 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) 525 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 526 527 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ 528 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ 529 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \ 530 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0) 531 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 532 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \ 533 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \ 534 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0) 535 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 536 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 537 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ 538 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 539 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 540 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 541 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 542 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ 543 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ 544 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 545 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ 546 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) 547 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 548 /** 549 * @} 550 */ 551 552 /** @defgroup ADC_regular_rank ADC rank into regular group 553 * @{ 554 */ 555 #define ADC_REGULAR_RANK_1 (0x00000001U) 556 #define ADC_REGULAR_RANK_2 (0x00000002U) 557 #define ADC_REGULAR_RANK_3 (0x00000003U) 558 #define ADC_REGULAR_RANK_4 (0x00000004U) 559 #define ADC_REGULAR_RANK_5 (0x00000005U) 560 #define ADC_REGULAR_RANK_6 (0x00000006U) 561 #define ADC_REGULAR_RANK_7 (0x00000007U) 562 #define ADC_REGULAR_RANK_8 (0x00000008U) 563 #define ADC_REGULAR_RANK_9 (0x00000009U) 564 #define ADC_REGULAR_RANK_10 (0x0000000AU) 565 #define ADC_REGULAR_RANK_11 (0x0000000BU) 566 #define ADC_REGULAR_RANK_12 (0x0000000CU) 567 #define ADC_REGULAR_RANK_13 (0x0000000DU) 568 #define ADC_REGULAR_RANK_14 (0x0000000EU) 569 #define ADC_REGULAR_RANK_15 (0x0000000FU) 570 #define ADC_REGULAR_RANK_16 (0x00000010U) 571 #define ADC_REGULAR_RANK_17 (0x00000011U) 572 #define ADC_REGULAR_RANK_18 (0x00000012U) 573 #define ADC_REGULAR_RANK_19 (0x00000013U) 574 #define ADC_REGULAR_RANK_20 (0x00000014U) 575 #define ADC_REGULAR_RANK_21 (0x00000015U) 576 #define ADC_REGULAR_RANK_22 (0x00000016U) 577 #define ADC_REGULAR_RANK_23 (0x00000017U) 578 #define ADC_REGULAR_RANK_24 (0x00000018U) 579 #define ADC_REGULAR_RANK_25 (0x00000019U) 580 #define ADC_REGULAR_RANK_26 (0x0000001AU) 581 #define ADC_REGULAR_RANK_27 (0x0000001BU) 582 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 583 #define ADC_REGULAR_RANK_28 (0x0000001CU) 584 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 590 * @{ 591 */ 592 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) 593 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 594 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 595 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 596 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) 597 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) 598 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 599 /** 600 * @} 601 */ 602 603 /** @defgroup ADC_conversion_group ADC conversion group 604 * @{ 605 */ 606 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 607 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 608 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 609 /** 610 * @} 611 */ 612 613 /** @defgroup ADC_Event_type ADC Event type 614 * @{ 615 */ 616 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 617 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 618 /** 619 * @} 620 */ 621 622 /** @defgroup ADC_interrupts_definition ADC interrupts definition 623 * @{ 624 */ 625 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 626 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 627 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 628 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */ 629 /** 630 * @} 631 */ 632 633 /** @defgroup ADC_flags_definition ADC flags definition 634 * @{ 635 */ 636 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 637 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 638 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 639 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 640 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 641 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ 642 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ 643 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ 644 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */ 645 /** 646 * @} 647 */ 648 649 /** 650 * @} 651 */ 652 653 654 /* Private constants ---------------------------------------------------------*/ 655 656 /** @addtogroup ADC_Private_Constants ADC Private Constants 657 * @{ 658 */ 659 660 /* List of external triggers of regular group for ADC1: */ 661 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 662 663 /* External triggers of regular group for ADC1 */ 664 #define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U) 665 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) 666 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) 667 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 668 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) 669 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 670 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) 671 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 672 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) 673 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 674 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) 675 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 676 677 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 678 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ 679 ADC_FLAG_OVR) 680 681 /** 682 * @} 683 */ 684 685 686 /* Exported macro ------------------------------------------------------------*/ 687 688 /** @defgroup ADC_Exported_Macros ADC Exported Macros 689 * @{ 690 */ 691 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 692 /* final user. */ 693 694 /** 695 * @brief Enable the ADC peripheral 696 * @param __HANDLE__: ADC handle 697 * @retval None 698 */ 699 #define __HAL_ADC_ENABLE(__HANDLE__) \ 700 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON 701 702 /** 703 * @brief Disable the ADC peripheral 704 * @param __HANDLE__: ADC handle 705 * @retval None 706 */ 707 #define __HAL_ADC_DISABLE(__HANDLE__) \ 708 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON 709 710 /** 711 * @brief Enable the ADC end of conversion interrupt. 712 * @param __HANDLE__: ADC handle 713 * @param __INTERRUPT__: ADC Interrupt 714 * This parameter can be any combination of the following values: 715 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 716 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 717 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 718 * @arg ADC_IT_OVR: ADC overrun interrupt source 719 * @retval None 720 */ 721 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 722 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 723 724 /** 725 * @brief Disable the ADC end of conversion interrupt. 726 * @param __HANDLE__: ADC handle 727 * @param __INTERRUPT__: ADC Interrupt 728 * This parameter can be any combination of the following values: 729 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 730 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 731 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 732 * @arg ADC_IT_OVR: ADC overrun interrupt source 733 * @retval None 734 */ 735 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 736 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 737 738 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 739 * @param __HANDLE__: ADC handle 740 * @param __INTERRUPT__: ADC interrupt source to check 741 * This parameter can be any combination of the following values: 742 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 743 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 744 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 745 * @arg ADC_IT_OVR: ADC overrun interrupt source 746 * @retval State of interruption (SET or RESET) 747 */ 748 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 749 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 750 751 /** 752 * @brief Get the selected ADC's flag status. 753 * @param __HANDLE__: ADC handle 754 * @param __FLAG__: ADC flag 755 * This parameter can be any combination of the following values: 756 * @arg ADC_FLAG_STRT: ADC Regular group start flag 757 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 758 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 759 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 760 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 761 * @arg ADC_FLAG_OVR: ADC overrun flag 762 * @arg ADC_FLAG_ADONS: ADC ready status flag 763 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 764 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 765 * @retval None 766 */ 767 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 768 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 769 770 /** 771 * @brief Clear the ADC's pending flags 772 * @param __HANDLE__: ADC handle 773 * @param __FLAG__: ADC flag 774 * @arg ADC_FLAG_STRT: ADC Regular group start flag 775 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 776 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 777 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 778 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 779 * @arg ADC_FLAG_OVR: ADC overrun flag 780 * @arg ADC_FLAG_ADONS: ADC ready status flag 781 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 782 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 783 * @retval None 784 */ 785 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 786 (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 787 788 /** @brief Reset ADC handle state 789 * @param __HANDLE__: ADC handle 790 * @retval None 791 */ 792 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 793 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 794 795 /** 796 * @} 797 */ 798 799 /* Private macro ------------------------------------------------------------*/ 800 801 /** @defgroup ADC_Private_Macros ADC Private Macros 802 * @{ 803 */ 804 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 805 /* code of final user. */ 806 807 /** 808 * @brief Verification of ADC state: enabled or disabled 809 * @param __HANDLE__: ADC handle 810 * @retval SET (ADC enabled) or RESET (ADC disabled) 811 */ 812 #define ADC_IS_ENABLE(__HANDLE__) \ 813 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 814 ) ? SET : RESET) 815 816 /** 817 * @brief Test if conversion trigger of regular group is software start 818 * or external trigger. 819 * @param __HANDLE__: ADC handle 820 * @retval SET (software start) or RESET (external trigger) 821 */ 822 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 823 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 824 825 /** 826 * @brief Test if conversion trigger of injected group is software start 827 * or external trigger. 828 * @param __HANDLE__: ADC handle 829 * @retval SET (software start) or RESET (external trigger) 830 */ 831 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 832 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 833 834 /** 835 * @brief Simultaneously clears and sets specific bits of the handle State 836 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 837 * the first parameter is the ADC handle State, the second parameter is the 838 * bit field to clear, the third and last parameter is the bit field to set. 839 * @retval None 840 */ 841 #define ADC_STATE_CLR_SET MODIFY_REG 842 843 /** 844 * @brief Clear ADC error code (set it to error code: "no error") 845 * @param __HANDLE__: ADC handle 846 * @retval None 847 */ 848 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 849 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 850 851 /** 852 * @brief Set ADC number of ranks into regular channel sequence length. 853 * @param _NbrOfConversion_: Regular channel sequence length 854 * @retval None 855 */ 856 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 857 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) 858 859 /** 860 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 861 * @param _SAMPLETIME_: Sample time parameter. 862 * @param _CHANNELNB_: Channel number. 863 * @retval None 864 */ 865 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 866 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) 867 868 /** 869 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 870 * @param _SAMPLETIME_: Sample time parameter. 871 * @param _CHANNELNB_: Channel number. 872 * @retval None 873 */ 874 #define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \ 875 ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) 876 877 /** 878 * @brief Set the selected regular channel rank for rank between 1 and 6. 879 * @param _CHANNELNB_: Channel number. 880 * @param _RANKNB_: Rank number. 881 * @retval None 882 */ 883 #define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \ 884 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) 885 886 /** 887 * @brief Set the selected regular channel rank for rank between 7 and 12. 888 * @param _CHANNELNB_: Channel number. 889 * @param _RANKNB_: Rank number. 890 * @retval None 891 */ 892 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \ 893 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) 894 895 /** 896 * @brief Set the selected regular channel rank for rank between 13 and 18. 897 * @param _CHANNELNB_: Channel number. 898 * @param _RANKNB_: Rank number. 899 * @retval None 900 */ 901 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 902 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) 903 904 /** 905 * @brief Set the selected regular channel rank for rank between 19 and 24. 906 * @param _CHANNELNB_: Channel number. 907 * @param _RANKNB_: Rank number. 908 * @retval None 909 */ 910 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 911 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) 912 913 /** 914 * @brief Set the selected regular channel rank for rank between 25 and 28. 915 * @param _CHANNELNB_: Channel number. 916 * @param _RANKNB_: Rank number. 917 * @retval None 918 */ 919 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 920 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) 921 922 /** 923 * @brief Set the injected sequence length. 924 * @param _JSQR_JL_: Sequence length. 925 * @retval None 926 */ 927 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) 928 929 /** 930 * @brief Set the selected injected channel rank 931 * Note: on STM32L1 devices, channel rank position in JSQR register 932 * is depending on total number of ranks selected into 933 * injected sequencer (ranks sequence starting from 4-JL) 934 * @param _CHANNELNB_: Channel number. 935 * @param _RANKNB_: Rank number. 936 * @param _JSQR_JL_: Sequence length. 937 * @retval None 938 */ 939 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 940 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) 941 942 /** 943 * @brief Enable the ADC DMA continuous request. 944 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 945 * @retval None 946 */ 947 #define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \ 948 ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) 949 950 /** 951 * @brief Enable ADC continuous conversion mode. 952 * @param _CONTINUOUS_MODE_: Continuous mode. 953 * @retval None 954 */ 955 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 956 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) 957 958 /** 959 * @brief Configures the number of discontinuous conversions for the regular group channels. 960 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 961 * @retval None 962 */ 963 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 964 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) 965 966 /** 967 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 968 * @param _SCAN_MODE_: Scan conversion mode. 969 * @retval None 970 */ 971 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 972 /* is equivalent to ADC_SCAN_ENABLE. */ 973 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 974 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 975 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 976 ) 977 978 979 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 980 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ 981 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) 982 983 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 984 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 985 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 986 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 987 988 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 989 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 990 991 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 992 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 993 994 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 995 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 996 997 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 998 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 999 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1000 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1001 1002 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 1003 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 1004 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 1005 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 1006 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ 1007 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 1008 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 1009 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 1010 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 1011 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ 1012 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ 1013 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 1014 ((REGTRIG) == ADC_SOFTWARE_START) ) 1015 1016 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 1017 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 1018 1019 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ 1020 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ 1021 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ 1022 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ 1023 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ 1024 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ 1025 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ 1026 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) 1027 1028 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ 1029 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ 1030 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ 1031 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) 1032 1033 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1034 1035 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 1036 ((BANK) == ADC_CHANNELS_BANK_B) ) 1037 #else 1038 1039 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 1040 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1041 1042 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 1043 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1044 ((CHANNEL) == ADC_CHANNEL_1) || \ 1045 ((CHANNEL) == ADC_CHANNEL_2) || \ 1046 ((CHANNEL) == ADC_CHANNEL_3) || \ 1047 ((CHANNEL) == ADC_CHANNEL_4) || \ 1048 ((CHANNEL) == ADC_CHANNEL_5) || \ 1049 ((CHANNEL) == ADC_CHANNEL_6) || \ 1050 ((CHANNEL) == ADC_CHANNEL_7) || \ 1051 ((CHANNEL) == ADC_CHANNEL_8) || \ 1052 ((CHANNEL) == ADC_CHANNEL_9) || \ 1053 ((CHANNEL) == ADC_CHANNEL_10) || \ 1054 ((CHANNEL) == ADC_CHANNEL_11) || \ 1055 ((CHANNEL) == ADC_CHANNEL_12) || \ 1056 ((CHANNEL) == ADC_CHANNEL_13) || \ 1057 ((CHANNEL) == ADC_CHANNEL_14) || \ 1058 ((CHANNEL) == ADC_CHANNEL_15) || \ 1059 ((CHANNEL) == ADC_CHANNEL_16) || \ 1060 ((CHANNEL) == ADC_CHANNEL_17) || \ 1061 ((CHANNEL) == ADC_CHANNEL_18) || \ 1062 ((CHANNEL) == ADC_CHANNEL_19) || \ 1063 ((CHANNEL) == ADC_CHANNEL_20) || \ 1064 ((CHANNEL) == ADC_CHANNEL_21) || \ 1065 ((CHANNEL) == ADC_CHANNEL_22) || \ 1066 ((CHANNEL) == ADC_CHANNEL_23) || \ 1067 ((CHANNEL) == ADC_CHANNEL_24) || \ 1068 ((CHANNEL) == ADC_CHANNEL_25) || \ 1069 ((CHANNEL) == ADC_CHANNEL_26) ) 1070 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 1071 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1072 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1073 ((CHANNEL) == ADC_CHANNEL_1) || \ 1074 ((CHANNEL) == ADC_CHANNEL_2) || \ 1075 ((CHANNEL) == ADC_CHANNEL_3) || \ 1076 ((CHANNEL) == ADC_CHANNEL_4) || \ 1077 ((CHANNEL) == ADC_CHANNEL_5) || \ 1078 ((CHANNEL) == ADC_CHANNEL_6) || \ 1079 ((CHANNEL) == ADC_CHANNEL_7) || \ 1080 ((CHANNEL) == ADC_CHANNEL_8) || \ 1081 ((CHANNEL) == ADC_CHANNEL_9) || \ 1082 ((CHANNEL) == ADC_CHANNEL_10) || \ 1083 ((CHANNEL) == ADC_CHANNEL_11) || \ 1084 ((CHANNEL) == ADC_CHANNEL_12) || \ 1085 ((CHANNEL) == ADC_CHANNEL_13) || \ 1086 ((CHANNEL) == ADC_CHANNEL_14) || \ 1087 ((CHANNEL) == ADC_CHANNEL_15) || \ 1088 ((CHANNEL) == ADC_CHANNEL_16) || \ 1089 ((CHANNEL) == ADC_CHANNEL_17) || \ 1090 ((CHANNEL) == ADC_CHANNEL_18) || \ 1091 ((CHANNEL) == ADC_CHANNEL_19) || \ 1092 ((CHANNEL) == ADC_CHANNEL_20) || \ 1093 ((CHANNEL) == ADC_CHANNEL_21) || \ 1094 ((CHANNEL) == ADC_CHANNEL_22) || \ 1095 ((CHANNEL) == ADC_CHANNEL_23) || \ 1096 ((CHANNEL) == ADC_CHANNEL_24) || \ 1097 ((CHANNEL) == ADC_CHANNEL_25) || \ 1098 ((CHANNEL) == ADC_CHANNEL_26) || \ 1099 ((CHANNEL) == ADC_CHANNEL_27) || \ 1100 ((CHANNEL) == ADC_CHANNEL_28) || \ 1101 ((CHANNEL) == ADC_CHANNEL_29) || \ 1102 ((CHANNEL) == ADC_CHANNEL_30) || \ 1103 ((CHANNEL) == ADC_CHANNEL_31) ) 1104 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1105 1106 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ 1107 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ 1108 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ 1109 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ 1110 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ 1111 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ 1112 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ 1113 ((TIME) == ADC_SAMPLETIME_384CYCLES) ) 1114 1115 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1116 1117 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1118 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1119 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1120 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1121 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1122 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1123 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1124 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1125 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1126 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1127 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1128 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1129 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1130 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1131 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1132 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1133 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1134 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1135 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1136 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1137 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1138 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1139 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1140 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1141 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1142 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1143 ((CHANNEL) == ADC_REGULAR_RANK_27) || \ 1144 ((CHANNEL) == ADC_REGULAR_RANK_28) ) 1145 #else 1146 1147 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1148 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1149 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1150 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1151 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1152 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1153 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1154 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1155 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1156 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1157 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1158 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1159 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1160 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1161 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1162 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1163 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1164 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1165 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1166 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1167 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1168 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1169 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1170 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1171 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1172 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1173 ((CHANNEL) == ADC_REGULAR_RANK_27) ) 1174 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1175 1176 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 1177 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1178 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1179 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1180 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1181 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1182 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1183 1184 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 1185 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 1186 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 1187 1188 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 1189 ((EVENT) == ADC_FLAG_OVR) ) 1190 1191 /** 1192 * @brief Verify that a ADC data is within range corresponding to 1193 * ADC resolution. 1194 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). 1195 * @param __ADC_DATA__: value checked against the resolution. 1196 * @retval SET: ADC data is within range corresponding to ADC resolution 1197 * RESET: ADC data is not within range corresponding to ADC resolution 1198 * 1199 */ 1200 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \ 1201 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \ 1202 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \ 1203 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) || \ 1204 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) ) 1205 1206 1207 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1208 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U))) 1209 #else 1210 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U))) 1211 #endif 1212 1213 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) 1214 1215 /** 1216 * @} 1217 */ 1218 1219 1220 /* Include ADC HAL Extension module */ 1221 #include "stm32l1xx_hal_adc_ex.h" 1222 1223 /* Exported functions --------------------------------------------------------*/ 1224 /** @addtogroup ADC_Exported_Functions 1225 * @{ 1226 */ 1227 1228 /** @addtogroup ADC_Exported_Functions_Group1 1229 * @{ 1230 */ 1231 1232 1233 /* Initialization and de-initialization functions **********************************/ 1234 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 1235 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1236 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 1237 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 1238 /** 1239 * @} 1240 */ 1241 1242 /* IO operation functions *****************************************************/ 1243 1244 /** @addtogroup ADC_Exported_Functions_Group2 1245 * @{ 1246 */ 1247 1248 1249 /* Blocking mode: Polling */ 1250 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 1251 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 1252 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1253 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 1254 1255 /* Non-blocking mode: Interruption */ 1256 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 1257 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 1258 1259 /* Non-blocking mode: DMA */ 1260 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 1261 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 1262 1263 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1264 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 1265 1266 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1267 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 1268 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 1269 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 1270 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 1271 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1272 /** 1273 * @} 1274 */ 1275 1276 1277 /* Peripheral Control functions ***********************************************/ 1278 /** @addtogroup ADC_Exported_Functions_Group3 1279 * @{ 1280 */ 1281 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 1282 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 1283 /** 1284 * @} 1285 */ 1286 1287 1288 /* Peripheral State functions *************************************************/ 1289 /** @addtogroup ADC_Exported_Functions_Group4 1290 * @{ 1291 */ 1292 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 1293 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1294 /** 1295 * @} 1296 */ 1297 1298 1299 /** 1300 * @} 1301 */ 1302 1303 1304 /* Internal HAL driver functions **********************************************/ 1305 /** @addtogroup ADC_Private_Functions 1306 * @{ 1307 */ 1308 1309 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 1310 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); 1311 /** 1312 * @} 1313 */ 1314 1315 1316 /** 1317 * @} 1318 */ 1319 1320 /** 1321 * @} 1322 */ 1323 1324 #ifdef __cplusplus 1325 } 1326 #endif 1327 1328 1329 #endif /* __STM32L1xx_HAL_ADC_H */ 1330 1331 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1332
