1 /** 2 ****************************************************************************** 3 * @file stm32l1xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32L1xx_HAL_ADC_H 21 #define __STM32L1xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l1xx_hal_def.h" 29 30 /** @addtogroup STM32L1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup ADC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup ADC_Exported_Types ADC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief Structure definition of ADC and regular group initialization 45 * @note Parameters of this structure are shared within 2 scopes: 46 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. 47 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. 48 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 49 * ADC state can be either: 50 * - For all parameters: ADC disabled 51 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. 52 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. 53 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 54 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 55 */ 56 typedef struct 57 { 58 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler. 59 This parameter can be a value of @ref ADC_ClockPrescaler 60 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 61 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 62 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */ 63 uint32_t Resolution; /*!< Configures the ADC resolution. 64 This parameter can be a value of @ref ADC_Resolution */ 65 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) 66 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). 67 This parameter can be a value of @ref ADC_Data_align */ 68 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 69 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 70 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 71 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 72 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). 73 Scan direction is upward: from rank1 to rank 'n'. 74 This parameter can be a value of @ref ADC_Scan_mode */ 75 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 76 This parameter can be a value of @ref ADC_EOCSelection. 77 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. 78 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) 79 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. 80 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). 81 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ 82 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 83 conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 84 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 85 This parameter can be a value of @ref ADC_LowPowerAutoWait. 86 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. 87 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed 88 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). 89 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */ 90 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 91 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 92 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */ 93 uint32_t ChannelsBank; /*!< Selects the ADC channels bank. 94 This parameter can be a value of @ref ADC_ChannelsBank. 95 Note: Banks availability depends on devices categories. 96 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */ 97 FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 98 after the selected trigger occurred (software start or external trigger). 99 This parameter can be set to ENABLE or DISABLE. */ 100 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 101 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 102 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 103 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */ 104 #else 105 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 106 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 107 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */ 108 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 109 FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 110 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 111 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 112 This parameter can be set to ENABLE or DISABLE. */ 113 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 114 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 115 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 116 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 117 If set to ADC_SOFTWARE_START, external triggers are disabled. 118 If set to external trigger source, triggering is on event rising edge by default. 119 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 120 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 121 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 122 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 123 FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 124 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 125 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 126 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 127 This parameter can be set to ENABLE or DISABLE. */ 128 }ADC_InitTypeDef; 129 130 /** 131 * @brief Structure definition of ADC channel for regular group 132 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 133 * ADC can be either disabled or enabled without conversion on going on regular group. 134 */ 135 typedef struct 136 { 137 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 138 This parameter can be a value of @ref ADC_channels 139 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. 140 Maximum number of channels by device category (without taking in account each device package constraints): 141 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26. 142 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 143 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8. 144 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '. 145 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */ 146 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 147 This parameter can be a value of @ref ADC_regular_rank 148 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ 149 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 150 Unit: ADC clock cycles 151 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). 152 This parameter can be a value of @ref ADC_sampling_times 153 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. 154 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. 155 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 156 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 157 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ 158 }ADC_ChannelConfTypeDef; 159 160 /** 161 * @brief ADC Configuration analog watchdog definition 162 * @note The setting of these parameters with function is conditioned to ADC state. 163 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups. 164 */ 165 typedef struct 166 { 167 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group. 168 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 169 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 170 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) 171 This parameter can be a value of @ref ADC_channels. */ 172 FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 173 This parameter can be set to ENABLE or DISABLE */ 174 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 175 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 176 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 177 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ 178 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ 179 }ADC_AnalogWDGConfTypeDef; 180 181 /** 182 * @brief HAL ADC state machine: ADC states definition (bitfields) 183 */ 184 /* States of ADC global scope */ 185 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 186 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 187 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ 188 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 189 190 /* States of ADC errors */ 191 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 192 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 193 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 194 195 /* States of ADC group regular */ 196 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 197 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 198 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 199 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 200 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32L1 device: End Of Sampling flag raised */ 201 202 /* States of ADC group injected */ 203 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, 204 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 205 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ 206 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */ 207 208 /* States of ADC analog watchdogs */ 209 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ 210 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */ 211 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */ 212 213 /* States of ADC multi-mode */ 214 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */ 215 216 217 /** 218 * @brief ADC handle Structure definition 219 */ 220 typedef struct __ADC_HandleTypeDef 221 { 222 ADC_TypeDef *Instance; /*!< Register base address */ 223 224 ADC_InitTypeDef Init; /*!< ADC required parameters */ 225 226 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */ 227 228 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 229 230 HAL_LockTypeDef Lock; /*!< ADC locking object */ 231 232 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 233 234 __IO uint32_t ErrorCode; /*!< ADC Error code */ 235 236 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 237 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 238 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 239 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 240 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 241 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */ 242 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 243 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 244 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 245 }ADC_HandleTypeDef; 246 247 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 248 /** 249 * @brief HAL ADC Callback ID enumeration definition 250 */ 251 typedef enum 252 { 253 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 254 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 255 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 256 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 257 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 258 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 259 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 260 } HAL_ADC_CallbackIDTypeDef; 261 262 /** 263 * @brief HAL ADC Callback pointer definition 264 */ 265 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 266 267 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 268 269 /** 270 * @} 271 */ 272 273 274 275 /* Exported constants --------------------------------------------------------*/ 276 277 /** @defgroup ADC_Exported_Constants ADC Exported Constants 278 * @{ 279 */ 280 281 /** @defgroup ADC_Error_Code ADC Error Code 282 * @{ 283 */ 284 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 285 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, 286 enable/disable, erroneous state */ 287 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 288 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 289 290 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 291 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 292 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 293 /** 294 * @} 295 */ 296 297 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler 298 * @{ 299 */ 300 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */ 301 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */ 302 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */ 303 /** 304 * @} 305 */ 306 307 /** @defgroup ADC_Resolution ADC Resolution 308 * @{ 309 */ 310 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 311 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */ 312 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */ 313 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */ 314 /** 315 * @} 316 */ 317 318 /** @defgroup ADC_Data_align ADC Data_align 319 * @{ 320 */ 321 #define ADC_DATAALIGN_RIGHT (0x00000000U) 322 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) 323 /** 324 * @} 325 */ 326 327 /** @defgroup ADC_Scan_mode ADC Scan mode 328 * @{ 329 */ 330 #define ADC_SCAN_DISABLE (0x00000000U) 331 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) 332 /** 333 * @} 334 */ 335 336 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group 337 * @{ 338 */ 339 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 340 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) 341 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) 342 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) 343 /** 344 * @} 345 */ 346 347 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular 348 * @{ 349 */ 350 /* List of external triggers with generic trigger name, sorted by trigger */ 351 /* name: */ 352 353 /* External triggers of regular group for ADC1 */ 354 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3 355 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2 356 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO 357 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1 358 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3 359 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO 360 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4 361 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO 362 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO 363 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2 364 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO 365 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11 366 #define ADC_SOFTWARE_START (0x00000010U) 367 /** 368 * @} 369 */ 370 371 /** @defgroup ADC_EOCSelection ADC EOCSelection 372 * @{ 373 */ 374 #define ADC_EOC_SEQ_CONV (0x00000000U) 375 #define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS) 376 /** 377 * @} 378 */ 379 380 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait 381 * @{ 382 */ 383 /*!< Note : For compatibility with other STM32 devices with ADC autowait */ 384 /* feature limited to enable or disable settings: */ 385 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */ 386 387 #define ADC_AUTOWAIT_DISABLE (0x00000000U) 388 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */ 389 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */ 390 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */ 391 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */ 392 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */ 393 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */ 394 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */ 395 396 /** 397 * @} 398 */ 399 400 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff 401 * @{ 402 */ 403 #define ADC_AUTOPOWEROFF_DISABLE (0x00000000U) 404 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */ 405 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */ 406 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */ 407 /** 408 * @} 409 */ 410 411 412 /** @defgroup ADC_ChannelsBank ADC ChannelsBank 413 * @{ 414 */ 415 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 416 #define ADC_CHANNELS_BANK_A (0x00000000U) 417 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) 418 419 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 420 ((BANK) == ADC_CHANNELS_BANK_B) ) 421 #else 422 #define ADC_CHANNELS_BANK_A (0x00000000U) 423 424 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 425 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 426 /** 427 * @} 428 */ 429 430 /** @defgroup ADC_channels ADC channels 431 * @{ 432 */ 433 /* Note: Depending on devices, some channels may not be available on package */ 434 /* pins. Refer to device datasheet for channels availability. */ 435 #define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */ 436 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 437 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 438 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 439 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */ 440 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 441 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 442 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 443 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */ 444 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 445 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */ 446 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */ 447 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */ 448 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 449 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 450 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 451 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */ 452 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 453 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 454 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 455 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 456 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 457 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */ 458 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 459 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */ 460 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */ 461 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 462 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 463 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 464 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */ 465 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 466 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */ 467 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */ 468 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 469 470 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 471 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 472 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */ 473 474 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 475 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */ 476 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */ 477 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) 478 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */ 479 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */ 480 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 481 /** 482 * @} 483 */ 484 485 /** @defgroup ADC_sampling_times ADC sampling times 486 * @{ 487 */ 488 #define ADC_SAMPLETIME_4CYCLES (0x00000000U) /*!< Sampling time 4 ADC clock cycles */ 489 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */ 490 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */ 491 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */ 492 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */ 493 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */ 494 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */ 495 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */ 496 /** 497 * @} 498 */ 499 500 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels 501 * @{ 502 */ 503 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \ 504 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \ 505 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \ 506 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2) 507 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \ 508 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \ 509 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \ 510 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2) 511 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 512 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 513 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \ 514 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 515 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 516 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 517 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \ 518 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \ 519 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \ 520 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2) 521 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \ 522 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 ) 523 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 524 525 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \ 526 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \ 527 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \ 528 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1) 529 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \ 530 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \ 531 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \ 532 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1) 533 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 534 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 535 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \ 536 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 537 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 538 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 539 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \ 540 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \ 541 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \ 542 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1) 543 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \ 544 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 ) 545 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 546 547 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \ 548 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \ 549 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \ 550 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0) 551 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \ 552 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \ 553 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \ 554 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0) 555 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 556 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 557 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \ 558 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 559 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 560 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 561 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \ 562 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \ 563 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \ 564 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0) 565 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \ 566 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 ) 567 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 568 /** 569 * @} 570 */ 571 572 /** @defgroup ADC_regular_rank ADC rank into regular group 573 * @{ 574 */ 575 #define ADC_REGULAR_RANK_1 (0x00000001U) 576 #define ADC_REGULAR_RANK_2 (0x00000002U) 577 #define ADC_REGULAR_RANK_3 (0x00000003U) 578 #define ADC_REGULAR_RANK_4 (0x00000004U) 579 #define ADC_REGULAR_RANK_5 (0x00000005U) 580 #define ADC_REGULAR_RANK_6 (0x00000006U) 581 #define ADC_REGULAR_RANK_7 (0x00000007U) 582 #define ADC_REGULAR_RANK_8 (0x00000008U) 583 #define ADC_REGULAR_RANK_9 (0x00000009U) 584 #define ADC_REGULAR_RANK_10 (0x0000000AU) 585 #define ADC_REGULAR_RANK_11 (0x0000000BU) 586 #define ADC_REGULAR_RANK_12 (0x0000000CU) 587 #define ADC_REGULAR_RANK_13 (0x0000000DU) 588 #define ADC_REGULAR_RANK_14 (0x0000000EU) 589 #define ADC_REGULAR_RANK_15 (0x0000000FU) 590 #define ADC_REGULAR_RANK_16 (0x00000010U) 591 #define ADC_REGULAR_RANK_17 (0x00000011U) 592 #define ADC_REGULAR_RANK_18 (0x00000012U) 593 #define ADC_REGULAR_RANK_19 (0x00000013U) 594 #define ADC_REGULAR_RANK_20 (0x00000014U) 595 #define ADC_REGULAR_RANK_21 (0x00000015U) 596 #define ADC_REGULAR_RANK_22 (0x00000016U) 597 #define ADC_REGULAR_RANK_23 (0x00000017U) 598 #define ADC_REGULAR_RANK_24 (0x00000018U) 599 #define ADC_REGULAR_RANK_25 (0x00000019U) 600 #define ADC_REGULAR_RANK_26 (0x0000001AU) 601 #define ADC_REGULAR_RANK_27 (0x0000001BU) 602 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 603 #define ADC_REGULAR_RANK_28 (0x0000001CU) 604 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 605 /** 606 * @} 607 */ 608 609 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 610 * @{ 611 */ 612 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) 613 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) 614 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) 615 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 616 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) 617 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) 618 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) 619 /** 620 * @} 621 */ 622 623 /** @defgroup ADC_conversion_group ADC conversion group 624 * @{ 625 */ 626 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC)) 627 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC)) 628 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC)) 629 /** 630 * @} 631 */ 632 633 /** @defgroup ADC_Event_type ADC Event type 634 * @{ 635 */ 636 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */ 637 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 638 /** 639 * @} 640 */ 641 642 /** @defgroup ADC_interrupts_definition ADC interrupts definition 643 * @{ 644 */ 645 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 646 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */ 647 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */ 648 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */ 649 /** 650 * @} 651 */ 652 653 /** @defgroup ADC_flags_definition ADC flags definition 654 * @{ 655 */ 656 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */ 657 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */ 658 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */ 659 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */ 660 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */ 661 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */ 662 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */ 663 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */ 664 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */ 665 /** 666 * @} 667 */ 668 669 /** 670 * @} 671 */ 672 673 674 /* Private constants ---------------------------------------------------------*/ 675 676 /** @addtogroup ADC_Private_Constants ADC Private Constants 677 * @{ 678 */ 679 680 /* List of external triggers of regular group for ADC1: */ 681 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 682 683 /* External triggers of regular group for ADC1 */ 684 #define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U) 685 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0)) 686 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 )) 687 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 688 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 )) 689 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) 690 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) 691 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 692 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 )) 693 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) 694 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 )) 695 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) 696 697 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */ 698 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \ 699 ADC_FLAG_OVR) 700 701 /** 702 * @} 703 */ 704 705 706 /* Exported macro ------------------------------------------------------------*/ 707 708 /** @defgroup ADC_Exported_Macros ADC Exported Macros 709 * @{ 710 */ 711 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 712 /* final user. */ 713 714 /** 715 * @brief Enable the ADC peripheral 716 * @param __HANDLE__: ADC handle 717 * @retval None 718 */ 719 #define __HAL_ADC_ENABLE(__HANDLE__) \ 720 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON 721 722 /** 723 * @brief Disable the ADC peripheral 724 * @param __HANDLE__: ADC handle 725 * @retval None 726 */ 727 #define __HAL_ADC_DISABLE(__HANDLE__) \ 728 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON 729 730 /** 731 * @brief Enable the ADC end of conversion interrupt. 732 * @param __HANDLE__: ADC handle 733 * @param __INTERRUPT__: ADC Interrupt 734 * This parameter can be any combination of the following values: 735 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 736 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 737 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 738 * @arg ADC_IT_OVR: ADC overrun interrupt source 739 * @retval None 740 */ 741 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 742 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 743 744 /** 745 * @brief Disable the ADC end of conversion interrupt. 746 * @param __HANDLE__: ADC handle 747 * @param __INTERRUPT__: ADC Interrupt 748 * This parameter can be any combination of the following values: 749 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 750 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 751 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 752 * @arg ADC_IT_OVR: ADC overrun interrupt source 753 * @retval None 754 */ 755 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 756 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 757 758 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 759 * @param __HANDLE__: ADC handle 760 * @param __INTERRUPT__: ADC interrupt source to check 761 * This parameter can be any combination of the following values: 762 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 763 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source 764 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 765 * @arg ADC_IT_OVR: ADC overrun interrupt source 766 * @retval State of interruption (SET or RESET) 767 */ 768 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 769 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 770 771 /** 772 * @brief Get the selected ADC's flag status. 773 * @param __HANDLE__: ADC handle 774 * @param __FLAG__: ADC flag 775 * This parameter can be any combination of the following values: 776 * @arg ADC_FLAG_STRT: ADC Regular group start flag 777 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 778 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 779 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 780 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 781 * @arg ADC_FLAG_OVR: ADC overrun flag 782 * @arg ADC_FLAG_ADONS: ADC ready status flag 783 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 784 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 785 * @retval None 786 */ 787 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 788 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 789 790 /** 791 * @brief Clear the ADC's pending flags 792 * @param __HANDLE__: ADC handle 793 * @param __FLAG__: ADC flag 794 * @arg ADC_FLAG_STRT: ADC Regular group start flag 795 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag 796 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 797 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag 798 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 799 * @arg ADC_FLAG_OVR: ADC overrun flag 800 * @arg ADC_FLAG_ADONS: ADC ready status flag 801 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag 802 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag 803 * @retval None 804 */ 805 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 806 (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) 807 808 /** @brief Reset ADC handle state 809 * @param __HANDLE__ ADC handle 810 * @retval None 811 */ 812 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 813 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 814 do{ \ 815 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 816 (__HANDLE__)->MspInitCallback = NULL; \ 817 (__HANDLE__)->MspDeInitCallback = NULL; \ 818 } while(0) 819 #else 820 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 821 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 822 #endif 823 824 /** 825 * @} 826 */ 827 828 /* Private macro ------------------------------------------------------------*/ 829 830 /** @defgroup ADC_Private_Macros ADC Private Macros 831 * @{ 832 */ 833 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 834 /* code of final user. */ 835 836 /** 837 * @brief Verification of ADC state: enabled or disabled 838 * @param __HANDLE__: ADC handle 839 * @retval SET (ADC enabled) or RESET (ADC disabled) 840 */ 841 #define ADC_IS_ENABLE(__HANDLE__) \ 842 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ 843 ) ? SET : RESET) 844 845 /** 846 * @brief Test if conversion trigger of regular group is software start 847 * or external trigger. 848 * @param __HANDLE__: ADC handle 849 * @retval SET (software start) or RESET (external trigger) 850 */ 851 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 852 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 853 854 /** 855 * @brief Test if conversion trigger of injected group is software start 856 * or external trigger. 857 * @param __HANDLE__: ADC handle 858 * @retval SET (software start) or RESET (external trigger) 859 */ 860 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 861 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) 862 863 /** 864 * @brief Simultaneously clears and sets specific bits of the handle State 865 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 866 * the first parameter is the ADC handle State, the second parameter is the 867 * bit field to clear, the third and last parameter is the bit field to set. 868 * @retval None 869 */ 870 #define ADC_STATE_CLR_SET MODIFY_REG 871 872 /** 873 * @brief Clear ADC error code (set it to error code: "no error") 874 * @param __HANDLE__: ADC handle 875 * @retval None 876 */ 877 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 878 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 879 880 /** 881 * @brief Set ADC number of ranks into regular channel sequence length. 882 * @param _NbrOfConversion_: Regular channel sequence length 883 * @retval None 884 */ 885 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ 886 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) 887 888 /** 889 * @brief Set the ADC's sample time for channel numbers between 10 and 18. 890 * @param _SAMPLETIME_: Sample time parameter. 891 * @param _CHANNELNB_: Channel number. 892 * @retval None 893 */ 894 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ 895 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10))) 896 897 /** 898 * @brief Set the ADC's sample time for channel numbers between 0 and 9. 899 * @param _SAMPLETIME_: Sample time parameter. 900 * @param _CHANNELNB_: Channel number. 901 * @retval None 902 */ 903 #define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \ 904 ((_SAMPLETIME_) << (3 * (_CHANNELNB_))) 905 906 /** 907 * @brief Set the selected regular channel rank for rank between 1 and 6. 908 * @param _CHANNELNB_: Channel number. 909 * @param _RANKNB_: Rank number. 910 * @retval None 911 */ 912 #define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \ 913 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1))) 914 915 /** 916 * @brief Set the selected regular channel rank for rank between 7 and 12. 917 * @param _CHANNELNB_: Channel number. 918 * @param _RANKNB_: Rank number. 919 * @retval None 920 */ 921 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \ 922 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7))) 923 924 /** 925 * @brief Set the selected regular channel rank for rank between 13 and 18. 926 * @param _CHANNELNB_: Channel number. 927 * @param _RANKNB_: Rank number. 928 * @retval None 929 */ 930 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ 931 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13))) 932 933 /** 934 * @brief Set the selected regular channel rank for rank between 19 and 24. 935 * @param _CHANNELNB_: Channel number. 936 * @param _RANKNB_: Rank number. 937 * @retval None 938 */ 939 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ 940 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19))) 941 942 /** 943 * @brief Set the selected regular channel rank for rank between 25 and 28. 944 * @param _CHANNELNB_: Channel number. 945 * @param _RANKNB_: Rank number. 946 * @retval None 947 */ 948 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ 949 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25))) 950 951 /** 952 * @brief Set the injected sequence length. 953 * @param _JSQR_JL_: Sequence length. 954 * @retval None 955 */ 956 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20) 957 958 /** 959 * @brief Set the selected injected channel rank 960 * Note: on STM32L1 devices, channel rank position in JSQR register 961 * is depending on total number of ranks selected into 962 * injected sequencer (ranks sequence starting from 4-JL) 963 * @param _CHANNELNB_: Channel number. 964 * @param _RANKNB_: Rank number. 965 * @param _JSQR_JL_: Sequence length. 966 * @retval None 967 */ 968 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ 969 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) 970 971 /** 972 * @brief Enable the ADC DMA continuous request. 973 * @param _DMACONTREQ_MODE_: DMA continuous request mode. 974 * @retval None 975 */ 976 #define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \ 977 ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS)) 978 979 /** 980 * @brief Enable ADC continuous conversion mode. 981 * @param _CONTINUOUS_MODE_: Continuous mode. 982 * @retval None 983 */ 984 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ 985 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) 986 987 /** 988 * @brief Configures the number of discontinuous conversions for the regular group channels. 989 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. 990 * @retval None 991 */ 992 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ 993 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) 994 995 /** 996 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 997 * @param _SCAN_MODE_: Scan conversion mode. 998 * @retval None 999 */ 1000 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */ 1001 /* is equivalent to ADC_SCAN_ENABLE. */ 1002 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \ 1003 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \ 1004 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \ 1005 ) 1006 1007 1008 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 1009 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \ 1010 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) ) 1011 1012 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 1013 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 1014 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 1015 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 1016 1017 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ 1018 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 1019 1020 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 1021 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 1022 1023 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ 1024 ((SCAN_MODE) == ADC_SCAN_ENABLE) ) 1025 1026 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1027 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1028 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1029 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1030 1031 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ 1032 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ 1033 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ 1034 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ 1035 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \ 1036 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ 1037 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ 1038 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ 1039 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ 1040 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \ 1041 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \ 1042 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ 1043 ((REGTRIG) == ADC_SOFTWARE_START) ) 1044 1045 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 1046 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 1047 1048 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \ 1049 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \ 1050 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \ 1051 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \ 1052 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \ 1053 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \ 1054 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \ 1055 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) ) 1056 1057 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \ 1058 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \ 1059 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \ 1060 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) ) 1061 1062 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1063 1064 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \ 1065 ((BANK) == ADC_CHANNELS_BANK_B) ) 1066 #else 1067 1068 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A)) 1069 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1070 1071 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) 1072 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1073 ((CHANNEL) == ADC_CHANNEL_1) || \ 1074 ((CHANNEL) == ADC_CHANNEL_2) || \ 1075 ((CHANNEL) == ADC_CHANNEL_3) || \ 1076 ((CHANNEL) == ADC_CHANNEL_4) || \ 1077 ((CHANNEL) == ADC_CHANNEL_5) || \ 1078 ((CHANNEL) == ADC_CHANNEL_6) || \ 1079 ((CHANNEL) == ADC_CHANNEL_7) || \ 1080 ((CHANNEL) == ADC_CHANNEL_8) || \ 1081 ((CHANNEL) == ADC_CHANNEL_9) || \ 1082 ((CHANNEL) == ADC_CHANNEL_10) || \ 1083 ((CHANNEL) == ADC_CHANNEL_11) || \ 1084 ((CHANNEL) == ADC_CHANNEL_12) || \ 1085 ((CHANNEL) == ADC_CHANNEL_13) || \ 1086 ((CHANNEL) == ADC_CHANNEL_14) || \ 1087 ((CHANNEL) == ADC_CHANNEL_15) || \ 1088 ((CHANNEL) == ADC_CHANNEL_16) || \ 1089 ((CHANNEL) == ADC_CHANNEL_17) || \ 1090 ((CHANNEL) == ADC_CHANNEL_18) || \ 1091 ((CHANNEL) == ADC_CHANNEL_19) || \ 1092 ((CHANNEL) == ADC_CHANNEL_20) || \ 1093 ((CHANNEL) == ADC_CHANNEL_21) || \ 1094 ((CHANNEL) == ADC_CHANNEL_22) || \ 1095 ((CHANNEL) == ADC_CHANNEL_23) || \ 1096 ((CHANNEL) == ADC_CHANNEL_24) || \ 1097 ((CHANNEL) == ADC_CHANNEL_25) || \ 1098 ((CHANNEL) == ADC_CHANNEL_26) ) 1099 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ 1100 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1101 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ 1102 ((CHANNEL) == ADC_CHANNEL_1) || \ 1103 ((CHANNEL) == ADC_CHANNEL_2) || \ 1104 ((CHANNEL) == ADC_CHANNEL_3) || \ 1105 ((CHANNEL) == ADC_CHANNEL_4) || \ 1106 ((CHANNEL) == ADC_CHANNEL_5) || \ 1107 ((CHANNEL) == ADC_CHANNEL_6) || \ 1108 ((CHANNEL) == ADC_CHANNEL_7) || \ 1109 ((CHANNEL) == ADC_CHANNEL_8) || \ 1110 ((CHANNEL) == ADC_CHANNEL_9) || \ 1111 ((CHANNEL) == ADC_CHANNEL_10) || \ 1112 ((CHANNEL) == ADC_CHANNEL_11) || \ 1113 ((CHANNEL) == ADC_CHANNEL_12) || \ 1114 ((CHANNEL) == ADC_CHANNEL_13) || \ 1115 ((CHANNEL) == ADC_CHANNEL_14) || \ 1116 ((CHANNEL) == ADC_CHANNEL_15) || \ 1117 ((CHANNEL) == ADC_CHANNEL_16) || \ 1118 ((CHANNEL) == ADC_CHANNEL_17) || \ 1119 ((CHANNEL) == ADC_CHANNEL_18) || \ 1120 ((CHANNEL) == ADC_CHANNEL_19) || \ 1121 ((CHANNEL) == ADC_CHANNEL_20) || \ 1122 ((CHANNEL) == ADC_CHANNEL_21) || \ 1123 ((CHANNEL) == ADC_CHANNEL_22) || \ 1124 ((CHANNEL) == ADC_CHANNEL_23) || \ 1125 ((CHANNEL) == ADC_CHANNEL_24) || \ 1126 ((CHANNEL) == ADC_CHANNEL_25) || \ 1127 ((CHANNEL) == ADC_CHANNEL_26) || \ 1128 ((CHANNEL) == ADC_CHANNEL_27) || \ 1129 ((CHANNEL) == ADC_CHANNEL_28) || \ 1130 ((CHANNEL) == ADC_CHANNEL_29) || \ 1131 ((CHANNEL) == ADC_CHANNEL_30) || \ 1132 ((CHANNEL) == ADC_CHANNEL_31) ) 1133 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1134 1135 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \ 1136 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \ 1137 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \ 1138 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \ 1139 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \ 1140 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \ 1141 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \ 1142 ((TIME) == ADC_SAMPLETIME_384CYCLES) ) 1143 1144 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1145 1146 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1147 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1148 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1149 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1150 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1151 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1152 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1153 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1154 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1155 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1156 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1157 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1158 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1159 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1160 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1161 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1162 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1163 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1164 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1165 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1166 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1167 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1168 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1169 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1170 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1171 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1172 ((CHANNEL) == ADC_REGULAR_RANK_27) || \ 1173 ((CHANNEL) == ADC_REGULAR_RANK_28) ) 1174 #else 1175 1176 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \ 1177 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \ 1178 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \ 1179 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \ 1180 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \ 1181 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \ 1182 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \ 1183 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \ 1184 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \ 1185 ((CHANNEL) == ADC_REGULAR_RANK_10) || \ 1186 ((CHANNEL) == ADC_REGULAR_RANK_11) || \ 1187 ((CHANNEL) == ADC_REGULAR_RANK_12) || \ 1188 ((CHANNEL) == ADC_REGULAR_RANK_13) || \ 1189 ((CHANNEL) == ADC_REGULAR_RANK_14) || \ 1190 ((CHANNEL) == ADC_REGULAR_RANK_15) || \ 1191 ((CHANNEL) == ADC_REGULAR_RANK_16) || \ 1192 ((CHANNEL) == ADC_REGULAR_RANK_17) || \ 1193 ((CHANNEL) == ADC_REGULAR_RANK_18) || \ 1194 ((CHANNEL) == ADC_REGULAR_RANK_19) || \ 1195 ((CHANNEL) == ADC_REGULAR_RANK_20) || \ 1196 ((CHANNEL) == ADC_REGULAR_RANK_21) || \ 1197 ((CHANNEL) == ADC_REGULAR_RANK_22) || \ 1198 ((CHANNEL) == ADC_REGULAR_RANK_23) || \ 1199 ((CHANNEL) == ADC_REGULAR_RANK_24) || \ 1200 ((CHANNEL) == ADC_REGULAR_RANK_25) || \ 1201 ((CHANNEL) == ADC_REGULAR_RANK_26) || \ 1202 ((CHANNEL) == ADC_REGULAR_RANK_27) ) 1203 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ 1204 1205 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 1206 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1207 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1208 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1209 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1210 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1211 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1212 1213 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \ 1214 ((CONVERSION) == ADC_INJECTED_GROUP) || \ 1215 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) ) 1216 1217 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 1218 ((EVENT) == ADC_FLAG_OVR) ) 1219 1220 /** 1221 * @brief Verify that a ADC data is within range corresponding to 1222 * ADC resolution. 1223 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). 1224 * @param __ADC_DATA__: value checked against the resolution. 1225 * @retval SET: ADC data is within range corresponding to ADC resolution 1226 * RESET: ADC data is not within range corresponding to ADC resolution 1227 * 1228 */ 1229 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \ 1230 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \ 1231 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \ 1232 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) || \ 1233 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) ) 1234 1235 1236 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 1237 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U))) 1238 #else 1239 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U))) 1240 #endif 1241 1242 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) 1243 1244 /** 1245 * @} 1246 */ 1247 1248 1249 /* Include ADC HAL Extension module */ 1250 #include "stm32l1xx_hal_adc_ex.h" 1251 1252 /* Exported functions --------------------------------------------------------*/ 1253 /** @addtogroup ADC_Exported_Functions 1254 * @{ 1255 */ 1256 1257 /** @addtogroup ADC_Exported_Functions_Group1 1258 * @{ 1259 */ 1260 1261 1262 /* Initialization and de-initialization functions **********************************/ 1263 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 1264 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1265 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 1266 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 1267 1268 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1269 /* Callbacks Register/UnRegister functions ***********************************/ 1270 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 1271 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1272 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1273 1274 /** 1275 * @} 1276 */ 1277 1278 /* IO operation functions *****************************************************/ 1279 1280 /** @addtogroup ADC_Exported_Functions_Group2 1281 * @{ 1282 */ 1283 1284 1285 /* Blocking mode: Polling */ 1286 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 1287 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 1288 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 1289 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 1290 1291 /* Non-blocking mode: Interruption */ 1292 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 1293 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 1294 1295 /* Non-blocking mode: DMA */ 1296 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 1297 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 1298 1299 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1300 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 1301 1302 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1303 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 1304 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 1305 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 1306 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 1307 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1308 /** 1309 * @} 1310 */ 1311 1312 1313 /* Peripheral Control functions ***********************************************/ 1314 /** @addtogroup ADC_Exported_Functions_Group3 1315 * @{ 1316 */ 1317 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 1318 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 1319 /** 1320 * @} 1321 */ 1322 1323 1324 /* Peripheral State functions *************************************************/ 1325 /** @addtogroup ADC_Exported_Functions_Group4 1326 * @{ 1327 */ 1328 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 1329 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1330 /** 1331 * @} 1332 */ 1333 1334 1335 /** 1336 * @} 1337 */ 1338 1339 1340 /* Internal HAL driver functions **********************************************/ 1341 /** @addtogroup ADC_Private_Functions 1342 * @{ 1343 */ 1344 1345 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 1346 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc); 1347 /** 1348 * @} 1349 */ 1350 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** 1357 * @} 1358 */ 1359 1360 #ifdef __cplusplus 1361 } 1362 #endif 1363 1364 1365 #endif /* __STM32L1xx_HAL_ADC_H */ 1366
