1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2016 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L0xx_LL_DMA_H
22 #define STM32L0xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx.h"
30
31 /** @addtogroup STM32L0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 #if defined(DMA1_Channel6)
55 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
56 #endif /*DMA1_Channel6*/
57 #if defined(DMA1_Channel7)
58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
59 #endif /*DMA1_Channel7*/
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
67 * @{
68 */
69 /* Define used to get CSELR register offset */
70 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
71
72 /* Defines used for the bit position in the register and perform offsets */
73 #define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U)
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
91 * @{
92 */
93 typedef struct
94 {
95 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
96 or as Source base address in case of memory to memory transfer direction.
97
98 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
99
100 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
101 or as Destination base address in case of memory to memory transfer direction.
102
103 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
104
105 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
106 from memory to memory or from peripheral to memory.
107 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
110
111 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
112 This parameter can be a value of @ref DMA_LL_EC_MODE
113 @note: The circular buffer mode cannot be used if the memory to memory
114 data transfer direction is configured on the selected Channel
115
116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
117
118 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
119 is incremented or not.
120 This parameter can be a value of @ref DMA_LL_EC_PERIPH
121
122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
123
124 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
125 is incremented or not.
126 This parameter can be a value of @ref DMA_LL_EC_MEMORY
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
129
130 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
131 in case of memory to memory transfer direction.
132 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
135
136 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
137 in case of memory to memory transfer direction.
138 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
141
142 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
143 The data unit is equal to the source buffer configuration set in PeripheralSize
144 or MemorySize parameters depending in the transfer direction.
145 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
146
147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
148
149 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
150 This parameter can be a value of @ref DMA_LL_EC_REQUEST
151
152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
153
154 uint32_t Priority; /*!< Specifies the channel priority level.
155 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
156
157 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
158
159 } LL_DMA_InitTypeDef;
160 /**
161 * @}
162 */
163 #endif /*USE_FULL_LL_DRIVER*/
164
165 /* Exported constants --------------------------------------------------------*/
166 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
167 * @{
168 */
169 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
170 * @brief Flags defines which can be used with LL_DMA_WriteReg function
171 * @{
172 */
173 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
174 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
175 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
176 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
177 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
178 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
179 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
180 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
181 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
182 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
183 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
184 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
185 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
186 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
187 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
188 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
189 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
190 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
191 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
192 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
193 #if defined(DMA1_Channel6)
194 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
195 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
196 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
197 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
198 #endif
199 #if defined(DMA1_Channel7)
200 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
201 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
202 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
203 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
204 #endif
205 /**
206 * @}
207 */
208
209 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
210 * @brief Flags defines which can be used with LL_DMA_ReadReg function
211 * @{
212 */
213 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
214 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
215 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
216 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
217 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
218 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
219 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
220 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
221 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
222 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
223 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
224 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
225 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
226 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
227 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
228 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
229 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
230 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
231 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
232 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
233 #if defined(DMA1_Channel6)
234 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
235 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
236 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
237 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
238 #endif
239 #if defined(DMA1_Channel7)
240 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
241 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
242 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
243 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
244 #endif
245 /**
246 * @}
247 */
248
249 /** @defgroup DMA_LL_EC_IT IT Defines
250 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
251 * @{
252 */
253 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
254 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
255 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
256 /**
257 * @}
258 */
259
260 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
261 * @{
262 */
263 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
264 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
265 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
266 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
267 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
268 #if defined(DMA1_Channel6)
269 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
270 #endif
271 #if defined(DMA1_Channel7)
272 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
273 #endif
274 #if defined(USE_FULL_LL_DRIVER)
275 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
276 #endif /*USE_FULL_LL_DRIVER*/
277 /**
278 * @}
279 */
280
281 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
282 * @{
283 */
284 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
285 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
286 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
287 /**
288 * @}
289 */
290
291 /** @defgroup DMA_LL_EC_MODE Transfer mode
292 * @{
293 */
294 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
295 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
296 /**
297 * @}
298 */
299
300 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
301 * @{
302 */
303 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
304 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
305 /**
306 * @}
307 */
308
309 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
310 * @{
311 */
312 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
313 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
314 /**
315 * @}
316 */
317
318 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
319 * @{
320 */
321 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
322 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
323 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
324 /**
325 * @}
326 */
327
328 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
329 * @{
330 */
331 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
332 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
333 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
334 /**
335 * @}
336 */
337
338 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
339 * @{
340 */
341 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
342 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
343 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
344 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
345 /**
346 * @}
347 */
348
349 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request
350 * @{
351 */
352 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */
353 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */
354 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */
355 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */
356 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */
357 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */
358 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */
359 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */
360 #define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */
361 #define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */
362 #define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */
363 #define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */
364 #define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */
365 #define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */
366 #define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */
367 #define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */
368 /**
369 * @}
370 */
371
372 /**
373 * @}
374 */
375
376 /* Exported macro ------------------------------------------------------------*/
377 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
378 * @{
379 */
380
381 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
382 * @{
383 */
384 /**
385 * @brief Write a value in DMA register
386 * @param __INSTANCE__ DMA Instance
387 * @param __REG__ Register to be written
388 * @param __VALUE__ Value to be written in the register
389 * @retval None
390 */
391 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
392
393 /**
394 * @brief Read a value in DMA register
395 * @param __INSTANCE__ DMA Instance
396 * @param __REG__ Register to be read
397 * @retval Register value
398 */
399 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
400 /**
401 * @}
402 */
403
404 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
405 * @{
406 */
407 /**
408 * @brief Convert DMAx_Channely into DMAx
409 * @param __CHANNEL_INSTANCE__ DMAx_Channely
410 * @retval DMAx
411 */
412 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
413
414 /**
415 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
416 * @param __CHANNEL_INSTANCE__ DMAx_Channely
417 * @retval LL_DMA_CHANNEL_y
418 */
419 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
420 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
421 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
427 LL_DMA_CHANNEL_7)
428 #elif defined (DMA1_Channel6)
429 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
430 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
435 LL_DMA_CHANNEL_6)
436 #else
437 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
438 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
442 LL_DMA_CHANNEL_5)
443 #endif /* DMA1_Channel6 && DMA1_Channel7 */
444
445 /**
446 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
447 * @param __DMA_INSTANCE__ DMAx
448 * @param __CHANNEL__ LL_DMA_CHANNEL_y
449 * @retval DMAx_Channely
450 */
451 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
452 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
453 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
459 DMA1_Channel7)
460 #elif defined (DMA1_Channel6)
461 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
462 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
467 DMA1_Channel6)
468 #else
469 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
470 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
474 DMA1_Channel5)
475 #endif /* DMA1_Channel6 && DMA1_Channel7 */
476
477 /**
478 * @}
479 */
480
481 /**
482 * @}
483 */
484
485 /* Exported functions --------------------------------------------------------*/
486 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
487 * @{
488 */
489
490 /** @defgroup DMA_LL_EF_Configuration Configuration
491 * @{
492 */
493 /**
494 * @brief Enable DMA channel.
495 * @rmtoll CCR EN LL_DMA_EnableChannel
496 * @param DMAx DMAx Instance
497 * @param Channel This parameter can be one of the following values:
498 * @arg @ref LL_DMA_CHANNEL_1
499 * @arg @ref LL_DMA_CHANNEL_2
500 * @arg @ref LL_DMA_CHANNEL_3
501 * @arg @ref LL_DMA_CHANNEL_4
502 * @arg @ref LL_DMA_CHANNEL_5
503 * @arg @ref LL_DMA_CHANNEL_6
504 * @arg @ref LL_DMA_CHANNEL_7
505 * @retval None
506 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)507 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
508 {
509 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
510 }
511
512 /**
513 * @brief Disable DMA channel.
514 * @rmtoll CCR EN LL_DMA_DisableChannel
515 * @param DMAx DMAx Instance
516 * @param Channel This parameter can be one of the following values:
517 * @arg @ref LL_DMA_CHANNEL_1
518 * @arg @ref LL_DMA_CHANNEL_2
519 * @arg @ref LL_DMA_CHANNEL_3
520 * @arg @ref LL_DMA_CHANNEL_4
521 * @arg @ref LL_DMA_CHANNEL_5
522 * @arg @ref LL_DMA_CHANNEL_6
523 * @arg @ref LL_DMA_CHANNEL_7
524 * @retval None
525 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)526 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
527 {
528 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
529 }
530
531 /**
532 * @brief Check if DMA channel is enabled or disabled.
533 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
534 * @param DMAx DMAx Instance
535 * @param Channel This parameter can be one of the following values:
536 * @arg @ref LL_DMA_CHANNEL_1
537 * @arg @ref LL_DMA_CHANNEL_2
538 * @arg @ref LL_DMA_CHANNEL_3
539 * @arg @ref LL_DMA_CHANNEL_4
540 * @arg @ref LL_DMA_CHANNEL_5
541 * @arg @ref LL_DMA_CHANNEL_6
542 * @arg @ref LL_DMA_CHANNEL_7
543 * @retval State of bit (1 or 0).
544 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)545 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
546 {
547 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
548 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
549 }
550
551 /**
552 * @brief Configure all parameters link to DMA transfer.
553 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
554 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
555 * CCR CIRC LL_DMA_ConfigTransfer\n
556 * CCR PINC LL_DMA_ConfigTransfer\n
557 * CCR MINC LL_DMA_ConfigTransfer\n
558 * CCR PSIZE LL_DMA_ConfigTransfer\n
559 * CCR MSIZE LL_DMA_ConfigTransfer\n
560 * CCR PL LL_DMA_ConfigTransfer
561 * @param DMAx DMAx Instance
562 * @param Channel This parameter can be one of the following values:
563 * @arg @ref LL_DMA_CHANNEL_1
564 * @arg @ref LL_DMA_CHANNEL_2
565 * @arg @ref LL_DMA_CHANNEL_3
566 * @arg @ref LL_DMA_CHANNEL_4
567 * @arg @ref LL_DMA_CHANNEL_5
568 * @arg @ref LL_DMA_CHANNEL_6
569 * @arg @ref LL_DMA_CHANNEL_7
570 * @param Configuration This parameter must be a combination of all the following values:
571 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
572 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
573 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
574 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
575 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
576 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
577 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
578 * @retval None
579 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)580 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
581 {
582 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
583 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
584 Configuration);
585 }
586
587 /**
588 * @brief Set Data transfer direction (read from peripheral or from memory).
589 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
590 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
591 * @param DMAx DMAx Instance
592 * @param Channel This parameter can be one of the following values:
593 * @arg @ref LL_DMA_CHANNEL_1
594 * @arg @ref LL_DMA_CHANNEL_2
595 * @arg @ref LL_DMA_CHANNEL_3
596 * @arg @ref LL_DMA_CHANNEL_4
597 * @arg @ref LL_DMA_CHANNEL_5
598 * @arg @ref LL_DMA_CHANNEL_6
599 * @arg @ref LL_DMA_CHANNEL_7
600 * @param Direction This parameter can be one of the following values:
601 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
602 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
603 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
604 * @retval None
605 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)606 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
607 {
608 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
609 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
610 }
611
612 /**
613 * @brief Get Data transfer direction (read from peripheral or from memory).
614 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
615 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
616 * @param DMAx DMAx Instance
617 * @param Channel This parameter can be one of the following values:
618 * @arg @ref LL_DMA_CHANNEL_1
619 * @arg @ref LL_DMA_CHANNEL_2
620 * @arg @ref LL_DMA_CHANNEL_3
621 * @arg @ref LL_DMA_CHANNEL_4
622 * @arg @ref LL_DMA_CHANNEL_5
623 * @arg @ref LL_DMA_CHANNEL_6
624 * @arg @ref LL_DMA_CHANNEL_7
625 * @retval Returned value can be one of the following values:
626 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
627 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
628 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
629 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)630 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
631 {
632 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
633 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
634 }
635
636 /**
637 * @brief Set DMA mode circular or normal.
638 * @note The circular buffer mode cannot be used if the memory-to-memory
639 * data transfer is configured on the selected Channel.
640 * @rmtoll CCR CIRC LL_DMA_SetMode
641 * @param DMAx DMAx Instance
642 * @param Channel This parameter can be one of the following values:
643 * @arg @ref LL_DMA_CHANNEL_1
644 * @arg @ref LL_DMA_CHANNEL_2
645 * @arg @ref LL_DMA_CHANNEL_3
646 * @arg @ref LL_DMA_CHANNEL_4
647 * @arg @ref LL_DMA_CHANNEL_5
648 * @arg @ref LL_DMA_CHANNEL_6
649 * @arg @ref LL_DMA_CHANNEL_7
650 * @param Mode This parameter can be one of the following values:
651 * @arg @ref LL_DMA_MODE_NORMAL
652 * @arg @ref LL_DMA_MODE_CIRCULAR
653 * @retval None
654 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)655 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
656 {
657 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
658 Mode);
659 }
660
661 /**
662 * @brief Get DMA mode circular or normal.
663 * @rmtoll CCR CIRC LL_DMA_GetMode
664 * @param DMAx DMAx Instance
665 * @param Channel This parameter can be one of the following values:
666 * @arg @ref LL_DMA_CHANNEL_1
667 * @arg @ref LL_DMA_CHANNEL_2
668 * @arg @ref LL_DMA_CHANNEL_3
669 * @arg @ref LL_DMA_CHANNEL_4
670 * @arg @ref LL_DMA_CHANNEL_5
671 * @arg @ref LL_DMA_CHANNEL_6
672 * @arg @ref LL_DMA_CHANNEL_7
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DMA_MODE_NORMAL
675 * @arg @ref LL_DMA_MODE_CIRCULAR
676 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)677 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
678 {
679 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
680 DMA_CCR_CIRC));
681 }
682
683 /**
684 * @brief Set Peripheral increment mode.
685 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
686 * @param DMAx DMAx Instance
687 * @param Channel This parameter can be one of the following values:
688 * @arg @ref LL_DMA_CHANNEL_1
689 * @arg @ref LL_DMA_CHANNEL_2
690 * @arg @ref LL_DMA_CHANNEL_3
691 * @arg @ref LL_DMA_CHANNEL_4
692 * @arg @ref LL_DMA_CHANNEL_5
693 * @arg @ref LL_DMA_CHANNEL_6
694 * @arg @ref LL_DMA_CHANNEL_7
695 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
696 * @arg @ref LL_DMA_PERIPH_INCREMENT
697 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
698 * @retval None
699 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)700 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
701 {
702 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
703 PeriphOrM2MSrcIncMode);
704 }
705
706 /**
707 * @brief Get Peripheral increment mode.
708 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
709 * @param DMAx DMAx Instance
710 * @param Channel This parameter can be one of the following values:
711 * @arg @ref LL_DMA_CHANNEL_1
712 * @arg @ref LL_DMA_CHANNEL_2
713 * @arg @ref LL_DMA_CHANNEL_3
714 * @arg @ref LL_DMA_CHANNEL_4
715 * @arg @ref LL_DMA_CHANNEL_5
716 * @arg @ref LL_DMA_CHANNEL_6
717 * @arg @ref LL_DMA_CHANNEL_7
718 * @retval Returned value can be one of the following values:
719 * @arg @ref LL_DMA_PERIPH_INCREMENT
720 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
721 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)722 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
723 {
724 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
725 DMA_CCR_PINC));
726 }
727
728 /**
729 * @brief Set Memory increment mode.
730 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
731 * @param DMAx DMAx Instance
732 * @param Channel This parameter can be one of the following values:
733 * @arg @ref LL_DMA_CHANNEL_1
734 * @arg @ref LL_DMA_CHANNEL_2
735 * @arg @ref LL_DMA_CHANNEL_3
736 * @arg @ref LL_DMA_CHANNEL_4
737 * @arg @ref LL_DMA_CHANNEL_5
738 * @arg @ref LL_DMA_CHANNEL_6
739 * @arg @ref LL_DMA_CHANNEL_7
740 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
741 * @arg @ref LL_DMA_MEMORY_INCREMENT
742 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
743 * @retval None
744 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)745 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
746 {
747 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
748 MemoryOrM2MDstIncMode);
749 }
750
751 /**
752 * @brief Get Memory increment mode.
753 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
754 * @param DMAx DMAx Instance
755 * @param Channel This parameter can be one of the following values:
756 * @arg @ref LL_DMA_CHANNEL_1
757 * @arg @ref LL_DMA_CHANNEL_2
758 * @arg @ref LL_DMA_CHANNEL_3
759 * @arg @ref LL_DMA_CHANNEL_4
760 * @arg @ref LL_DMA_CHANNEL_5
761 * @arg @ref LL_DMA_CHANNEL_6
762 * @arg @ref LL_DMA_CHANNEL_7
763 * @retval Returned value can be one of the following values:
764 * @arg @ref LL_DMA_MEMORY_INCREMENT
765 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
766 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)767 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
768 {
769 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
770 DMA_CCR_MINC));
771 }
772
773 /**
774 * @brief Set Peripheral size.
775 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
776 * @param DMAx DMAx Instance
777 * @param Channel This parameter can be one of the following values:
778 * @arg @ref LL_DMA_CHANNEL_1
779 * @arg @ref LL_DMA_CHANNEL_2
780 * @arg @ref LL_DMA_CHANNEL_3
781 * @arg @ref LL_DMA_CHANNEL_4
782 * @arg @ref LL_DMA_CHANNEL_5
783 * @arg @ref LL_DMA_CHANNEL_6
784 * @arg @ref LL_DMA_CHANNEL_7
785 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
786 * @arg @ref LL_DMA_PDATAALIGN_BYTE
787 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
788 * @arg @ref LL_DMA_PDATAALIGN_WORD
789 * @retval None
790 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)791 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
792 {
793 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
794 PeriphOrM2MSrcDataSize);
795 }
796
797 /**
798 * @brief Get Peripheral size.
799 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
800 * @param DMAx DMAx Instance
801 * @param Channel This parameter can be one of the following values:
802 * @arg @ref LL_DMA_CHANNEL_1
803 * @arg @ref LL_DMA_CHANNEL_2
804 * @arg @ref LL_DMA_CHANNEL_3
805 * @arg @ref LL_DMA_CHANNEL_4
806 * @arg @ref LL_DMA_CHANNEL_5
807 * @arg @ref LL_DMA_CHANNEL_6
808 * @arg @ref LL_DMA_CHANNEL_7
809 * @retval Returned value can be one of the following values:
810 * @arg @ref LL_DMA_PDATAALIGN_BYTE
811 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
812 * @arg @ref LL_DMA_PDATAALIGN_WORD
813 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)814 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
815 {
816 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
817 DMA_CCR_PSIZE));
818 }
819
820 /**
821 * @brief Set Memory size.
822 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
823 * @param DMAx DMAx Instance
824 * @param Channel This parameter can be one of the following values:
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @arg @ref LL_DMA_CHANNEL_5
830 * @arg @ref LL_DMA_CHANNEL_6
831 * @arg @ref LL_DMA_CHANNEL_7
832 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
833 * @arg @ref LL_DMA_MDATAALIGN_BYTE
834 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
835 * @arg @ref LL_DMA_MDATAALIGN_WORD
836 * @retval None
837 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)838 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
839 {
840 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
841 MemoryOrM2MDstDataSize);
842 }
843
844 /**
845 * @brief Get Memory size.
846 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
847 * @param DMAx DMAx Instance
848 * @param Channel This parameter can be one of the following values:
849 * @arg @ref LL_DMA_CHANNEL_1
850 * @arg @ref LL_DMA_CHANNEL_2
851 * @arg @ref LL_DMA_CHANNEL_3
852 * @arg @ref LL_DMA_CHANNEL_4
853 * @arg @ref LL_DMA_CHANNEL_5
854 * @arg @ref LL_DMA_CHANNEL_6
855 * @arg @ref LL_DMA_CHANNEL_7
856 * @retval Returned value can be one of the following values:
857 * @arg @ref LL_DMA_MDATAALIGN_BYTE
858 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
859 * @arg @ref LL_DMA_MDATAALIGN_WORD
860 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)861 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
862 {
863 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
864 DMA_CCR_MSIZE));
865 }
866
867 /**
868 * @brief Set Channel priority level.
869 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
870 * @param DMAx DMAx Instance
871 * @param Channel This parameter can be one of the following values:
872 * @arg @ref LL_DMA_CHANNEL_1
873 * @arg @ref LL_DMA_CHANNEL_2
874 * @arg @ref LL_DMA_CHANNEL_3
875 * @arg @ref LL_DMA_CHANNEL_4
876 * @arg @ref LL_DMA_CHANNEL_5
877 * @arg @ref LL_DMA_CHANNEL_6
878 * @arg @ref LL_DMA_CHANNEL_7
879 * @param Priority This parameter can be one of the following values:
880 * @arg @ref LL_DMA_PRIORITY_LOW
881 * @arg @ref LL_DMA_PRIORITY_MEDIUM
882 * @arg @ref LL_DMA_PRIORITY_HIGH
883 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
884 * @retval None
885 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)886 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
887 {
888 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
889 Priority);
890 }
891
892 /**
893 * @brief Get Channel priority level.
894 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
895 * @param DMAx DMAx Instance
896 * @param Channel This parameter can be one of the following values:
897 * @arg @ref LL_DMA_CHANNEL_1
898 * @arg @ref LL_DMA_CHANNEL_2
899 * @arg @ref LL_DMA_CHANNEL_3
900 * @arg @ref LL_DMA_CHANNEL_4
901 * @arg @ref LL_DMA_CHANNEL_5
902 * @arg @ref LL_DMA_CHANNEL_6
903 * @arg @ref LL_DMA_CHANNEL_7
904 * @retval Returned value can be one of the following values:
905 * @arg @ref LL_DMA_PRIORITY_LOW
906 * @arg @ref LL_DMA_PRIORITY_MEDIUM
907 * @arg @ref LL_DMA_PRIORITY_HIGH
908 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
909 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)910 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
911 {
912 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
913 DMA_CCR_PL));
914 }
915
916 /**
917 * @brief Set Number of data to transfer.
918 * @note This action has no effect if
919 * channel is enabled.
920 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
921 * @param DMAx DMAx Instance
922 * @param Channel This parameter can be one of the following values:
923 * @arg @ref LL_DMA_CHANNEL_1
924 * @arg @ref LL_DMA_CHANNEL_2
925 * @arg @ref LL_DMA_CHANNEL_3
926 * @arg @ref LL_DMA_CHANNEL_4
927 * @arg @ref LL_DMA_CHANNEL_5
928 * @arg @ref LL_DMA_CHANNEL_6
929 * @arg @ref LL_DMA_CHANNEL_7
930 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
931 * @retval None
932 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)933 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
934 {
935 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
936 DMA_CNDTR_NDT, NbData);
937 }
938
939 /**
940 * @brief Get Number of data to transfer.
941 * @note Once the channel is enabled, the return value indicate the
942 * remaining bytes to be transmitted.
943 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
944 * @param DMAx DMAx Instance
945 * @param Channel This parameter can be one of the following values:
946 * @arg @ref LL_DMA_CHANNEL_1
947 * @arg @ref LL_DMA_CHANNEL_2
948 * @arg @ref LL_DMA_CHANNEL_3
949 * @arg @ref LL_DMA_CHANNEL_4
950 * @arg @ref LL_DMA_CHANNEL_5
951 * @arg @ref LL_DMA_CHANNEL_6
952 * @arg @ref LL_DMA_CHANNEL_7
953 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
954 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)955 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
956 {
957 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
958 DMA_CNDTR_NDT));
959 }
960
961 /**
962 * @brief Configure the Source and Destination addresses.
963 * @note This API must not be called when the DMA channel is enabled.
964 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
965 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
966 * CMAR MA LL_DMA_ConfigAddresses
967 * @param DMAx DMAx Instance
968 * @param Channel This parameter can be one of the following values:
969 * @arg @ref LL_DMA_CHANNEL_1
970 * @arg @ref LL_DMA_CHANNEL_2
971 * @arg @ref LL_DMA_CHANNEL_3
972 * @arg @ref LL_DMA_CHANNEL_4
973 * @arg @ref LL_DMA_CHANNEL_5
974 * @arg @ref LL_DMA_CHANNEL_6
975 * @arg @ref LL_DMA_CHANNEL_7
976 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
977 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
978 * @param Direction This parameter can be one of the following values:
979 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
980 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
981 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
982 * @retval None
983 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)984 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
985 uint32_t DstAddress, uint32_t Direction)
986 {
987 /* Direction Memory to Periph */
988 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
989 {
990 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
991 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
992 }
993 /* Direction Periph to Memory and Memory to Memory */
994 else
995 {
996 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
997 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
998 }
999 }
1000
1001 /**
1002 * @brief Set the Memory address.
1003 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1004 * @note This API must not be called when the DMA channel is enabled.
1005 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1006 * @param DMAx DMAx Instance
1007 * @param Channel This parameter can be one of the following values:
1008 * @arg @ref LL_DMA_CHANNEL_1
1009 * @arg @ref LL_DMA_CHANNEL_2
1010 * @arg @ref LL_DMA_CHANNEL_3
1011 * @arg @ref LL_DMA_CHANNEL_4
1012 * @arg @ref LL_DMA_CHANNEL_5
1013 * @arg @ref LL_DMA_CHANNEL_6
1014 * @arg @ref LL_DMA_CHANNEL_7
1015 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1016 * @retval None
1017 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1018 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1019 {
1020 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1021 }
1022
1023 /**
1024 * @brief Set the Peripheral address.
1025 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1026 * @note This API must not be called when the DMA channel is enabled.
1027 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1028 * @param DMAx DMAx Instance
1029 * @param Channel This parameter can be one of the following values:
1030 * @arg @ref LL_DMA_CHANNEL_1
1031 * @arg @ref LL_DMA_CHANNEL_2
1032 * @arg @ref LL_DMA_CHANNEL_3
1033 * @arg @ref LL_DMA_CHANNEL_4
1034 * @arg @ref LL_DMA_CHANNEL_5
1035 * @arg @ref LL_DMA_CHANNEL_6
1036 * @arg @ref LL_DMA_CHANNEL_7
1037 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1038 * @retval None
1039 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1040 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1041 {
1042 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1043 }
1044
1045 /**
1046 * @brief Get Memory address.
1047 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1048 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1049 * @param DMAx DMAx Instance
1050 * @param Channel This parameter can be one of the following values:
1051 * @arg @ref LL_DMA_CHANNEL_1
1052 * @arg @ref LL_DMA_CHANNEL_2
1053 * @arg @ref LL_DMA_CHANNEL_3
1054 * @arg @ref LL_DMA_CHANNEL_4
1055 * @arg @ref LL_DMA_CHANNEL_5
1056 * @arg @ref LL_DMA_CHANNEL_6
1057 * @arg @ref LL_DMA_CHANNEL_7
1058 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1059 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1060 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1061 {
1062 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1063 }
1064
1065 /**
1066 * @brief Get Peripheral address.
1067 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1068 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1069 * @param DMAx DMAx Instance
1070 * @param Channel This parameter can be one of the following values:
1071 * @arg @ref LL_DMA_CHANNEL_1
1072 * @arg @ref LL_DMA_CHANNEL_2
1073 * @arg @ref LL_DMA_CHANNEL_3
1074 * @arg @ref LL_DMA_CHANNEL_4
1075 * @arg @ref LL_DMA_CHANNEL_5
1076 * @arg @ref LL_DMA_CHANNEL_6
1077 * @arg @ref LL_DMA_CHANNEL_7
1078 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1079 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1080 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1081 {
1082 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1083 }
1084
1085 /**
1086 * @brief Set the Memory to Memory Source address.
1087 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1088 * @note This API must not be called when the DMA channel is enabled.
1089 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1090 * @param DMAx DMAx Instance
1091 * @param Channel This parameter can be one of the following values:
1092 * @arg @ref LL_DMA_CHANNEL_1
1093 * @arg @ref LL_DMA_CHANNEL_2
1094 * @arg @ref LL_DMA_CHANNEL_3
1095 * @arg @ref LL_DMA_CHANNEL_4
1096 * @arg @ref LL_DMA_CHANNEL_5
1097 * @arg @ref LL_DMA_CHANNEL_6
1098 * @arg @ref LL_DMA_CHANNEL_7
1099 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1100 * @retval None
1101 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1102 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1103 {
1104 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1105 }
1106
1107 /**
1108 * @brief Set the Memory to Memory Destination address.
1109 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1110 * @note This API must not be called when the DMA channel is enabled.
1111 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1112 * @param DMAx DMAx Instance
1113 * @param Channel This parameter can be one of the following values:
1114 * @arg @ref LL_DMA_CHANNEL_1
1115 * @arg @ref LL_DMA_CHANNEL_2
1116 * @arg @ref LL_DMA_CHANNEL_3
1117 * @arg @ref LL_DMA_CHANNEL_4
1118 * @arg @ref LL_DMA_CHANNEL_5
1119 * @arg @ref LL_DMA_CHANNEL_6
1120 * @arg @ref LL_DMA_CHANNEL_7
1121 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1122 * @retval None
1123 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1124 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1125 {
1126 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1127 }
1128
1129 /**
1130 * @brief Get the Memory to Memory Source address.
1131 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1132 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1133 * @param DMAx DMAx Instance
1134 * @param Channel This parameter can be one of the following values:
1135 * @arg @ref LL_DMA_CHANNEL_1
1136 * @arg @ref LL_DMA_CHANNEL_2
1137 * @arg @ref LL_DMA_CHANNEL_3
1138 * @arg @ref LL_DMA_CHANNEL_4
1139 * @arg @ref LL_DMA_CHANNEL_5
1140 * @arg @ref LL_DMA_CHANNEL_6
1141 * @arg @ref LL_DMA_CHANNEL_7
1142 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1143 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1144 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1145 {
1146 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1147 }
1148
1149 /**
1150 * @brief Get the Memory to Memory Destination address.
1151 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1152 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1153 * @param DMAx DMAx Instance
1154 * @param Channel This parameter can be one of the following values:
1155 * @arg @ref LL_DMA_CHANNEL_1
1156 * @arg @ref LL_DMA_CHANNEL_2
1157 * @arg @ref LL_DMA_CHANNEL_3
1158 * @arg @ref LL_DMA_CHANNEL_4
1159 * @arg @ref LL_DMA_CHANNEL_5
1160 * @arg @ref LL_DMA_CHANNEL_6
1161 * @arg @ref LL_DMA_CHANNEL_7
1162 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1163 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1164 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1165 {
1166 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1167 }
1168
1169 /**
1170 * @brief Set DMA request for DMA instance on Channel x.
1171 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1172 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1173 * CSELR C2S LL_DMA_SetPeriphRequest\n
1174 * CSELR C3S LL_DMA_SetPeriphRequest\n
1175 * CSELR C4S LL_DMA_SetPeriphRequest\n
1176 * CSELR C5S LL_DMA_SetPeriphRequest\n
1177 * CSELR C6S LL_DMA_SetPeriphRequest\n
1178 * CSELR C7S LL_DMA_SetPeriphRequest
1179 * @param DMAx DMAx Instance
1180 * @param Channel This parameter can be one of the following values:
1181 * @arg @ref LL_DMA_CHANNEL_1
1182 * @arg @ref LL_DMA_CHANNEL_2
1183 * @arg @ref LL_DMA_CHANNEL_3
1184 * @arg @ref LL_DMA_CHANNEL_4
1185 * @arg @ref LL_DMA_CHANNEL_5
1186 * @arg @ref LL_DMA_CHANNEL_6
1187 * @arg @ref LL_DMA_CHANNEL_7
1188 * @param Request This parameter can be one of the following values:
1189 * @arg @ref LL_DMA_REQUEST_0
1190 * @arg @ref LL_DMA_REQUEST_1
1191 * @arg @ref LL_DMA_REQUEST_2
1192 * @arg @ref LL_DMA_REQUEST_3
1193 * @arg @ref LL_DMA_REQUEST_4
1194 * @arg @ref LL_DMA_REQUEST_5
1195 * @arg @ref LL_DMA_REQUEST_6
1196 * @arg @ref LL_DMA_REQUEST_7
1197 * @arg @ref LL_DMA_REQUEST_8
1198 * @arg @ref LL_DMA_REQUEST_9
1199 * @arg @ref LL_DMA_REQUEST_10
1200 * @arg @ref LL_DMA_REQUEST_11
1201 * @arg @ref LL_DMA_REQUEST_12
1202 * @arg @ref LL_DMA_REQUEST_13
1203 * @arg @ref LL_DMA_REQUEST_14
1204 * @arg @ref LL_DMA_REQUEST_15
1205 * @retval None
1206 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1207 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1208 {
1209 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1210 DMA_CSELR_C1S << ((Channel - 1U) * 4U), Request << DMA_POSITION_CSELR_CXS);
1211 }
1212
1213 /**
1214 * @brief Get DMA request for DMA instance on Channel x.
1215 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1216 * CSELR C2S LL_DMA_GetPeriphRequest\n
1217 * CSELR C3S LL_DMA_GetPeriphRequest\n
1218 * CSELR C4S LL_DMA_GetPeriphRequest\n
1219 * CSELR C5S LL_DMA_GetPeriphRequest\n
1220 * CSELR C6S LL_DMA_GetPeriphRequest\n
1221 * CSELR C7S LL_DMA_GetPeriphRequest
1222 * @param DMAx DMAx Instance
1223 * @param Channel This parameter can be one of the following values:
1224 * @arg @ref LL_DMA_CHANNEL_1
1225 * @arg @ref LL_DMA_CHANNEL_2
1226 * @arg @ref LL_DMA_CHANNEL_3
1227 * @arg @ref LL_DMA_CHANNEL_4
1228 * @arg @ref LL_DMA_CHANNEL_5
1229 * @arg @ref LL_DMA_CHANNEL_6
1230 * @arg @ref LL_DMA_CHANNEL_7
1231 * @retval Returned value can be one of the following values:
1232 * @arg @ref LL_DMA_REQUEST_0
1233 * @arg @ref LL_DMA_REQUEST_1
1234 * @arg @ref LL_DMA_REQUEST_2
1235 * @arg @ref LL_DMA_REQUEST_3
1236 * @arg @ref LL_DMA_REQUEST_4
1237 * @arg @ref LL_DMA_REQUEST_5
1238 * @arg @ref LL_DMA_REQUEST_6
1239 * @arg @ref LL_DMA_REQUEST_7
1240 * @arg @ref LL_DMA_REQUEST_8
1241 * @arg @ref LL_DMA_REQUEST_9
1242 * @arg @ref LL_DMA_REQUEST_10
1243 * @arg @ref LL_DMA_REQUEST_11
1244 * @arg @ref LL_DMA_REQUEST_12
1245 * @arg @ref LL_DMA_REQUEST_13
1246 * @arg @ref LL_DMA_REQUEST_14
1247 * @arg @ref LL_DMA_REQUEST_15
1248 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1249 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1250 {
1251 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
1252 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);
1253 }
1254
1255 /**
1256 * @}
1257 */
1258
1259 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1260 * @{
1261 */
1262
1263 /**
1264 * @brief Get Channel 1 global interrupt flag.
1265 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1266 * @param DMAx DMAx Instance
1267 * @retval State of bit (1 or 0).
1268 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1269 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1270 {
1271 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1272 }
1273
1274 /**
1275 * @brief Get Channel 2 global interrupt flag.
1276 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1277 * @param DMAx DMAx Instance
1278 * @retval State of bit (1 or 0).
1279 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1280 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1281 {
1282 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1283 }
1284
1285 /**
1286 * @brief Get Channel 3 global interrupt flag.
1287 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1288 * @param DMAx DMAx Instance
1289 * @retval State of bit (1 or 0).
1290 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1291 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1292 {
1293 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1294 }
1295
1296 /**
1297 * @brief Get Channel 4 global interrupt flag.
1298 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1299 * @param DMAx DMAx Instance
1300 * @retval State of bit (1 or 0).
1301 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1303 {
1304 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1305 }
1306
1307 /**
1308 * @brief Get Channel 5 global interrupt flag.
1309 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1310 * @param DMAx DMAx Instance
1311 * @retval State of bit (1 or 0).
1312 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1314 {
1315 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1316 }
1317
1318 #if defined(DMA1_Channel6)
1319 /**
1320 * @brief Get Channel 6 global interrupt flag.
1321 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1322 * @param DMAx DMAx Instance
1323 * @retval State of bit (1 or 0).
1324 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1325 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1326 {
1327 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1328 }
1329 #endif
1330
1331 #if defined(DMA1_Channel7)
1332 /**
1333 * @brief Get Channel 7 global interrupt flag.
1334 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1335 * @param DMAx DMAx Instance
1336 * @retval State of bit (1 or 0).
1337 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1338 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1339 {
1340 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1341 }
1342 #endif
1343
1344 /**
1345 * @brief Get Channel 1 transfer complete flag.
1346 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1347 * @param DMAx DMAx Instance
1348 * @retval State of bit (1 or 0).
1349 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1350 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1351 {
1352 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1353 }
1354
1355 /**
1356 * @brief Get Channel 2 transfer complete flag.
1357 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1358 * @param DMAx DMAx Instance
1359 * @retval State of bit (1 or 0).
1360 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1361 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1362 {
1363 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1364 }
1365
1366 /**
1367 * @brief Get Channel 3 transfer complete flag.
1368 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1369 * @param DMAx DMAx Instance
1370 * @retval State of bit (1 or 0).
1371 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1372 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1373 {
1374 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1375 }
1376
1377 /**
1378 * @brief Get Channel 4 transfer complete flag.
1379 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1380 * @param DMAx DMAx Instance
1381 * @retval State of bit (1 or 0).
1382 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1383 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1384 {
1385 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1386 }
1387
1388 /**
1389 * @brief Get Channel 5 transfer complete flag.
1390 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1391 * @param DMAx DMAx Instance
1392 * @retval State of bit (1 or 0).
1393 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1394 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1395 {
1396 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1397 }
1398
1399 #if defined(DMA1_Channel6)
1400 /**
1401 * @brief Get Channel 6 transfer complete flag.
1402 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1403 * @param DMAx DMAx Instance
1404 * @retval State of bit (1 or 0).
1405 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1406 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1407 {
1408 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1409 }
1410 #endif
1411
1412 #if defined(DMA1_Channel7)
1413 /**
1414 * @brief Get Channel 7 transfer complete flag.
1415 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1416 * @param DMAx DMAx Instance
1417 * @retval State of bit (1 or 0).
1418 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1419 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1420 {
1421 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1422 }
1423 #endif
1424
1425 /**
1426 * @brief Get Channel 1 half transfer flag.
1427 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1428 * @param DMAx DMAx Instance
1429 * @retval State of bit (1 or 0).
1430 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1431 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1432 {
1433 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1434 }
1435
1436 /**
1437 * @brief Get Channel 2 half transfer flag.
1438 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1439 * @param DMAx DMAx Instance
1440 * @retval State of bit (1 or 0).
1441 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1442 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1443 {
1444 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1445 }
1446
1447 /**
1448 * @brief Get Channel 3 half transfer flag.
1449 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1450 * @param DMAx DMAx Instance
1451 * @retval State of bit (1 or 0).
1452 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1453 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1454 {
1455 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1456 }
1457
1458 /**
1459 * @brief Get Channel 4 half transfer flag.
1460 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1461 * @param DMAx DMAx Instance
1462 * @retval State of bit (1 or 0).
1463 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1464 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1465 {
1466 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1467 }
1468
1469 /**
1470 * @brief Get Channel 5 half transfer flag.
1471 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1472 * @param DMAx DMAx Instance
1473 * @retval State of bit (1 or 0).
1474 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1475 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1476 {
1477 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1478 }
1479
1480 #if defined(DMA1_Channel6)
1481 /**
1482 * @brief Get Channel 6 half transfer flag.
1483 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1484 * @param DMAx DMAx Instance
1485 * @retval State of bit (1 or 0).
1486 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1487 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1488 {
1489 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1490 }
1491 #endif
1492
1493 #if defined(DMA1_Channel7)
1494 /**
1495 * @brief Get Channel 7 half transfer flag.
1496 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1497 * @param DMAx DMAx Instance
1498 * @retval State of bit (1 or 0).
1499 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1500 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1501 {
1502 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1503 }
1504 #endif
1505
1506 /**
1507 * @brief Get Channel 1 transfer error flag.
1508 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1509 * @param DMAx DMAx Instance
1510 * @retval State of bit (1 or 0).
1511 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1512 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1513 {
1514 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1515 }
1516
1517 /**
1518 * @brief Get Channel 2 transfer error flag.
1519 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1520 * @param DMAx DMAx Instance
1521 * @retval State of bit (1 or 0).
1522 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1523 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1524 {
1525 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1526 }
1527
1528 /**
1529 * @brief Get Channel 3 transfer error flag.
1530 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1531 * @param DMAx DMAx Instance
1532 * @retval State of bit (1 or 0).
1533 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1534 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1535 {
1536 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1537 }
1538
1539 /**
1540 * @brief Get Channel 4 transfer error flag.
1541 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1542 * @param DMAx DMAx Instance
1543 * @retval State of bit (1 or 0).
1544 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1545 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1546 {
1547 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Get Channel 5 transfer error flag.
1552 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1553 * @param DMAx DMAx Instance
1554 * @retval State of bit (1 or 0).
1555 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1556 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1557 {
1558 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1559 }
1560
1561 #if defined(DMA1_Channel6)
1562 /**
1563 * @brief Get Channel 6 transfer error flag.
1564 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1565 * @param DMAx DMAx Instance
1566 * @retval State of bit (1 or 0).
1567 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1568 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1569 {
1570 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1571 }
1572 #endif
1573
1574 #if defined(DMA1_Channel7)
1575 /**
1576 * @brief Get Channel 7 transfer error flag.
1577 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1578 * @param DMAx DMAx Instance
1579 * @retval State of bit (1 or 0).
1580 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1581 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1582 {
1583 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1584 }
1585 #endif
1586
1587 /**
1588 * @brief Clear Channel 1 global interrupt flag.
1589 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1590 * @param DMAx DMAx Instance
1591 * @retval None
1592 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1593 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1594 {
1595 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1596 }
1597
1598 /**
1599 * @brief Clear Channel 2 global interrupt flag.
1600 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1601 * @param DMAx DMAx Instance
1602 * @retval None
1603 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1604 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1605 {
1606 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1607 }
1608
1609 /**
1610 * @brief Clear Channel 3 global interrupt flag.
1611 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1612 * @param DMAx DMAx Instance
1613 * @retval None
1614 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1615 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1616 {
1617 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1618 }
1619
1620 /**
1621 * @brief Clear Channel 4 global interrupt flag.
1622 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1623 * @param DMAx DMAx Instance
1624 * @retval None
1625 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1626 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1627 {
1628 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1629 }
1630
1631 /**
1632 * @brief Clear Channel 5 global interrupt flag.
1633 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1634 * @param DMAx DMAx Instance
1635 * @retval None
1636 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)1637 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1638 {
1639 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1640 }
1641
1642 #if defined(DMA1_Channel6)
1643 /**
1644 * @brief Clear Channel 6 global interrupt flag.
1645 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1646 * @param DMAx DMAx Instance
1647 * @retval None
1648 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)1649 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1650 {
1651 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1652 }
1653 #endif
1654
1655 #if defined(DMA1_Channel7)
1656 /**
1657 * @brief Clear Channel 7 global interrupt flag.
1658 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1659 * @param DMAx DMAx Instance
1660 * @retval None
1661 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)1662 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1663 {
1664 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1665 }
1666 #endif
1667
1668 /**
1669 * @brief Clear Channel 1 transfer complete flag.
1670 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1671 * @param DMAx DMAx Instance
1672 * @retval None
1673 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)1674 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1675 {
1676 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1677 }
1678
1679 /**
1680 * @brief Clear Channel 2 transfer complete flag.
1681 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1682 * @param DMAx DMAx Instance
1683 * @retval None
1684 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)1685 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1686 {
1687 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1688 }
1689
1690 /**
1691 * @brief Clear Channel 3 transfer complete flag.
1692 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1693 * @param DMAx DMAx Instance
1694 * @retval None
1695 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)1696 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1697 {
1698 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1699 }
1700
1701 /**
1702 * @brief Clear Channel 4 transfer complete flag.
1703 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1704 * @param DMAx DMAx Instance
1705 * @retval None
1706 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)1707 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1708 {
1709 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1710 }
1711
1712 /**
1713 * @brief Clear Channel 5 transfer complete flag.
1714 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1715 * @param DMAx DMAx Instance
1716 * @retval None
1717 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)1718 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1719 {
1720 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1721 }
1722
1723 #if defined(DMA1_Channel6)
1724 /**
1725 * @brief Clear Channel 6 transfer complete flag.
1726 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1727 * @param DMAx DMAx Instance
1728 * @retval None
1729 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)1730 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1731 {
1732 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1733 }
1734 #endif
1735
1736 #if defined(DMA1_Channel7)
1737 /**
1738 * @brief Clear Channel 7 transfer complete flag.
1739 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1740 * @param DMAx DMAx Instance
1741 * @retval None
1742 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)1743 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1744 {
1745 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1746 }
1747 #endif
1748
1749 /**
1750 * @brief Clear Channel 1 half transfer flag.
1751 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1752 * @param DMAx DMAx Instance
1753 * @retval None
1754 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)1755 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1756 {
1757 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1758 }
1759
1760 /**
1761 * @brief Clear Channel 2 half transfer flag.
1762 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1763 * @param DMAx DMAx Instance
1764 * @retval None
1765 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)1766 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1767 {
1768 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1769 }
1770
1771 /**
1772 * @brief Clear Channel 3 half transfer flag.
1773 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1774 * @param DMAx DMAx Instance
1775 * @retval None
1776 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)1777 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1778 {
1779 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1780 }
1781
1782 /**
1783 * @brief Clear Channel 4 half transfer flag.
1784 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1785 * @param DMAx DMAx Instance
1786 * @retval None
1787 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)1788 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1789 {
1790 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1791 }
1792
1793 /**
1794 * @brief Clear Channel 5 half transfer flag.
1795 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1796 * @param DMAx DMAx Instance
1797 * @retval None
1798 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)1799 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1800 {
1801 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1802 }
1803
1804 #if defined(DMA1_Channel6)
1805 /**
1806 * @brief Clear Channel 6 half transfer flag.
1807 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1808 * @param DMAx DMAx Instance
1809 * @retval None
1810 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)1811 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1812 {
1813 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1814 }
1815 #endif
1816
1817 #if defined(DMA1_Channel7)
1818 /**
1819 * @brief Clear Channel 7 half transfer flag.
1820 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1821 * @param DMAx DMAx Instance
1822 * @retval None
1823 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)1824 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1825 {
1826 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1827 }
1828 #endif
1829
1830 /**
1831 * @brief Clear Channel 1 transfer error flag.
1832 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1833 * @param DMAx DMAx Instance
1834 * @retval None
1835 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)1836 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1837 {
1838 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1839 }
1840
1841 /**
1842 * @brief Clear Channel 2 transfer error flag.
1843 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1844 * @param DMAx DMAx Instance
1845 * @retval None
1846 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)1847 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1848 {
1849 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1850 }
1851
1852 /**
1853 * @brief Clear Channel 3 transfer error flag.
1854 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1855 * @param DMAx DMAx Instance
1856 * @retval None
1857 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)1858 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1859 {
1860 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1861 }
1862
1863 /**
1864 * @brief Clear Channel 4 transfer error flag.
1865 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1866 * @param DMAx DMAx Instance
1867 * @retval None
1868 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)1869 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1870 {
1871 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1872 }
1873
1874 /**
1875 * @brief Clear Channel 5 transfer error flag.
1876 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1877 * @param DMAx DMAx Instance
1878 * @retval None
1879 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)1880 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1881 {
1882 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1883 }
1884
1885 #if defined(DMA1_Channel6)
1886 /**
1887 * @brief Clear Channel 6 transfer error flag.
1888 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1889 * @param DMAx DMAx Instance
1890 * @retval None
1891 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)1892 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1893 {
1894 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1895 }
1896 #endif
1897
1898 #if defined(DMA1_Channel7)
1899 /**
1900 * @brief Clear Channel 7 transfer error flag.
1901 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1902 * @param DMAx DMAx Instance
1903 * @retval None
1904 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)1905 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1906 {
1907 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1908 }
1909 #endif
1910
1911 /**
1912 * @}
1913 */
1914
1915 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1916 * @{
1917 */
1918 /**
1919 * @brief Enable Transfer complete interrupt.
1920 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1921 * @param DMAx DMAx Instance
1922 * @param Channel This parameter can be one of the following values:
1923 * @arg @ref LL_DMA_CHANNEL_1
1924 * @arg @ref LL_DMA_CHANNEL_2
1925 * @arg @ref LL_DMA_CHANNEL_3
1926 * @arg @ref LL_DMA_CHANNEL_4
1927 * @arg @ref LL_DMA_CHANNEL_5
1928 * @arg @ref LL_DMA_CHANNEL_6
1929 * @arg @ref LL_DMA_CHANNEL_7
1930 * @retval None
1931 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1932 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1933 {
1934 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1935 }
1936
1937 /**
1938 * @brief Enable Half transfer interrupt.
1939 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1940 * @param DMAx DMAx Instance
1941 * @param Channel This parameter can be one of the following values:
1942 * @arg @ref LL_DMA_CHANNEL_1
1943 * @arg @ref LL_DMA_CHANNEL_2
1944 * @arg @ref LL_DMA_CHANNEL_3
1945 * @arg @ref LL_DMA_CHANNEL_4
1946 * @arg @ref LL_DMA_CHANNEL_5
1947 * @arg @ref LL_DMA_CHANNEL_6
1948 * @arg @ref LL_DMA_CHANNEL_7
1949 * @retval None
1950 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)1951 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1952 {
1953 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1954 }
1955
1956 /**
1957 * @brief Enable Transfer error interrupt.
1958 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1959 * @param DMAx DMAx Instance
1960 * @param Channel This parameter can be one of the following values:
1961 * @arg @ref LL_DMA_CHANNEL_1
1962 * @arg @ref LL_DMA_CHANNEL_2
1963 * @arg @ref LL_DMA_CHANNEL_3
1964 * @arg @ref LL_DMA_CHANNEL_4
1965 * @arg @ref LL_DMA_CHANNEL_5
1966 * @arg @ref LL_DMA_CHANNEL_6
1967 * @arg @ref LL_DMA_CHANNEL_7
1968 * @retval None
1969 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)1970 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1971 {
1972 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1973 }
1974
1975 /**
1976 * @brief Disable Transfer complete interrupt.
1977 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1978 * @param DMAx DMAx Instance
1979 * @param Channel This parameter can be one of the following values:
1980 * @arg @ref LL_DMA_CHANNEL_1
1981 * @arg @ref LL_DMA_CHANNEL_2
1982 * @arg @ref LL_DMA_CHANNEL_3
1983 * @arg @ref LL_DMA_CHANNEL_4
1984 * @arg @ref LL_DMA_CHANNEL_5
1985 * @arg @ref LL_DMA_CHANNEL_6
1986 * @arg @ref LL_DMA_CHANNEL_7
1987 * @retval None
1988 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)1989 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1990 {
1991 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1992 }
1993
1994 /**
1995 * @brief Disable Half transfer interrupt.
1996 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1997 * @param DMAx DMAx Instance
1998 * @param Channel This parameter can be one of the following values:
1999 * @arg @ref LL_DMA_CHANNEL_1
2000 * @arg @ref LL_DMA_CHANNEL_2
2001 * @arg @ref LL_DMA_CHANNEL_3
2002 * @arg @ref LL_DMA_CHANNEL_4
2003 * @arg @ref LL_DMA_CHANNEL_5
2004 * @arg @ref LL_DMA_CHANNEL_6
2005 * @arg @ref LL_DMA_CHANNEL_7
2006 * @retval None
2007 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2008 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2009 {
2010 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
2011 }
2012
2013 /**
2014 * @brief Disable Transfer error interrupt.
2015 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2016 * @param DMAx DMAx Instance
2017 * @param Channel This parameter can be one of the following values:
2018 * @arg @ref LL_DMA_CHANNEL_1
2019 * @arg @ref LL_DMA_CHANNEL_2
2020 * @arg @ref LL_DMA_CHANNEL_3
2021 * @arg @ref LL_DMA_CHANNEL_4
2022 * @arg @ref LL_DMA_CHANNEL_5
2023 * @arg @ref LL_DMA_CHANNEL_6
2024 * @arg @ref LL_DMA_CHANNEL_7
2025 * @retval None
2026 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2027 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2028 {
2029 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
2030 }
2031
2032 /**
2033 * @brief Check if Transfer complete Interrupt is enabled.
2034 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2035 * @param DMAx DMAx Instance
2036 * @param Channel This parameter can be one of the following values:
2037 * @arg @ref LL_DMA_CHANNEL_1
2038 * @arg @ref LL_DMA_CHANNEL_2
2039 * @arg @ref LL_DMA_CHANNEL_3
2040 * @arg @ref LL_DMA_CHANNEL_4
2041 * @arg @ref LL_DMA_CHANNEL_5
2042 * @arg @ref LL_DMA_CHANNEL_6
2043 * @arg @ref LL_DMA_CHANNEL_7
2044 * @retval State of bit (1 or 0).
2045 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2046 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2047 {
2048 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2049 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2050 }
2051
2052 /**
2053 * @brief Check if Half transfer Interrupt is enabled.
2054 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2055 * @param DMAx DMAx Instance
2056 * @param Channel This parameter can be one of the following values:
2057 * @arg @ref LL_DMA_CHANNEL_1
2058 * @arg @ref LL_DMA_CHANNEL_2
2059 * @arg @ref LL_DMA_CHANNEL_3
2060 * @arg @ref LL_DMA_CHANNEL_4
2061 * @arg @ref LL_DMA_CHANNEL_5
2062 * @arg @ref LL_DMA_CHANNEL_6
2063 * @arg @ref LL_DMA_CHANNEL_7
2064 * @retval State of bit (1 or 0).
2065 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2066 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2067 {
2068 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2069 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2070 }
2071
2072 /**
2073 * @brief Check if Transfer error Interrupt is enabled.
2074 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2075 * @param DMAx DMAx Instance
2076 * @param Channel This parameter can be one of the following values:
2077 * @arg @ref LL_DMA_CHANNEL_1
2078 * @arg @ref LL_DMA_CHANNEL_2
2079 * @arg @ref LL_DMA_CHANNEL_3
2080 * @arg @ref LL_DMA_CHANNEL_4
2081 * @arg @ref LL_DMA_CHANNEL_5
2082 * @arg @ref LL_DMA_CHANNEL_6
2083 * @arg @ref LL_DMA_CHANNEL_7
2084 * @retval State of bit (1 or 0).
2085 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2086 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2087 {
2088 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2089 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2090 }
2091
2092 /**
2093 * @}
2094 */
2095
2096 #if defined(USE_FULL_LL_DRIVER)
2097 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2098 * @{
2099 */
2100 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2101 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2102 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2103
2104 /**
2105 * @}
2106 */
2107 #endif /* USE_FULL_LL_DRIVER */
2108
2109 /**
2110 * @}
2111 */
2112
2113 /**
2114 * @}
2115 */
2116
2117 #endif /* DMA1 */
2118
2119 /**
2120 * @}
2121 */
2122
2123 #ifdef __cplusplus
2124 }
2125 #endif
2126
2127 #endif /* STM32L0xx_LL_DMA_H */
2128
2129
