1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright(c) 2016 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32L0xx_LL_DAC_H
22 #define __STM32L0xx_LL_DAC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l0xx.h"
30
31 /** @addtogroup STM32L0xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DAC1)
36
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
48
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into register CR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel register offset of data holding register DHRx */
54 /* - channel register offset of data output register DORx */
55 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
56 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
57 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
58
59 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
60 #if defined(DAC_CHANNEL2_SUPPORT)
61 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
62 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
63 #else
64 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
65 #endif /* DAC_CHANNEL2_SUPPORT */
66
67 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
68 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
69 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
70 #if defined(DAC_CHANNEL2_SUPPORT)
71 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
72 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
73 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
74 #endif /* DAC_CHANNEL2_SUPPORT */
75 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
76 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
77 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
78 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
79
80 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
81 #if defined(DAC_CHANNEL2_SUPPORT)
82 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
83 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
84 #else
85 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
86 #endif /* DAC_CHANNEL2_SUPPORT */
87
88 #define DAC_REG_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of registers offset (DHR12Rx, DHR12Lx, DHR8Rx, DORx, ...) when shifted to position 0 */
89
90 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
91 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
92 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
93 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 28 bits) */
94
95 /* DAC registers bits positions */
96 #if defined(DAC_CHANNEL2_SUPPORT)
97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
100 #endif /* DAC_CHANNEL2_SUPPORT */
101
102 /* Miscellaneous data */
103 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
104
105 /**
106 * @}
107 */
108
109
110 /* Private macros ------------------------------------------------------------*/
111 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
112 * @{
113 */
114
115 /**
116 * @brief Driver macro reserved for internal use: set a pointer to
117 * a register from a register basis from which an offset
118 * is applied.
119 * @param __REG__ Register basis from which the offset is applied.
120 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
121 * @retval Pointer to register address
122 */
123 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
124 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
125
126 /**
127 * @}
128 */
129
130
131 /* Exported types ------------------------------------------------------------*/
132 #if defined(USE_FULL_LL_DRIVER)
133 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
134 * @{
135 */
136
137 /**
138 * @brief Structure definition of some features of DAC instance.
139 */
140 typedef struct
141 {
142 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
143 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
144
145 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
146
147 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
148 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
149
150 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
151
152 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
153 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
154 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
155 @note If waveform automatic generation mode is disabled, this parameter is discarded.
156
157 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
158
159 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
160 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
161
162 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
163
164 } LL_DAC_InitTypeDef;
165
166 /**
167 * @}
168 */
169 #endif /* USE_FULL_LL_DRIVER */
170
171 /* Exported constants --------------------------------------------------------*/
172 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
173 * @{
174 */
175
176 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
177 * @brief Flags defines which can be used with LL_DAC_ReadReg function
178 * @{
179 */
180 /* DAC channel 1 flags */
181 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
182
183 #if defined(DAC_CHANNEL2_SUPPORT)
184 /* DAC channel 2 flags */
185 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
186 #endif /* DAC_CHANNEL2_SUPPORT */
187 /**
188 * @}
189 */
190
191 /** @defgroup DAC_LL_EC_IT DAC interruptions
192 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
193 * @{
194 */
195 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
196 #if defined(DAC_CHANNEL2_SUPPORT)
197 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
198 #endif /* DAC_CHANNEL2_SUPPORT */
199 /**
200 * @}
201 */
202
203 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
204 * @{
205 */
206 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
207 #if defined(DAC_CHANNEL2_SUPPORT)
208 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
209 #endif /* DAC_CHANNEL2_SUPPORT */
210 /**
211 * @}
212 */
213
214 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
215 * @{
216 */
217 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
218 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
219 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
220 #define LL_DAC_TRIG_EXT_TIM3_CH3 ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM3 CH3 event. */
221 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
222 #define LL_DAC_TRIG_EXT_TIM7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
223 #define LL_DAC_TRIG_EXT_TIM21_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM21 TRGO. */
224 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
225 /**
226 * @}
227 */
228
229 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
230 * @{
231 */
232 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
233 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
234 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
235 /**
236 * @}
237 */
238
239 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
240 * @{
241 */
242 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
243 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
244 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
245 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
254 /**
255 * @}
256 */
257
258 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
259 * @{
260 */
261 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
262 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
263 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
264 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
265 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
266 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
267 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
268 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
269 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
270 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
271 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
272 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
273 /**
274 * @}
275 */
276
277 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
278 * @{
279 */
280 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
281 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
282 /**
283 * @}
284 */
285
286
287 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
288 * @{
289 */
290 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
291 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
292 /**
293 * @}
294 */
295
296 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
297 * @{
298 */
299 /* List of DAC registers intended to be used (most commonly) with */
300 /* DMA transfer. */
301 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
302 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
303 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
304 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
305 /**
306 * @}
307 */
308
309 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
310 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
311 * not timeout values.
312 * For details on delays values, refer to descriptions in source code
313 * above each literal definition.
314 * @{
315 */
316
317 /* Delay for DAC channel voltage settling time from DAC channel startup */
318 /* (transition from disable to enable). */
319 /* Note: DAC channel startup time depends on board application environment: */
320 /* impedance connected to DAC channel output. */
321 /* The delay below is specified under conditions: */
322 /* - voltage maximum transition (lowest to highest value) */
323 /* - until voltage reaches final value +-1LSB */
324 /* - DAC channel output buffer enabled */
325 /* - load impedance of 5kOhm (min), 50pF (max) */
326 /* Literal set to maximum value (refer to device datasheet, */
327 /* parameter "tWAKEUP"). */
328 /* Unit: us */
329 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
330
331 /* Delay for DAC channel voltage settling time. */
332 /* Note: DAC channel startup time depends on board application environment: */
333 /* impedance connected to DAC channel output. */
334 /* The delay below is specified under conditions: */
335 /* - voltage maximum transition (lowest to highest value) */
336 /* - until voltage reaches final value +-1LSB */
337 /* - DAC channel output buffer enabled */
338 /* - load impedance of 5kOhm min, 50pF max */
339 /* Literal set to maximum value (refer to device datasheet, */
340 /* parameter "tSETTLING"). */
341 /* Unit: us */
342 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
343 /**
344 * @}
345 */
346
347 /**
348 * @}
349 */
350
351 /* Exported macro ------------------------------------------------------------*/
352 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
353 * @{
354 */
355
356 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
357 * @{
358 */
359
360 /**
361 * @brief Write a value in DAC register
362 * @param __INSTANCE__ DAC Instance
363 * @param __REG__ Register to be written
364 * @param __VALUE__ Value to be written in the register
365 * @retval None
366 */
367 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
368
369 /**
370 * @brief Read a value in DAC register
371 * @param __INSTANCE__ DAC Instance
372 * @param __REG__ Register to be read
373 * @retval Register value
374 */
375 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
376
377 /**
378 * @}
379 */
380
381 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
382 * @{
383 */
384
385 /**
386 * @brief Helper macro to get DAC channel number in decimal format
387 * from literals LL_DAC_CHANNEL_x.
388 * Example:
389 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
390 * will return decimal number "1".
391 * @note The input can be a value from functions where a channel
392 * number is returned.
393 * @param __CHANNEL__ This parameter can be one of the following values:
394 * @arg @ref LL_DAC_CHANNEL_1
395 * @arg @ref LL_DAC_CHANNEL_2 (1)
396 *
397 * (1) On this STM32 serie, parameter not available on all devices.
398 * Refer to device datasheet for channels availability.
399 * @retval 1...2 (value "2" depending on DAC channel 2 availability)
400 */
401 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
402 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
403
404 /**
405 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
406 * from number in decimal format.
407 * Example:
408 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
409 * will return a data equivalent to "LL_DAC_CHANNEL_1".
410 * @note If the input parameter does not correspond to a DAC channel,
411 * this macro returns value '0'.
412 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
413 * @retval Returned value can be one of the following values:
414 * @arg @ref LL_DAC_CHANNEL_1
415 * @arg @ref LL_DAC_CHANNEL_2 (1)
416 *
417 * (1) On this STM32 serie, parameter not available on all devices.
418 * Refer to device datasheet for channels availability.
419 */
420 #if defined(DAC_CHANNEL2_SUPPORT)
421 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
422 (((__DECIMAL_NB__) == 1U) \
423 ? ( \
424 LL_DAC_CHANNEL_1 \
425 ) \
426 : \
427 (((__DECIMAL_NB__) == 2U) \
428 ? ( \
429 LL_DAC_CHANNEL_2 \
430 ) \
431 : \
432 ( \
433 0 \
434 ) \
435 ) \
436 )
437 #else
438 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
439 (((__DECIMAL_NB__) == 1U) \
440 ? ( \
441 LL_DAC_CHANNEL_1 \
442 ) \
443 : \
444 ( \
445 0 \
446 ) \
447 )
448 #endif /* DAC_CHANNEL2_SUPPORT */
449
450 /**
451 * @brief Helper macro to define the DAC conversion data full-scale digital
452 * value corresponding to the selected DAC resolution.
453 * @note DAC conversion data full-scale corresponds to voltage range
454 * determined by analog voltage references Vref+ and Vref-
455 * (refer to reference manual).
456 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
457 * @arg @ref LL_DAC_RESOLUTION_12B
458 * @arg @ref LL_DAC_RESOLUTION_8B
459 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
460 */
461 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
462 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
463
464 /**
465 * @brief Helper macro to calculate the DAC conversion data (unit: digital
466 * value) corresponding to a voltage (unit: mVolt).
467 * @note This helper macro is intended to provide input data in voltage
468 * rather than digital value,
469 * to be used with LL DAC functions such as
470 * @ref LL_DAC_ConvertData12RightAligned().
471 * @note Analog reference voltage (Vref+) must be either known from
472 * user board environment or can be calculated using ADC measurement
473 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
474 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
475 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
476 * (unit: mVolt).
477 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
478 * @arg @ref LL_DAC_RESOLUTION_12B
479 * @arg @ref LL_DAC_RESOLUTION_8B
480 * @retval DAC conversion data (unit: digital value)
481 */
482 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
483 __DAC_VOLTAGE__,\
484 __DAC_RESOLUTION__) \
485 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
486 / (__VREFANALOG_VOLTAGE__) \
487 )
488
489 /**
490 * @}
491 */
492
493 /**
494 * @}
495 */
496
497
498 /* Exported functions --------------------------------------------------------*/
499 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
500 * @{
501 */
502 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
503 * @{
504 */
505
506 /**
507 * @brief Set the conversion trigger source for the selected DAC channel.
508 * @note For conversion trigger source to be effective, DAC trigger
509 * must be enabled using function @ref LL_DAC_EnableTrigger().
510 * @note To set conversion trigger source, DAC channel must be disabled.
511 * Otherwise, the setting is discarded.
512 * @note Availability of parameters of trigger sources from timer
513 * depends on timers availability on the selected device.
514 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
515 * CR TSEL2 LL_DAC_SetTriggerSource
516 * @param DACx DAC instance
517 * @param DAC_Channel This parameter can be one of the following values:
518 * @arg @ref LL_DAC_CHANNEL_1
519 * @arg @ref LL_DAC_CHANNEL_2 (1)
520 *
521 * (1) On this STM32 serie, parameter not available on all devices.
522 * Refer to device datasheet for channels availability.
523 * @param TriggerSource This parameter can be one of the following values:
524 * @arg @ref LL_DAC_TRIG_SOFTWARE
525 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
526 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
527 * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
528 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
529 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
530 * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
531 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
532 * @retval None
533 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)534 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
535 {
536 MODIFY_REG(DACx->CR,
537 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
538 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
539 }
540
541 /**
542 * @brief Get the conversion trigger source for the selected DAC channel.
543 * @note For conversion trigger source to be effective, DAC trigger
544 * must be enabled using function @ref LL_DAC_EnableTrigger().
545 * @note Availability of parameters of trigger sources from timer
546 * depends on timers availability on the selected device.
547 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
548 * CR TSEL2 LL_DAC_GetTriggerSource
549 * @param DACx DAC instance
550 * @param DAC_Channel This parameter can be one of the following values:
551 * @arg @ref LL_DAC_CHANNEL_1
552 * @arg @ref LL_DAC_CHANNEL_2 (1)
553 *
554 * (1) On this STM32 serie, parameter not available on all devices.
555 * Refer to device datasheet for channels availability.
556 * @retval Returned value can be one of the following values:
557 * @arg @ref LL_DAC_TRIG_SOFTWARE
558 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
559 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
560 * @arg @ref LL_DAC_TRIG_EXT_TIM3_CH3
561 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
562 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
563 * @arg @ref LL_DAC_TRIG_EXT_TIM21_TRGO
564 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
565 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)566 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
567 {
568 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
569 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
570 );
571 }
572
573 /**
574 * @brief Set the waveform automatic generation mode
575 * for the selected DAC channel.
576 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
577 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
578 * @param DACx DAC instance
579 * @param DAC_Channel This parameter can be one of the following values:
580 * @arg @ref LL_DAC_CHANNEL_1
581 * @arg @ref LL_DAC_CHANNEL_2 (1)
582 *
583 * (1) On this STM32 serie, parameter not available on all devices.
584 * Refer to device datasheet for channels availability.
585 * @param WaveAutoGeneration This parameter can be one of the following values:
586 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
587 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
588 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
589 * @retval None
590 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)591 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
592 {
593 MODIFY_REG(DACx->CR,
594 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
595 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
596 }
597
598 /**
599 * @brief Get the waveform automatic generation mode
600 * for the selected DAC channel.
601 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
602 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
603 * @param DACx DAC instance
604 * @param DAC_Channel This parameter can be one of the following values:
605 * @arg @ref LL_DAC_CHANNEL_1
606 * @arg @ref LL_DAC_CHANNEL_2 (1)
607 *
608 * (1) On this STM32 serie, parameter not available on all devices.
609 * Refer to device datasheet for channels availability.
610 * @retval Returned value can be one of the following values:
611 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
612 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
613 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
614 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)615 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
616 {
617 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
618 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
619 );
620 }
621
622 /**
623 * @brief Set the noise waveform generation for the selected DAC channel:
624 * Noise mode and parameters LFSR (linear feedback shift register).
625 * @note For wave generation to be effective, DAC channel
626 * wave generation mode must be enabled using
627 * function @ref LL_DAC_SetWaveAutoGeneration().
628 * @note This setting can be set when the selected DAC channel is disabled
629 * (otherwise, the setting operation is ignored).
630 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
631 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
632 * @param DACx DAC instance
633 * @param DAC_Channel This parameter can be one of the following values:
634 * @arg @ref LL_DAC_CHANNEL_1
635 * @arg @ref LL_DAC_CHANNEL_2 (1)
636 *
637 * (1) On this STM32 serie, parameter not available on all devices.
638 * Refer to device datasheet for channels availability.
639 * @param NoiseLFSRMask This parameter can be one of the following values:
640 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
641 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
652 * @retval None
653 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)654 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
655 {
656 MODIFY_REG(DACx->CR,
657 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
658 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
659 }
660
661 /**
662 * @brief Set the noise waveform generation for the selected DAC channel:
663 * Noise mode and parameters LFSR (linear feedback shift register).
664 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
665 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
666 * @param DACx DAC instance
667 * @param DAC_Channel This parameter can be one of the following values:
668 * @arg @ref LL_DAC_CHANNEL_1
669 * @arg @ref LL_DAC_CHANNEL_2 (1)
670 *
671 * (1) On this STM32 serie, parameter not available on all devices.
672 * Refer to device datasheet for channels availability.
673 * @retval Returned value can be one of the following values:
674 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
675 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
676 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
677 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
678 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
679 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
680 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
681 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
682 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
683 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
684 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
685 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
686 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)687 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
688 {
689 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
690 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
691 );
692 }
693
694 /**
695 * @brief Set the triangle waveform generation for the selected DAC channel:
696 * triangle mode and amplitude.
697 * @note For wave generation to be effective, DAC channel
698 * wave generation mode must be enabled using
699 * function @ref LL_DAC_SetWaveAutoGeneration().
700 * @note This setting can be set when the selected DAC channel is disabled
701 * (otherwise, the setting operation is ignored).
702 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
703 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
704 * @param DACx DAC instance
705 * @param DAC_Channel This parameter can be one of the following values:
706 * @arg @ref LL_DAC_CHANNEL_1
707 * @arg @ref LL_DAC_CHANNEL_2 (1)
708 *
709 * (1) On this STM32 serie, parameter not available on all devices.
710 * Refer to device datasheet for channels availability.
711 * @param TriangleAmplitude This parameter can be one of the following values:
712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
724 * @retval None
725 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)726 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
727 {
728 MODIFY_REG(DACx->CR,
729 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
730 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
731 }
732
733 /**
734 * @brief Set the triangle waveform generation for the selected DAC channel:
735 * triangle mode and amplitude.
736 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
737 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
738 * @param DACx DAC instance
739 * @param DAC_Channel This parameter can be one of the following values:
740 * @arg @ref LL_DAC_CHANNEL_1
741 * @arg @ref LL_DAC_CHANNEL_2 (1)
742 *
743 * (1) On this STM32 serie, parameter not available on all devices.
744 * Refer to device datasheet for channels availability.
745 * @retval Returned value can be one of the following values:
746 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
747 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
748 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
749 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
750 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
751 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
752 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
753 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
754 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
755 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
756 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
757 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
758 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)759 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
760 {
761 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
762 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
763 );
764 }
765
766 /**
767 * @brief Set the output buffer for the selected DAC channel.
768 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
769 * CR BOFF2 LL_DAC_SetOutputBuffer
770 * @param DACx DAC instance
771 * @param DAC_Channel This parameter can be one of the following values:
772 * @arg @ref LL_DAC_CHANNEL_1
773 * @arg @ref LL_DAC_CHANNEL_2 (1)
774 *
775 * (1) On this STM32 serie, parameter not available on all devices.
776 * Refer to device datasheet for channels availability.
777 * @param OutputBuffer This parameter can be one of the following values:
778 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
779 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
780 * @retval None
781 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)782 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
783 {
784 MODIFY_REG(DACx->CR,
785 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
786 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
787 }
788
789 /**
790 * @brief Get the output buffer state for the selected DAC channel.
791 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
792 * CR BOFF2 LL_DAC_GetOutputBuffer
793 * @param DACx DAC instance
794 * @param DAC_Channel This parameter can be one of the following values:
795 * @arg @ref LL_DAC_CHANNEL_1
796 * @arg @ref LL_DAC_CHANNEL_2 (1)
797 *
798 * (1) On this STM32 serie, parameter not available on all devices.
799 * Refer to device datasheet for channels availability.
800 * @retval Returned value can be one of the following values:
801 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
802 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
803 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)804 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
805 {
806 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
807 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
808 );
809 }
810
811 /**
812 * @}
813 */
814
815 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
816 * @{
817 */
818
819 /**
820 * @brief Enable DAC DMA transfer request of the selected channel.
821 * @note To configure DMA source address (peripheral address),
822 * use function @ref LL_DAC_DMA_GetRegAddr().
823 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
824 * CR DMAEN2 LL_DAC_EnableDMAReq
825 * @param DACx DAC instance
826 * @param DAC_Channel This parameter can be one of the following values:
827 * @arg @ref LL_DAC_CHANNEL_1
828 * @arg @ref LL_DAC_CHANNEL_2 (1)
829 *
830 * (1) On this STM32 serie, parameter not available on all devices.
831 * Refer to device datasheet for channels availability.
832 * @retval None
833 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)834 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
835 {
836 SET_BIT(DACx->CR,
837 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
838 }
839
840 /**
841 * @brief Disable DAC DMA transfer request of the selected channel.
842 * @note To configure DMA source address (peripheral address),
843 * use function @ref LL_DAC_DMA_GetRegAddr().
844 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
845 * CR DMAEN2 LL_DAC_DisableDMAReq
846 * @param DACx DAC instance
847 * @param DAC_Channel This parameter can be one of the following values:
848 * @arg @ref LL_DAC_CHANNEL_1
849 * @arg @ref LL_DAC_CHANNEL_2 (1)
850 *
851 * (1) On this STM32 serie, parameter not available on all devices.
852 * Refer to device datasheet for channels availability.
853 * @retval None
854 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)855 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
856 {
857 CLEAR_BIT(DACx->CR,
858 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
859 }
860
861 /**
862 * @brief Get DAC DMA transfer request state of the selected channel.
863 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
864 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
865 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
866 * @param DACx DAC instance
867 * @param DAC_Channel This parameter can be one of the following values:
868 * @arg @ref LL_DAC_CHANNEL_1
869 * @arg @ref LL_DAC_CHANNEL_2 (1)
870 *
871 * (1) On this STM32 serie, parameter not available on all devices.
872 * Refer to device datasheet for channels availability.
873 * @retval State of bit (1 or 0).
874 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)875 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
876 {
877 return (READ_BIT(DACx->CR,
878 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
879 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
880 }
881
882 /**
883 * @brief Function to help to configure DMA transfer to DAC: retrieve the
884 * DAC register address from DAC instance and a list of DAC registers
885 * intended to be used (most commonly) with DMA transfer.
886 * @note These DAC registers are data holding registers:
887 * when DAC conversion is requested, DAC generates a DMA transfer
888 * request to have data available in DAC data holding registers.
889 * @note This macro is intended to be used with LL DMA driver, refer to
890 * function "LL_DMA_ConfigAddresses()".
891 * Example:
892 * LL_DMA_ConfigAddresses(DMA1,
893 * LL_DMA_CHANNEL_1,
894 * (uint32_t)&< array or variable >,
895 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
896 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
897 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
898 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
899 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
900 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
901 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
902 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
903 * @param DACx DAC instance
904 * @param DAC_Channel This parameter can be one of the following values:
905 * @arg @ref LL_DAC_CHANNEL_1
906 * @arg @ref LL_DAC_CHANNEL_2 (1)
907 *
908 * (1) On this STM32 serie, parameter not available on all devices.
909 * Refer to device datasheet for channels availability.
910 * @param Register This parameter can be one of the following values:
911 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
912 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
913 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
914 * @retval DAC register address
915 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)916 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
917 {
918 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
919 /* DAC channel selected. */
920 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> Register) & DAC_REG_REGOFFSET_MASK_POSBIT0))));
921 }
922 /**
923 * @}
924 */
925
926 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
927 * @{
928 */
929
930 /**
931 * @brief Enable DAC selected channel.
932 * @rmtoll CR EN1 LL_DAC_Enable\n
933 * CR EN2 LL_DAC_Enable
934 * @note After enable from off state, DAC channel requires a delay
935 * for output voltage to reach accuracy +/- 1 LSB.
936 * Refer to device datasheet, parameter "tWAKEUP".
937 * @param DACx DAC instance
938 * @param DAC_Channel This parameter can be one of the following values:
939 * @arg @ref LL_DAC_CHANNEL_1
940 * @arg @ref LL_DAC_CHANNEL_2 (1)
941 *
942 * (1) On this STM32 serie, parameter not available on all devices.
943 * Refer to device datasheet for channels availability.
944 * @retval None
945 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)946 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
947 {
948 SET_BIT(DACx->CR,
949 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
950 }
951
952 /**
953 * @brief Disable DAC selected channel.
954 * @rmtoll CR EN1 LL_DAC_Disable\n
955 * CR EN2 LL_DAC_Disable
956 * @param DACx DAC instance
957 * @param DAC_Channel This parameter can be one of the following values:
958 * @arg @ref LL_DAC_CHANNEL_1
959 * @arg @ref LL_DAC_CHANNEL_2 (1)
960 *
961 * (1) On this STM32 serie, parameter not available on all devices.
962 * Refer to device datasheet for channels availability.
963 * @retval None
964 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)965 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
966 {
967 CLEAR_BIT(DACx->CR,
968 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
969 }
970
971 /**
972 * @brief Get DAC enable state of the selected channel.
973 * (0: DAC channel is disabled, 1: DAC channel is enabled)
974 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
975 * CR EN2 LL_DAC_IsEnabled
976 * @param DACx DAC instance
977 * @param DAC_Channel This parameter can be one of the following values:
978 * @arg @ref LL_DAC_CHANNEL_1
979 * @arg @ref LL_DAC_CHANNEL_2 (1)
980 *
981 * (1) On this STM32 serie, parameter not available on all devices.
982 * Refer to device datasheet for channels availability.
983 * @retval State of bit (1 or 0).
984 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)985 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
986 {
987 return (READ_BIT(DACx->CR,
988 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
989 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
990 }
991
992 /**
993 * @brief Enable DAC trigger of the selected channel.
994 * @note - If DAC trigger is disabled, DAC conversion is performed
995 * automatically once the data holding register is updated,
996 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
997 * @ref LL_DAC_ConvertData12RightAligned(), ...
998 * - If DAC trigger is enabled, DAC conversion is performed
999 * only when a hardware of software trigger event is occurring.
1000 * Select trigger source using
1001 * function @ref LL_DAC_SetTriggerSource().
1002 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
1003 * CR TEN2 LL_DAC_EnableTrigger
1004 * @param DACx DAC instance
1005 * @param DAC_Channel This parameter can be one of the following values:
1006 * @arg @ref LL_DAC_CHANNEL_1
1007 * @arg @ref LL_DAC_CHANNEL_2 (1)
1008 *
1009 * (1) On this STM32 serie, parameter not available on all devices.
1010 * Refer to device datasheet for channels availability.
1011 * @retval None
1012 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1013 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1014 {
1015 SET_BIT(DACx->CR,
1016 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1017 }
1018
1019 /**
1020 * @brief Disable DAC trigger of the selected channel.
1021 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
1022 * CR TEN2 LL_DAC_DisableTrigger
1023 * @param DACx DAC instance
1024 * @param DAC_Channel This parameter can be one of the following values:
1025 * @arg @ref LL_DAC_CHANNEL_1
1026 * @arg @ref LL_DAC_CHANNEL_2 (1)
1027 *
1028 * (1) On this STM32 serie, parameter not available on all devices.
1029 * Refer to device datasheet for channels availability.
1030 * @retval None
1031 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)1032 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1033 {
1034 CLEAR_BIT(DACx->CR,
1035 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1036 }
1037
1038 /**
1039 * @brief Get DAC trigger state of the selected channel.
1040 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
1041 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
1042 * CR TEN2 LL_DAC_IsTriggerEnabled
1043 * @param DACx DAC instance
1044 * @param DAC_Channel This parameter can be one of the following values:
1045 * @arg @ref LL_DAC_CHANNEL_1
1046 * @arg @ref LL_DAC_CHANNEL_2 (1)
1047 *
1048 * (1) On this STM32 serie, parameter not available on all devices.
1049 * Refer to device datasheet for channels availability.
1050 * @retval State of bit (1 or 0).
1051 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)1052 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1053 {
1054 return (READ_BIT(DACx->CR,
1055 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1056 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
1057 }
1058
1059 /**
1060 * @brief Trig DAC conversion by software for the selected DAC channel.
1061 * @note Preliminarily, DAC trigger must be set to software trigger
1062 * using function @ref LL_DAC_SetTriggerSource()
1063 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
1064 * and DAC trigger must be enabled using
1065 * function @ref LL_DAC_EnableTrigger().
1066 * @note For devices featuring DAC with 2 channels: this function
1067 * can perform a SW start of both DAC channels simultaneously.
1068 * Two channels can be selected as parameter.
1069 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
1070 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
1071 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
1072 * @param DACx DAC instance
1073 * @param DAC_Channel This parameter can a combination of the following values:
1074 * @arg @ref LL_DAC_CHANNEL_1
1075 * @arg @ref LL_DAC_CHANNEL_2 (1)
1076 *
1077 * (1) On this STM32 serie, parameter not available on all devices.
1078 * Refer to device datasheet for channels availability.
1079 * @retval None
1080 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1081 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1082 {
1083 SET_BIT(DACx->SWTRIGR,
1084 (DAC_Channel & DAC_SWTR_CHX_MASK));
1085 }
1086
1087 /**
1088 * @brief Set the data to be loaded in the data holding register
1089 * in format 12 bits left alignment (LSB aligned on bit 0),
1090 * for the selected DAC channel.
1091 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1092 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1093 * @param DACx DAC instance
1094 * @param DAC_Channel This parameter can be one of the following values:
1095 * @arg @ref LL_DAC_CHANNEL_1
1096 * @arg @ref LL_DAC_CHANNEL_2 (1)
1097 *
1098 * (1) On this STM32 serie, parameter not available on all devices.
1099 * Refer to device datasheet for channels availability.
1100 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1101 * @retval None
1102 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1103 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1104 {
1105 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1106
1107 MODIFY_REG(*preg,
1108 DAC_DHR12R1_DACC1DHR,
1109 Data);
1110 }
1111
1112 /**
1113 * @brief Set the data to be loaded in the data holding register
1114 * in format 12 bits left alignment (MSB aligned on bit 15),
1115 * for the selected DAC channel.
1116 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1117 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1118 * @param DACx DAC instance
1119 * @param DAC_Channel This parameter can be one of the following values:
1120 * @arg @ref LL_DAC_CHANNEL_1
1121 * @arg @ref LL_DAC_CHANNEL_2 (1)
1122 *
1123 * (1) On this STM32 serie, parameter not available on all devices.
1124 * Refer to device datasheet for channels availability.
1125 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1126 * @retval None
1127 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1128 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1129 {
1130 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1131
1132 MODIFY_REG(*preg,
1133 DAC_DHR12L1_DACC1DHR,
1134 Data);
1135 }
1136
1137 /**
1138 * @brief Set the data to be loaded in the data holding register
1139 * in format 8 bits left alignment (LSB aligned on bit 0),
1140 * for the selected DAC channel.
1141 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1142 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1143 * @param DACx DAC instance
1144 * @param DAC_Channel This parameter can be one of the following values:
1145 * @arg @ref LL_DAC_CHANNEL_1
1146 * @arg @ref LL_DAC_CHANNEL_2 (1)
1147 *
1148 * (1) On this STM32 serie, parameter not available on all devices.
1149 * Refer to device datasheet for channels availability.
1150 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1151 * @retval None
1152 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1153 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1154 {
1155 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1156
1157 MODIFY_REG(*preg,
1158 DAC_DHR8R1_DACC1DHR,
1159 Data);
1160 }
1161
1162 #if defined(DAC_CHANNEL2_SUPPORT)
1163 /**
1164 * @brief Set the data to be loaded in the data holding register
1165 * in format 12 bits left alignment (LSB aligned on bit 0),
1166 * for both DAC channels.
1167 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1168 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1169 * @param DACx DAC instance
1170 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1171 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1172 * @retval None
1173 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1174 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1175 {
1176 MODIFY_REG(DACx->DHR12RD,
1177 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1178 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1179 }
1180
1181 /**
1182 * @brief Set the data to be loaded in the data holding register
1183 * in format 12 bits left alignment (MSB aligned on bit 15),
1184 * for both DAC channels.
1185 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1186 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1187 * @param DACx DAC instance
1188 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1189 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1190 * @retval None
1191 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1192 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1193 {
1194 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1195 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1196 /* the 4 LSB must be taken into account for the shift value. */
1197 MODIFY_REG(DACx->DHR12LD,
1198 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1199 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1200 }
1201
1202 /**
1203 * @brief Set the data to be loaded in the data holding register
1204 * in format 8 bits left alignment (LSB aligned on bit 0),
1205 * for both DAC channels.
1206 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1207 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1208 * @param DACx DAC instance
1209 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1210 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1211 * @retval None
1212 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1213 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1214 {
1215 MODIFY_REG(DACx->DHR8RD,
1216 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1217 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1218 }
1219
1220 #endif /* DAC_CHANNEL2_SUPPORT */
1221 /**
1222 * @brief Retrieve output data currently generated for the selected DAC channel.
1223 * @note Whatever alignment and resolution settings
1224 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1225 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1226 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1227 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1228 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1229 * @param DACx DAC instance
1230 * @param DAC_Channel This parameter can be one of the following values:
1231 * @arg @ref LL_DAC_CHANNEL_1
1232 * @arg @ref LL_DAC_CHANNEL_2 (1)
1233 *
1234 * (1) On this STM32 serie, parameter not available on all devices.
1235 * Refer to device datasheet for channels availability.
1236 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1237 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1238 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1239 {
1240 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_REGOFFSET_MASK_POSBIT0);
1241
1242 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1243 }
1244
1245 /**
1246 * @}
1247 */
1248
1249 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1250 * @{
1251 */
1252 /**
1253 * @brief Get DAC underrun flag for DAC channel 1
1254 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1255 * @param DACx DAC instance
1256 * @retval State of bit (1 or 0).
1257 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1258 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1259 {
1260 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1261 }
1262
1263 #if defined(DAC_CHANNEL2_SUPPORT)
1264 /**
1265 * @brief Get DAC underrun flag for DAC channel 2
1266 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1267 * @param DACx DAC instance
1268 * @retval State of bit (1 or 0).
1269 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1270 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1271 {
1272 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1273 }
1274 #endif /* DAC_CHANNEL2_SUPPORT */
1275
1276 /**
1277 * @brief Clear DAC underrun flag for DAC channel 1
1278 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1279 * @param DACx DAC instance
1280 * @retval None
1281 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1282 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1283 {
1284 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1285 }
1286
1287 #if defined(DAC_CHANNEL2_SUPPORT)
1288 /**
1289 * @brief Clear DAC underrun flag for DAC channel 2
1290 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1291 * @param DACx DAC instance
1292 * @retval None
1293 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1294 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1295 {
1296 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1297 }
1298 #endif /* DAC_CHANNEL2_SUPPORT */
1299
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup DAC_LL_EF_IT_Management IT management
1305 * @{
1306 */
1307
1308 /**
1309 * @brief Enable DMA underrun interrupt for DAC channel 1
1310 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1311 * @param DACx DAC instance
1312 * @retval None
1313 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1314 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1315 {
1316 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1317 }
1318
1319 #if defined(DAC_CHANNEL2_SUPPORT)
1320 /**
1321 * @brief Enable DMA underrun interrupt for DAC channel 2
1322 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1323 * @param DACx DAC instance
1324 * @retval None
1325 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1326 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1327 {
1328 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1329 }
1330 #endif /* DAC_CHANNEL2_SUPPORT */
1331
1332 /**
1333 * @brief Disable DMA underrun interrupt for DAC channel 1
1334 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1335 * @param DACx DAC instance
1336 * @retval None
1337 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1338 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1339 {
1340 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1341 }
1342
1343 #if defined(DAC_CHANNEL2_SUPPORT)
1344 /**
1345 * @brief Disable DMA underrun interrupt for DAC channel 2
1346 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1347 * @param DACx DAC instance
1348 * @retval None
1349 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1350 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1351 {
1352 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1353 }
1354 #endif /* DAC_CHANNEL2_SUPPORT */
1355
1356 /**
1357 * @brief Get DMA underrun interrupt for DAC channel 1
1358 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1359 * @param DACx DAC instance
1360 * @retval State of bit (1 or 0).
1361 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1362 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1363 {
1364 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1365 }
1366
1367 #if defined(DAC_CHANNEL2_SUPPORT)
1368 /**
1369 * @brief Get DMA underrun interrupt for DAC channel 2
1370 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1371 * @param DACx DAC instance
1372 * @retval State of bit (1 or 0).
1373 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1374 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1375 {
1376 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1377 }
1378 #endif /* DAC_CHANNEL2_SUPPORT */
1379
1380 /**
1381 * @}
1382 */
1383
1384 #if defined(USE_FULL_LL_DRIVER)
1385 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1386 * @{
1387 */
1388
1389 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1390 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1391 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1392
1393 /**
1394 * @}
1395 */
1396 #endif /* USE_FULL_LL_DRIVER */
1397
1398 /**
1399 * @}
1400 */
1401
1402 /**
1403 * @}
1404 */
1405
1406 #endif /* DAC1 */
1407
1408 /**
1409 * @}
1410 */
1411
1412 #ifdef __cplusplus
1413 }
1414 #endif
1415
1416 #endif /* __STM32L0xx_LL_DAC_H */
1417
1418 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1419
