1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) MPU API to configure and enable regions
17 (+) API to access to MCU info (CPUID register)
18
19 @endverbatim
20 ******************************************************************************
21 * @attention
22 *
23 * Copyright (c) 2016 STMicroelectronics.
24 * All rights reserved.
25 *
26 * This software is licensed under terms that can be found in the LICENSE file in
27 * the root directory of this software component.
28 * If no LICENSE file comes with this software, it is provided AS-IS.
29 *
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32L0xx_LL_CORTEX_H
35 #define __STM32L0xx_LL_CORTEX_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l0xx.h"
43
44 /** @addtogroup STM32L0xx_LL_Driver
45 * @{
46 */
47
48 /** @defgroup CORTEX_LL CORTEX
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56
57 /* Private macros ------------------------------------------------------------*/
58
59 /* Exported types ------------------------------------------------------------*/
60 /* Exported constants --------------------------------------------------------*/
61 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
62 * @{
63 */
64
65 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
66 * @{
67 */
68 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/
69 #define LL_SYSTICK_CLKSOURCE_HCLK (SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
70 /**
71 * @}
72 */
73
74 #if __MPU_PRESENT
75
76 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
77 * @{
78 */
79 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE (0x00000000U) /*!< Disable NMI and privileged SW access */
80 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
81 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
82 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
83 /**
84 * @}
85 */
86
87 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
88 * @{
89 */
90 #define LL_MPU_REGION_NUMBER0 (0x00U) /*!< REGION Number 0 */
91 #define LL_MPU_REGION_NUMBER1 (0x01U) /*!< REGION Number 1 */
92 #define LL_MPU_REGION_NUMBER2 (0x02U) /*!< REGION Number 2 */
93 #define LL_MPU_REGION_NUMBER3 (0x03U) /*!< REGION Number 3 */
94 #define LL_MPU_REGION_NUMBER4 (0x04U) /*!< REGION Number 4 */
95 #define LL_MPU_REGION_NUMBER5 (0x05U) /*!< REGION Number 5 */
96 #define LL_MPU_REGION_NUMBER6 (0x06U) /*!< REGION Number 6 */
97 #define LL_MPU_REGION_NUMBER7 (0x07U) /*!< REGION Number 7 */
98 /**
99 * @}
100 */
101
102 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
103 * @{
104 */
105 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
106 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
107 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
108 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
109 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
110 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
111 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
112 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
113 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
114 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
115 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
116 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
117 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
118 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
119 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
120 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
123 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
124 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
133 /**
134 * @}
135 */
136
137 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
138 * @{
139 */
140 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
141 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
142 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
143 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
144 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
145 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
146 /**
147 * @}
148 */
149
150 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
151 * @{
152 */
153 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
154 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
155 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
156 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
157 /**
158 * @}
159 */
160
161 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
162 * @{
163 */
164 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0x00U) /*!< Instruction fetches enabled */
165 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
166 /**
167 * @}
168 */
169
170 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
171 * @{
172 */
173 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
174 #define LL_MPU_ACCESS_NOT_SHAREABLE (0x00U) /*!< Not Shareable memory attribute */
175 /**
176 * @}
177 */
178
179 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
180 * @{
181 */
182 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
183 #define LL_MPU_ACCESS_NOT_CACHEABLE (0x00U) /*!< Not Cacheable memory attribute */
184 /**
185 * @}
186 */
187
188 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
189 * @{
190 */
191 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
192 #define LL_MPU_ACCESS_NOT_BUFFERABLE (0x00U) /*!< Not Bufferable memory attribute */
193 /**
194 * @}
195 */
196 #endif /* __MPU_PRESENT */
197 /**
198 * @}
199 */
200
201 /* Exported macro ------------------------------------------------------------*/
202
203 /* Exported functions --------------------------------------------------------*/
204 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
205 * @{
206 */
207
208 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
209 * @{
210 */
211
212 /**
213 * @brief This function checks if the Systick counter flag is active or not.
214 * @note It can be used in timeout function on application side.
215 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
216 * @retval State of bit (1 or 0).
217 */
LL_SYSTICK_IsActiveCounterFlag(void)218 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
219 {
220 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
221 }
222
223 /**
224 * @brief Configures the SysTick clock source
225 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
226 * @param Source This parameter can be one of the following values:
227 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
228 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
229 * @retval None
230 */
LL_SYSTICK_SetClkSource(uint32_t Source)231 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
232 {
233 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
234 {
235 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
236 }
237 else
238 {
239 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
240 }
241 }
242
243 /**
244 * @brief Get the SysTick clock source
245 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
246 * @retval Returned value can be one of the following values:
247 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
248 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
249 */
LL_SYSTICK_GetClkSource(void)250 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
251 {
252 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
253 }
254
255 /**
256 * @brief Enable SysTick exception request
257 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
258 * @retval None
259 */
LL_SYSTICK_EnableIT(void)260 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
261 {
262 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
263 }
264
265 /**
266 * @brief Disable SysTick exception request
267 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
268 * @retval None
269 */
LL_SYSTICK_DisableIT(void)270 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
271 {
272 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
273 }
274
275 /**
276 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
277 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
278 * @retval State of bit (1 or 0).
279 */
LL_SYSTICK_IsEnabledIT(void)280 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
281 {
282 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
283 }
284
285 /**
286 * @}
287 */
288
289 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
290 * @{
291 */
292
293 /**
294 * @brief Processor uses sleep as its low power mode
295 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
296 * @retval None
297 */
LL_LPM_EnableSleep(void)298 __STATIC_INLINE void LL_LPM_EnableSleep(void)
299 {
300 /* Clear SLEEPDEEP bit of Cortex System Control Register */
301 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
302 }
303
304 /**
305 * @brief Processor uses deep sleep as its low power mode
306 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
307 * @retval None
308 */
LL_LPM_EnableDeepSleep(void)309 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
310 {
311 /* Set SLEEPDEEP bit of Cortex System Control Register */
312 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
313 }
314
315 /**
316 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
317 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
318 * empty main application.
319 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
320 * @retval None
321 */
LL_LPM_EnableSleepOnExit(void)322 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
323 {
324 /* Set SLEEPONEXIT bit of Cortex System Control Register */
325 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
326 }
327
328 /**
329 * @brief Do not sleep when returning to Thread mode.
330 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
331 * @retval None
332 */
LL_LPM_DisableSleepOnExit(void)333 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
334 {
335 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
336 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
337 }
338
339 /**
340 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
341 * processor.
342 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
343 * @retval None
344 */
LL_LPM_EnableEventOnPend(void)345 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
346 {
347 /* Set SEVEONPEND bit of Cortex System Control Register */
348 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
349 }
350
351 /**
352 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
353 * excluded
354 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
355 * @retval None
356 */
LL_LPM_DisableEventOnPend(void)357 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
358 {
359 /* Clear SEVEONPEND bit of Cortex System Control Register */
360 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
361 }
362
363 /**
364 * @}
365 */
366
367 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
368 * @{
369 */
370
371 /**
372 * @brief Get Implementer code
373 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
374 * @retval Value should be equal to 0x41 for ARM
375 */
LL_CPUID_GetImplementer(void)376 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
377 {
378 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
379 }
380
381 /**
382 * @brief Get Variant number (The r value in the rnpn product revision identifier)
383 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
384 * @retval Value between 0 and 255 (0x0: revision 0)
385 */
LL_CPUID_GetVariant(void)386 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
387 {
388 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
389 }
390
391 /**
392 * @brief Get Architecture number
393 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
394 * @retval Value should be equal to 0xC for Cortex-M0+ devices
395 */
LL_CPUID_GetArchitecture(void)396 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
397 {
398 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
399 }
400
401 /**
402 * @brief Get Part number
403 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
404 * @retval Value should be equal to 0xC60 for Cortex-M0+
405 */
LL_CPUID_GetParNo(void)406 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
407 {
408 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
409 }
410
411 /**
412 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
413 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
414 * @retval Value between 0 and 255 (0x1: patch 1)
415 */
LL_CPUID_GetRevision(void)416 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
417 {
418 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
419 }
420
421 /**
422 * @}
423 */
424
425 #if __MPU_PRESENT
426 /** @defgroup CORTEX_LL_EF_MPU MPU
427 * @{
428 */
429
430 /**
431 * @brief Enable MPU with input options
432 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
433 * @param Options This parameter can be one of the following values:
434 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
435 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
436 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
437 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
438 * @retval None
439 */
LL_MPU_Enable(uint32_t Options)440 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
441 {
442 /* Enable the MPU*/
443 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
444 /* Ensure MPU settings take effects */
445 __DSB();
446 /* Sequence instruction fetches using update settings */
447 __ISB();
448 }
449
450 /**
451 * @brief Disable MPU
452 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
453 * @retval None
454 */
LL_MPU_Disable(void)455 __STATIC_INLINE void LL_MPU_Disable(void)
456 {
457 /* Make sure outstanding transfers are done */
458 __DMB();
459 /* Disable MPU*/
460 WRITE_REG(MPU->CTRL, 0U);
461 }
462
463 /**
464 * @brief Check if MPU is enabled or not
465 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
466 * @retval State of bit (1 or 0).
467 */
LL_MPU_IsEnabled(void)468 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
469 {
470 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
471 }
472
473 /**
474 * @brief Enable a MPU region
475 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
476 * @param Region This parameter can be one of the following values:
477 * @arg @ref LL_MPU_REGION_NUMBER0
478 * @arg @ref LL_MPU_REGION_NUMBER1
479 * @arg @ref LL_MPU_REGION_NUMBER2
480 * @arg @ref LL_MPU_REGION_NUMBER3
481 * @arg @ref LL_MPU_REGION_NUMBER4
482 * @arg @ref LL_MPU_REGION_NUMBER5
483 * @arg @ref LL_MPU_REGION_NUMBER6
484 * @arg @ref LL_MPU_REGION_NUMBER7
485 * @retval None
486 */
LL_MPU_EnableRegion(uint32_t Region)487 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
488 {
489 /* Set Region number */
490 WRITE_REG(MPU->RNR, Region);
491 /* Enable the MPU region */
492 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
493 }
494
495 /**
496 * @brief Configure and enable a region
497 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
498 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
499 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
500 * MPU_RASR XN LL_MPU_ConfigRegion\n
501 * MPU_RASR AP LL_MPU_ConfigRegion\n
502 * MPU_RASR S LL_MPU_ConfigRegion\n
503 * MPU_RASR C LL_MPU_ConfigRegion\n
504 * MPU_RASR B LL_MPU_ConfigRegion\n
505 * MPU_RASR SIZE LL_MPU_ConfigRegion
506 * @param Region This parameter can be one of the following values:
507 * @arg @ref LL_MPU_REGION_NUMBER0
508 * @arg @ref LL_MPU_REGION_NUMBER1
509 * @arg @ref LL_MPU_REGION_NUMBER2
510 * @arg @ref LL_MPU_REGION_NUMBER3
511 * @arg @ref LL_MPU_REGION_NUMBER4
512 * @arg @ref LL_MPU_REGION_NUMBER5
513 * @arg @ref LL_MPU_REGION_NUMBER6
514 * @arg @ref LL_MPU_REGION_NUMBER7
515 * @param Address Value of region base address
516 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
517 * @param Attributes This parameter can be a combination of the following values:
518 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
519 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
520 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
521 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
522 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
523 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
524 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
525 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
526 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
527 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
528 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
529 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
530 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
531 * @retval None
532 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)533 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
534 {
535 /* Set Region number */
536 WRITE_REG(MPU->RNR, Region);
537 /* Set base address */
538 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
539 /* Configure MPU */
540 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
541 }
542
543 /**
544 * @brief Disable a region
545 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
546 * MPU_RASR ENABLE LL_MPU_DisableRegion
547 * @param Region This parameter can be one of the following values:
548 * @arg @ref LL_MPU_REGION_NUMBER0
549 * @arg @ref LL_MPU_REGION_NUMBER1
550 * @arg @ref LL_MPU_REGION_NUMBER2
551 * @arg @ref LL_MPU_REGION_NUMBER3
552 * @arg @ref LL_MPU_REGION_NUMBER4
553 * @arg @ref LL_MPU_REGION_NUMBER5
554 * @arg @ref LL_MPU_REGION_NUMBER6
555 * @arg @ref LL_MPU_REGION_NUMBER7
556 * @retval None
557 */
LL_MPU_DisableRegion(uint32_t Region)558 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
559 {
560 /* Set Region number */
561 WRITE_REG(MPU->RNR, Region);
562 /* Disable the MPU region */
563 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
564 }
565
566 /**
567 * @}
568 */
569
570 #endif /* __MPU_PRESENT */
571 /**
572 * @}
573 */
574
575 /**
576 * @}
577 */
578
579 /**
580 * @}
581 */
582
583 #ifdef __cplusplus
584 }
585 #endif
586
587 #endif /* __STM32L0xx_LL_CORTEX_H */
588
589
